#include <iostream>
#include <math.h>
#include <unistd.h>
#include <memory>

const std::size_t N = 1 << 20;

__global__
void vec_add(float* const c, const float* const a, const float* const b, const std::size_t n)
{
    // shared memory spaces are block-scoped and for intra-thread communication, 10 was meaningless here
    //__shared__ int shared_memory[10];

    // grids have blocks, blocks have threads
    // thread indices are not unique within a grid, so unique-ify it using block information
    const std::size_t i = threadIdx.x + (blockIdx.x * blockDim.x);
    //threadIdx.y + (blockIdx.y * blockDim.y);
    //threadIdx.z + (blockIdx.z * blockDim.z);

    // sometimes the grid is oversized statically for a problem that has an upper bound, though an instance may be smaller
    // so this guard is used in those cases
    // otherwise if the problem is the same size every time, the grid can be exactly sized, and the guard can be removed
    if (i < n)
    {
        c[i] = a[i] + b[i];
    }

    // barriers
    //__syncthreads(); all threads must hit this point before the kernel can finish
}

int main(void)
{
    // grids and blocks are topologically laid out similar to the problem
    // for 1D arrays, a grid size of (1,1,1) = 1D, and a block size of (N,1,1) = N, would be enough to fully cover the array
    const dim3 grid_size(1, 1, 1);
    const dim3 block_size(N, 1, 1);

    std::unique_ptr<float[]> h_a(new float[N]);
    std::unique_ptr<float[]> h_b(new float[N]);
    std::unique_ptr<float[]> h_c(new float[N]);

    std::size_t error_count = 0;

    float* d_a = NULL;
    float* d_b = NULL;
    float* d_c = NULL;

    cudaMalloc(&d_a, N * sizeof(h_a[0]));
    cudaMalloc(&d_b, N * sizeof(h_b[0]));
    cudaMalloc(&d_c, N * sizeof(h_c[0]));

    for (std::size_t i = 0; i < N; ++ i)
    {
        h_a[i] = 1;
        h_b[i] = 2;
    }

    // for the time being, this code does not work
    cudaMemcpy(d_a, h_a.get(), N * sizeof(h_a[0]), cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b.get(), N * sizeof(h_b[0]), cudaMemcpyHostToDevice);
    cudaMemset(d_c, 0, N * sizeof(h_c[0]));
    vec_add<<<grid_size, block_size>>>(d_c, d_a, d_b, N);

    cudaDeviceSynchronize(); // kernels are launched async, host immediately returns, so block until the computation is done

    // kernels are launched async from the host, but are scheduled serially per device
    // since this machine has a single GPU, they'd be scheduled sequentially, but the host would be operating async

    cudaMemcpy(h_c.get(), d_c, sizeof(h_c), cudaMemcpyDeviceToHost);

    for (std::size_t i = 0; i < N; ++ i)
    {
        //if ((3 * (i + 1)) != h_c[i])
        std::cout << h_c[i] << std::endl;
        if (3 != h_c[i])
        {
            //std::cout << i << std::endl;
            //++ error_count;
        }
    }

    std::cout << 100.0 * (static_cast<double>(error_count) / N) << "% mismatched" << std::endl << std::flush;

    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);
    return 0;
}


	.file	"tmpxft_0032d0fb_00000000-6_notes.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4303:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4303:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m
	.type	_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m, @function
_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m:
.LFB4325:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7vec_addPfPKfS1_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4325:
	.size	_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m, .-_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m
	.globl	_Z7vec_addPfPKfS1_m
	.type	_Z7vec_addPfPKfS1_m, @function
_Z7vec_addPfPKfS1_m:
.LFB4326:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m
	.cfi_endproc
.LFE4326:
	.size	_Z7vec_addPfPKfS1_m, .-_Z7vec_addPfPKfS1_m
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7vec_addPfPKfS1_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4328:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7vec_addPfPKfS1_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4328:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev,"axG",@progbits,_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED5Ev,comdat
	.align 2
	.weak	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev
	.type	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev, @function
_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev:
.LFB4640:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rdi
	testq	%rdi, %rdi
	je	.L10
	jmp	_ZdaPv@PLT
.L10:
	ret
	.cfi_endproc
.LFE4640:
	.size	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev, .-_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev
	.weak	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	.set	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev,_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev
	.section	.rodata.str1.1
.LC4:
	.string	"% mismatched"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4292:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4292
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4194304, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	addq	$1048575, %rax
	movq	%rax, 60(%rsp)
.LEHB0:
	call	_Znam@PLT
.LEHE0:
	movl	$4194304, %edi
	movq	%rax, (%rsp)
	movq	%rax, %r12
.LEHB1:
	call	_Znam@PLT
.LEHE1:
	movl	$4194304, %edi
	movq	%rax, 8(%rsp)
	movq	%rax, %rbp
.LEHB2:
	call	_Znam@PLT
.LEHE2:
	movq	%rax, 16(%rsp)
	movq	%rax, %rbx
	leaq	24(%rsp), %rdi
	xorl	%eax, %eax
	movl	$4194304, %esi
	movq	%rax, 24(%rsp)
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
.LEHB3:
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
	xorl	%eax, %eax
.L13:
	movss	%xmm1, (%r12,%rax,4)
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax
	jne	.L13
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$4194304, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$4194304, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$4194304, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L14
.L16:
	call	cudaDeviceSynchronize@PLT
	jmp	.L31
.L14:
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1048576, %ecx
	movq	40(%rsp), %rdi
	call	_Z33__device_stub__Z7vec_addPfPKfS1_mPfPKfS1_m
	jmp	.L16
.L31:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$8, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%ebp, %ebp
	leaq	_ZSt4cout(%rip), %r12
.L17:
	movq	%r12, %rdi
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	incq	%rbp
	cmpq	$1048576, %rbp
	jne	.L17
	xorps	%xmm0, %xmm0
	movq	%r12, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC4(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
.LEHE3:
	leaq	16(%rsp), %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	leaq	8(%rsp), %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	movq	%rsp, %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	jmp	.L29
.L25:
	endbr64
	movq	%rax, %rbx
.L18:
	leaq	16(%rsp), %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	jmp	.L19
.L24:
	endbr64
	movq	%rax, %rbx
.L19:
	leaq	8(%rsp), %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	jmp	.L20
.L23:
	endbr64
	movq	%rax, %rbx
.L20:
	movq	%rsp, %rdi
	call	_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED1Ev
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L29
	movq	%rbx, %rdi
.LEHB4:
	call	_Unwind_Resume@PLT
.LEHE4:
.L29:
	call	__stack_chk_fail@PLT
.L22:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4292:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4292:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4292-.LLSDACSB4292
.LLSDACSB4292:
	.uleb128 .LEHB0-.LFB4292
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB4292
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L23-.LFB4292
	.uleb128 0
	.uleb128 .LEHB2-.LFB4292
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L24-.LFB4292
	.uleb128 0
	.uleb128 .LEHB3-.LFB4292
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L25-.LFB4292
	.uleb128 0
	.uleb128 .LEHB4-.LFB4292
	.uleb128 .LEHE4-.LEHB4
	.uleb128 0
	.uleb128 0
.LLSDACSE4292:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	1073741824
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <unistd.h>
#include <memory>

const std::size_t N = 1 << 20;

__global__
void vec_add(float* const c, const float* const a, const float* const b, const std::size_t n)
{
    // shared memory spaces are block-scoped and for intra-thread communication, 10 was meaningless here
    //__shared__ int shared_memory[10];

    // grids have blocks, blocks have threads
    // thread indices are not unique within a grid, so unique-ify it using block information
    const std::size_t i = threadIdx.x + (blockIdx.x * blockDim.x);
    //threadIdx.y + (blockIdx.y * blockDim.y);
    //threadIdx.z + (blockIdx.z * blockDim.z);

    // sometimes the grid is oversized statically for a problem that has an upper bound, though an instance may be smaller
    // so this guard is used in those cases
    // otherwise if the problem is the same size every time, the grid can be exactly sized, and the guard can be removed
    if (i < n)
    {
        c[i] = a[i] + b[i];
    }

    // barriers
    //__syncthreads(); all threads must hit this point before the kernel can finish
}

int main(void)
{
    // grids and blocks are topologically laid out similar to the problem
    // for 1D arrays, a grid size of (1,1,1) = 1D, and a block size of (N,1,1) = N, would be enough to fully cover the array
    const dim3 grid_size(1, 1, 1);
    const dim3 block_size(N, 1, 1);

    std::unique_ptr<float[]> h_a(new float[N]);
    std::unique_ptr<float[]> h_b(new float[N]);
    std::unique_ptr<float[]> h_c(new float[N]);

    std::size_t error_count = 0;

    float* d_a = NULL;
    float* d_b = NULL;
    float* d_c = NULL;

    hipMalloc(&d_a, N * sizeof(h_a[0]));
    hipMalloc(&d_b, N * sizeof(h_b[0]));
    hipMalloc(&d_c, N * sizeof(h_c[0]));

    for (std::size_t i = 0; i < N; ++ i)
    {
        h_a[i] = 1;
        h_b[i] = 2;
    }

    // for the time being, this code does not work
    hipMemcpy(d_a, h_a.get(), N * sizeof(h_a[0]), hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b.get(), N * sizeof(h_b[0]), hipMemcpyHostToDevice);
    hipMemset(d_c, 0, N * sizeof(h_c[0]));
    vec_add<<<grid_size, block_size>>>(d_c, d_a, d_b, N);

    hipDeviceSynchronize(); // kernels are launched async, host immediately returns, so block until the computation is done

    // kernels are launched async from the host, but are scheduled serially per device
    // since this machine has a single GPU, they'd be scheduled sequentially, but the host would be operating async

    hipMemcpy(h_c.get(), d_c, sizeof(h_c), hipMemcpyDeviceToHost);

    for (std::size_t i = 0; i < N; ++ i)
    {
        //if ((3 * (i + 1)) != h_c[i])
        std::cout << h_c[i] << std::endl;
        if (3 != h_c[i])
        {
            //std::cout << i << std::endl;
            //++ error_count;
        }
    }

    std::cout << 100.0 * (static_cast<double>(error_count) / N) << "% mismatched" << std::endl << std::flush;

    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);
    return 0;
}


	.text
	.file	"notes.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__vec_addPfPKfS1_m # -- Begin function _Z22__device_stub__vec_addPfPKfS1_m
	.type	_Z22__device_stub__vec_addPfPKfS1_m,@function
_Z22__device_stub__vec_addPfPKfS1_m:    # @_Z22__device_stub__vec_addPfPKfS1_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7vec_addPfPKfS1_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__vec_addPfPKfS1_m, .Lfunc_end0-_Z22__device_stub__vec_addPfPKfS1_m
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
.Ltmp0:
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
.Ltmp1:
# %bb.1:
.Ltmp3:
	movq	%rax, %r14
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
.Ltmp4:
# %bb.2:
	movq	%rax, %r15
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	movq	%rax, (%rdi)
	movq	%rax, 16(%rsp)
	movq	%rax, 8(%rsp)
.Ltmp6:
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
.Ltmp7:
# %bb.3:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp8:
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
.Ltmp9:
# %bb.4:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit25
.Ltmp10:
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
.Ltmp11:
# %bb.5:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit26.preheader
	xorl	%eax, %eax
.LBB1_6:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit26
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax,4)      # imm = 0x3F800000
	movl	$1073741824, (%r14,%rax,4)      # imm = 0x40000000
	incq	%rax
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB1_6
# %bb.7:
	movq	24(%rsp), %rdi
.Ltmp12:
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp13:
# %bb.8:
	movq	16(%rsp), %rdi
.Ltmp14:
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp15:
# %bb.9:
	movq	8(%rsp), %rdi
.Ltmp16:
	movl	$4194304, %edx                  # imm = 0x400000
	xorl	%esi, %esi
	callq	hipMemset
.Ltmp17:
# %bb.10:
.Ltmp18:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$4296015872, %rdx               # imm = 0x100100000
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp19:
# %bb.11:
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
.Ltmp20:
	movl	$1048576, %ecx                  # imm = 0x100000
	callq	_Z22__device_stub__vec_addPfPKfS1_m
.Ltmp21:
.LBB1_13:
.Ltmp22:
	callq	hipDeviceSynchronize
.Ltmp23:
# %bb.14:
	movq	8(%rsp), %rsi
.Ltmp24:
	movl	$8, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp25:
# %bb.15:                               # %.preheader.preheader
	xorl	%r13d, %r13d
.LBB1_16:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r13,4), %xmm0
.Ltmp26:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.17:                               # %_ZNSolsEf.exit
                                        #   in Loop: Header=BB1_16 Depth=1
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
.Ltmp28:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp29:
# %bb.18:                               # %.noexc
                                        #   in Loop: Header=BB1_16 Depth=1
.Ltmp30:
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
.Ltmp31:
# %bb.19:                               # %.noexc44
                                        #   in Loop: Header=BB1_16 Depth=1
.Ltmp32:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp33:
# %bb.20:                               # %_ZNSolsEPFRSoS_E.exit
                                        #   in Loop: Header=BB1_16 Depth=1
	incq	%r13
	cmpq	$1048576, %r13                  # imm = 0x100000
	jne	.LBB1_16
# %bb.21:
.Ltmp35:
	movl	$_ZSt4cout, %edi
	xorps	%xmm0, %xmm0
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp36:
# %bb.22:                               # %_ZNSolsEd.exit
.Ltmp37:
	movq	%rax, %r12
	movl	$.L.str, %esi
	movl	$12, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.23:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	(%r12), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
.Ltmp39:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp40:
# %bb.24:                               # %.noexc46
.Ltmp41:
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
.Ltmp42:
# %bb.25:                               # %.noexc47
.Ltmp43:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp44:
# %bb.26:                               # %_ZNSolsEPFRSoS_E.exit27
.Ltmp45:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp46:
# %bb.27:                               # %_ZNSolsEPFRSoS_E.exit28
	movq	24(%rsp), %rdi
.Ltmp47:
	callq	hipFree
.Ltmp48:
# %bb.28:
	movq	16(%rsp), %rdi
.Ltmp49:
	callq	hipFree
.Ltmp50:
# %bb.29:
	movq	8(%rsp), %rdi
.Ltmp51:
	callq	hipFree
.Ltmp52:
# %bb.30:                               # %_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev.exit34
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%rbx, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_32:
	.cfi_def_cfa_offset 80
.Ltmp5:
	movq	%rax, %r12
	jmp	.LBB1_35
.LBB1_31:
.Ltmp2:
	movq	%rax, %r12
	jmp	.LBB1_36
.LBB1_33:
.Ltmp53:
	jmp	.LBB1_34
.LBB1_37:
.Ltmp34:
.LBB1_34:                               # %_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev.exit37
	movq	%rax, %r12
	movq	%r15, %rdi
	callq	_ZdaPv
.LBB1_35:                               # %_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev.exit40
	movq	%r14, %rdi
	callq	_ZdaPv
.LBB1_36:                               # %_ZNSt10unique_ptrIA_fSt14default_deleteIS0_EED2Ev.exit43
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp25-.Ltmp6                 #   Call between .Ltmp6 and .Ltmp25
	.uleb128 .Ltmp53-.Lfunc_begin0          #     jumps to .Ltmp53
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp26-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Ltmp33-.Ltmp26                #   Call between .Ltmp26 and .Ltmp33
	.uleb128 .Ltmp34-.Lfunc_begin0          #     jumps to .Ltmp34
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp35-.Lfunc_begin0          # >> Call Site 6 <<
	.uleb128 .Ltmp52-.Ltmp35                #   Call between .Ltmp35 and .Ltmp52
	.uleb128 .Ltmp53-.Lfunc_begin0          #     jumps to .Ltmp53
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp52-.Lfunc_begin0          # >> Call Site 7 <<
	.uleb128 .Lfunc_end1-.Ltmp52            #   Call between .Ltmp52 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7vec_addPfPKfS1_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7vec_addPfPKfS1_m,@object     # @_Z7vec_addPfPKfS1_m
	.section	.rodata,"a",@progbits
	.globl	_Z7vec_addPfPKfS1_m
	.p2align	3, 0x0
_Z7vec_addPfPKfS1_m:
	.quad	_Z22__device_stub__vec_addPfPKfS1_m
	.size	_Z7vec_addPfPKfS1_m, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"% mismatched"
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7vec_addPfPKfS1_m"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__vec_addPfPKfS1_m
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z7vec_addPfPKfS1_m
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7vec_addPfPKfS1_m     ; -- Begin function _Z7vec_addPfPKfS1_m
	.globl	_Z7vec_addPfPKfS1_m
	.p2align	8
	.type	_Z7vec_addPfPKfS1_m,@function
_Z7vec_addPfPKfS1_m:                    ; @_Z7vec_addPfPKfS1_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[1:2]
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7vec_addPfPKfS1_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7vec_addPfPKfS1_m, .Lfunc_end0-_Z7vec_addPfPKfS1_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 152
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7vec_addPfPKfS1_m
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7vec_addPfPKfS1_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
