/*************************************************************************************************
 * File: matrixmath.cu
 * Date: 11/06/2018
 * 
 * Compiling: Requires a Nvidia CUDA capable graphics card and the Nvidia GPU Computing Toolkit.
 *            Linux & Windows: nvcc -Wno-deprecated-gpu-targets -O3 -o prog2 matrixmath.cu
 *          
 * Usage:   Linux: >> prog2
 *          Windows: PS > ./prog2.exe
 * 
 * Description: This file runs a parallel program using CUDA to find the sum of squares. The first 
 *      part of the program asks whether you would like to run the optimized completely parallel 
 *      solution or an equivalent sequential solution. Both solutions use CUDA, but 1 is optimized 
 *      to be ran on many cores using atomic addition while the other runs the entire calculation 
 *      on a single pass-through, similar to how a sequential CPU program would run. Once the type 
 *      of kernel to run has been decided the user is asked how large they would like the sum of 
 *      squares to calculate. This calculation is done by creating an NxN matrix and a N sized vector.
 *      The matrix (A) and the vector (B) create a new vector C that satisfies the following formula:
 *      C[i] += A[i][j] * B[j]
 *
 *************************************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#include <fstream>

#define GRIDVAL 20.0

/**
 * __global__ void matrixSum(int, int, int, int, int)
 * - Function is a __global__ function meaning it is accessible for GPGPU processing.
 *   The function takes in a NxN matrix as *a, and a N length vector *b and an empty 
 *   N length vector *c along with the N value (both l and w are N in this case). The
 *   function calculates c[x] += a[x][y] * b[y] and performs an atomicAdd function when
 *   adding into c[x]. This function is meant to be highly parallelized.
 **/
__global__ void matrixSum(int *a, int *b, int *c, int l, int w) {
    // grab x position on grid
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    // grab y position on grid
    int y = threadIdx.y + blockIdx.y * blockDim.y;
    // safety check + math run
    if( x >= 0 && y >= 0 && x < w && y < l) {
        // perform c[x] += a[y][x] * b[y] using an atomic add
        atomicAdd(&c[x], a[(x*w)+y] * b[y]);
    }
}

/**
 * __global__ void singleSum(int, int, int ,int ,int)
 * - Function is a __global__ function meaning it is accessible for GPGPU processing.
 *   The function takes in a NxN matrix as *a, and a N length vector *b and an empty
 *   N length vector *c along with the N value (both l and w are N in this case). The
 *   function loops through each y value and each x value calculating 
 *   c[x] += a[x][y] * b[y]. The function is meant to run on a single CUDA core and is
 *   meant to represent a sequential run of the matrixSum function
 **/
__global__ void singleSum(int *a, int *b, int *c, int l, int w) {
    // loop through all y values
    for(int i = 0; i < w; i++) {
        // loop through all x values
        for(int j = 0; j < l; j++) {
            // perform c[i] += a[y][x] * b[x]
            c[i] += a[(i*w)+j]*b[j];
        }
    }
}

/**
 * int main(int, char*[])
 * - Function is the entry point for the program. Welcomes the user, then asks the user 
 *   whether they want to run a sequential or parallel calculation for the sum of squares.
 *   Once a selection is made the program asks the user for the max square to use (also 
 *   known as the size N for the NxN matrix and N length vectors). When both these values
 *   have been entered then the NxN matrix and N length vectors are allocated and initialized
 *   with their starting values, the function then calls the external __global__ function 
 *   with the appropriate grid/block set-up and returns the result out.
 */
int main(int argc, char* argv[]) {

    // declare a size variable and a sequential flag
    int size, sequential;

    // give a hello prompt and prompt for either sequential or parallel
    std::cout << "Sum of Squares using CUDA." << std::endl;
    std::cout << "Enter 1 for Sequential calculation or enter 0 for Parallel calculation: ";
    std::cin >> sequential;
    
    // let the user know the selection they just made
    if (sequential == 1) 
        std::cout << "SEQUENTIAL calculation is ON." << std::endl << std::endl;
    else 
        std::cout << "PARALLEL calculation is ON." << std::endl << std::endl;
    
    // prompt user for N value of the matrix and vector
    std::cout << "Enter in the maximum square to calculate: ";
    std::cin >> size;

    // prepare a NxN matrix, and two N length vectors and populate them with valid data
    int *a = new int[size*size];
    int *b = new int[size];
    int *c = new int[size];
    for(int i = 0; i < size; i++) {
        for(int j = 0; j < size; j++) {
            a[(i*size)+j] = j+1;
        }
        b[i] = i+1;
        c[i] = 0;
    }

    // declare 3 variables that will be used on the GPU
    int *gpu_a, *gpu_b, *gpu_c;

    // allocate space on the GPU for the incoming matrix and vectors
    cudaMalloc( (void**)&gpu_a, (size * size)*sizeof(int));
    cudaMalloc( (void**)&gpu_b, (size)*sizeof(int));
    cudaMalloc( (void**)&gpu_c, (size)*sizeof(int));

    // copy all the matrix and vector data to the GPU, set gpu_c to be all 0s
    cudaMemcpy(gpu_a, a, size*size*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(gpu_b, b, size*sizeof(int), cudaMemcpyHostToDevice);
    cudaMemset(gpu_c, 0, size*sizeof(int));

    // create a dim3 go find the number of blocks and number of threads per block given the user's input size
    // and the staticly defined GRIDVAL variable
    dim3 threadsPerBlock(GRIDVAL, GRIDVAL, 1);
    dim3 numBlocks(ceil(size/GRIDVAL), ceil(size/GRIDVAL), 1);

    // if we are running the sequential program, run the singleSum function with 1 block and 1 thread
    if (sequential == 1) 
        singleSum<<<1, 1>>>(gpu_a, gpu_b, gpu_c, size, size);
    // if w are running the parallel program, run the matrixSum function with the previously calculated num of blocks & threads
    else
        matrixSum<<<numBlocks, threadsPerBlock>>>(gpu_a, gpu_b, gpu_c, size, size);
    
    // copy the results from the GPGPU computation back to the CPU
    cudaMemcpy(c, gpu_c, size*sizeof(int), cudaMemcpyDeviceToHost);

    // output the result of C
    printf("Resulting values of the vector C:\n");
    for(int i = 0; i < size; i++) {
        printf("%d | ", c[i]);
    }
    printf("\n");

    //return a 0 for successful program run.
    return 0;
}

	.file	"tmpxft_0025d6d1_00000000-6_matrixmath.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3769:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3769:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii
	.type	_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii, @function
_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii:
.LFB3791:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9matrixSumPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3791:
	.size	_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii, .-_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii
	.globl	_Z9matrixSumPiS_S_ii
	.type	_Z9matrixSumPiS_S_ii, @function
_Z9matrixSumPiS_S_ii:
.LFB3792:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3792:
	.size	_Z9matrixSumPiS_S_ii, .-_Z9matrixSumPiS_S_ii
	.globl	_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii
	.type	_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii, @function
_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii:
.LFB3793:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9singleSumPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3793:
	.size	_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii, .-_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii
	.globl	_Z9singleSumPiS_S_ii
	.type	_Z9singleSumPiS_S_ii, @function
_Z9singleSumPiS_S_ii:
.LFB3794:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3794:
	.size	_Z9singleSumPiS_S_ii, .-_Z9singleSumPiS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Sum of Squares using CUDA."
.LC1:
	.string	"Enter 1 for Sequential calculation or enter 0 for Parallel calculation: "
.LC2:
	.string	"SEQUENTIAL calculation is ON."
.LC3:
	.string	"PARALLEL calculation is ON."
.LC4:
	.string	"Enter in the maximum square to calculate: "
.LC6:
	.string	"Resulting values of the vector C:\n"
.LC7:
	.string	"%d | "
.LC8:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3766:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	leaq	_ZSt3cin(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	_ZSt4cout(%rip), %rbx
	movq	%rbx, %rdi
	subq	$96, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	12(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	cmpl	$1, 12(%rsp)
	leaq	.LC2(%rip), %rsi
	je	.L30
	leaq	.LC3(%rip), %rsi
.L30:
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	%rbx, %rdi
	leaq	.LC4(%rip), %rsi
	movabsq	$2305843009213693950, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	8(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	movl	8(%rsp), %edi
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	8(%rsp), %rdi
	movq	%rax, %r12
	cmpq	%rdi, %rbx
	jb	.L16
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	8(%rsp), %rdi
	movq	%rax, %rbp
	cmpq	%rdi, %rbx
	jnb	.L17
.L16:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L31
	call	__cxa_throw_bad_array_new_length@PLT
.L17:
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	8(%rsp), %rdi
	movq	%r12, %rcx
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rdi, %rsi
	salq	$2, %rdi
.L19:
	cmpl	%eax, %esi
	jle	.L32
	movq	%rcx, %r8
	xorl	%edx, %edx
.L20:
	incl	%edx
	addq	$4, %r8
	movl	%edx, -4(%r8)
	cmpl	%esi, %edx
	jne	.L20
	leal	1(%rax), %edx
	addq	%rdi, %rcx
	movl	%edx, 0(%rbp,%rax,4)
	xorl	%edx, %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	jmp	.L19
.L32:
	imull	%esi, %esi
	leaq	16(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rsi
	leaq	24(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	8(%rsp), %edx
	movq	16(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	imull	%edx, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	8(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	8(%rsp), %rdx
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	salq	$2, %rdx
	call	cudaMemset@PLT
	cvtsi2sdl	8(%rsp), %xmm0
	divsd	.LC5(%rip), %xmm0
	call	ceil@PLT
	cmpl	$1, 12(%rsp)
	cvttsd2siq	%xmm0, %rax
	movl	%eax, 52(%rsp)
	movl	%eax, 56(%rsp)
	jne	.L21
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	8(%rsp), %ecx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%ecx, %r8d
	call	_Z34__device_stub__Z9singleSumPiS_S_iiPiS_S_ii
	jmp	.L23
.L21:
	movq	52(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$85899345940, %rdx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	8(%rsp), %ecx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%ecx, %r8d
	call	_Z34__device_stub__Z9matrixSumPiS_S_iiPiS_S_ii
.L23:
	movslq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%ebp, %ebp
	movl	$2, %ecx
	leaq	.LC7(%rip), %r12
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L24:
	cmpl	%ebp, 8(%rsp)
	jle	.L33
	movl	(%rbx,%rbp,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	jmp	.L24
.L33:
	xorl	%eax, %eax
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
.L31:
	call	__stack_chk_fail@PLT
.L26:
	addq	$96, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3766:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z9singleSumPiS_S_ii"
.LC10:
	.string	"_Z9matrixSumPiS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3796:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9singleSumPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9matrixSumPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3796:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	0
	.long	1077149696
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*************************************************************************************************
 * File: matrixmath.cu
 * Date: 11/06/2018
 * 
 * Compiling: Requires a Nvidia CUDA capable graphics card and the Nvidia GPU Computing Toolkit.
 *            Linux & Windows: nvcc -Wno-deprecated-gpu-targets -O3 -o prog2 matrixmath.cu
 *          
 * Usage:   Linux: >> prog2
 *          Windows: PS > ./prog2.exe
 * 
 * Description: This file runs a parallel program using CUDA to find the sum of squares. The first 
 *      part of the program asks whether you would like to run the optimized completely parallel 
 *      solution or an equivalent sequential solution. Both solutions use CUDA, but 1 is optimized 
 *      to be ran on many cores using atomic addition while the other runs the entire calculation 
 *      on a single pass-through, similar to how a sequential CPU program would run. Once the type 
 *      of kernel to run has been decided the user is asked how large they would like the sum of 
 *      squares to calculate. This calculation is done by creating an NxN matrix and a N sized vector.
 *      The matrix (A) and the vector (B) create a new vector C that satisfies the following formula:
 *      C[i] += A[i][j] * B[j]
 *
 *************************************************************************************************/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
#include <fstream>

#define GRIDVAL 20.0

/**
 * __global__ void matrixSum(int, int, int, int, int)
 * - Function is a __global__ function meaning it is accessible for GPGPU processing.
 *   The function takes in a NxN matrix as *a, and a N length vector *b and an empty 
 *   N length vector *c along with the N value (both l and w are N in this case). The
 *   function calculates c[x] += a[x][y] * b[y] and performs an atomicAdd function when
 *   adding into c[x]. This function is meant to be highly parallelized.
 **/
__global__ void matrixSum(int *a, int *b, int *c, int l, int w) {
    // grab x position on grid
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    // grab y position on grid
    int y = threadIdx.y + blockIdx.y * blockDim.y;
    // safety check + math run
    if( x >= 0 && y >= 0 && x < w && y < l) {
        // perform c[x] += a[y][x] * b[y] using an atomic add
        atomicAdd(&c[x], a[(x*w)+y] * b[y]);
    }
}

/**
 * __global__ void singleSum(int, int, int ,int ,int)
 * - Function is a __global__ function meaning it is accessible for GPGPU processing.
 *   The function takes in a NxN matrix as *a, and a N length vector *b and an empty
 *   N length vector *c along with the N value (both l and w are N in this case). The
 *   function loops through each y value and each x value calculating 
 *   c[x] += a[x][y] * b[y]. The function is meant to run on a single CUDA core and is
 *   meant to represent a sequential run of the matrixSum function
 **/
__global__ void singleSum(int *a, int *b, int *c, int l, int w) {
    // loop through all y values
    for(int i = 0; i < w; i++) {
        // loop through all x values
        for(int j = 0; j < l; j++) {
            // perform c[i] += a[y][x] * b[x]
            c[i] += a[(i*w)+j]*b[j];
        }
    }
}

/**
 * int main(int, char*[])
 * - Function is the entry point for the program. Welcomes the user, then asks the user 
 *   whether they want to run a sequential or parallel calculation for the sum of squares.
 *   Once a selection is made the program asks the user for the max square to use (also 
 *   known as the size N for the NxN matrix and N length vectors). When both these values
 *   have been entered then the NxN matrix and N length vectors are allocated and initialized
 *   with their starting values, the function then calls the external __global__ function 
 *   with the appropriate grid/block set-up and returns the result out.
 */
int main(int argc, char* argv[]) {

    // declare a size variable and a sequential flag
    int size, sequential;

    // give a hello prompt and prompt for either sequential or parallel
    std::cout << "Sum of Squares using CUDA." << std::endl;
    std::cout << "Enter 1 for Sequential calculation or enter 0 for Parallel calculation: ";
    std::cin >> sequential;
    
    // let the user know the selection they just made
    if (sequential == 1) 
        std::cout << "SEQUENTIAL calculation is ON." << std::endl << std::endl;
    else 
        std::cout << "PARALLEL calculation is ON." << std::endl << std::endl;
    
    // prompt user for N value of the matrix and vector
    std::cout << "Enter in the maximum square to calculate: ";
    std::cin >> size;

    // prepare a NxN matrix, and two N length vectors and populate them with valid data
    int *a = new int[size*size];
    int *b = new int[size];
    int *c = new int[size];
    for(int i = 0; i < size; i++) {
        for(int j = 0; j < size; j++) {
            a[(i*size)+j] = j+1;
        }
        b[i] = i+1;
        c[i] = 0;
    }

    // declare 3 variables that will be used on the GPU
    int *gpu_a, *gpu_b, *gpu_c;

    // allocate space on the GPU for the incoming matrix and vectors
    hipMalloc( (void**)&gpu_a, (size * size)*sizeof(int));
    hipMalloc( (void**)&gpu_b, (size)*sizeof(int));
    hipMalloc( (void**)&gpu_c, (size)*sizeof(int));

    // copy all the matrix and vector data to the GPU, set gpu_c to be all 0s
    hipMemcpy(gpu_a, a, size*size*sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(gpu_b, b, size*sizeof(int), hipMemcpyHostToDevice);
    hipMemset(gpu_c, 0, size*sizeof(int));

    // create a dim3 go find the number of blocks and number of threads per block given the user's input size
    // and the staticly defined GRIDVAL variable
    dim3 threadsPerBlock(GRIDVAL, GRIDVAL, 1);
    dim3 numBlocks(ceil(size/GRIDVAL), ceil(size/GRIDVAL), 1);

    // if we are running the sequential program, run the singleSum function with 1 block and 1 thread
    if (sequential == 1) 
        singleSum<<<1, 1>>>(gpu_a, gpu_b, gpu_c, size, size);
    // if w are running the parallel program, run the matrixSum function with the previously calculated num of blocks & threads
    else
        matrixSum<<<numBlocks, threadsPerBlock>>>(gpu_a, gpu_b, gpu_c, size, size);
    
    // copy the results from the GPGPU computation back to the CPU
    hipMemcpy(c, gpu_c, size*sizeof(int), hipMemcpyDeviceToHost);

    // output the result of C
    printf("Resulting values of the vector C:\n");
    for(int i = 0; i < size; i++) {
        printf("%d | ", c[i]);
    }
    printf("\n");

    //return a 0 for successful program run.
    return 0;
}

	.text
	.file	"matrixmath.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__matrixSumPiS_S_ii # -- Begin function _Z24__device_stub__matrixSumPiS_S_ii
	.type	_Z24__device_stub__matrixSumPiS_S_ii,@function
_Z24__device_stub__matrixSumPiS_S_ii:   # @_Z24__device_stub__matrixSumPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9matrixSumPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__matrixSumPiS_S_ii, .Lfunc_end0-_Z24__device_stub__matrixSumPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__singleSumPiS_S_ii # -- Begin function _Z24__device_stub__singleSumPiS_S_ii
	.type	_Z24__device_stub__singleSumPiS_S_ii,@function
_Z24__device_stub__singleSumPiS_S_ii:   # @_Z24__device_stub__singleSumPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9singleSumPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__singleSumPiS_S_ii, .Lfunc_end1-_Z24__device_stub__singleSumPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x4034000000000000              # double 20
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$72, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	20(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZNSirsERi
	cmpl	$1, (%rbx)
	jne	.LBB2_2
# %bb.1:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$29, %edx
	jmp	.LBB2_3
.LBB2_2:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$27, %edx
.LBB2_3:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$42, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	4(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZNSirsERi
	movslq	(%rbx), %r13
	movl	%r13d, %r12d
	imull	%r12d, %r12d
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r15
	leaq	(,%r13,4), %rax
	testq	%r13, %r13
	movq	$-1, %rbx
	cmovnsq	%rax, %rbx
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %r14
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %rbx
	testq	%r13, %r13
	jle	.LBB2_8
# %bb.4:                                # %.preheader.lr.ph
	movl	%r13d, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB2_5:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movl	%ecx, %esi
	leaq	(%r15,%rsi,4), %rsi
	xorl	%edi, %edi
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	1(%rdi), %r8
	movl	%r8d, (%rsi,%rdi,4)
	movq	%r8, %rdi
	cmpq	%r8, %rax
	jne	.LBB2_6
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB2_5 Depth=1
	leaq	1(%rdx), %rsi
	movl	%esi, (%r14,%rdx,4)
	movl	$0, (%rbx,%rdx,4)
	addl	%eax, %ecx
	movq	%rsi, %rdx
	cmpq	%rax, %rsi
	jne	.LBB2_5
.LBB2_8:                                # %._crit_edge42
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movslq	4(%rsp), %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipMalloc
	movslq	4(%rsp), %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	4(%rsp), %edx
	imull	%edx, %edx
	shlq	$2, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movslq	4(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movslq	4(%rsp), %rdx
	shlq	$2, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	cmpl	$1, 20(%rsp)
	jne	.LBB2_11
# %bb.9:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.10:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	%ecx, %r8d
	callq	_Z24__device_stub__singleSumPiS_S_ii
	jmp	.LBB2_13
.LBB2_11:
	cvtsi2sdl	4(%rsp), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rdi
	movl	%edi, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$85899345940, %rdx              # imm = 0x1400000014
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.12:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	%ecx, %r8d
	callq	_Z24__device_stub__matrixSumPiS_S_ii
.LBB2_13:
	movq	8(%rsp), %rsi
	movslq	4(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	cmpl	$0, 4(%rsp)
	jle	.LBB2_16
# %bb.14:                               # %.lr.ph45.preheader
	xorl	%r14d, %r14d
.LBB2_15:                               # %.lr.ph45
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	movslq	4(%rsp), %rax
	cmpq	%rax, %r14
	jl	.LBB2_15
.LBB2_16:                               # %._crit_edge46
	movl	$10, %edi
	callq	putchar@PLT
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9matrixSumPiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9singleSumPiS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9matrixSumPiS_S_ii,@object    # @_Z9matrixSumPiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9matrixSumPiS_S_ii
	.p2align	3, 0x0
_Z9matrixSumPiS_S_ii:
	.quad	_Z24__device_stub__matrixSumPiS_S_ii
	.size	_Z9matrixSumPiS_S_ii, 8

	.type	_Z9singleSumPiS_S_ii,@object    # @_Z9singleSumPiS_S_ii
	.globl	_Z9singleSumPiS_S_ii
	.p2align	3, 0x0
_Z9singleSumPiS_S_ii:
	.quad	_Z24__device_stub__singleSumPiS_S_ii
	.size	_Z9singleSumPiS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Sum of Squares using CUDA."
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Enter 1 for Sequential calculation or enter 0 for Parallel calculation: "
	.size	.L.str.1, 73

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"SEQUENTIAL calculation is ON."
	.size	.L.str.2, 30

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"PARALLEL calculation is ON."
	.size	.L.str.3, 28

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Enter in the maximum square to calculate: "
	.size	.L.str.4, 43

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%d | "
	.size	.L.str.6, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9matrixSumPiS_S_ii"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9singleSumPiS_S_ii"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Resulting values of the vector C:"
	.size	.Lstr, 34

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__matrixSumPiS_S_ii
	.addrsig_sym _Z24__device_stub__singleSumPiS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9matrixSumPiS_S_ii
	.addrsig_sym _Z9singleSumPiS_S_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9matrixSumPiS_S_ii    ; -- Begin function _Z9matrixSumPiS_S_ii
	.globl	_Z9matrixSumPiS_S_ii
	.p2align	8
	.type	_Z9matrixSumPiS_S_ii,@function
_Z9matrixSumPiS_S_ii:                   ; @_Z9matrixSumPiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v1, v2, v0
	v_cmp_gt_i32_e64 s2, s4, v2
	v_cmp_lt_i32_e64 s3, -1, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mad_u64_u32 v[4:5], null, v0, s5, v[2:3]
	v_mov_b32_e32 v1, 0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v3, v1
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v2, v4
	global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9matrixSumPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9matrixSumPiS_S_ii, .Lfunc_end0-_Z9matrixSumPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9singleSumPiS_S_ii    ; -- Begin function _Z9singleSumPiS_S_ii
	.globl	_Z9singleSumPiS_S_ii
	.p2align	8
	.type	_Z9singleSumPiS_S_ii,@function
_Z9singleSumPiS_S_ii:                   ; @_Z9singleSumPiS_S_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB1_6
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s11, 0
	s_cselect_b32 s0, -1, 0
	s_mov_b32 s10, s11
	v_cndmask_b32_e64 v0, 0, 1, s0
	s_mov_b32 s12, s11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v0
	v_mov_b32_e32 v0, 0
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_lshl_b64 s[14:15], s[10:11], 2
	s_mov_b32 s13, s11
	s_waitcnt lgkmcnt(0)
	s_add_u32 s14, s4, s14
	s_addc_u32 s15, s5, s15
	s_lshl_b64 s[16:17], s[12:13], 2
	s_mov_b64 s[18:19], s[6:7]
	s_add_u32 s16, s8, s16
	s_addc_u32 s17, s9, s17
	s_mov_b32 s1, s2
	global_load_b32 v1, v0, s[16:17]
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b32 v2, v0, s[14:15]
	global_load_b32 v3, v0, s[18:19]
	s_add_i32 s1, s1, -1
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_add_u32 s18, s18, 4
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[16:17]
	s_cbranch_scc0 .LBB1_4
.LBB1_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s12, s12, 1
	s_add_i32 s10, s10, s3
	s_cmp_eq_u32 s12, s3
	s_cbranch_scc0 .LBB1_2
.LBB1_6:                                ; %._crit_edge20
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9singleSumPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9singleSumPiS_S_ii, .Lfunc_end1-_Z9singleSumPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 22
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9matrixSumPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9matrixSumPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9singleSumPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z9singleSumPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
