/******************************************************************************
 *cr
 *cr         (C) Copyright 2010-2013 The Board of Trustees of the
 *cr                        University of Illinois
 *cr                         All Rights Reserved
 *cr
 ******************************************************************************/

#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)

// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048

// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128

/******************************************************************************
 GPU kernels
*******************************************************************************/

__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
        nextLevelNodes[gq_idx] = neighbor;
      }
    }
  }
}

__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
  
  //setup block's shared queue
  __shared__ unsigned int s_nextLevelNodes[BQ_CAPACITY], s_numNextLevelNodes, s_start;

  if (threadIdx.x == 0) s_numNextLevelNodes = 0; //init block's numNExtLevelNodes
  __syncthreads();

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int bq_idx = atomicAdd(&s_numNextLevelNodes,1);
        if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
          s_nextLevelNodes[bq_idx] = neighbor;
        }else{//if not, put right into global queue
          s_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
          unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
          nextLevelNodes[gq_idx] = neighbor;
        }
      }
    }
  }
  __syncthreads();//wait for entire block to finish

  //update global numNextLevelNodes for other blocks to determine their start 
  if (threadIdx.x == 0){
    s_start = atomicAdd(numNextLevelNodes, s_numNextLevelNodes);
  }
  __syncthreads();

  for (unsigned int i = threadIdx.x; i < s_numNextLevelNodes; i += blockDim.x){
    nextLevelNodes[i+s_start] = s_nextLevelNodes[i];
  }
}



__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;

  //setup block's shared queue
  __shared__ unsigned int b_nextLevelNodes[BQ_CAPACITY], b_numNextLevelNodes, b_start;

  //setup warp queues

  unsigned int wqueue_idx = threadIdx.x % WARP_SIZE;
  __shared__ unsigned int w_nextLevelNodes[WQ_CAPACITY][WARP_SIZE];//allows for coalescing later
  __shared__ unsigned int w_numNextLevelNodes[WARP_SIZE], w_start[WARP_SIZE];

  //init block's numNextLevelNodes
  if (threadIdx.x == 0) b_numNextLevelNodes = 0; 
  //init each warp queue's numNextLevelNodes
  if (threadIdx.x < WARP_SIZE) {
    w_numNextLevelNodes[threadIdx.x] = 0; 
  } 
  __syncthreads();

  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment warp level numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int queue_idx = atomicAdd(&(w_numNextLevelNodes[wqueue_idx]),1);
        if(queue_idx < WQ_CAPACITY){//make sure there is room in this thread's warp queue
          w_nextLevelNodes[queue_idx][wqueue_idx] = neighbor;
        }else{//if not, fall back to block and global queues
          //increment block level numNextLevelNodes and use old value as index for this node's place in the queue
          w_numNextLevelNodes[wqueue_idx] = WQ_CAPACITY;//w_numNextLevelNodes[wqueue_idx] >= WQ_CAPACITY so reset to WQ_CAPACITY
          unsigned int bq_idx = atomicAdd(&b_numNextLevelNodes,1);
          if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
            b_nextLevelNodes[bq_idx] = neighbor;
          }else{//if not, put right into global queue
            b_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
            unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
            nextLevelNodes[gq_idx] = neighbor;
          }
        }
      }
    }
  }
  __syncthreads();//wait for entire block to finish

  //update block's numNextLevelNodes so other warps can determine their start
  unsigned int offset = threadIdx.x/WARP_SIZE;
  if (offset == 0){//only first thread in a warp 
    w_start[wqueue_idx] = atomicAdd(&b_numNextLevelNodes, w_numNextLevelNodes[wqueue_idx]);
  }
  __syncthreads();
  //let each thread in the warp move elements from warp queue to block queue in coalesced fashion
  for (unsigned int i = offset; i < w_numNextLevelNodes[wqueue_idx]; i += NUM_WARPS){
    unsigned int bq_idx = w_start[wqueue_idx] + i;
    if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
      b_nextLevelNodes[bq_idx] = w_nextLevelNodes[i][wqueue_idx];
    }else{//if not, put right into global queue
      b_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
      unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
      nextLevelNodes[gq_idx] = w_nextLevelNodes[i][wqueue_idx];
    }
  }
  __syncthreads();


  // //update global numNextLevelNodes for other blocks to determine their start 
  if (threadIdx.x == 0){
    b_start = atomicAdd(numNextLevelNodes, b_numNextLevelNodes);
  }
  __syncthreads();
  for (unsigned int i = threadIdx.x; i < b_numNextLevelNodes; i += blockDim.x){
    nextLevelNodes[i+b_start] = b_nextLevelNodes[i];
  }
}

/******************************************************************************
 Functions
*******************************************************************************/

void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  // Loop over all nodes in the curent level
  for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
    unsigned int node = currLevelNodes[idx];
    // Loop over all neighbors of the node113
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
      ++nbrIdx) {
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      // If the neighbor hasn't been visited yet
      if(!nodeVisited[neighbor]) {
        // Mark it and add it to the queue
        nodeVisited[neighbor] = 1;
        nextLevelNodes[*numNextLevelNodes] = neighbor;
        ++(*numNextLevelNodes);
      }
    }
  }

}

void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}

void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}

void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}


	.file	"tmpxft_003761cf_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11cpu_queuingPjS_S_S_S_S_S_
	.type	_Z11cpu_queuingPjS_S_S_S_S_S_, @function
_Z11cpu_queuingPjS_S_S_S_S_S_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r10
	xorl	%eax, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	32(%rsp), %r11
.L3:
	cmpl	(%r9), %eax
	jnb	.L10
	movl	%eax, %edx
	movl	(%rcx,%rdx,4), %edx
	movq	%rdx, %rbx
	movl	(%rdi,%rdx,4), %edx
	incl	%ebx
	leaq	(%rdi,%rbx,4), %r12
.L4:
	cmpl	(%r12), %edx
	jnb	.L11
	movl	%edx, %ebx
	movl	(%rsi,%rbx,4), %ebp
	movq	%rbp, %rbx
	leaq	(%r10,%rbp,4), %rbp
	cmpl	$0, 0(%rbp)
	jne	.L5
	movl	$1, 0(%rbp)
	movl	(%r11), %ebp
	movl	%ebx, (%r8,%rbp,4)
	incl	(%r11)
.L5:
	incl	%edx
	jmp	.L4
.L11:
	incl	%eax
	jmp	.L3
.L10:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z11cpu_queuingPjS_S_S_S_S_S_, .-_Z11cpu_queuingPjS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L12:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.globl	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, @function
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.cfi_endproc
.LFE2037:
	.size	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, .-_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z18gpu_global_queuingPjS_S_S_S_S_S_
	.type	_Z18gpu_global_queuingPjS_S_S_S_S_S_, @function
_Z18gpu_global_queuingPjS_S_S_S_S_S_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movq	%rsi, %rbp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	movq	112(%rsp), %rbx
	movabsq	$4294967341, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	%rbx, 112(%rsp)
	movq	8(%rsp), %rdi
	movq	%r15, %r9
	movq	%r14, %r8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z57__device_stub__Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.L17:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z18gpu_global_queuingPjS_S_S_S_S_S_, .-_Z18gpu_global_queuingPjS_S_S_S_S_S_
	.globl	_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.type	_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L20:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.globl	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, @function
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.cfi_endproc
.LFE2039:
	.size	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, .-_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z17gpu_block_queuingPjS_S_S_S_S_S_
	.type	_Z17gpu_block_queuingPjS_S_S_S_S_S_, @function
_Z17gpu_block_queuingPjS_S_S_S_S_S_:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movq	%rsi, %rbp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	movq	112(%rsp), %rbx
	movabsq	$4294967341, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	%rbx, 112(%rsp)
	movq	8(%rsp), %rdi
	movq	%r15, %r9
	movq	%r14, %r8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z56__device_stub__Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.L25:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_Z17gpu_block_queuingPjS_S_S_S_S_S_, .-_Z17gpu_block_queuingPjS_S_S_S_S_S_
	.globl	_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.type	_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, @function
_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L28:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_, .-_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.globl	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, @function
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
	.cfi_endproc
.LFE2041:
	.size	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .-_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z16gpu_warp_queuingPjS_S_S_S_S_S_
	.type	_Z16gpu_warp_queuingPjS_S_S_S_S_S_, @function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	movl	$8388609, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	salq	$9, %rdx
	movq	%rsi, %rbp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	movq	112(%rsp), %rbx
	movabsq	$4294967341, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	%rbx, 112(%rsp)
	movq	8(%rsp), %rdi
	movq	%r15, %r9
	movq	%r14, %r8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_PjS_S_S_S_S_S_
.L33:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	_Z16gpu_warp_queuingPjS_S_S_S_S_S_, .-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
.LC1:
	.string	"_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
.LC2:
	.string	"_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/******************************************************************************
 *cr
 *cr         (C) Copyright 2010-2013 The Board of Trustees of the
 *cr                        University of Illinois
 *cr                         All Rights Reserved
 *cr
 ******************************************************************************/

#define BLOCK_SIZE 512
#define WARP_SIZE 32
#define NUM_WARPS (BLOCK_SIZE/WARP_SIZE)

// Maximum number of elements that can be inserted into a block queue
#define BQ_CAPACITY 2048

// Maximum number of elements that can be inserted into a warp queue
#define WQ_CAPACITY 128

/******************************************************************************
 GPU kernels
*******************************************************************************/

__global__ void gpu_global_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
        nextLevelNodes[gq_idx] = neighbor;
      }
    }
  }
}

__global__ void gpu_block_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {
  
  //setup block's shared queue
  __shared__ unsigned int s_nextLevelNodes[BQ_CAPACITY], s_numNextLevelNodes, s_start;

  if (threadIdx.x == 0) s_numNextLevelNodes = 0; //init block's numNExtLevelNodes
  __syncthreads();

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int bq_idx = atomicAdd(&s_numNextLevelNodes,1);
        if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
          s_nextLevelNodes[bq_idx] = neighbor;
        }else{//if not, put right into global queue
          s_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
          unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
          nextLevelNodes[gq_idx] = neighbor;
        }
      }
    }
  }
  __syncthreads();//wait for entire block to finish

  //update global numNextLevelNodes for other blocks to determine their start 
  if (threadIdx.x == 0){
    s_start = atomicAdd(numNextLevelNodes, s_numNextLevelNodes);
  }
  __syncthreads();

  for (unsigned int i = threadIdx.x; i < s_numNextLevelNodes; i += blockDim.x){
    nextLevelNodes[i+s_start] = s_nextLevelNodes[i];
  }
}



__global__ void gpu_warp_queuing_kernel(unsigned int *nodePtrs,
  unsigned int *nodeNeighbors, unsigned int *nodeVisited,
  unsigned int *currLevelNodes, unsigned int *nextLevelNodes,
  unsigned int *numCurrLevelNodes, unsigned int *numNextLevelNodes) {

  // INSERT KERNEL CODE HERE
  unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;

  //setup block's shared queue
  __shared__ unsigned int b_nextLevelNodes[BQ_CAPACITY], b_numNextLevelNodes, b_start;

  //setup warp queues

  unsigned int wqueue_idx = threadIdx.x % WARP_SIZE;
  __shared__ unsigned int w_nextLevelNodes[WQ_CAPACITY][WARP_SIZE];//allows for coalescing later
  __shared__ unsigned int w_numNextLevelNodes[WARP_SIZE], w_start[WARP_SIZE];

  //init block's numNextLevelNodes
  if (threadIdx.x == 0) b_numNextLevelNodes = 0; 
  //init each warp queue's numNextLevelNodes
  if (threadIdx.x < WARP_SIZE) {
    w_numNextLevelNodes[threadIdx.x] = 0; 
  } 
  __syncthreads();

  //large number of nodes is too many for our threads so each thread may have to do more than one
  for (idx=idx; idx < *numCurrLevelNodes; idx += gridDim.x * blockDim.x){
    unsigned int node = currLevelNodes[idx];
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1]; ++nbrIdx) {
      //check if node was visited, if it wasn't, flag it as visited and update queue
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      unsigned int visited = atomicAdd(&(nodeVisited[neighbor]), 1); 
      if(!visited){
        //increment warp level numNextLevelNodes and use old value as index for this node's place in the queue
        unsigned int queue_idx = atomicAdd(&(w_numNextLevelNodes[wqueue_idx]),1);
        if(queue_idx < WQ_CAPACITY){//make sure there is room in this thread's warp queue
          w_nextLevelNodes[queue_idx][wqueue_idx] = neighbor;
        }else{//if not, fall back to block and global queues
          //increment block level numNextLevelNodes and use old value as index for this node's place in the queue
          w_numNextLevelNodes[wqueue_idx] = WQ_CAPACITY;//w_numNextLevelNodes[wqueue_idx] >= WQ_CAPACITY so reset to WQ_CAPACITY
          unsigned int bq_idx = atomicAdd(&b_numNextLevelNodes,1);
          if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
            b_nextLevelNodes[bq_idx] = neighbor;
          }else{//if not, put right into global queue
            b_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
            unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
            nextLevelNodes[gq_idx] = neighbor;
          }
        }
      }
    }
  }
  __syncthreads();//wait for entire block to finish

  //update block's numNextLevelNodes so other warps can determine their start
  unsigned int offset = threadIdx.x/WARP_SIZE;
  if (offset == 0){//only first thread in a warp 
    w_start[wqueue_idx] = atomicAdd(&b_numNextLevelNodes, w_numNextLevelNodes[wqueue_idx]);
  }
  __syncthreads();
  //let each thread in the warp move elements from warp queue to block queue in coalesced fashion
  for (unsigned int i = offset; i < w_numNextLevelNodes[wqueue_idx]; i += NUM_WARPS){
    unsigned int bq_idx = w_start[wqueue_idx] + i;
    if (bq_idx < BQ_CAPACITY){//make sure there is room in block queue
      b_nextLevelNodes[bq_idx] = w_nextLevelNodes[i][wqueue_idx];
    }else{//if not, put right into global queue
      b_numNextLevelNodes = BQ_CAPACITY;//s_numNextLevelNodes >= BQ_CAPACITY so reset to BQ_CAPACITY
      unsigned int gq_idx = atomicAdd(numNextLevelNodes,1);
      nextLevelNodes[gq_idx] = w_nextLevelNodes[i][wqueue_idx];
    }
  }
  __syncthreads();


  // //update global numNextLevelNodes for other blocks to determine their start 
  if (threadIdx.x == 0){
    b_start = atomicAdd(numNextLevelNodes, b_numNextLevelNodes);
  }
  __syncthreads();
  for (unsigned int i = threadIdx.x; i < b_numNextLevelNodes; i += blockDim.x){
    nextLevelNodes[i+b_start] = b_nextLevelNodes[i];
  }
}

/******************************************************************************
 Functions
*******************************************************************************/

void cpu_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  // Loop over all nodes in the curent level
  for(unsigned int idx = 0; idx < *numCurrLevelNodes; ++idx) {
    unsigned int node = currLevelNodes[idx];
    // Loop over all neighbors of the node113
    for(unsigned int nbrIdx = nodePtrs[node]; nbrIdx < nodePtrs[node + 1];
      ++nbrIdx) {
      unsigned int neighbor = nodeNeighbors[nbrIdx];
      // If the neighbor hasn't been visited yet
      if(!nodeVisited[neighbor]) {
        // Mark it and add it to the queue
        nodeVisited[neighbor] = 1;
        nextLevelNodes[*numNextLevelNodes] = neighbor;
        ++(*numNextLevelNodes);
      }
    }
  }

}

void gpu_global_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_global_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}

void gpu_block_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_block_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}

void gpu_warp_queuing(unsigned int *nodePtrs, unsigned int *nodeNeighbors,
  unsigned int *nodeVisited, unsigned int *currLevelNodes,
  unsigned int *nextLevelNodes, unsigned int *numCurrLevelNodes,
  unsigned int *numNextLevelNodes) {

  const unsigned int numBlocks = 45;
  gpu_warp_queuing_kernel <<< numBlocks , BLOCK_SIZE >>> (nodePtrs,
    nodeNeighbors, nodeVisited, currLevelNodes, nextLevelNodes,
    numCurrLevelNodes, numNextLevelNodes);

}


	.text
	.file	"kernel.hip"
	.globl	_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_,@function
_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_: # @_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end0-_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_,@function
_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_: # @_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end1-_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_ # -- Begin function _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.type	_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@function
_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_: # @_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end2-_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11cpu_queuingPjS_S_S_S_S_S_   # -- Begin function _Z11cpu_queuingPjS_S_S_S_S_S_
	.type	_Z11cpu_queuingPjS_S_S_S_S_S_,@function
_Z11cpu_queuingPjS_S_S_S_S_S_:          # @_Z11cpu_queuingPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	movl	(%r9), %r11d
	testl	%r11d, %r11d
	je	.LBB3_9
# %bb.1:                                # %.lr.ph24.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	40(%rsp), %rax
	xorl	%r10d, %r10d
.LBB3_2:                                # %.lr.ph24
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_3 Depth 2
	movl	(%rcx,%r10,4), %r14d
	movl	(%rdi,%r14,4), %ebx
	incl	%r14d
	movl	(%rdi,%r14,4), %ebp
	cmpl	%ebp, %ebx
	jae	.LBB3_7
.LBB3_3:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rsi,%rbx,4), %r11d
	cmpl	$0, (%rdx,%r11,4)
	jne	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_3 Depth=2
	movl	$1, (%rdx,%r11,4)
	movl	(%rax), %r15d
	movl	%r11d, (%r8,%r15,4)
	incl	(%rax)
	movl	(%rdi,%r14,4), %ebp
.LBB3_5:                                #   in Loop: Header=BB3_3 Depth=2
	incq	%rbx
	movl	%ebp, %r11d
	cmpq	%r11, %rbx
	jb	.LBB3_3
# %bb.6:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	(%r9), %r11d
.LBB3_7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%r10
	movl	%r11d, %ebx
	cmpq	%rbx, %r10
	jb	.LBB3_2
# %bb.8:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB3_9:                                # %._crit_edge25
	retq
.Lfunc_end3:
	.size	_Z11cpu_queuingPjS_S_S_S_S_S_, .Lfunc_end3-_Z11cpu_queuingPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18gpu_global_queuingPjS_S_S_S_S_S_ # -- Begin function _Z18gpu_global_queuingPjS_S_S_S_S_S_
	.type	_Z18gpu_global_queuingPjS_S_S_S_S_S_,@function
_Z18gpu_global_queuingPjS_S_S_S_S_S_:   # @_Z18gpu_global_queuingPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movabsq	$4294967341, %rdi               # imm = 0x10000002D
	leaq	467(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_ # TAILCALL
.Lfunc_end4:
	.size	_Z18gpu_global_queuingPjS_S_S_S_S_S_, .Lfunc_end4-_Z18gpu_global_queuingPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z17gpu_block_queuingPjS_S_S_S_S_S_ # -- Begin function _Z17gpu_block_queuingPjS_S_S_S_S_S_
	.type	_Z17gpu_block_queuingPjS_S_S_S_S_S_,@function
_Z17gpu_block_queuingPjS_S_S_S_S_S_:    # @_Z17gpu_block_queuingPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movabsq	$4294967341, %rdi               # imm = 0x10000002D
	leaq	467(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_ # TAILCALL
.Lfunc_end5:
	.size	_Z17gpu_block_queuingPjS_S_S_S_S_S_, .Lfunc_end5-_Z17gpu_block_queuingPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z16gpu_warp_queuingPjS_S_S_S_S_S_ # -- Begin function _Z16gpu_warp_queuingPjS_S_S_S_S_S_
	.type	_Z16gpu_warp_queuingPjS_S_S_S_S_S_,@function
_Z16gpu_warp_queuingPjS_S_S_S_S_S_:     # @_Z16gpu_warp_queuingPjS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movabsq	$4294967341, %rdi               # imm = 0x10000002D
	leaq	467(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_ # TAILCALL
.Lfunc_end6:
	.size	_Z16gpu_warp_queuingPjS_S_S_S_S_S_, .Lfunc_end6-_Z16gpu_warp_queuingPjS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_:
	.quad	_Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.size	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, 8

	.type	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.p2align	3, 0x0
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_:
	.quad	_Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.size	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, 8

	.type	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@object # @_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.p2align	3, 0x0
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_:
	.quad	_Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.size	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_"
	.size	.L__unnamed_1, 44

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_"
	.size	.L__unnamed_2, 43

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_"
	.size	.L__unnamed_3, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym _Z39__device_stub__gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym _Z38__device_stub__gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_ ; -- Begin function _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
	.p2align	8
	.type	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_,@function
_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_: ; @_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b32 s4, s[0:1], 0x44
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s21, s[18:19], 0x0
	s_and_b32 s20, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s20, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s21, v1
	s_cbranch_execz .LBB0_11
; %bb.1:                                ; %.lr.ph31
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[12:15], s[0:1], 0x30
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v0, 1
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s20
	s_mov_b32 s2, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v3
	s_mov_b32 s3, exec_lo
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_co_u32 v10, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[10:11], off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e64 v6, v2
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v7, v3
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[7:8], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	global_atomic_add_u32 v9, v[9:10], v0, off glc
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v9
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s20, exec_lo
	s_mov_b32 s15, exec_lo
	v_mbcnt_lo_u32_b32 v9, s20, 0
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v9
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v10, s20
	global_atomic_add_u32 v10, v3, v10, s[12:13] glc
.LBB0_7:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v10, v3 :: v_dual_add_nc_u32 v9, s15, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
	global_store_b32 v[9:10], v2, off
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v2, v[4:5], off
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v7, s0, v7, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_u32_e32 vcc_lo, v6, v2
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_4
; %bb.9:                                ; %._crit_edge.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b32 v7, v3, s[18:19]
.LBB0_10:                               ; %Flow54
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v1, s1, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v1, v7
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
.LBB0_11:                               ; %._crit_edge32
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end0-_Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 24
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_ ; -- Begin function _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
	.p2align	8
	.type	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_,@function
_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_: ; @_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
; %bb.0:
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mov_b32_e32 v1, 0
	ds_store_b32 v1, v1 offset:8192
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b256 s[4:11], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_mov_b32 s20, exec_lo
	s_load_b32 s2, s[0:1], 0x44
	s_load_b32 s21, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_cmpx_gt_u32_e64 s21, v1
	s_cbranch_execz .LBB1_18
; %bb.3:                                ; %.lr.ph42
	s_load_b32 s2, s[10:11], 0x0
	s_load_b256 s[12:19], s[0:1], 0x0
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v10, 0x800
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v9, 1
	s_mov_b32 s10, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s3
.LBB1_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	v_mov_b32_e32 v2, v3
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, s0, s18, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s19, v5, s0
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, s12, v4
	v_add_co_ci_u32_e64 v14, s0, s13, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s12, v11
	v_add_co_ci_u32_e64 v5, s0, s13, v12, s0
	s_clause 0x1
	global_load_b32 v6, v[13:14], off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e64 v6, v2
	s_cbranch_execz .LBB1_17
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	v_mov_b32_e32 v7, v3
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, s0, s14, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s15, v8, s0
.LBB1_6:                                ; %.lr.ph
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[7:8], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, s16, v11
	v_add_co_ci_u32_e64 v12, s0, s17, v12, s0
	global_atomic_add_u32 v11, v[11:12], v9, off glc
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB1_15
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	s_mov_b32 s23, exec_lo
	s_mov_b32 s22, exec_lo
	v_mbcnt_lo_u32_b32 v11, s23, 0
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB1_9
; %bb.8:                                ;   in Loop: Header=BB1_6 Depth=2
	s_bcnt1_i32_b32 s0, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s0
	ds_add_rtn_u32 v12, v3, v12 offset:8192
.LBB1_9:                                ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s0, v12
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, s0, v11
	v_cmpx_lt_u32_e32 0x7ff, v11
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB1_13
; %bb.10:                               ;   in Loop: Header=BB1_6 Depth=2
	s_mov_b32 s23, exec_lo
	s_mov_b32 s24, exec_lo
	v_mbcnt_lo_u32_b32 v11, s23, 0
	ds_store_b32 v3, v10 offset:8192
                                        ; implicit-def: $vgpr12
	v_cmpx_eq_u32_e32 0, v11
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_6 Depth=2
	s_bcnt1_i32_b32 s0, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s0
	global_atomic_add_u32 v12, v3, v12, s[8:9] glc
.LBB1_12:                               ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v12, v3 :: v_dual_add_nc_u32 v11, s0, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, s4, v11
	v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
	global_store_b32 v[11:12], v2, off
                                        ; implicit-def: $vgpr11
.LBB1_13:                               ; %Flow74
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_and_not1_saveexec_b32 s0, s22
	s_cbranch_execz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_6 Depth=2
	v_lshlrev_b32_e32 v11, 2, v11
	ds_store_b32 v11, v2
.LBB1_15:                               ; %Flow76
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v2, v[4:5], off
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v7, s1, v7, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s1, 0, v8, s1
	s_waitcnt vmcnt(0)
	v_cmp_ge_u32_e64 s0, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s21, s0, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB1_6
; %bb.16:                               ; %._crit_edge.loopexit
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	global_load_b32 v7, v3, s[6:7]
.LBB1_17:                               ; %Flow77
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v1, s2, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e64 s0, v1, v7
	s_or_b32 s10, s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_4
.LBB1_18:                               ; %Flow79
	s_or_b32 exec_lo, exec_lo, s20
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_22
; %bb.19:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v3, s1, 0
                                        ; implicit-def: $vgpr4
	ds_load_b32 v2, v1 offset:8192
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_21
; %bb.20:
	s_bcnt1_i32_b32 s1, s1
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v4, v2, s1
	global_atomic_add_u32 v4, v1, v4, s[8:9] glc
.LBB1_21:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v2, v3, s[2:3]
	ds_store_b32 v1, v4 offset:8196
.LBB1_22:                               ; %Flow73
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	ds_load_b32 v3, v2 offset:8192
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_u32_e64 v0, v3
	s_cbranch_execz .LBB1_25
; %bb.23:                               ; %.lr.ph46
	ds_load_b32 v4, v2 offset:8196
	v_lshlrev_b32_e32 v5, 2, v0
	s_lshl_b32 s1, s3, 2
	s_mov_b32 s2, 0
.LBB1_24:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v8, v5
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v1, v4, v0
	v_add_nc_u32_e32 v0, s3, v0
	v_add_nc_u32_e32 v5, s1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_cmp_ge_u32_e32 vcc_lo, v0, v3
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s4, v6
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[6:7], v8, off
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_24
.LBB1_25:                               ; %Flow72
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 8200
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end1-_Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1048
; NumSgprs: 27
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8200 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_ ; -- Begin function _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.globl	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
	.p2align	8
	.type	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_,@function
_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_: ; @_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
; %bb.0:
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mov_b32_e32 v1, 0
	ds_store_b32 v1, v1 offset:24832
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b32 s3, s[0:1], 0x44
	v_cmp_gt_u32_e64 s2, 32, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
	ds_store_b32 v1, v2 offset:24576
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b256 s[4:11], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s10, 0xffff, s3
	s_mov_b32 s11, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
	v_and_b32_e32 v2, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 2, v2
	s_load_b32 s20, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s20, v1
	s_cbranch_execz .LBB2_24
; %bb.5:                                ; %.lr.ph69
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x38
	s_load_b256 s[12:19], s[0:1], 0x0
	v_lshl_or_b32 v10, v2, 2, 0x6000
	v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v12, 0x80
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v11, 1
	v_mov_b32_e32 v13, 0x800
	s_mov_b32 s20, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s10
.LBB2_6:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_8 Depth 2
	v_mov_b32_e32 v2, v3
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, s0, s18, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s19, v5, s0
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	v_lshlrev_b64 v[14:15], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v16, s0, s12, v4
	v_add_co_ci_u32_e64 v17, s0, s13, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s12, v14
	v_add_co_ci_u32_e64 v5, s0, s13, v15, s0
	s_clause 0x1
	global_load_b32 v6, v[16:17], off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e64 v6, v2
	s_cbranch_execz .LBB2_23
; %bb.7:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_6 Depth=1
	v_mov_b32_e32 v7, v3
	s_mov_b32 s22, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, s0, s14, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s15, v8, s0
.LBB2_8:                                ; %.lr.ph
                                        ;   Parent Loop BB2_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[7:8], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[14:15], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s0, s16, v14
	v_add_co_ci_u32_e64 v15, s0, s17, v15, s0
	global_atomic_add_u32 v14, v[14:15], v11, off glc
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v14
	s_cbranch_execz .LBB2_21
; %bb.9:                                ;   in Loop: Header=BB2_8 Depth=2
	ds_add_rtn_u32 v14, v10, v11
	s_mov_b32 s23, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_u32_e32 0x7f, v14
	s_xor_b32 s23, exec_lo, s23
	s_cbranch_execz .LBB2_19
; %bb.10:                               ;   in Loop: Header=BB2_8 Depth=2
	s_mov_b32 s24, exec_lo
	s_mov_b32 s25, exec_lo
	v_mbcnt_lo_u32_b32 v14, s24, 0
	ds_store_b32 v10, v12
                                        ; implicit-def: $vgpr15
	v_cmpx_eq_u32_e32 0, v14
	s_cbranch_execz .LBB2_12
; %bb.11:                               ;   in Loop: Header=BB2_8 Depth=2
	s_bcnt1_i32_b32 s0, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v15, s0
	ds_add_rtn_u32 v15, v3, v15 offset:24832
.LBB2_12:                               ;   in Loop: Header=BB2_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s0, v15
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, s0, v14
	v_cmpx_lt_u32_e32 0x7ff, v14
	s_xor_b32 s24, exec_lo, s24
	s_cbranch_execz .LBB2_16
; %bb.13:                               ;   in Loop: Header=BB2_8 Depth=2
	s_mov_b32 s25, exec_lo
	s_mov_b32 s26, exec_lo
	v_mbcnt_lo_u32_b32 v14, s25, 0
	ds_store_b32 v3, v13 offset:24832
                                        ; implicit-def: $vgpr15
	v_cmpx_eq_u32_e32 0, v14
	s_cbranch_execz .LBB2_15
; %bb.14:                               ;   in Loop: Header=BB2_8 Depth=2
	s_bcnt1_i32_b32 s0, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v15, s0
	global_atomic_add_u32 v15, v3, v15, s[8:9] glc
.LBB2_15:                               ;   in Loop: Header=BB2_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v15, v3 :: v_dual_add_nc_u32 v14, s0, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s0, s4, v14
	v_add_co_ci_u32_e64 v15, s0, s5, v15, s0
	global_store_b32 v[14:15], v2, off
                                        ; implicit-def: $vgpr14
.LBB2_16:                               ; %Flow116
                                        ;   in Loop: Header=BB2_8 Depth=2
	s_and_not1_saveexec_b32 s0, s24
	s_cbranch_execz .LBB2_18
; %bb.17:                               ;   in Loop: Header=BB2_8 Depth=2
	v_lshlrev_b32_e32 v14, 2, v14
	ds_store_b32 v14, v2 offset:16384
.LBB2_18:                               ; %Flow117
                                        ;   in Loop: Header=BB2_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14
.LBB2_19:                               ; %Flow118
                                        ;   in Loop: Header=BB2_8 Depth=2
	s_and_not1_saveexec_b32 s0, s23
	s_cbranch_execz .LBB2_21
; %bb.20:                               ;   in Loop: Header=BB2_8 Depth=2
	v_lshl_or_b32 v14, v14, 7, v9
	ds_store_b32 v14, v2
.LBB2_21:                               ;   in Loop: Header=BB2_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v2, v[4:5], off
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v7, s1, v7, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s1, 0, v8, s1
	s_waitcnt vmcnt(0)
	v_cmp_ge_u32_e64 s0, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s22, s0, s22
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB2_8
; %bb.22:                               ; %._crit_edge.loopexit
                                        ;   in Loop: Header=BB2_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	global_load_b32 v7, v3, s[6:7]
.LBB2_23:                               ; %Flow120
                                        ;   in Loop: Header=BB2_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v1, s3, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e64 s0, v1, v7
	s_or_b32 s20, s0, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB2_6
.LBB2_24:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB2_30
; %bb.25:
	ds_load_b32 v2, v9 offset:24576
	s_mov_b32 s0, exec_lo
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr1
.LBB2_26:                               ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s3, s0
	s_waitcnt lgkmcnt(0)
	v_readlane_b32 s6, v2, s3
	s_lshl_b32 s7, 1, s3
	v_writelane_b32 v1, s2, s3
	s_and_not1_b32 s0, s0, s7
	s_delay_alu instid0(VALU_DEP_2)
	s_add_i32 s2, s2, s6
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB2_26
; %bb.27:                               ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v2, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v2
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s3
	s_cbranch_execz .LBB2_29
; %bb.28:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s2
	ds_add_rtn_u32 v2, v2, v3 offset:24832
.LBB2_29:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v1
	ds_store_b32 v9, v1 offset:24704
.LBB2_30:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v9 offset:24576
	v_lshrrev_b32_e32 v4, 5, v0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB2_39
; %bb.31:                               ; %.lr.ph73
	ds_load_b32 v5, v9 offset:24704
	v_lshl_or_b32 v6, v4, 7, v9
	v_mov_b32_e32 v7, 0x800
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v8, v1, 2, 0x4000
.LBB2_32:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, v5, v4
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e32 0x7ff, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB2_36
; %bb.33:                               ;   in Loop: Header=BB2_32 Depth=1
	s_mov_b32 s6, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v1, s6, 0
	ds_store_b32 v2, v7 offset:24832
                                        ; implicit-def: $vgpr9
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_35
; %bb.34:                               ;   in Loop: Header=BB2_32 Depth=1
	s_bcnt1_i32_b32 s0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v9, s0
	global_atomic_add_u32 v9, v2, v9, s[8:9] glc
.LBB2_35:                               ;   in Loop: Header=BB2_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v9
	ds_load_b32 v11, v6
	v_add_nc_u32_e32 v1, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_co_u32 v9, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[9:10], v11, off
.LBB2_36:                               ; %Flow112
                                        ;   in Loop: Header=BB2_32 Depth=1
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB2_38
; %bb.37:                               ;   in Loop: Header=BB2_32 Depth=1
	ds_load_b32 v1, v6
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v8, v1
.LBB2_38:                               ;   in Loop: Header=BB2_32 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v4, 16, v4
	v_add_nc_u32_e32 v8, 64, v8
	v_add_nc_u32_e32 v6, 0x800, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u32_e64 s0, v4, v3
	s_or_b32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_32
.LBB2_39:                               ; %Flow114
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_43
; %bb.40:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v3, s1, 0
                                        ; implicit-def: $vgpr4
	ds_load_b32 v2, v1 offset:24832
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB2_42
; %bb.41:
	s_bcnt1_i32_b32 s1, s1
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v4, v2, s1
	global_atomic_add_u32 v4, v1, v4, s[8:9] glc
.LBB2_42:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v2, v3, s[2:3]
	ds_store_b32 v1, v4 offset:24836
.LBB2_43:                               ; %Flow111
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	ds_load_b32 v3, v2 offset:24832
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_u32_e64 v0, v3
	s_cbranch_execz .LBB2_46
; %bb.44:                               ; %.lr.ph77
	ds_load_b32 v4, v2 offset:24836
	v_lshl_or_b32 v5, v0, 2, 0x4000
	s_lshl_b32 s1, s10, 2
	s_mov_b32 s2, 0
.LBB2_45:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v8, v5
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v1, v4, v0
	v_add_nc_u32_e32 v0, s10, v0
	v_add_nc_u32_e32 v5, s1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_cmp_ge_u32_e32 vcc_lo, v0, v3
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s4, v6
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[6:7], v8, off
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_45
.LBB2_46:                               ; %Flow110
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 24840
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_, .Lfunc_end2-_Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1696
; NumSgprs: 29
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 24840 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z25gpu_global_queuing_kernelPjS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8200
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z24gpu_block_queuing_kernelPjS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 24840
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z23gpu_warp_queuing_kernelPjS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
