// CUDA runtime
#include <cuda_runtime.h>
#include <stdio.h>
// Helper functions and utilities to work with CUDA
// #include <helper_functions.h>

/**********************************************
 * Check whether we read back the same input
 * The double check is just for debug purposes.
 * We can comment it out when benchmarking the time.
 **********************************************/
#define GPU_DEBUG


/*
  Define all constant variavle below with a REASONABLE name
*/

#define out_channel_num 6 // number of feature maps
#define out_y_dim 358 // height of output map
#define out_x_dim 638 // width of output map
#define in_y_dim 720  // height of input map
#define in_x_dim 1280 // width of output map
#define conv_window_y 6 // height of convolution window
#define conv_window_x 6 // width of convolution window
#define filter_size (conv_window_y * conv_window_x) // size of convolution window
#define stride 2  // stride of layer
#define init_bias_thread_x 16 // thread x dimension of init_bias
#define init_bias_thread_y 16 // thread y dimension of init_bias
#define init_bias_thread_z 2 // thread z dimension of init_bias
#define feature_maps_thread_x 8 // thread x dimension of feature_maps
#define feature_maps_thread_y 8 // thread y dimension of feature_maps
#define feature_maps_thread_z 8 // thread z dimension of feature_maps
#define sigmoid_thread_x 14 // thread x dimension of sigmoid
#define sigmoid_thread_y 14 // thread y dimension of sigmoid
#define sigmoid_thread_z 2 // thread z dimension of sigmoid

/******************************************
 * Device function declaration
 *****************************************/
__global__ void layer1_init_bias(float* d_y, float* d_bias);
__global__ void layer1_feature_maps(float* d_y, unsigned char* d_in_layer, float* d_weight);
__global__ void layer1_sigmoid(float* d_y, unsigned char* d_out_layer);

/************************************************************************************
 * Input   : input image, pointer to output result, coefficients bias and weights
 * Output  : neuron outputs of the feature maps represented as an image
 * Procedure: perform feed forward computation through the feature extraction layers
     *******************************************************************************/
void cuda_convolution_layer1(unsigned char in_layer[], unsigned char out_layer[],
           const float bias[], const float weight[]) {

  /*********************************
   * allocate device memory on GPU
   *********************************/

  unsigned int size_y = out_channel_num*out_y_dim*out_x_dim;
  unsigned int mem_size_y = sizeof(float) * size_y;
  float *d_y;

  unsigned int size_bias = out_channel_num;
  unsigned int mem_size_bias = sizeof(float) * size_bias;
  float *d_bias;

  unsigned int size_weight = out_channel_num*filter_size;
  unsigned int mem_size_weight = sizeof(float) * size_weight;
  float *d_weight;

  unsigned int size_in_layer = in_y_dim*in_x_dim;
  unsigned int mem_size_in_layer = sizeof(unsigned char) * size_in_layer;
  unsigned char *d_in_layer;

  unsigned int size_out_layer = out_channel_num*out_y_dim*out_x_dim;
  unsigned int mem_size_out_layer = sizeof(unsigned char) * size_out_layer;
  unsigned char *d_out_layer;

  cudaError_t error;


  /********************************
   * Allocate device memory on GPU.
   * Check the first cudaMalloc error,
   * in case GPU is busy.
   ********************************/
  error = cudaMalloc((void **) &d_y, mem_size_y);
  /* Check the error code of the first CUDA API call */
  if (error != cudaSuccess){
    printf("cudaMalloc returned error code %d, line(%d)\n", error, __LINE__);
    printf("CUDA error: %s\n", cudaGetErrorString(error));
  }else{
    printf("cudaMalloc success.\n");
  }
  /* if no error for the first cudaMalloc, continue other cudaMalloc */
  error = cudaMalloc((void **) &d_in_layer, mem_size_in_layer);
  error = cudaMalloc((void **) &d_bias, mem_size_bias);
  error = cudaMalloc((void **) &d_weight, mem_size_weight);
  error = cudaMalloc((void **) &d_out_layer, mem_size_out_layer);

  /*********************************************
   * copy data from host (CPU) to device (GPU)
   ********************************************/
  error = cudaMemcpy(d_in_layer, in_layer, mem_size_in_layer, cudaMemcpyHostToDevice);
  error = cudaMemcpy(d_bias, bias, mem_size_bias, cudaMemcpyHostToDevice);
  error = cudaMemcpy(d_weight, weight, mem_size_weight, cudaMemcpyHostToDevice);

  /* Synchronize all the cudaMemcpy API before doing the actual computation */
  cudaDeviceSynchronize();

  /*********************************************
   * Layer 1, Step 1: 
   * init values of feature maps at bias value 
   ********************************************/
  /* 16*16*z(choose the correct z dimension) threads per block */
  /* NOTE: threads per block limit is 1024 for K80 */
  /* NOTE: if you use another GPU, check the deviceQuery */

  dim3 threadsPerBlock = dim3(init_bias_thread_x, init_bias_thread_y, init_bias_thread_z);
  dim3 blocksPerGrid = dim3((out_x_dim + init_bias_thread_x - 1) / init_bias_thread_x, 
          (out_y_dim + init_bias_thread_y - 1) / init_bias_thread_y, 
          (out_channel_num + init_bias_thread_z - 1) / init_bias_thread_z);
  layer1_init_bias<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_bias);

  /* Just in case, put a sync here */
  cudaDeviceSynchronize();

  /*********************************************
   * Layer 1, Step 2: 
   * loop over output feature maps
   ********************************************/
  /* 8*8*z(choose the correct z dimension) threads per block */
  /***********************************************
   * The layer size is not diviadable by 8 either.
   * Mask out extra threads in the kernel.
   **********************************************/  

  threadsPerBlock = dim3(feature_maps_thread_x, feature_maps_thread_y, feature_maps_thread_z);
  blocksPerGrid = dim3((out_x_dim + feature_maps_thread_x - 1) / feature_maps_thread_x, 
          (out_y_dim + feature_maps_thread_y - 1) / feature_maps_thread_y, 
          (out_channel_num + feature_maps_thread_z - 1) / feature_maps_thread_z);

  // record time to execute layer1_feature_maps
  float time;
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);
  layer1_feature_maps<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_in_layer, d_weight);
  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&time, start, stop);
  printf("Time to execute layer1_feature_maps:  %3.1f ms \n", time);
  
  /* Just in case, put a sync here */
  cudaDeviceSynchronize();

  /********************************************
   14*14*z(choose the correct z dimension) threads per block
   ********************************************
   * Layer 1, Step 3: 
   * sigmoid activation function
   ********************************************/

  threadsPerBlock = dim3(sigmoid_thread_x, sigmoid_thread_y, sigmoid_thread_z);
  blocksPerGrid = dim3((out_x_dim + sigmoid_thread_x - 1) / sigmoid_thread_x, 
          (out_y_dim + sigmoid_thread_y - 1) / sigmoid_thread_y, 
          (out_channel_num + sigmoid_thread_z - 1) / sigmoid_thread_z);
  layer1_sigmoid<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_out_layer);

  /* Just in case, put a sync here */
  cudaDeviceSynchronize();

  /* Read back the output from device (GPU) to host (CPU) */
  error = cudaMemcpy(out_layer, d_out_layer, mem_size_out_layer, cudaMemcpyDeviceToHost);


  /* Just in case, put a sync here */
  cudaDeviceSynchronize();

  /* release device memory */
  cudaFree(d_y);
  cudaFree(d_in_layer);
  cudaFree(d_bias);
  cudaFree(d_weight);
  cudaFree(d_out_layer);

}


/*********************************************
 * GPU kernel
 * Layer 1, Step 1: 
 * init values of feature maps at bias value
 * 16*16*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_init_bias(float* d_y, float* d_bias) {

  int col = threadIdx.x + blockIdx.x * init_bias_thread_x;
  int row = threadIdx.y + blockIdx.y * init_bias_thread_y;
  int depth = threadIdx.z + blockIdx.z * init_bias_thread_z;

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)  // prevent out of bound access
    d_y[depth * out_y_dim * out_x_dim + row * out_x_dim + col] = d_bias[depth]; // load the bias

}

/*********************************************
 * GPU kernel
 * Layer 1, Step 2: 
 * loop over output feature maps
 * 8*8*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_feature_maps(float* d_y, unsigned char* d_in_layer, float* d_weight) {

  int col = threadIdx.x + blockIdx.x * feature_maps_thread_x;
  int row = threadIdx.y + blockIdx.y * feature_maps_thread_y;
  int depth = threadIdx.z + blockIdx.z * feature_maps_thread_z;

  // cache d_in_layer
  __shared__ unsigned char in_layer[feature_maps_thread_y * stride + conv_window_y][feature_maps_thread_x * stride + conv_window_x];

  // process [0, feature_maps_thread_y * stride - 1][0, feature_maps_thread_x * stride + conv_window_x - 1]
  for (int i = 0; i < stride; i++) 
      in_layer[threadIdx.y * stride + i][threadIdx.x * stride + depth] = 
        d_in_layer[(row * stride + i) * in_x_dim + col * stride + depth];

  // process [feature_maps_thread_y * stride, feature_maps_thread_y * stride + conv_window_y - 1][0, feature_maps_thread_x * stride - 1]
  if (threadIdx.y == 0 && depth < conv_window_y)
    for (int i = 0; i < stride; i++) {
      in_layer[feature_maps_thread_y * stride + depth][threadIdx.x * stride + i] = 
        d_in_layer[((row + feature_maps_thread_y) * stride + depth) * in_x_dim + col * stride + i];
    }

  // process [feature_maps_thread_y * stride, feature_maps_thread_y * stride + conv_window_y - 1][feature_maps_thread_x * stride, feature_maps_thread_x * stride + conv_window_x - 1]
  if (threadIdx.x < conv_window_x && threadIdx.y == 0 && depth < conv_window_y)
    in_layer[feature_maps_thread_y * stride + depth][feature_maps_thread_x * stride + threadIdx.x] = 
      d_in_layer[((row + feature_maps_thread_y) * stride + depth) * in_x_dim + (col - threadIdx.x + feature_maps_thread_x) * stride + threadIdx.x];

  // cache d_weight
  __shared__ float weight[out_channel_num][filter_size];
  if (threadIdx.y < out_y_dim && threadIdx.x < out_x_dim && depth < out_channel_num)
    weight[depth][threadIdx.y * conv_window_x + threadIdx.x] = d_weight[depth * filter_size + threadIdx.y * conv_window_x + threadIdx.x];

  __syncthreads();

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)  // prevent out of bound access
    for (int k = 0; k < conv_window_y; k++)  // loop over convolution window (row)
      for (int l = 0; l < conv_window_x; l++)  // loop over convolution window (column)
        // perform convolution over a window
        d_y[depth * out_y_dim * out_x_dim + row * out_x_dim + col] += 
          in_layer[threadIdx.y * stride + k][threadIdx.x * stride + l] * weight[depth][k * conv_window_x + l];

}

/*********************************************
 * GPU kernel
 * Layer 1, Step 3: 
 * sigmoid activation function
 * 14*14*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_sigmoid(float* d_y, unsigned char* d_out_layer){

  int col = threadIdx.x + blockIdx.x * sigmoid_thread_x;
  int row = threadIdx.y + blockIdx.y * sigmoid_thread_y;
  int depth = threadIdx.z + blockIdx.z * sigmoid_thread_z;
  int idx = depth * out_y_dim * out_x_dim + row * out_x_dim + col;  // index in the grid

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)
    d_out_layer[idx] = (unsigned char)(255.999f / (1 + expf(-d_y[idx] / 256))); // apply the sigmoid function to the result

}
	.file	"tmpxft_002338d9_00000000-6_2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z16layer1_init_biasPfS_PfS_
	.type	_Z38__device_stub__Z16layer1_init_biasPfS_PfS_, @function
_Z38__device_stub__Z16layer1_init_biasPfS_PfS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z16layer1_init_biasPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z38__device_stub__Z16layer1_init_biasPfS_PfS_, .-_Z38__device_stub__Z16layer1_init_biasPfS_PfS_
	.globl	_Z16layer1_init_biasPfS_
	.type	_Z16layer1_init_biasPfS_, @function
_Z16layer1_init_biasPfS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z16layer1_init_biasPfS_PfS_
	.cfi_endproc
.LFE2053:
	.size	_Z16layer1_init_biasPfS_, .-_Z16layer1_init_biasPfS_
	.globl	_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_
	.type	_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_, @function
_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19layer1_feature_mapsPfPhS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_, .-_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_
	.globl	_Z19layer1_feature_mapsPfPhS_
	.type	_Z19layer1_feature_mapsPfPhS_, @function
_Z19layer1_feature_mapsPfPhS_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_
	.cfi_endproc
.LFE2055:
	.size	_Z19layer1_feature_mapsPfPhS_, .-_Z19layer1_feature_mapsPfPhS_
	.globl	_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh
	.type	_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh, @function
_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14layer1_sigmoidPfPh(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh, .-_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh
	.globl	_Z14layer1_sigmoidPfPh
	.type	_Z14layer1_sigmoidPfPh, @function
_Z14layer1_sigmoidPfPh:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh
	.cfi_endproc
.LFE2057:
	.size	_Z14layer1_sigmoidPfPh, .-_Z14layer1_sigmoidPfPh
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaMalloc returned error code %d, line(%d)\n"
.LC1:
	.string	"CUDA error: %s\n"
.LC2:
	.string	"cudaMalloc success.\n"
.LC3:
	.string	"Time to execute layer1_feature_maps:  %3.1f ms \n"
	.text
	.globl	_Z23cuda_convolution_layer1PhS_PKfS1_
	.type	_Z23cuda_convolution_layer1PhS_PKfS1_, @function
_Z23cuda_convolution_layer1PhS_PKfS1_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	movl	$5481696, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L19
	movl	%eax, %edx
	movl	%eax, %ebx
	movl	$88, %ecx
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebx, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L20
.L19:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L20:
	leaq	32(%rsp), %rdi
	movl	$921600, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$24, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$864, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1370424, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$921600, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$24, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$864, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2, %ecx
	movabsq	$68719476752, %rdx
	movl	$3, %esi
	movabsq	$98784247848, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z38__device_stub__Z16layer1_init_biasPfS_PfS_
.L21:
	call	cudaDeviceSynchronize@PLT
	leaq	48(%rsp), %rdi
	movabsq	$34359738376, %rax
	movl	$8, 72(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$193273528400, %rax
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	24(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z43__device_stub__Z19layer1_feature_mapsPfPhS_PfPhS_
.L22:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2, %ecx
	movabsq	$60129542158, %rdx
	movl	$3, %esi
	movabsq	$111669149742, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z36__device_stub__Z14layer1_sigmoidPfPhPfPh
.L23:
	call	cudaDeviceSynchronize@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$1370424, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$96, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z23cuda_convolution_layer1PhS_PKfS1_, .-_Z23cuda_convolution_layer1PhS_PKfS1_
	.section	.rodata.str1.1
.LC4:
	.string	"_Z14layer1_sigmoidPfPh"
.LC5:
	.string	"_Z19layer1_feature_mapsPfPhS_"
.LC6:
	.string	"_Z16layer1_init_biasPfS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14layer1_sigmoidPfPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19layer1_feature_mapsPfPhS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16layer1_init_biasPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// CUDA runtime
#include <hip/hip_runtime.h>
#include <stdio.h>
// Helper functions and utilities to work with CUDA
// #include <helper_functions.h>

/**********************************************
 * Check whether we read back the same input
 * The double check is just for debug purposes.
 * We can comment it out when benchmarking the time.
 **********************************************/
#define GPU_DEBUG


/*
  Define all constant variavle below with a REASONABLE name
*/

#define out_channel_num 6 // number of feature maps
#define out_y_dim 358 // height of output map
#define out_x_dim 638 // width of output map
#define in_y_dim 720  // height of input map
#define in_x_dim 1280 // width of output map
#define conv_window_y 6 // height of convolution window
#define conv_window_x 6 // width of convolution window
#define filter_size (conv_window_y * conv_window_x) // size of convolution window
#define stride 2  // stride of layer
#define init_bias_thread_x 16 // thread x dimension of init_bias
#define init_bias_thread_y 16 // thread y dimension of init_bias
#define init_bias_thread_z 2 // thread z dimension of init_bias
#define feature_maps_thread_x 8 // thread x dimension of feature_maps
#define feature_maps_thread_y 8 // thread y dimension of feature_maps
#define feature_maps_thread_z 8 // thread z dimension of feature_maps
#define sigmoid_thread_x 14 // thread x dimension of sigmoid
#define sigmoid_thread_y 14 // thread y dimension of sigmoid
#define sigmoid_thread_z 2 // thread z dimension of sigmoid

/******************************************
 * Device function declaration
 *****************************************/
__global__ void layer1_init_bias(float* d_y, float* d_bias);
__global__ void layer1_feature_maps(float* d_y, unsigned char* d_in_layer, float* d_weight);
__global__ void layer1_sigmoid(float* d_y, unsigned char* d_out_layer);

/************************************************************************************
 * Input   : input image, pointer to output result, coefficients bias and weights
 * Output  : neuron outputs of the feature maps represented as an image
 * Procedure: perform feed forward computation through the feature extraction layers
     *******************************************************************************/
void cuda_convolution_layer1(unsigned char in_layer[], unsigned char out_layer[],
           const float bias[], const float weight[]) {

  /*********************************
   * allocate device memory on GPU
   *********************************/

  unsigned int size_y = out_channel_num*out_y_dim*out_x_dim;
  unsigned int mem_size_y = sizeof(float) * size_y;
  float *d_y;

  unsigned int size_bias = out_channel_num;
  unsigned int mem_size_bias = sizeof(float) * size_bias;
  float *d_bias;

  unsigned int size_weight = out_channel_num*filter_size;
  unsigned int mem_size_weight = sizeof(float) * size_weight;
  float *d_weight;

  unsigned int size_in_layer = in_y_dim*in_x_dim;
  unsigned int mem_size_in_layer = sizeof(unsigned char) * size_in_layer;
  unsigned char *d_in_layer;

  unsigned int size_out_layer = out_channel_num*out_y_dim*out_x_dim;
  unsigned int mem_size_out_layer = sizeof(unsigned char) * size_out_layer;
  unsigned char *d_out_layer;

  hipError_t error;


  /********************************
   * Allocate device memory on GPU.
   * Check the first cudaMalloc error,
   * in case GPU is busy.
   ********************************/
  error = hipMalloc((void **) &d_y, mem_size_y);
  /* Check the error code of the first CUDA API call */
  if (error != hipSuccess){
    printf("hipMalloc returned error code %d, line(%d)\n", error, __LINE__);
    printf("CUDA error: %s\n", hipGetErrorString(error));
  }else{
    printf("hipMalloc success.\n");
  }
  /* if no error for the first cudaMalloc, continue other cudaMalloc */
  error = hipMalloc((void **) &d_in_layer, mem_size_in_layer);
  error = hipMalloc((void **) &d_bias, mem_size_bias);
  error = hipMalloc((void **) &d_weight, mem_size_weight);
  error = hipMalloc((void **) &d_out_layer, mem_size_out_layer);

  /*********************************************
   * copy data from host (CPU) to device (GPU)
   ********************************************/
  error = hipMemcpy(d_in_layer, in_layer, mem_size_in_layer, hipMemcpyHostToDevice);
  error = hipMemcpy(d_bias, bias, mem_size_bias, hipMemcpyHostToDevice);
  error = hipMemcpy(d_weight, weight, mem_size_weight, hipMemcpyHostToDevice);

  /* Synchronize all the cudaMemcpy API before doing the actual computation */
  hipDeviceSynchronize();

  /*********************************************
   * Layer 1, Step 1: 
   * init values of feature maps at bias value 
   ********************************************/
  /* 16*16*z(choose the correct z dimension) threads per block */
  /* NOTE: threads per block limit is 1024 for K80 */
  /* NOTE: if you use another GPU, check the deviceQuery */

  dim3 threadsPerBlock = dim3(init_bias_thread_x, init_bias_thread_y, init_bias_thread_z);
  dim3 blocksPerGrid = dim3((out_x_dim + init_bias_thread_x - 1) / init_bias_thread_x, 
          (out_y_dim + init_bias_thread_y - 1) / init_bias_thread_y, 
          (out_channel_num + init_bias_thread_z - 1) / init_bias_thread_z);
  layer1_init_bias<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_bias);

  /* Just in case, put a sync here */
  hipDeviceSynchronize();

  /*********************************************
   * Layer 1, Step 2: 
   * loop over output feature maps
   ********************************************/
  /* 8*8*z(choose the correct z dimension) threads per block */
  /***********************************************
   * The layer size is not diviadable by 8 either.
   * Mask out extra threads in the kernel.
   **********************************************/  

  threadsPerBlock = dim3(feature_maps_thread_x, feature_maps_thread_y, feature_maps_thread_z);
  blocksPerGrid = dim3((out_x_dim + feature_maps_thread_x - 1) / feature_maps_thread_x, 
          (out_y_dim + feature_maps_thread_y - 1) / feature_maps_thread_y, 
          (out_channel_num + feature_maps_thread_z - 1) / feature_maps_thread_z);

  // record time to execute layer1_feature_maps
  float time;
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);
  layer1_feature_maps<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_in_layer, d_weight);
  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&time, start, stop);
  printf("Time to execute layer1_feature_maps:  %3.1f ms \n", time);
  
  /* Just in case, put a sync here */
  hipDeviceSynchronize();

  /********************************************
   14*14*z(choose the correct z dimension) threads per block
   ********************************************
   * Layer 1, Step 3: 
   * sigmoid activation function
   ********************************************/

  threadsPerBlock = dim3(sigmoid_thread_x, sigmoid_thread_y, sigmoid_thread_z);
  blocksPerGrid = dim3((out_x_dim + sigmoid_thread_x - 1) / sigmoid_thread_x, 
          (out_y_dim + sigmoid_thread_y - 1) / sigmoid_thread_y, 
          (out_channel_num + sigmoid_thread_z - 1) / sigmoid_thread_z);
  layer1_sigmoid<<<blocksPerGrid, threadsPerBlock>>>(d_y, d_out_layer);

  /* Just in case, put a sync here */
  hipDeviceSynchronize();

  /* Read back the output from device (GPU) to host (CPU) */
  error = hipMemcpy(out_layer, d_out_layer, mem_size_out_layer, hipMemcpyDeviceToHost);


  /* Just in case, put a sync here */
  hipDeviceSynchronize();

  /* release device memory */
  hipFree(d_y);
  hipFree(d_in_layer);
  hipFree(d_bias);
  hipFree(d_weight);
  hipFree(d_out_layer);

}


/*********************************************
 * GPU kernel
 * Layer 1, Step 1: 
 * init values of feature maps at bias value
 * 16*16*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_init_bias(float* d_y, float* d_bias) {

  int col = threadIdx.x + blockIdx.x * init_bias_thread_x;
  int row = threadIdx.y + blockIdx.y * init_bias_thread_y;
  int depth = threadIdx.z + blockIdx.z * init_bias_thread_z;

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)  // prevent out of bound access
    d_y[depth * out_y_dim * out_x_dim + row * out_x_dim + col] = d_bias[depth]; // load the bias

}

/*********************************************
 * GPU kernel
 * Layer 1, Step 2: 
 * loop over output feature maps
 * 8*8*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_feature_maps(float* d_y, unsigned char* d_in_layer, float* d_weight) {

  int col = threadIdx.x + blockIdx.x * feature_maps_thread_x;
  int row = threadIdx.y + blockIdx.y * feature_maps_thread_y;
  int depth = threadIdx.z + blockIdx.z * feature_maps_thread_z;

  // cache d_in_layer
  __shared__ unsigned char in_layer[feature_maps_thread_y * stride + conv_window_y][feature_maps_thread_x * stride + conv_window_x];

  // process [0, feature_maps_thread_y * stride - 1][0, feature_maps_thread_x * stride + conv_window_x - 1]
  for (int i = 0; i < stride; i++) 
      in_layer[threadIdx.y * stride + i][threadIdx.x * stride + depth] = 
        d_in_layer[(row * stride + i) * in_x_dim + col * stride + depth];

  // process [feature_maps_thread_y * stride, feature_maps_thread_y * stride + conv_window_y - 1][0, feature_maps_thread_x * stride - 1]
  if (threadIdx.y == 0 && depth < conv_window_y)
    for (int i = 0; i < stride; i++) {
      in_layer[feature_maps_thread_y * stride + depth][threadIdx.x * stride + i] = 
        d_in_layer[((row + feature_maps_thread_y) * stride + depth) * in_x_dim + col * stride + i];
    }

  // process [feature_maps_thread_y * stride, feature_maps_thread_y * stride + conv_window_y - 1][feature_maps_thread_x * stride, feature_maps_thread_x * stride + conv_window_x - 1]
  if (threadIdx.x < conv_window_x && threadIdx.y == 0 && depth < conv_window_y)
    in_layer[feature_maps_thread_y * stride + depth][feature_maps_thread_x * stride + threadIdx.x] = 
      d_in_layer[((row + feature_maps_thread_y) * stride + depth) * in_x_dim + (col - threadIdx.x + feature_maps_thread_x) * stride + threadIdx.x];

  // cache d_weight
  __shared__ float weight[out_channel_num][filter_size];
  if (threadIdx.y < out_y_dim && threadIdx.x < out_x_dim && depth < out_channel_num)
    weight[depth][threadIdx.y * conv_window_x + threadIdx.x] = d_weight[depth * filter_size + threadIdx.y * conv_window_x + threadIdx.x];

  __syncthreads();

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)  // prevent out of bound access
    for (int k = 0; k < conv_window_y; k++)  // loop over convolution window (row)
      for (int l = 0; l < conv_window_x; l++)  // loop over convolution window (column)
        // perform convolution over a window
        d_y[depth * out_y_dim * out_x_dim + row * out_x_dim + col] += 
          in_layer[threadIdx.y * stride + k][threadIdx.x * stride + l] * weight[depth][k * conv_window_x + l];

}

/*********************************************
 * GPU kernel
 * Layer 1, Step 3: 
 * sigmoid activation function
 * 14*14*z(choose the correct z dimension) threads per block
 ********************************************/
__global__ void layer1_sigmoid(float* d_y, unsigned char* d_out_layer){

  int col = threadIdx.x + blockIdx.x * sigmoid_thread_x;
  int row = threadIdx.y + blockIdx.y * sigmoid_thread_y;
  int depth = threadIdx.z + blockIdx.z * sigmoid_thread_z;
  int idx = depth * out_y_dim * out_x_dim + row * out_x_dim + col;  // index in the grid

  if (row < out_y_dim && col < out_x_dim && depth < out_channel_num)
    d_out_layer[idx] = (unsigned char)(255.999f / (1 + expf(-d_y[idx] / 256))); // apply the sigmoid function to the result

}
	.text
	.file	"2.hip"
	.globl	_Z23cuda_convolution_layer1PhS_PKfS1_ # -- Begin function _Z23cuda_convolution_layer1PhS_PKfS1_
	.type	_Z23cuda_convolution_layer1PhS_PKfS1_,@function
_Z23cuda_convolution_layer1PhS_PKfS1_:  # @_Z23cuda_convolution_layer1PhS_PKfS1_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, %r12
	movq	%rsp, %rdi
	movl	$5481696, %esi                  # imm = 0x53A4E0
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	movl	%eax, %ebp
	movl	$.L.str, %edi
	movl	%eax, %esi
	movl	$88, %edx
	xorl	%eax, %eax
	callq	printf
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB0_3
.LBB0_2:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB0_3:
	leaq	24(%rsp), %rbx
	movl	$921600, %esi                   # imm = 0xE1000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rbp
	movl	$24, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r13
	movl	$864, %esi                      # imm = 0x360
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$1370424, %esi                  # imm = 0x14E938
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$921600, %edx                   # imm = 0xE1000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$24, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$864, %edx                      # imm = 0x360
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movabsq	$98784247848, %rdi              # imm = 0x1700000028
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$3, %esi
	movl	$2, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_5
# %bb.4:
	movq	(%rsp), %rdi
	movq	40(%rsp), %rsi
	callq	_Z31__device_stub__layer1_init_biasPfS_
.LBB0_5:
	callq	hipDeviceSynchronize
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$193273528400, %rdi             # imm = 0x2D00000050
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_7
# %bb.6:
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdx
	callq	_Z34__device_stub__layer1_feature_mapsPfPhS_
.LBB0_7:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	68(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	callq	hipDeviceSynchronize
	movabsq	$111669149742, %rdi             # imm = 0x1A0000002E
	movabsq	$60129542158, %rdx              # imm = 0xE0000000E
	movl	$3, %esi
	movl	$2, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_9
# %bb.8:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z29__device_stub__layer1_sigmoidPfPh
.LBB0_9:
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rsi
	movl	$1370424, %edx                  # imm = 0x14E938
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23cuda_convolution_layer1PhS_PKfS1_, .Lfunc_end0-_Z23cuda_convolution_layer1PhS_PKfS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__layer1_init_biasPfS_ # -- Begin function _Z31__device_stub__layer1_init_biasPfS_
	.type	_Z31__device_stub__layer1_init_biasPfS_,@function
_Z31__device_stub__layer1_init_biasPfS_: # @_Z31__device_stub__layer1_init_biasPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16layer1_init_biasPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__layer1_init_biasPfS_, .Lfunc_end1-_Z31__device_stub__layer1_init_biasPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__layer1_feature_mapsPfPhS_ # -- Begin function _Z34__device_stub__layer1_feature_mapsPfPhS_
	.type	_Z34__device_stub__layer1_feature_mapsPfPhS_,@function
_Z34__device_stub__layer1_feature_mapsPfPhS_: # @_Z34__device_stub__layer1_feature_mapsPfPhS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19layer1_feature_mapsPfPhS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__layer1_feature_mapsPfPhS_, .Lfunc_end2-_Z34__device_stub__layer1_feature_mapsPfPhS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__layer1_sigmoidPfPh # -- Begin function _Z29__device_stub__layer1_sigmoidPfPh
	.type	_Z29__device_stub__layer1_sigmoidPfPh,@function
_Z29__device_stub__layer1_sigmoidPfPh:  # @_Z29__device_stub__layer1_sigmoidPfPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14layer1_sigmoidPfPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29__device_stub__layer1_sigmoidPfPh, .Lfunc_end3-_Z29__device_stub__layer1_sigmoidPfPh
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16layer1_init_biasPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19layer1_feature_mapsPfPhS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14layer1_sigmoidPfPh, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hipMalloc returned error code %d, line(%d)\n"
	.size	.L.str, 44

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CUDA error: %s\n"
	.size	.L.str.1, 16

	.type	_Z16layer1_init_biasPfS_,@object # @_Z16layer1_init_biasPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z16layer1_init_biasPfS_
	.p2align	3, 0x0
_Z16layer1_init_biasPfS_:
	.quad	_Z31__device_stub__layer1_init_biasPfS_
	.size	_Z16layer1_init_biasPfS_, 8

	.type	_Z19layer1_feature_mapsPfPhS_,@object # @_Z19layer1_feature_mapsPfPhS_
	.globl	_Z19layer1_feature_mapsPfPhS_
	.p2align	3, 0x0
_Z19layer1_feature_mapsPfPhS_:
	.quad	_Z34__device_stub__layer1_feature_mapsPfPhS_
	.size	_Z19layer1_feature_mapsPfPhS_, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"Time to execute layer1_feature_maps:  %3.1f ms \n"
	.size	.L.str.3, 49

	.type	_Z14layer1_sigmoidPfPh,@object  # @_Z14layer1_sigmoidPfPh
	.section	.rodata,"a",@progbits
	.globl	_Z14layer1_sigmoidPfPh
	.p2align	3, 0x0
_Z14layer1_sigmoidPfPh:
	.quad	_Z29__device_stub__layer1_sigmoidPfPh
	.size	_Z14layer1_sigmoidPfPh, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16layer1_init_biasPfS_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19layer1_feature_mapsPfPhS_"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14layer1_sigmoidPfPh"
	.size	.L__unnamed_3, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"hipMalloc success."
	.size	.Lstr, 19

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__layer1_init_biasPfS_
	.addrsig_sym _Z34__device_stub__layer1_feature_mapsPfPhS_
	.addrsig_sym _Z29__device_stub__layer1_sigmoidPfPh
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16layer1_init_biasPfS_
	.addrsig_sym _Z19layer1_feature_mapsPfPhS_
	.addrsig_sym _Z14layer1_sigmoidPfPh
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16layer1_init_biasPfS_ ; -- Begin function _Z16layer1_init_biasPfS_
	.globl	_Z16layer1_init_biasPfS_
	.p2align	8
	.type	_Z16layer1_init_biasPfS_,@function
_Z16layer1_init_biasPfS_:               ; @_Z16layer1_init_biasPfS_
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v3, s14, 4, v1
	v_lshl_add_u32 v2, s13, 4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, s15, 1, v0
	v_cmp_gt_i32_e32 vcc_lo, 0x166, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, 0x27e, v2
	v_cmp_gt_i32_e64 s3, 6, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_mul_lo_u32 v0, 0x37c34, v0
	v_mul_lo_u32 v1, 0x27e, v3
	v_add3_u32 v0, v1, v2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	global_load_b32 v4, v[4:5], off
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16layer1_init_biasPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16layer1_init_biasPfS_, .Lfunc_end0-_Z16layer1_init_biasPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z19layer1_feature_mapsPfPhS_ ; -- Begin function _Z19layer1_feature_mapsPfPhS_
	.globl	_Z19layer1_feature_mapsPfPhS_
	.p2align	8
	.type	_Z19layer1_feature_mapsPfPhS_,@function
_Z19layer1_feature_mapsPfPhS_:          ; @_Z19layer1_feature_mapsPfPhS_
; %bb.0:                                ; %.critedge
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 20, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_lshl_add_u32 v2, s14, 3, v3
	v_lshl_add_u32 v5, s13, 3, v1
	v_lshl_add_u32 v6, s15, 3, v4
	v_cmp_eq_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v0, 0xa00, v2
	v_lshlrev_b32_e32 v7, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v7, v6, v0
	v_add_nc_u32_e32 v10, 0x500, v0
	v_ashrrev_i32_e32 v9, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_lshlrev_b32_e32 v0, 1, v1
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 6, v6
	s_clause 0x1
	global_load_u8 v9, v[8:9], off
	global_load_u8 v10, v[10:11], off
	v_lshlrev_b32_e32 v8, 1, v2
	v_add_nc_u32_e32 v11, v6, v0
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v6, v8
	v_mad_u32_u24 v11, v3, 44, v11
	s_waitcnt vmcnt(1)
	ds_store_b8 v11, v9 offset:864
	s_waitcnt vmcnt(0)
	ds_store_b8 v11, v10 offset:886
	v_mul_lo_u32 v8, 0x500, v8
	s_and_saveexec_b32 s8, s1
	s_cbranch_execz .LBB1_2
; %bb.1:                                ; %.preheader64
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v7, v8, v7, 0x5000
	v_ashrrev_i32_e32 v10, 31, v7
	v_add_co_u32 v9, s0, s6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	global_load_u16 v7, v[9:10], off
	v_mad_u64_u32 v[9:10], null, v6, 22, v[0:1]
	s_waitcnt vmcnt(0)
	ds_store_b16 v9, v7 offset:1216
.LBB1_2:                                ; %.loopexit65
	s_or_b32 exec_lo, exec_lo, s8
	v_cmp_gt_u32_e64 s0, 6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_lshl_add_u32 v7, s13, 4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v8, v7, 0x5010
	global_load_u8 v9, v7, s[6:7]
	v_mad_u64_u32 v[7:8], null, v6, 22, v[1:2]
	s_waitcnt vmcnt(0)
	ds_store_b8 v7, v9 offset:1232
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u32_e64 s0, 0x166, v3
	v_cmp_gt_u32_e64 s1, 0x27e, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, s0
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_mad_u32_u24 v1, v3, 6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v6, 36, v[1:2]
	v_mov_b32_e32 v8, 0
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s2, v7
	v_add_co_ci_u32_e64 v8, s0, s3, v8, s0
	global_load_b32 v7, v[7:8], off
	v_mul_lo_u32 v8, 0x90, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v1, v1, 2, v8
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v7
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_i32_e64 s0, 0x166, v2
	v_cmp_gt_i32_e64 s1, 0x27e, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_12
; %bb.7:                                ; %.preheader63
	v_mul_lo_u32 v1, 0x37c34, v6
	v_mul_lo_u32 v2, 0x27e, v2
	v_mul_u32_u24_e32 v6, 44, v3
	s_mulk_i32 s15, 0x480
	s_mov_b32 s0, 0
	v_mad_u32_u24 v3, 0x90, v4, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v0, v6, v0, 0x360
	v_add3_u32 v1, v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v5, v[1:2], off
.LBB1_8:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
	v_mov_b32_e32 v4, v3
	s_mov_b32 s1, 0
.LBB1_9:                                ;   Parent Loop BB1_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s1, v0
	s_add_i32 s1, s1, 1
	ds_load_u8 v6, v6
	ds_load_b32 v7, v4
	s_cmp_eq_u32 s1, 6
	s_waitcnt lgkmcnt(1)
	v_cvt_f32_ubyte0_e32 v6, v6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v5, v7, v6 :: v_dual_add_nc_u32 v4, 4, v4
	s_cbranch_scc0 .LBB1_9
; %bb.10:                               ;   in Loop: Header=BB1_8 Depth=1
	v_add_nc_u32_e32 v3, 24, v3
	v_add_nc_u32_e32 v0, 22, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 6
	s_cbranch_scc0 .LBB1_8
; %bb.11:                               ; %.loopexit
	global_store_b32 v[1:2], v5, off
.LBB1_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19layer1_feature_mapsPfPhS_
		.amdhsa_group_segment_fixed_size 1348
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19layer1_feature_mapsPfPhS_, .Lfunc_end1-_Z19layer1_feature_mapsPfPhS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1348 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z14layer1_sigmoidPfPh  ; -- Begin function _Z14layer1_sigmoidPfPh
	.globl	_Z14layer1_sigmoidPfPh
	.p2align	8
	.type	_Z14layer1_sigmoidPfPh,@function
_Z14layer1_sigmoidPfPh:                 ; @_Z14layer1_sigmoidPfPh
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, 14, v[1:2]
	v_mad_u64_u32 v[0:1], null, s13, 14, v[4:5]
	v_lshl_add_u32 v1, s15, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x166, v2
	v_cmp_gt_i32_e64 s3, 6, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, 0x27e, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mul_lo_u32 v1, 0x37c34, v1
	v_mul_lo_u32 v2, 0x27e, v2
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v2, v0, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, 0xbb800000, v2
	v_mul_f32_e32 v3, 0x3fb8aa3b, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0x3fb8aa3b, v2, -v3
	v_rndne_f32_e32 v5, v3
	v_sub_f32_e32 v3, v3, v5
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v4, v2, 0x32a5705f, v4
	v_add_f32_e32 v3, v3, v4
	v_cvt_i32_f32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v3, v3, v4
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
	v_add_f32_e32 v2, 1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v2, v2, 0x437fffbe
	v_div_scale_f32 v6, vcc_lo, 0x437fffbe, v2, 0x437fffbe
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v5, v6
	v_div_fmas_f32 v3, v3, v4, v5
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v3, v2, 0x437fffbe
	v_cvt_i32_f32_e32 v2, v2
	global_store_b8 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14layer1_sigmoidPfPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14layer1_sigmoidPfPh, .Lfunc_end2-_Z14layer1_sigmoidPfPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16layer1_init_biasPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16layer1_init_biasPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 1348
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19layer1_feature_mapsPfPhS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19layer1_feature_mapsPfPhS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14layer1_sigmoidPfPh
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14layer1_sigmoidPfPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
