__device__ float Pq2Luma(float N) {
  float pq_m1 = 0.1593017578125; // ( 2610.0 / 4096.0 ) / 4.0;
  float pq_m2 = 78.84375; // ( 2523.0 / 4096.0 ) * 128.0;
  float pq_c1 = 0.8359375; // 3424.0 / 4096.0 or pq_c3 - pq_c2 + 1.0;
  float pq_c2 = 18.8515625; // ( 2413.0 / 4096.0 ) * 32.0;
  float pq_c3 = 18.6875; // ( 2392.0 / 4096.0 ) * 32.0;
  float pq_C = 10000.0;

  float Np = powf( N, 1.0 / pq_m2 );
  float L = Np - pq_c1;
  if ( L < 0.0 ) {
    L = 0.0;
  }
  L = L / ( pq_c2 - pq_c3 * Np );
  L = powf( L, 1.0 / pq_m1 );
  L = L * pq_C;
  return L; // returns cd/m^2
}

__device__ float Luma2Pq(float C) {
  float pq_m1 = 0.1593017578125; // ( 2610.0 / 4096.0 ) / 4.0;
  float pq_m2 = 78.84375; // ( 2523.0 / 4096.0 ) * 128.0;
  float pq_c1 = 0.8359375; // 3424.0 / 4096.0 or pq_c3 - pq_c2 + 1.0;
  float pq_c2 = 18.8515625; // ( 2413.0 / 4096.0 ) * 32.0;
  float pq_c3 = 18.6875; // ( 2392.0 / 4096.0 ) * 32.0;
  float pq_C = 10000.0;

  float L = C / pq_C;
  float Lm = powf( L, pq_m1 );
  float N = ( pq_c1 + pq_c2 * Lm ) / ( 1.0 + pq_c3 * Lm );
  N = powf( N, pq_m2 );
  return N;
}

__device__ float Luma(float R, float G, float B) {
  float lumaRec2020 = R * 0.2627f + G * 0.6780f + B * 0.0593f;
  return lumaRec2020;
} 


__global__ void LegalOverlayKernel(int p_Width, int p_Height, float p_Luminance, float p_OverlayR, float p_OverlayG, float p_OverlayB, int p_OverlayDisplay, int p_OverlayLuma, const float* p_Input, float* p_Output)
{
   const int x = blockIdx.x * blockDim.x + threadIdx.x;
   const int y = blockIdx.y * blockDim.y + threadIdx.y;

   if ((x < p_Width) && (y < p_Height))
   {
       const int index = ((y * p_Width) + x) * 4;
      
      float t = Luma2Pq(p_Luminance);
      int overlay = p_OverlayDisplay;
      int lumaWarn = p_OverlayLuma;

      float rOver, gOver, bOver;
      rOver = p_OverlayR / 100;
      gOver = p_OverlayG / 100;
      bOver = p_OverlayB / 100;

      float r, g, b, a;
      r = p_Input[index + 0];
      g = p_Input[index + 1];
      b = p_Input[index + 2];
      a = p_Input[index + 3];

      if  (lumaWarn && overlay) {
        float rY, gY, bY;
        rY = Pq2Luma(r);
        gY = Pq2Luma(g);
        bY = Pq2Luma(b);
        float luma = Luma(rY, gY, bY);
        float pqLuma = Luma2Pq(luma);
        if ( pqLuma >= t ) {
          // if any channel is over threshold, replace with overlay color
          r = rOver;
          g = gOver;
          b = bOver;
        }
      } else if (overlay && ( r >= t || g >= t || b >= t ) ) {
        r = rOver;
        g = gOver;
        b = bOver;
      }

      p_Output[index + 0] = r;
      p_Output[index + 1] = g;
      p_Output[index + 2] = b;
      p_Output[index + 3] = a;   
   }
}

void RunCudaKernel(int p_Width, int p_Height, float p_Luminance, float* p_OverlayRgb, int p_OverlayDisplay, int p_OverlayLuma, const float* p_Input, float* p_Output)
{
    dim3 threads(128, 1, 1);
    dim3 blocks(((p_Width + threads.x - 1) / threads.x), p_Height, 1);

    LegalOverlayKernel<<<blocks, threads>>>(p_Width, p_Height, p_Luminance, p_OverlayRgb[0], p_OverlayRgb[1], p_OverlayRgb[2], p_OverlayDisplay, p_OverlayLuma, p_Input, p_Output);
}



	.file	"tmpxft_0024fe78_00000000-6_CudaKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7Pq2Lumaf
	.type	_Z7Pq2Lumaf, @function
_Z7Pq2Lumaf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z7Pq2Lumaf, .-_Z7Pq2Lumaf
	.globl	_Z7Luma2Pqf
	.type	_Z7Luma2Pqf, @function
_Z7Luma2Pqf:
.LFB2156:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z7Pq2Lumaf
	.cfi_endproc
.LFE2156:
	.size	_Z7Luma2Pqf, .-_Z7Luma2Pqf
	.globl	_Z4Lumafff
	.type	_Z4Lumafff, @function
_Z4Lumafff:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z4Lumafff, .-_Z4Lumafff
	.globl	_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf
	.type	_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf, @function
_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movss	%xmm0, 36(%rsp)
	movss	%xmm1, 32(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z18LegalOverlayKerneliiffffiiPKfPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf, .-_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf
	.globl	_Z18LegalOverlayKerneliiffffiiPKfPf
	.type	_Z18LegalOverlayKerneliiffffiiPKfPf, @function
_Z18LegalOverlayKerneliiffffiiPKfPf:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf
	.cfi_endproc
.LFE2037:
	.size	_Z18LegalOverlayKerneliiffffiiPKfPf, .-_Z18LegalOverlayKerneliiffffiiPKfPf
	.globl	_Z13RunCudaKerneliifPfiiPKfS_
	.type	_Z13RunCudaKerneliifPfiiPKfS_, @function
_Z13RunCudaKerneliifPfiiPKfS_:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	127(%rdi), %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$7, %eax
	movq	%r9, %r14
	xorl	%r9d, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdx, %rbx
	movl	$33554433, %edx
	salq	$7, %rdx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%esi, 40(%rsp)
	movl	$1, %esi
	movq	112(%rsp), %r15
	movl	%eax, 36(%rsp)
	movq	36(%rsp), %rdi
	movl	%ecx, 8(%rsp)
	movl	$1, %ecx
	movss	%xmm0, 12(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L14
	movss	8(%rbx), %xmm3
	movss	4(%rbx), %xmm2
	movq	%r15, %r9
	movq	%r14, %r8
	movss	(%rbx), %xmm1
	movl	8(%rsp), %edx
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r13d, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%r12d, %esi
	movl	%ebp, %edi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z49__device_stub__Z18LegalOverlayKerneliiffffiiPKfPfiiffffiiPKfPf
.L14:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	_Z13RunCudaKerneliifPfiiPKfS_, .-_Z13RunCudaKerneliifPfiiPKfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18LegalOverlayKerneliiffffiiPKfPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18LegalOverlayKerneliiffffiiPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ float Pq2Luma(float N) {
  float pq_m1 = 0.1593017578125; // ( 2610.0 / 4096.0 ) / 4.0;
  float pq_m2 = 78.84375; // ( 2523.0 / 4096.0 ) * 128.0;
  float pq_c1 = 0.8359375; // 3424.0 / 4096.0 or pq_c3 - pq_c2 + 1.0;
  float pq_c2 = 18.8515625; // ( 2413.0 / 4096.0 ) * 32.0;
  float pq_c3 = 18.6875; // ( 2392.0 / 4096.0 ) * 32.0;
  float pq_C = 10000.0;

  float Np = powf( N, 1.0 / pq_m2 );
  float L = Np - pq_c1;
  if ( L < 0.0 ) {
    L = 0.0;
  }
  L = L / ( pq_c2 - pq_c3 * Np );
  L = powf( L, 1.0 / pq_m1 );
  L = L * pq_C;
  return L; // returns cd/m^2
}

__device__ float Luma2Pq(float C) {
  float pq_m1 = 0.1593017578125; // ( 2610.0 / 4096.0 ) / 4.0;
  float pq_m2 = 78.84375; // ( 2523.0 / 4096.0 ) * 128.0;
  float pq_c1 = 0.8359375; // 3424.0 / 4096.0 or pq_c3 - pq_c2 + 1.0;
  float pq_c2 = 18.8515625; // ( 2413.0 / 4096.0 ) * 32.0;
  float pq_c3 = 18.6875; // ( 2392.0 / 4096.0 ) * 32.0;
  float pq_C = 10000.0;

  float L = C / pq_C;
  float Lm = powf( L, pq_m1 );
  float N = ( pq_c1 + pq_c2 * Lm ) / ( 1.0 + pq_c3 * Lm );
  N = powf( N, pq_m2 );
  return N;
}

__device__ float Luma(float R, float G, float B) {
  float lumaRec2020 = R * 0.2627f + G * 0.6780f + B * 0.0593f;
  return lumaRec2020;
} 


__global__ void LegalOverlayKernel(int p_Width, int p_Height, float p_Luminance, float p_OverlayR, float p_OverlayG, float p_OverlayB, int p_OverlayDisplay, int p_OverlayLuma, const float* p_Input, float* p_Output)
{
   const int x = blockIdx.x * blockDim.x + threadIdx.x;
   const int y = blockIdx.y * blockDim.y + threadIdx.y;

   if ((x < p_Width) && (y < p_Height))
   {
       const int index = ((y * p_Width) + x) * 4;
      
      float t = Luma2Pq(p_Luminance);
      int overlay = p_OverlayDisplay;
      int lumaWarn = p_OverlayLuma;

      float rOver, gOver, bOver;
      rOver = p_OverlayR / 100;
      gOver = p_OverlayG / 100;
      bOver = p_OverlayB / 100;

      float r, g, b, a;
      r = p_Input[index + 0];
      g = p_Input[index + 1];
      b = p_Input[index + 2];
      a = p_Input[index + 3];

      if  (lumaWarn && overlay) {
        float rY, gY, bY;
        rY = Pq2Luma(r);
        gY = Pq2Luma(g);
        bY = Pq2Luma(b);
        float luma = Luma(rY, gY, bY);
        float pqLuma = Luma2Pq(luma);
        if ( pqLuma >= t ) {
          // if any channel is over threshold, replace with overlay color
          r = rOver;
          g = gOver;
          b = bOver;
        }
      } else if (overlay && ( r >= t || g >= t || b >= t ) ) {
        r = rOver;
        g = gOver;
        b = bOver;
      }

      p_Output[index + 0] = r;
      p_Output[index + 1] = g;
      p_Output[index + 2] = b;
      p_Output[index + 3] = a;   
   }
}

void RunCudaKernel(int p_Width, int p_Height, float p_Luminance, float* p_OverlayRgb, int p_OverlayDisplay, int p_OverlayLuma, const float* p_Input, float* p_Output)
{
    dim3 threads(128, 1, 1);
    dim3 blocks(((p_Width + threads.x - 1) / threads.x), p_Height, 1);

    LegalOverlayKernel<<<blocks, threads>>>(p_Width, p_Height, p_Luminance, p_OverlayRgb[0], p_OverlayRgb[1], p_OverlayRgb[2], p_OverlayDisplay, p_OverlayLuma, p_Input, p_Output);
}



	.text
	.file	"CudaKernel.hip"
	.globl	_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf # -- Begin function _Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf
	.type	_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf,@function
_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf: # @_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	4(%rsp), %r15
	movl	%edx, (%r15)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%r15, 48(%rbx)
	movq	%rdx, 56(%rbx)
	movq	%rcx, 64(%rbx)
	movq	%r8, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18LegalOverlayKerneliiffffiiPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf, .Lfunc_end0-_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z13RunCudaKerneliifPfiiPKfS_   # -- Begin function _Z13RunCudaKerneliifPfiiPKfS_
	.type	_Z13RunCudaKerneliifPfiiPKfS_,@function
_Z13RunCudaKerneliifPfiiPKfS_:          # @_Z13RunCudaKerneliifPfiiPKfS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movq	%rdx, %r12
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movl	%esi, %r13d
	movl	%edi, %ebx
	movq	80(%rsp), %r15
	leal	127(%rbx), %eax
	shrl	$7, %eax
	movq	%r13, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 80
	movss	(%r12), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movss	4(%r12), %xmm2                  # xmm2 = mem[0],zero,zero,zero
	movss	8(%r12), %xmm3                  # xmm3 = mem[0],zero,zero,zero
	movl	%ebx, %edi
	movl	%r13d, %esi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	16(%rsp), %r8                   # 8-byte Reload
	movq	%r15, %r9
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf # TAILCALL
.Lfunc_end1:
	.size	_Z13RunCudaKerneliifPfiiPKfS_, .Lfunc_end1-_Z13RunCudaKerneliifPfiiPKfS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18LegalOverlayKerneliiffffiiPKfPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18LegalOverlayKerneliiffffiiPKfPf,@object # @_Z18LegalOverlayKerneliiffffiiPKfPf
	.section	.rodata,"a",@progbits
	.globl	_Z18LegalOverlayKerneliiffffiiPKfPf
	.p2align	3, 0x0
_Z18LegalOverlayKerneliiffffiiPKfPf:
	.quad	_Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf
	.size	_Z18LegalOverlayKerneliiffffiiPKfPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18LegalOverlayKerneliiffffiiPKfPf"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__LegalOverlayKerneliiffffiiPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18LegalOverlayKerneliiffffiiPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z7Luma2Pqf
	.type	_Z7Luma2Pqf,@function
_Z7Luma2Pqf:                            ; @_Z7Luma2Pqf
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_div_scale_f32 v1, null, 0x461c4000, 0x461c4000, v0
	v_div_scale_f32 v4, vcc_lo, v0, 0x461c4000, v0
	s_mov_b32 s2, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v4, v2
	v_fma_f32 v5, -v1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v5, v2
	v_fma_f32 v1, -v1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v3
	v_div_fixup_f32 v0, v1, 0x461c4000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v1, |v0|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, v2
	v_add_f32_e32 v4, -1.0, v1
	v_add_f32_e32 v2, 1.0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, v4, v3 :: v_dual_add_f32 v6, -1.0, v2
	v_mul_f32_e32 v7, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v6
	v_fma_f32 v2, v5, v2, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v1
	v_add_f32_e32 v1, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
	v_sub_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_sub_f32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v2, v1
	v_add_f32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v3, v1
	v_add_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v2, v5
	v_dual_mul_f32 v4, v2, v2 :: v_dual_sub_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v2, v2, -v4
	v_add_f32_e32 v5, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v2, v5
	v_add_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	v_mul_f32_e32 v9, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v5, v6
	v_fma_f32 v10, v5, v2, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v6, -v7
	v_fmac_f32_e32 v4, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v5, v1
	v_ldexp_f32 v1, v1, 1
	v_add_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v3, v2
	v_ldexp_f32 v2, v2, 1
	v_dual_sub_f32 v7, v6, v7 :: v_dual_add_f32 v8, 0x3f2aaaaa, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v7, 0xbf2aaaaa, v8
	v_add_f32_e32 v4, 0x31739010, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_dual_add_f32 v5, v9, v10 :: v_dual_sub_f32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v5, v3, -v7
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_add_f32_e32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_add_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v4, v7 :: v_dual_sub_f32 v2, v5, v2
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, 0x3f317218, v3
	v_sub_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v1, v6
	v_fma_f32 v7, 0x3f317218, v3, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v1, v2
	v_fmac_f32_e32 v7, 0xb102e308, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v5, v1 :: v_dual_add_f32 v2, v8, v7
	v_sub_f32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v5 :: v_dual_add_f32 v4, v2, v3
	v_sub_f32_e32 v6, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v3, v6 :: v_dual_sub_f32 v8, v2, v8
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v1
	v_sub_f32_e32 v9, v4, v6
	v_sub_f32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v3, v2 :: v_dual_sub_f32 v3, v5, v7
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v2
	v_sub_f32_e32 v5, v5, v3
	v_dual_sub_f32 v3, v7, v5 :: v_dual_add_f32 v6, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v6, v4
	v_cndmask_b32_e64 v3, 0x3e232000, 1.0, vcc_lo
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v2, v6
	v_sub_f32_e32 v1, v1, v4
	v_mul_f32_e32 v5, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v2, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v5, v2
	v_cndmask_b32_e32 v4, v1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_sub_f32_e32 v7, v4, v6
	v_trunc_f32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
	v_add_f32_e32 v8, v8, v9
	v_sub_f32_e32 v1, v1, v5
	v_cvt_i32_f32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v8, v8
	v_sub_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_dual_mul_f32 v5, 0.5, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v8, v5
	v_dual_add_f32 v1, v6, v1 :: v_dual_cndmask_b32 v2, 0x7f800000, v2
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v8, v5
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e64 s1, 0x7f800000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v3, 1.0, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v1, v2, s1
	v_cmp_eq_f32_e64 s1, 0, v0
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v3, 0, v0, s0
	v_cmp_class_f32_e64 s0, v0, 0x204
	v_cndmask_b32_e32 v4, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v2, v3
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_mov_b32 s0, 0x4196d000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_cndmask_b32_e32 v2, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x41958000, v2
	v_fmaak_f32 v2, s0, v2, 0x3f560000
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[2:3], v2
	v_add_f64 v[0:1], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[0:1], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3]
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v1, |v0|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, v2
	v_add_f32_e32 v2, 1.0, v1
	v_add_f32_e32 v4, -1.0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	v_add_f32_e32 v6, -1.0, v2
	v_sub_f32_e32 v1, v1, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v2, v5
	v_fma_f32 v2, v5, v2, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v1
	v_add_f32_e32 v1, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v4, v1
	v_dual_sub_f32 v4, v4, v6 :: v_dual_sub_f32 v7, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v4, v1 :: v_dual_sub_f32 v2, v7, v2
	v_add_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v6, v1
	v_mul_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v1
	v_sub_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v2, v2 :: v_dual_sub_f32 v1, v1, v3
	v_fma_f32 v3, v2, v2, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v1, v1
	v_fmac_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v4, v3
	v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	v_mul_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v6, -v7
	v_fmac_f32_e32 v4, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v4
	v_dual_sub_f32 v7, v6, v7 :: v_dual_add_f32 v8, 0x3f2aaaaa, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v7 :: v_dual_mul_f32 v9, v2, v5
	v_add_f32_e32 v4, 0x31739010, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v5, v2, -v9
	v_dual_add_f32 v7, 0xbf2aaaaa, v8 :: v_dual_fmac_f32 v10, v5, v1
	v_ldexp_f32 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v3, v2
	v_sub_f32_e32 v6, v6, v7
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v9, v10
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v6, v8, v3
	v_sub_f32_e32 v8, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v4, v4, v6
	v_fma_f32 v6, v5, v3, -v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v10, v8
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v8, v3
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v7, v6
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v4, v7
	v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v7
	v_fma_f32 v7, 0x3f317218, v3, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v1, v6
	v_dual_fmac_f32 v7, 0xb102e308, v3 :: v_dual_sub_f32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v4, v2
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v5, v1 :: v_dual_add_f32 v2, v8, v7
	v_dual_sub_f32 v5, v3, v5 :: v_dual_add_f32 v4, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v6, v4, v2
	v_sub_f32_e32 v9, v4, v6
	v_dual_sub_f32 v3, v3, v6 :: v_dual_sub_f32 v8, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, v2, v9 :: v_dual_sub_f32 v7, v7, v8
	v_add_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v1
	v_sub_f32_e32 v3, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v5, v2
	v_sub_f32_e32 v5, v5, v3
	v_sub_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v7, v5 :: v_dual_add_f32 v6, v4, v2
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v6, v4
	v_cndmask_b32_e64 v3, 0x429db000, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v6, v1
	v_sub_f32_e32 v4, v2, v6
	v_mul_f32_e32 v5, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v4
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v1
	v_add_f32_e32 v1, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v1, v5, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v4, v6
	v_trunc_f32_e32 v4, v3
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v8, v9
	v_sub_f32_e32 v1, v1, v5
	v_cvt_i32_f32_e32 v5, v10
	v_exp_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v2, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_mul_f32_e32 v5, 0.5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v1, v6, v1 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	v_trunc_f32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	v_cmp_neq_f32_e64 s0, v8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e64 s1, 0x7f800000, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 1.0, v0, s0
	v_cndmask_b32_e64 v4, 0, v0, s0
	v_cndmask_b32_e64 v1, v1, v2, s1
	v_cmp_eq_f32_e64 s1, 0, v0
	v_cmp_class_f32_e64 s0, v0, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	v_cndmask_b32_e64 v2, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_bfi_b32 v2, 0x7fffffff, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z7Luma2Pqf, .Lfunc_end0-_Z7Luma2Pqf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2380
; NumSgprs: 34
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z7Pq2Lumaf
	.type	_Z7Pq2Lumaf,@function
_Z7Pq2Lumaf:                            ; @_Z7Pq2Lumaf
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_frexp_mant_f32_e64 v1, |v0|
	s_mov_b32 s2, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_ldexp_f32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, -1.0, v1
	v_add_f32_e32 v2, 1.0, v1
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, v4, v3 :: v_dual_add_f32 v6, -1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v2, v5
	v_sub_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v5, v2, -v7
	v_fmac_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v7, v2
	v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v7, v2
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v4, v1
	v_add_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v6, v1
	v_mul_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v1
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v3
	v_fma_f32 v3, v2, v2, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v1, v1
	v_fmac_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v4, v3
	v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	v_mul_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v6, -v7
	v_dual_fmac_f32 v4, v3, v6 :: v_dual_mul_f32 v9, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v7, v4
	v_fma_f32 v10, v5, v2, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v7, v6, v7 :: v_dual_fmac_f32 v10, v5, v1
	v_add_f32_e32 v8, 0x3f2aaaaa, v6
	v_ldexp_f32 v1, v1, 1
	v_sub_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v3, v2
	v_ldexp_f32 v2, v2, 1
	v_add_f32_e32 v4, 0x31739010, v4
	v_add_f32_e32 v7, 0xbf2aaaaa, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_dual_add_f32 v5, v9, v10 :: v_dual_sub_f32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v5, v3, -v7
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_add_f32_e32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_sub_f32_e32 v7, v4, v7
	v_add_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, 0x3f317218, v3, -v8
	v_dual_fmac_f32 v7, 0xb102e308, v3 :: v_dual_sub_f32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v4, v2
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v5, v1 :: v_dual_add_f32 v2, v8, v7
	v_dual_sub_f32 v5, v3, v5 :: v_dual_add_f32 v4, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v6, v4, v2
	v_dual_sub_f32 v3, v3, v6 :: v_dual_sub_f32 v8, v2, v8
	v_sub_f32_e32 v9, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v8
	v_add_f32_e32 v5, v7, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v9
	v_dual_add_f32 v2, v3, v2 :: v_dual_sub_f32 v3, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v3
	v_add_f32_e32 v2, v5, v2
	v_sub_f32_e32 v5, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v7, v5 :: v_dual_add_f32 v6, v4, v2
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v6, v4
	v_cndmask_b32_e64 v3, 0x3c4fcdac, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v6, v1
	v_sub_f32_e32 v4, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v4
	v_mul_f32_e32 v5, v3, v2
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v1
	v_add_f32_e32 v1, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v1, v5, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v4, v6
	v_trunc_f32_e32 v4, v3
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v8, v9
	v_sub_f32_e32 v1, v1, v5
	v_cvt_i32_f32_e32 v5, v10
	v_exp_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v2, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	v_dual_mul_f32 v5, 0.5, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v8, v5
	v_dual_add_f32 v1, v6, v1 :: v_dual_cndmask_b32 v2, 0x7f800000, v2
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v8, v5
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e64 s1, 0x7f800000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v3, 1.0, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v1, v2, s1
	v_cmp_eq_f32_e64 s1, 0, v0
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v3, 0, v0, s0
	v_cmp_class_f32_e64 s0, v0, 0x204
	v_cndmask_b32_e32 v4, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v2, v3
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_mov_b32 s0, 0xc1958000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, 0xbf560000, v0
	v_fmaak_f32 v0, s0, v0, 0x4196d000
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v0, v0, v1
	v_div_scale_f32 v5, vcc_lo, v1, v0, v1
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_mul_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v4, v5
	v_fmac_f32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v4, v5
	v_div_fmas_f32 v2, v2, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v2, v0, v1
	v_frexp_mant_f32_e64 v1, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_ldexp_f32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, 1.0, v1
	v_add_f32_e32 v4, -1.0, v1
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, v4, v3 :: v_dual_add_f32 v6, -1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v2, v5
	v_sub_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v5, v2, -v7
	v_fmac_f32_e32 v2, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v7, v2
	v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v7, v2
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v4, v1
	v_add_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v6, v1
	v_mul_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v5, v1
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v3
	v_fma_f32 v3, v2, v2, -v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v1, v1
	v_fmac_f32_e32 v3, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v4, v3
	v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	v_mul_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v6, -v7
	v_dual_fmac_f32 v4, v3, v6 :: v_dual_mul_f32 v9, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v7, v4
	v_fma_f32 v10, v5, v2, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v7, v6, v7 :: v_dual_fmac_f32 v10, v5, v1
	v_add_f32_e32 v8, 0x3f2aaaaa, v6
	v_ldexp_f32 v1, v1, 1
	v_sub_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v3, v2
	v_ldexp_f32 v2, v2, 1
	v_add_f32_e32 v4, 0x31739010, v4
	v_add_f32_e32 v7, 0xbf2aaaaa, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v9, v10 :: v_dual_sub_f32 v6, v6, v7
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_sub_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v5, v3, -v7
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, v0
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_add_f32_e32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_sub_f32_e32 v7, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v5, v2, v4
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3f317218, v3, -v8
	v_add_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, 0xb102e308, v3 :: v_dual_sub_f32 v2, v5, v2
	v_sub_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_dual_add_f32 v3, v5, v1 :: v_dual_add_f32 v2, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v3, v5 :: v_dual_add_f32 v4, v2, v3
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v6, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v4, v6
	v_dual_sub_f32 v3, v3, v6 :: v_dual_sub_f32 v8, v2, v8
	v_dual_sub_f32 v2, v2, v9 :: v_dual_sub_f32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v3, v2
	v_add_f32_e32 v5, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v5, v7
	v_add_f32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v3
	v_sub_f32_e32 v1, v1, v3
	v_dual_sub_f32 v3, v7, v5 :: v_dual_add_f32 v6, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v6, v4
	v_cndmask_b32_e64 v3, 0x40c8e06b, 1.0, vcc_lo
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, v3, v2
	v_sub_f32_e32 v4, v2, v6
	v_fma_f32 v2, v3, v2, -v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v4
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v2, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v5, v2
	v_cndmask_b32_e32 v4, v1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_sub_f32_e32 v7, v4, v6
	v_trunc_f32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
	v_add_f32_e32 v8, v8, v9
	v_sub_f32_e32 v1, v1, v5
	v_cvt_i32_f32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v8, v8
	v_sub_f32_e32 v1, v2, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v5, 0.5, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	v_trunc_f32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v1, v6, v1 :: v_dual_cndmask_b32 v2, 0x7f800000, v2
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	v_cmp_neq_f32_e64 s0, v8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e64 s1, 0x7f800000, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 1.0, v0, s0
	v_cndmask_b32_e64 v4, 0, v0, s0
	v_cndmask_b32_e64 v1, v1, v2, s1
	v_cmp_eq_f32_e64 s1, 0, v0
	v_cmp_class_f32_e64 s0, v0, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	v_cndmask_b32_e64 v2, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_bfi_b32 v2, 0x7fffffff, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x461c4000, v1
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	_Z7Pq2Lumaf, .Lfunc_end1-_Z7Pq2Lumaf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2240
; NumSgprs: 34
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z18LegalOverlayKerneliiffffiiPKfPf ; -- Begin function _Z18LegalOverlayKerneliiffffiiPKfPf
	.globl	_Z18LegalOverlayKerneliiffffiiPKfPf
	.p2align	8
	.type	_Z18LegalOverlayKerneliiffffiiPKfPf,@function
_Z18LegalOverlayKerneliiffffiiPKfPf:    ; @_Z18LegalOverlayKerneliiffffiiPKfPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_11
; %bb.1:
	s_load_b128 s[12:15], s[0:1], 0x20
	v_mul_lo_u32 v1, v1, s4
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z7Luma2Pqf@rel32@lo+4
	s_addc_u32 s1, s1, _Z7Luma2Pqf@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_lshl_u32 v12, v1, v0, 2
	v_mov_b32_e32 v0, s6
	s_swappc_b64 s[30:31], s[0:1]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v16, v0
	s_mov_b32 s0, 0x42c80000
	s_cmp_eq_u32 s11, 0
	v_div_scale_f32 v4, null, s0, s0, s9
	v_lshlrev_b64 v[18:19], 2, v[12:13]
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	v_add_co_u32 v0, vcc_lo, s12, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v19, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v4, v6, 1.0
	global_load_b128 v[12:15], v[0:1], off
	v_div_scale_f32 v0, null, s0, s0, s7
	v_div_scale_f32 v1, null, s0, s0, s8
	v_fmac_f32_e32 v6, v9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v2, v0
	v_div_scale_f32 v9, s1, s9, 0x42c80000, s9
	v_rcp_f32_e32 v3, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v0, v2, 1.0
	v_fma_f32 v7, -v1, v3, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v5, v2
	v_div_scale_f32 v5, vcc_lo, s7, 0x42c80000, s7
	v_fmac_f32_e32 v3, v7, v3
	v_div_scale_f32 v7, s0, s8, 0x42c80000, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, v5, v2
	v_mul_f32_e32 v10, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v0, v8, v5
	v_fmac_f32_e32 v8, v11, v2
	v_mul_f32_e32 v11, v9, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, -v1, v10, v7
	v_fma_f32 v0, -v0, v8, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, -v4, v11, v9
	v_fmac_f32_e32 v10, v17, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v0, v0, v2, v8
	v_fmac_f32_e32 v11, v5, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v1, -v1, v10, v7
	s_mov_b32 vcc_lo, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s10, 0
	v_fma_f32 v2, -v4, v11, v9
	v_div_fmas_f32 v1, v1, v3, v10
	s_mov_b32 vcc_lo, s1
	s_cselect_b32 s1, -1, 0
	v_div_fixup_f32 v20, v0, 0x42c80000, s7
	v_div_fmas_f32 v2, v2, v6, v11
	v_div_fixup_f32 v21, v1, 0x42c80000, s8
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s1
	v_div_fixup_f32 v22, v2, 0x42c80000, s9
	s_cbranch_vccz .LBB2_7
; %bb.2:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v12 :: v_dual_mov_b32 v1, v13
	v_mov_b32_e32 v2, v14
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_6
; %bb.3:
	v_max3_f32 v2, v12, v13, v14
	v_dual_mov_b32 v0, v12 :: v_dual_mov_b32 v1, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ge_f32_e32 vcc_lo, v2, v16
	v_mov_b32_e32 v2, v14
	s_and_saveexec_b32 s0, vcc_lo
; %bb.4:
	v_dual_mov_b32 v0, v20 :: v_dual_mov_b32 v1, v21
	v_mov_b32_e32 v2, v22
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
.LBB2_6:                                ; %Flow105
	s_mov_b32 s0, 0
	s_branch .LBB2_8
.LBB2_7:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr0
.LBB2_8:                                ; %Flow106
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_10
; %bb.9:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, v12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, _Z7Pq2Lumaf@rel32@lo+4
	s_addc_u32 s5, s5, _Z7Pq2Lumaf@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[4:5]
	v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v0, v13
	s_swappc_b64 s[30:31], s[4:5]
	v_dual_mov_b32 v17, v0 :: v_dual_mov_b32 v0, v14
	s_swappc_b64 s[30:31], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x3f2d9168, v17
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z7Luma2Pqf@rel32@lo+4
	s_addc_u32 s1, s1, _Z7Luma2Pqf@rel32@hi+12
	v_fmamk_f32 v1, v11, 0x3e86809d, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v0, 0x3d72e48f, v1
	s_swappc_b64 s[30:31], s[0:1]
	v_cmp_nge_f32_e32 vcc_lo, v0, v16
	v_dual_cndmask_b32 v2, v22, v14 :: v_dual_cndmask_b32 v1, v21, v13
	v_cndmask_b32_e32 v0, v20, v12, vcc_lo
.LBB2_10:
	v_add_co_u32 v4, vcc_lo, s14, v18
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v19, vcc_lo
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v3, v15
	global_store_b128 v[4:5], v[0:3], off
.LBB2_11:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18LegalOverlayKerneliiffffiiPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18LegalOverlayKerneliiffffiiPKfPf, .Lfunc_end2-_Z18LegalOverlayKerneliiffffiiPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 808
; NumSgprs: 35
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18LegalOverlayKerneliiffffiiPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z18LegalOverlayKerneliiffffiiPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
