//matrix_mult.cu
//template provided by Prof. Andrew Grimshaw
//implementation by Jerry Sun(ys7va) 2017.05.08
//the program will take 4 parameters to specify the size of two matrices
//if only provided 1 value N, it will calculate the multiplication of two N * N matrices
#include<stdio.h>
#include<sys/time.h>
#include<stdlib.h>
#include<iostream>
#include<cuda_runtime.h>
using namespace std;

//Macro to specify block size
#define T_block 32

//----------------------------------- Structures and Globals---------------------------------------------
//store dimension of a matrix
typedef struct {
	int dimension1;
	int dimension2;
} ArrayMetadata2D;

// metadata variables describing dimensionalities of all data structures involved in the computation
ArrayMetadata2D A_MD, B_MD, C_MD;
// pointers for input and output arrays in the host memory
// *_CPU is for CPU calculation
// C_GPU_result is for storing GPU calculation result
float *A_CPU, *B_CPU, *C_CPU, *C_GPU_result;
// pointers for input and output arrays in the device memory (NVIDIA DRAM)
float *A_GPU, *B_GPU, *C_GPU;

//----------------------------------- host function definitions -----------------------------------------
void allocateAndInitializeHost();       //allocate and initialize all necessary memory on host machine
void computeCpuMMM();                   //matrix multiplication on CPU
void computeGpuMMM();                   //matrix multiplication on GPU, may use different kernel method
void copyMatricesToGPU();               //copy value in A_CPU & B_CPU to A_GPU & B_GPU respectively
void copyResultFromGPU();               //copy calculated value in C_GPU back into C_GPU_result
void compareHostAndGpuOutput();         //check if the result in C_GPU_result and C_CPU is identical
void die(const char *error);            //end the program
void check_error(cudaError e);          //check memory allocation on cuda
long long start_timer();                //timer for measurement
long long stop_timer(long long start_time, const char *name);  //timer for measurement

//----------------------------------- CUDA function definitions -----------------------------------------
//baseline approach for kernel method, each thread is responsible for one cell in final result
__global__ void mult_matrix_baseline(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3);
//shared memory version for kernel method, a block of threads read data from DRAM together into shared
//memory and then do calculation block-wise
__global__ void mult_matrix_shared(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3);


//-------------------------------------------------------------------------------------------------------
int main(int argc, char **argv) {
    //parse the command-line argument
	A_MD.dimension1 = (argc > 1) ? atoi(argv[1]) : 100;
	A_MD.dimension2 = (argc > 2) ? atoi(argv[2]) : A_MD.dimension1;
	B_MD.dimension1 = (argc > 3) ? atoi(argv[3]) : A_MD.dimension2;
	B_MD.dimension2 = (argc > 4) ? atoi(argv[4]) : B_MD.dimension1;
	C_MD.dimension1 = A_MD.dimension1;
	C_MD.dimension2 = B_MD.dimension2;

	printf("Matrix A is %d-by-%d\n", A_MD.dimension1, A_MD.dimension2);
	printf("Matrix B is %d-by-%d\n", B_MD.dimension1, B_MD.dimension2);
	printf("Matrix C is %d-by-%d\n", C_MD.dimension1, C_MD.dimension2);
    //if dim2 of A and dim1 of B is different then they can't be multiplied
	if (A_MD.dimension2 != B_MD.dimension1) die("Dimension inconsistent for two matrices");

    //allocate all necessary memory on host
	allocateAndInitializeHost();

	// matrix multiplication in the CPU, commented for large-scale
	// long long CPU_start_time = start_timer();
	// computeCpuMMM();
	// long long CPU_time = stop_timer(CPU_start_time, "\nCPU");

	// matrix multiplication on the GPU
	long long GPU_start_time = start_timer();
	computeGpuMMM();
	long long GPU_time = stop_timer(GPU_start_time, "\tTotal");

    //check the final result
	//commented when CPU result is not available
    //compareHostAndGpuOutput();

	return 0;
}


__global__ void mult_matrix_baseline(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3) {
    // retrieve the corresponding row & col in final output matrix
    int r = blockIdx.x * T_block + threadIdx.x;
    int c = blockIdx.y * T_block + threadIdx.y;
    // check if index is in bound
    if (r < dim_1 && c < dim_3) {
        float sum = 0;
        // calculate inner product of two vectors
        for (int i = 0; i < dim_2; i++) {
                sum += A[r * dim_1 + i] * B[i * dim_2 + c];
            }
        // assign final results
        C[r * dim_3 + c] = sum;
    }
}

// Compute C = A * B
__global__ void mult_matrix_shared(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3) {

  // store corresponding value in registers
  int b_x = blockIdx.x;
  int b_y = blockIdx.y;
  int t_x = threadIdx.x;
  int t_y = threadIdx.y;

  // retrieve row & col number in final output
  int r = b_y * T_block + t_y;
  int c = b_x * T_block + t_x;

  float s = 0;
  // initiate share memory space
  __shared__ float block_A[T_block][T_block];
  __shared__ float block_B[T_block][T_block];

  // bool variable to check if inbound
  bool inplace = r < dim_1 && c < dim_3;

  // iterate through all blocks in using a ceiling function to deal with corner cases
  for (int m = 0; m < (dim_2 - 1) / T_block + 1; m++) {
    // column num for the retrieved cell in matrix A
    int col = m * T_block + t_x;
    // load value from matrix A, if not available assign 0
    block_A[t_y][t_x] = (r < dim_1 && col < dim_2) ? A[r * dim_1 + col] : 0.0;
    // row num for the retrieved cell in matrix B
	int row = m * T_block + t_y;
    // load value from matrix B, if not available assign 0
	block_B[t_y][t_x] = (row < dim_2 && c < dim_3) ? B[row * dim_3 + c] : 0.0;
    // sync all threads, wait till all threads finish loading
    __syncthreads();

    //if inplace calculate the inner product within two blocks in A and B
	if (inplace)
		for (int i = 0; i < T_block; i++)
			s += block_A[t_y][i] * block_B[i][t_x];
    //sync threads, wait till all threads finish using shared memory in current iteration
    __syncthreads();
  }

  //assign final result
  if (inplace)
    C[r * dim_3 + c] = s;
}

// GPU version MM
void computeGpuMMM() {
	copyMatricesToGPU();
    //for a matrix multiplication problem, only three dimensions are needed
    //two dims for the final matrix, and one for dim2 of A and dim1 of B(identical)
	int dim_1 = A_MD.dimension1;
	int dim_2 = A_MD.dimension2;
	int dim_3 = B_MD.dimension2;
    //initialize gridblock, and threadblock size
    //here we assume each thread always responsible for cell
    dim3 thread(T_block, T_block);
    //if dim_1 not divisible by T_block, we use ceiling function
    //in order to handle corner cases
    dim3 grid((dim_1 - 1) / T_block + 1, (dim_3 - 1) / T_block + 1);
	long long exec_start_time = start_timer();
	//call kernel method, passing in three GPU pointers and three dimensions
    mult_matrix_shared <<<grid, thread>>> (A_GPU, B_GPU, C_GPU, dim_1, dim_2, dim_3);
    //synchroniztion
	cudaThreadSynchronize();
	stop_timer(exec_start_time, "\tkernal excution time");
	//copy the result from GPU
	copyResultFromGPU();
}



// allocate and initialize A and B using a random number generator,
// also initialize C_CPU and C_GPU_resul
void allocateAndInitializeHost() {
	size_t sizeofA = A_MD.dimension1 * A_MD.dimension2 * sizeof(float);
	A_CPU = (float*) malloc(sizeofA);
	srand(time(NULL));
  	for (int i = 0; i < A_MD.dimension1; i++) {
		for (int j = 0; j < A_MD.dimension2; j++) {
			int index = i * A_MD.dimension2 + j;
			A_CPU[index] = (rand() % 1000) * 0.001;
		}
	}

	size_t sizeofB = B_MD.dimension1 * B_MD.dimension2 * sizeof(float);
	B_CPU = (float*) malloc(sizeofB);
  	for (int i = 0; i < B_MD.dimension1; i++) {
		for (int j = 0; j < B_MD.dimension2; j++) {
			int index = i * B_MD.dimension2 + j;
			B_CPU[index] = (rand() % 1000) * 0.001;
		}
	}

	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	C_GPU_result = (float*) malloc(sizeofC);
	C_CPU = (float*) malloc(sizeofC);

}

// allocate memory in the GPU for all matrices, and copy A and B content from the host CPU memory to the GPU memory
void copyMatricesToGPU() {
	long long memory_start_time = start_timer();
	size_t sizeofA = A_MD.dimension1 * A_MD.dimension2 * sizeof(float);
	check_error(cudaMalloc((void **) &A_GPU, sizeofA));
	check_error(cudaMemcpy(A_GPU, A_CPU, sizeofA, cudaMemcpyHostToDevice));

	size_t sizeofB = B_MD.dimension1 * B_MD.dimension2 * sizeof(float);
	check_error(cudaMalloc((void **) &B_GPU, sizeofB));
	check_error(cudaMemcpy(B_GPU, B_CPU, sizeofB, cudaMemcpyHostToDevice));

	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	check_error(cudaMalloc((void **) &C_GPU, sizeofC));
	stop_timer(memory_start_time, "\nGPU:\tTransfer to GPU");

}

// copy results from C_GPU which is in GPU card memory to C_CPU_result which is in the host CPU for result comparison
void copyResultFromGPU() {
	long long memory_start_time = start_timer();
	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	check_error(cudaMemcpy(C_GPU_result, C_GPU, sizeofC, cudaMemcpyDeviceToHost));
	stop_timer(memory_start_time, "\tTransfer from GPU");
}

// do a straightforward matrix-matrix multiplication in the CPU
// notice that this implementation can be massively improved in the CPU by doing proper cache blocking but we are
// not providing you the efficient CPU implementation as that reveals too much about the ideal GPU implementation
void computeCpuMMM() {

	// compute C[i][j] as the sum of A[i][k] * B[k][j] for all columns k of A
	for (int i = 0; i < A_MD.dimension1; i++) {
		int a_i = i * A_MD.dimension2;
		int c_i = i * C_MD.dimension2;
		for (int j = 0; j < B_MD.dimension2; j++) {
			int c_index = c_i + j;
			C_CPU[c_index] = 0;
			for (int k = 0; k < B_MD.dimension1; k++) {
				int a_index = a_i + k;
				int b_index = k * B_MD.dimension2 + j;
				C_CPU[c_index] += A_CPU[a_index] * B_CPU[b_index];
			}
		}
	}
}

// function to determine if the GPU computation is done correctly by comparing the output from the GPU with that
void compareHostAndGpuOutput() {
	int totalElements = C_MD.dimension1 * C_MD.dimension2;
	int missmatchCount = 0;
	for (int i = 0; i < totalElements; i++) {
		if (fabs(C_GPU_result[i] - C_CPU[i]) > 0.01) {
			missmatchCount++;
			printf("mismatch at index %i: %f\t%f\n", i, C_CPU[i], C_GPU_result[i]);
		}
	}
	if (missmatchCount > 0) {
		printf("Computation is incorrect: outputs do not match in %d indexes\n", missmatchCount);
	} else {
		printf("Computation is correct: CPU and GPU outputs match\n");
	}
}

// Prints the specified error message and then exits
void die(const char *error) {
        printf("%s", error);
        exit(1);
}

// If the specified error code refers to a real error, report it and quit the program
void check_error(cudaError e) {
        if (e != cudaSuccess) {
                printf("\nCUDA error: %s\n", cudaGetErrorString(e));
                exit(1);
        }
}

// Returns the current time in microseconds
long long start_timer() {
	struct timeval tv;
	gettimeofday(&tv, NULL);
	return tv.tv_sec * 1000000 + tv.tv_usec;
}


// Prints the time elapsed since the specified time
long long stop_timer(long long start_time, const char *label) {
	struct timeval tv;
	gettimeofday(&tv, NULL);
	long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
	printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
	return end_time - start_time;
}

	.file	"tmpxft_0035060a_00000000-6_matrix_mult.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3648:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3648:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z25allocateAndInitializeHostv
	.type	_Z25allocateAndInitializeHostv, @function
_Z25allocateAndInitializeHostv:
.LFB3637:
	.cfi_startproc
	endbr64
	movl	A_MD(%rip), %edi
	imull	4+A_MD(%rip), %edi
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, A_CPU(%rip)
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L3:
	cmpl	%ebp, A_MD(%rip)
	jle	.L13
	xorl	%r12d, %r12d
.L5:
	movl	4+A_MD(%rip), %eax
	cmpl	%r12d, %eax
	jle	.L14
	imull	%ebp, %eax
	leal	(%rax,%r12), %ebx
	incl	%r12d
	call	rand@PLT
	movl	$1000, %ecx
	movslq	%ebx, %rbx
	cltd
	idivl	%ecx
	movq	A_CPU(%rip), %rax
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%rbx,4)
	jmp	.L5
.L14:
	incl	%ebp
	jmp	.L3
.L13:
	movl	B_MD(%rip), %edi
	imull	4+B_MD(%rip), %edi
	xorl	%ebp, %ebp
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, B_CPU(%rip)
.L6:
	cmpl	%ebp, B_MD(%rip)
	jle	.L15
	xorl	%r12d, %r12d
.L8:
	movl	4+B_MD(%rip), %eax
	cmpl	%r12d, %eax
	jle	.L16
	imull	%ebp, %eax
	leal	(%rax,%r12), %ebx
	incl	%r12d
	call	rand@PLT
	movl	$1000, %ecx
	movslq	%ebx, %rbx
	cltd
	idivl	%ecx
	movq	B_CPU(%rip), %rax
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%rbx,4)
	jmp	.L8
.L16:
	incl	%ebp
	jmp	.L6
.L15:
	movl	C_MD(%rip), %ebx
	imull	4+C_MD(%rip), %ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, C_GPU_result(%rip)
	call	malloc@PLT
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	movq	%rax, C_CPU(%rip)
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z25allocateAndInitializeHostv, .-_Z25allocateAndInitializeHostv
	.globl	_Z13computeCpuMMMv
	.type	_Z13computeCpuMMMv, @function
_Z13computeCpuMMMv:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	4+B_MD(%rip), %rcx
	xorl	%edx, %edx
	movslq	4+C_MD(%rip), %rdi
	movslq	4+A_MD(%rip), %r9
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	C_CPU(%rip), %rsi
	movl	B_MD(%rip), %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	B_CPU(%rip), %r13
	salq	$2, %rdi
	salq	$2, %r9
	movl	A_MD(%rip), %r12d
	movq	A_CPU(%rip), %r8
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	salq	$2, %rcx
.L18:
	cmpl	%edx, %r12d
	jle	.L25
	movq	%r13, %r11
	movq	%rsi, %rbx
	xorl	%r10d, %r10d
.L19:
	cmpl	%r10d, %ebp
	jle	.L26
	movq	%r11, %r15
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L21:
	movss	%xmm0, (%rbx)
	cmpl	%eax, %r14d
	jle	.L27
	movss	(%r8,%rax,4), %xmm1
	mulss	(%r15), %xmm1
	incq	%rax
	addq	%rcx, %r15
	addss	%xmm1, %xmm0
	jmp	.L21
.L27:
	incl	%r10d
	addq	$4, %r11
	addq	$4, %rbx
	jmp	.L19
.L26:
	incl	%edx
	addq	%rdi, %rsi
	addq	%r9, %r8
	jmp	.L18
.L25:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	_Z13computeCpuMMMv, .-_Z13computeCpuMMMv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"mismatch at index %i: %f\t%f\n"
.LC5:
	.string	"Computation is incorrect: outputs do not match in %d indexes\n"
.LC6:
	.string	"Computation is correct: CPU and GPU outputs match\n"
	.text
	.globl	_Z23compareHostAndGpuOutputv
	.type	_Z23compareHostAndGpuOutputv, @function
_Z23compareHostAndGpuOutputv:
.LFB3641:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	C_MD(%rip), %r12d
	imull	4+C_MD(%rip), %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L29:
	cmpl	%ebx, %r12d
	jle	.L36
	movq	C_GPU_result(%rip), %rax
	movss	(%rax,%rbx,4), %xmm1
	movq	C_CPU(%rip), %rax
	movss	(%rax,%rbx,4), %xmm0
	movaps	%xmm1, %xmm2
	subss	%xmm0, %xmm2
	andps	.LC2(%rip), %xmm2
	cvtss2sd	%xmm2, %xmm2
	comisd	.LC3(%rip), %xmm2
	jbe	.L30
	movl	%ebx, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	incl	%ebp
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
.L30:
	incq	%rbx
	jmp	.L29
.L36:
	testl	%ebp, %ebp
	jle	.L33
	popq	%rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movl	%ebp, %edx
	leaq	.LC5(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L33:
	.cfi_restore_state
	popq	%rbx
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3641:
	.size	_Z23compareHostAndGpuOutputv, .-_Z23compareHostAndGpuOutputv
	.section	.rodata.str1.1
.LC7:
	.string	"%s"
	.text
	.globl	_Z3diePKc
	.type	_Z3diePKc, @function
_Z3diePKc:
.LFB3642:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	leaq	.LC7(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdi, %rdx
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
	.cfi_endproc
.LFE3642:
	.size	_Z3diePKc, .-_Z3diePKc
	.section	.rodata.str1.1
.LC8:
	.string	"\nCUDA error: %s\n"
	.text
	.globl	_Z11check_error9cudaError
	.type	_Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB3643:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L39
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L39:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3643:
	.size	_Z11check_error9cudaError, .-_Z11check_error9cudaError
	.globl	_Z11start_timerv
	.type	_Z11start_timerv, @function
_Z11start_timerv:
.LFB3644:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	xorl	%esi, %esi
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	imulq	$1000000, 8(%rsp), %rax
	addq	16(%rsp), %rax
	movq	24(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3644:
	.size	_Z11start_timerv, .-_Z11start_timerv
	.section	.rodata.str1.1
.LC10:
	.string	"%s: %.5f sec\n"
	.text
	.globl	_Z10stop_timerxPKc
	.type	_Z10stop_timerxPKc, @function
_Z10stop_timerxPKc:
.LFB3645:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rsi, %r12
	xorl	%esi, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	movq	%r12, %rdx
	movl	$2, %edi
	movb	$1, %al
	imulq	$1000000, 8(%rsp), %rbx
	addq	16(%rsp), %rbx
	leaq	.LC10(%rip), %rsi
	subq	%rbp, %rbx
	cvtsi2ssq	%rbx, %xmm0
	divss	.LC9(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3645:
	.size	_Z10stop_timerxPKc, .-_Z10stop_timerxPKc
	.section	.rodata.str1.1
.LC11:
	.string	"\nGPU:\tTransfer to GPU"
	.text
	.globl	_Z17copyMatricesToGPUv
	.type	_Z17copyMatricesToGPUv, @function
_Z17copyMatricesToGPUv:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_Z11start_timerv
	movl	A_MD(%rip), %ebx
	imull	4+A_MD(%rip), %ebx
	leaq	A_GPU(%rip), %rdi
	movq	%rax, %rbp
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	A_CPU(%rip), %rsi
	movq	%rbx, %rdx
	movq	A_GPU(%rip), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movl	B_MD(%rip), %ebx
	imull	4+B_MD(%rip), %ebx
	leaq	B_GPU(%rip), %rdi
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	B_CPU(%rip), %rsi
	movq	%rbx, %rdx
	movq	B_GPU(%rip), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movl	C_MD(%rip), %esi
	imull	4+C_MD(%rip), %esi
	leaq	C_GPU(%rip), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	popq	%rdx
	.cfi_def_cfa_offset 24
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	leaq	.LC11(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z10stop_timerxPKc
	.cfi_endproc
.LFE3638:
	.size	_Z17copyMatricesToGPUv, .-_Z17copyMatricesToGPUv
	.section	.rodata.str1.1
.LC12:
	.string	"\tTransfer from GPU"
	.text
	.globl	_Z17copyResultFromGPUv
	.type	_Z17copyResultFromGPUv, @function
_Z17copyResultFromGPUv:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	call	_Z11start_timerv
	movl	C_MD(%rip), %edx
	movl	$2, %ecx
	imull	4+C_MD(%rip), %edx
	movq	C_GPU(%rip), %rsi
	movq	C_GPU_result(%rip), %rdi
	movq	%rax, %rbx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z11check_error9cudaError
	movq	%rbx, %rdi
	leaq	.LC12(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_Z10stop_timerxPKc
	.cfi_endproc
.LFE3639:
	.size	_Z17copyResultFromGPUv, .-_Z17copyResultFromGPUv
	.globl	_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii
	.type	_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii, @function
_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii:
.LFB3670:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20mult_matrix_baselinePfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L54:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3670:
	.size	_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii, .-_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii
	.globl	_Z20mult_matrix_baselinePfS_S_iii
	.type	_Z20mult_matrix_baselinePfS_S_iii, @function
_Z20mult_matrix_baselinePfS_S_iii:
.LFB3671:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20mult_matrix_baselinePfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE3671:
	.size	_Z20mult_matrix_baselinePfS_S_iii, .-_Z20mult_matrix_baselinePfS_S_iii
	.globl	_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii
	.type	_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii:
.LFB3672:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18mult_matrix_sharedPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L59:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3672:
	.size	_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii
	.globl	_Z18mult_matrix_sharedPfS_S_iii
	.type	_Z18mult_matrix_sharedPfS_S_iii, @function
_Z18mult_matrix_sharedPfS_S_iii:
.LFB3673:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE3673:
	.size	_Z18mult_matrix_sharedPfS_S_iii, .-_Z18mult_matrix_sharedPfS_S_iii
	.section	.rodata.str1.1
.LC13:
	.string	"\tkernal excution time"
	.text
	.globl	_Z13computeGpuMMMv
	.type	_Z13computeGpuMMMv, @function
_Z13computeGpuMMMv:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	call	_Z17copyMatricesToGPUv
	movl	A_MD(%rip), %ebp
	movabsq	$137438953504, %rax
	movl	$32, %ecx
	movq	%rax, 8(%rsp)
	movl	4+B_MD(%rip), %r12d
	leal	-1(%rbp), %eax
	movl	$1, 16(%rsp)
	movl	4+A_MD(%rip), %ebx
	cltd
	movl	$1, 28(%rsp)
	idivl	%ecx
	incl	%eax
	movl	%eax, 20(%rsp)
	leal	-1(%r12), %eax
	cltd
	idivl	%ecx
	incl	%eax
	movl	%eax, 24(%rsp)
	call	_Z11start_timerv
	movl	16(%rsp), %ecx
	movl	28(%rsp), %esi
	xorl	%r9d, %r9d
	movq	8(%rsp), %rdx
	movq	20(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %r13
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	movq	C_GPU(%rip), %rdx
	movl	%r12d, %r9d
	movl	%ebx, %r8d
	movl	%ebp, %ecx
	movq	B_GPU(%rip), %rsi
	movq	A_GPU(%rip), %rdi
	call	_Z45__device_stub__Z18mult_matrix_sharedPfS_S_iiiPfS_S_iii
.L65:
	call	cudaThreadSynchronize@PLT
	movq	%r13, %rdi
	leaq	.LC13(%rip), %rsi
	call	_Z10stop_timerxPKc
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z17copyResultFromGPUv
	.cfi_endproc
.LFE3636:
	.size	_Z13computeGpuMMMv, .-_Z13computeGpuMMMv
	.section	.rodata.str1.1
.LC14:
	.string	"Matrix A is %d-by-%d\n"
.LC15:
	.string	"Matrix B is %d-by-%d\n"
.LC16:
	.string	"Matrix C is %d-by-%d\n"
.LC17:
	.string	"Dimension inconsistent for two matrices"
.LC18:
	.string	"\tTotal"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %r13d
	decl	%edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	$100, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	jle	.L68
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
.L68:
	movl	%ebx, A_MD(%rip)
	movl	%ebx, %ebp
	cmpl	$2, %r13d
	jle	.L69
	movq	16(%r12), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
.L69:
	movl	%ebp, 4+A_MD(%rip)
	movl	%ebp, %eax
	cmpl	$3, %r13d
	jle	.L70
	movq	24(%r12), %rdi
	call	atoi@PLT
.L70:
	movl	%eax, B_MD(%rip)
	cmpl	$4, %r13d
	jle	.L71
	movq	32(%r12), %rdi
	call	atoi@PLT
.L71:
	movl	%eax, 4+B_MD(%rip)
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	$2, %edi
	movl	%eax, 4+C_MD(%rip)
	leaq	.LC14(%rip), %rsi
	xorl	%eax, %eax
	movl	%ebx, C_MD(%rip)
	call	__printf_chk@PLT
	movl	4+B_MD(%rip), %ecx
	movl	B_MD(%rip), %edx
	xorl	%eax, %eax
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	4+C_MD(%rip), %ecx
	xorl	%eax, %eax
	movl	C_MD(%rip), %edx
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	B_MD(%rip), %eax
	cmpl	%eax, 4+A_MD(%rip)
	je	.L72
	leaq	.LC17(%rip), %rdi
	call	_Z3diePKc
.L72:
	call	_Z25allocateAndInitializeHostv
	call	_Z11start_timerv
	movq	%rax, %rbx
	call	_Z13computeGpuMMMv
	movq	%rbx, %rdi
	leaq	.LC18(%rip), %rsi
	call	_Z10stop_timerxPKc
	popq	%rdx
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC19:
	.string	"_Z18mult_matrix_sharedPfS_S_iii"
.LC20:
	.string	"_Z20mult_matrix_baselinePfS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3675:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18mult_matrix_sharedPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20mult_matrix_baselinePfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3675:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	C_GPU
	.bss
	.align 8
	.type	C_GPU, @object
	.size	C_GPU, 8
C_GPU:
	.zero	8
	.globl	B_GPU
	.align 8
	.type	B_GPU, @object
	.size	B_GPU, 8
B_GPU:
	.zero	8
	.globl	A_GPU
	.align 8
	.type	A_GPU, @object
	.size	A_GPU, 8
A_GPU:
	.zero	8
	.globl	C_GPU_result
	.align 8
	.type	C_GPU_result, @object
	.size	C_GPU_result, 8
C_GPU_result:
	.zero	8
	.globl	C_CPU
	.align 8
	.type	C_CPU, @object
	.size	C_CPU, 8
C_CPU:
	.zero	8
	.globl	B_CPU
	.align 8
	.type	B_CPU, @object
	.size	B_CPU, 8
B_CPU:
	.zero	8
	.globl	A_CPU
	.align 8
	.type	A_CPU, @object
	.size	A_CPU, 8
A_CPU:
	.zero	8
	.globl	C_MD
	.align 8
	.type	C_MD, @object
	.size	C_MD, 8
C_MD:
	.zero	8
	.globl	B_MD
	.align 8
	.type	B_MD, @object
	.size	B_MD, 8
B_MD:
	.zero	8
	.globl	A_MD
	.align 8
	.type	A_MD, @object
	.size	A_MD, 8
A_MD:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-755914244
	.long	1062232653
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC3:
	.long	1202590843
	.long	1065646817
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC9:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//matrix_mult.cu
//template provided by Prof. Andrew Grimshaw
//implementation by Jerry Sun(ys7va) 2017.05.08
//the program will take 4 parameters to specify the size of two matrices
//if only provided 1 value N, it will calculate the multiplication of two N * N matrices
#include<stdio.h>
#include<sys/time.h>
#include<stdlib.h>
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;

//Macro to specify block size
#define T_block 32

//----------------------------------- Structures and Globals---------------------------------------------
//store dimension of a matrix
typedef struct {
	int dimension1;
	int dimension2;
} ArrayMetadata2D;

// metadata variables describing dimensionalities of all data structures involved in the computation
ArrayMetadata2D A_MD, B_MD, C_MD;
// pointers for input and output arrays in the host memory
// *_CPU is for CPU calculation
// C_GPU_result is for storing GPU calculation result
float *A_CPU, *B_CPU, *C_CPU, *C_GPU_result;
// pointers for input and output arrays in the device memory (NVIDIA DRAM)
float *A_GPU, *B_GPU, *C_GPU;

//----------------------------------- host function definitions -----------------------------------------
void allocateAndInitializeHost();       //allocate and initialize all necessary memory on host machine
void computeCpuMMM();                   //matrix multiplication on CPU
void computeGpuMMM();                   //matrix multiplication on GPU, may use different kernel method
void copyMatricesToGPU();               //copy value in A_CPU & B_CPU to A_GPU & B_GPU respectively
void copyResultFromGPU();               //copy calculated value in C_GPU back into C_GPU_result
void compareHostAndGpuOutput();         //check if the result in C_GPU_result and C_CPU is identical
void die(const char *error);            //end the program
void check_error(hipError_t e);          //check memory allocation on cuda
long long start_timer();                //timer for measurement
long long stop_timer(long long start_time, const char *name);  //timer for measurement

//----------------------------------- CUDA function definitions -----------------------------------------
//baseline approach for kernel method, each thread is responsible for one cell in final result
__global__ void mult_matrix_baseline(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3);
//shared memory version for kernel method, a block of threads read data from DRAM together into shared
//memory and then do calculation block-wise
__global__ void mult_matrix_shared(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3);


//-------------------------------------------------------------------------------------------------------
int main(int argc, char **argv) {
    //parse the command-line argument
	A_MD.dimension1 = (argc > 1) ? atoi(argv[1]) : 100;
	A_MD.dimension2 = (argc > 2) ? atoi(argv[2]) : A_MD.dimension1;
	B_MD.dimension1 = (argc > 3) ? atoi(argv[3]) : A_MD.dimension2;
	B_MD.dimension2 = (argc > 4) ? atoi(argv[4]) : B_MD.dimension1;
	C_MD.dimension1 = A_MD.dimension1;
	C_MD.dimension2 = B_MD.dimension2;

	printf("Matrix A is %d-by-%d\n", A_MD.dimension1, A_MD.dimension2);
	printf("Matrix B is %d-by-%d\n", B_MD.dimension1, B_MD.dimension2);
	printf("Matrix C is %d-by-%d\n", C_MD.dimension1, C_MD.dimension2);
    //if dim2 of A and dim1 of B is different then they can't be multiplied
	if (A_MD.dimension2 != B_MD.dimension1) die("Dimension inconsistent for two matrices");

    //allocate all necessary memory on host
	allocateAndInitializeHost();

	// matrix multiplication in the CPU, commented for large-scale
	// long long CPU_start_time = start_timer();
	// computeCpuMMM();
	// long long CPU_time = stop_timer(CPU_start_time, "\nCPU");

	// matrix multiplication on the GPU
	long long GPU_start_time = start_timer();
	computeGpuMMM();
	long long GPU_time = stop_timer(GPU_start_time, "\tTotal");

    //check the final result
	//commented when CPU result is not available
    //compareHostAndGpuOutput();

	return 0;
}


__global__ void mult_matrix_baseline(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3) {
    // retrieve the corresponding row & col in final output matrix
    int r = blockIdx.x * T_block + threadIdx.x;
    int c = blockIdx.y * T_block + threadIdx.y;
    // check if index is in bound
    if (r < dim_1 && c < dim_3) {
        float sum = 0;
        // calculate inner product of two vectors
        for (int i = 0; i < dim_2; i++) {
                sum += A[r * dim_1 + i] * B[i * dim_2 + c];
            }
        // assign final results
        C[r * dim_3 + c] = sum;
    }
}

// Compute C = A * B
__global__ void mult_matrix_shared(float *A, float *B, float *C, int dim_1, int dim_2, int dim_3) {

  // store corresponding value in registers
  int b_x = blockIdx.x;
  int b_y = blockIdx.y;
  int t_x = threadIdx.x;
  int t_y = threadIdx.y;

  // retrieve row & col number in final output
  int r = b_y * T_block + t_y;
  int c = b_x * T_block + t_x;

  float s = 0;
  // initiate share memory space
  __shared__ float block_A[T_block][T_block];
  __shared__ float block_B[T_block][T_block];

  // bool variable to check if inbound
  bool inplace = r < dim_1 && c < dim_3;

  // iterate through all blocks in using a ceiling function to deal with corner cases
  for (int m = 0; m < (dim_2 - 1) / T_block + 1; m++) {
    // column num for the retrieved cell in matrix A
    int col = m * T_block + t_x;
    // load value from matrix A, if not available assign 0
    block_A[t_y][t_x] = (r < dim_1 && col < dim_2) ? A[r * dim_1 + col] : 0.0;
    // row num for the retrieved cell in matrix B
	int row = m * T_block + t_y;
    // load value from matrix B, if not available assign 0
	block_B[t_y][t_x] = (row < dim_2 && c < dim_3) ? B[row * dim_3 + c] : 0.0;
    // sync all threads, wait till all threads finish loading
    __syncthreads();

    //if inplace calculate the inner product within two blocks in A and B
	if (inplace)
		for (int i = 0; i < T_block; i++)
			s += block_A[t_y][i] * block_B[i][t_x];
    //sync threads, wait till all threads finish using shared memory in current iteration
    __syncthreads();
  }

  //assign final result
  if (inplace)
    C[r * dim_3 + c] = s;
}

// GPU version MM
void computeGpuMMM() {
	copyMatricesToGPU();
    //for a matrix multiplication problem, only three dimensions are needed
    //two dims for the final matrix, and one for dim2 of A and dim1 of B(identical)
	int dim_1 = A_MD.dimension1;
	int dim_2 = A_MD.dimension2;
	int dim_3 = B_MD.dimension2;
    //initialize gridblock, and threadblock size
    //here we assume each thread always responsible for cell
    dim3 thread(T_block, T_block);
    //if dim_1 not divisible by T_block, we use ceiling function
    //in order to handle corner cases
    dim3 grid((dim_1 - 1) / T_block + 1, (dim_3 - 1) / T_block + 1);
	long long exec_start_time = start_timer();
	//call kernel method, passing in three GPU pointers and three dimensions
    mult_matrix_shared <<<grid, thread>>> (A_GPU, B_GPU, C_GPU, dim_1, dim_2, dim_3);
    //synchroniztion
	hipDeviceSynchronize();
	stop_timer(exec_start_time, "\tkernal excution time");
	//copy the result from GPU
	copyResultFromGPU();
}



// allocate and initialize A and B using a random number generator,
// also initialize C_CPU and C_GPU_resul
void allocateAndInitializeHost() {
	size_t sizeofA = A_MD.dimension1 * A_MD.dimension2 * sizeof(float);
	A_CPU = (float*) malloc(sizeofA);
	srand(time(NULL));
  	for (int i = 0; i < A_MD.dimension1; i++) {
		for (int j = 0; j < A_MD.dimension2; j++) {
			int index = i * A_MD.dimension2 + j;
			A_CPU[index] = (rand() % 1000) * 0.001;
		}
	}

	size_t sizeofB = B_MD.dimension1 * B_MD.dimension2 * sizeof(float);
	B_CPU = (float*) malloc(sizeofB);
  	for (int i = 0; i < B_MD.dimension1; i++) {
		for (int j = 0; j < B_MD.dimension2; j++) {
			int index = i * B_MD.dimension2 + j;
			B_CPU[index] = (rand() % 1000) * 0.001;
		}
	}

	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	C_GPU_result = (float*) malloc(sizeofC);
	C_CPU = (float*) malloc(sizeofC);

}

// allocate memory in the GPU for all matrices, and copy A and B content from the host CPU memory to the GPU memory
void copyMatricesToGPU() {
	long long memory_start_time = start_timer();
	size_t sizeofA = A_MD.dimension1 * A_MD.dimension2 * sizeof(float);
	check_error(hipMalloc((void **) &A_GPU, sizeofA));
	check_error(hipMemcpy(A_GPU, A_CPU, sizeofA, hipMemcpyHostToDevice));

	size_t sizeofB = B_MD.dimension1 * B_MD.dimension2 * sizeof(float);
	check_error(hipMalloc((void **) &B_GPU, sizeofB));
	check_error(hipMemcpy(B_GPU, B_CPU, sizeofB, hipMemcpyHostToDevice));

	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	check_error(hipMalloc((void **) &C_GPU, sizeofC));
	stop_timer(memory_start_time, "\nGPU:\tTransfer to GPU");

}

// copy results from C_GPU which is in GPU card memory to C_CPU_result which is in the host CPU for result comparison
void copyResultFromGPU() {
	long long memory_start_time = start_timer();
	size_t sizeofC = C_MD.dimension1 * C_MD.dimension2 * sizeof(float);
	check_error(hipMemcpy(C_GPU_result, C_GPU, sizeofC, hipMemcpyDeviceToHost));
	stop_timer(memory_start_time, "\tTransfer from GPU");
}

// do a straightforward matrix-matrix multiplication in the CPU
// notice that this implementation can be massively improved in the CPU by doing proper cache blocking but we are
// not providing you the efficient CPU implementation as that reveals too much about the ideal GPU implementation
void computeCpuMMM() {

	// compute C[i][j] as the sum of A[i][k] * B[k][j] for all columns k of A
	for (int i = 0; i < A_MD.dimension1; i++) {
		int a_i = i * A_MD.dimension2;
		int c_i = i * C_MD.dimension2;
		for (int j = 0; j < B_MD.dimension2; j++) {
			int c_index = c_i + j;
			C_CPU[c_index] = 0;
			for (int k = 0; k < B_MD.dimension1; k++) {
				int a_index = a_i + k;
				int b_index = k * B_MD.dimension2 + j;
				C_CPU[c_index] += A_CPU[a_index] * B_CPU[b_index];
			}
		}
	}
}

// function to determine if the GPU computation is done correctly by comparing the output from the GPU with that
void compareHostAndGpuOutput() {
	int totalElements = C_MD.dimension1 * C_MD.dimension2;
	int missmatchCount = 0;
	for (int i = 0; i < totalElements; i++) {
		if (fabs(C_GPU_result[i] - C_CPU[i]) > 0.01) {
			missmatchCount++;
			printf("mismatch at index %i: %f\t%f\n", i, C_CPU[i], C_GPU_result[i]);
		}
	}
	if (missmatchCount > 0) {
		printf("Computation is incorrect: outputs do not match in %d indexes\n", missmatchCount);
	} else {
		printf("Computation is correct: CPU and GPU outputs match\n");
	}
}

// Prints the specified error message and then exits
void die(const char *error) {
        printf("%s", error);
        exit(1);
}

// If the specified error code refers to a real error, report it and quit the program
void check_error(hipError_t e) {
        if (e != hipSuccess) {
                printf("\nCUDA error: %s\n", hipGetErrorString(e));
                exit(1);
        }
}

// Returns the current time in microseconds
long long start_timer() {
	struct timeval tv;
	gettimeofday(&tv, NULL);
	return tv.tv_sec * 1000000 + tv.tv_usec;
}


// Prints the time elapsed since the specified time
long long stop_timer(long long start_time, const char *label) {
	struct timeval tv;
	gettimeofday(&tv, NULL);
	long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
	printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
	return end_time - start_time;
}

	.text
	.file	"matrix_mult.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$1, %edi
	jle	.LBB0_1
# %bb.2:
	movq	%rsi, %r14
	movl	%edi, %r15d
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movl	%eax, A_MD(%rip)
	cmpl	$2, %r15d
	je	.LBB0_3
# %bb.4:
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebp
	movl	%eax, A_MD+4(%rip)
	cmpl	$3, %r15d
	jbe	.LBB0_5
# %bb.6:
	movq	24(%r14), %rdi
	callq	atoi
	movl	%eax, B_MD(%rip)
	cmpl	$4, %r15d
	je	.LBB0_8
# %bb.7:
	movq	32(%r14), %rdi
	callq	atoi
	jmp	.LBB0_8
.LBB0_1:                                # %.thread
	movl	$100, A_MD(%rip)
	movl	$100, %ebx
.LBB0_3:                                # %.thread9
	movl	%ebx, A_MD+4(%rip)
	movl	%ebx, %ebp
.LBB0_5:                                # %.thread14
	movl	%ebp, B_MD(%rip)
	movl	%ebp, %eax
.LBB0_8:
	movl	%eax, B_MD+4(%rip)
	movl	%ebx, C_MD(%rip)
	movl	%eax, C_MD+4(%rip)
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	movl	B_MD(%rip), %esi
	movl	B_MD+4(%rip), %edx
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	C_MD(%rip), %esi
	movl	C_MD+4(%rip), %edx
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	A_MD+4(%rip), %eax
	cmpl	B_MD(%rip), %eax
	jne	.LBB0_10
# %bb.9:
	callq	_Z25allocateAndInitializeHostv
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%rbx), %r14          # imm = 0xF4240
	addq	8(%rbx), %r14
	callq	_Z13computeGpuMMMv
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	callq	_Z10stop_timerxPKc
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_10:
	.cfi_def_cfa_offset 64
	movl	$.L.str.11, %edi
	movl	$.L.str.3, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z3diePKc                       # -- Begin function _Z3diePKc
	.type	_Z3diePKc,@function
_Z3diePKc:                              # @_Z3diePKc
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdi, %rsi
	movl	$.L.str.11, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z3diePKc, .Lfunc_end1-_Z3diePKc
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z25allocateAndInitializeHostv
.LCPI2_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
	.text
	.globl	_Z25allocateAndInitializeHostv
	.type	_Z25allocateAndInitializeHostv,@function
_Z25allocateAndInitializeHostv:         # @_Z25allocateAndInitializeHostv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movslq	A_MD(%rip), %rax
	movslq	A_MD+4(%rip), %rdi
	imulq	%rax, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, A_CPU(%rip)
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	A_MD(%rip), %eax
	testl	%eax, %eax
	jle	.LBB2_7
# %bb.1:                                # %.preheader23.preheader
	movl	A_MD+4(%rip), %ebp
.LBB2_2:                                # %.preheader23
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%ebp, %ebp
	jle	.LBB2_6
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_2 Depth=1
	xorl	%r14d, %r14d
.LBB2_4:                                # %.lr.ph
                                        #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebx, %ebp
	addl	%r14d, %ebp
	callq	rand
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	A_CPU(%rip), %rax
	movslq	%ebp, %rcx
	movss	%xmm0, (%rax,%rcx,4)
	incl	%r14d
	movl	A_MD+4(%rip), %ebp
	cmpl	%ebp, %r14d
	jl	.LBB2_4
# %bb.5:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB2_2 Depth=1
	movl	A_MD(%rip), %eax
.LBB2_6:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jl	.LBB2_2
.LBB2_7:                                # %._crit_edge26
	movl	B_MD(%rip), %r14d
	movl	B_MD+4(%rip), %ebx
	movl	%ebx, %eax
	imull	%r14d, %eax
	movslq	%eax, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, B_CPU(%rip)
	testl	%r14d, %r14d
	jle	.LBB2_14
# %bb.8:                                # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB2_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_11 Depth 2
	testl	%ebx, %ebx
	jle	.LBB2_13
# %bb.10:                               # %.lr.ph28.preheader
                                        #   in Loop: Header=BB2_9 Depth=1
	xorl	%r14d, %r14d
.LBB2_11:                               # %.lr.ph28
                                        #   Parent Loop BB2_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebp, %ebx
	addl	%r14d, %ebx
	callq	rand
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$1000, %ecx, %ecx               # imm = 0x3E8
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	B_CPU(%rip), %rax
	movslq	%ebx, %rcx
	movss	%xmm0, (%rax,%rcx,4)
	incl	%r14d
	movl	B_MD+4(%rip), %ebx
	cmpl	%ebx, %r14d
	jl	.LBB2_11
# %bb.12:                               # %._crit_edge29.loopexit
                                        #   in Loop: Header=BB2_9 Depth=1
	movl	B_MD(%rip), %r14d
.LBB2_13:                               # %._crit_edge29
                                        #   in Loop: Header=BB2_9 Depth=1
	incl	%ebp
	cmpl	%r14d, %ebp
	jl	.LBB2_9
.LBB2_14:                               # %._crit_edge31
	movslq	C_MD(%rip), %rax
	movslq	C_MD+4(%rip), %rbx
	imulq	%rax, %rbx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, C_GPU_result(%rip)
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, C_CPU(%rip)
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25allocateAndInitializeHostv, .Lfunc_end2-_Z25allocateAndInitializeHostv
	.cfi_endproc
                                        # -- End function
	.globl	_Z11start_timerv                # -- Begin function _Z11start_timerv
	.type	_Z11start_timerv,@function
_Z11start_timerv:                       # @_Z11start_timerv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%rbx), %rax          # imm = 0xF4240
	addq	8(%rbx), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z11start_timerv, .Lfunc_end3-_Z11start_timerv
	.cfi_endproc
                                        # -- End function
	.globl	_Z13computeGpuMMMv              # -- Begin function _Z13computeGpuMMMv
	.type	_Z13computeGpuMMMv,@function
_Z13computeGpuMMMv:                     # @_Z13computeGpuMMMv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	callq	_Z17copyMatricesToGPUv
	movl	A_MD(%rip), %r14d
	movl	A_MD+4(%rip), %ebx
	leal	-1(%r14), %eax
	leal	30(%r14), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	movl	B_MD+4(%rip), %r15d
	sarl	$5, %ecx
	incl	%ecx
	leal	-1(%r15), %eax
	leal	30(%r15), %r12d
	testl	%eax, %eax
	cmovnsl	%eax, %r12d
	sarl	$5, %r12d
	incl	%r12d
	shlq	$32, %r12
	orq	%rcx, %r12
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r13), %rbp
	movq	8(%r13), %r13
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	A_GPU(%rip), %rdi
	movq	B_GPU(%rip), %rsi
	movq	C_GPU(%rip), %rdx
	movl	%r14d, %ecx
	movl	%ebx, %r8d
	movl	%r15d, %r9d
	callq	_Z33__device_stub__mult_matrix_sharedPfS_S_iii
.LBB4_2:
	imulq	$1000000, %rbp, %rbx            # imm = 0xF4240
	addq	%r13, %rbx
	callq	hipDeviceSynchronize
	movl	$.L.str.5, %esi
	movq	%rbx, %rdi
	callq	_Z10stop_timerxPKc
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z17copyResultFromGPUv          # TAILCALL
.Lfunc_end4:
	.size	_Z13computeGpuMMMv, .Lfunc_end4-_Z13computeGpuMMMv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10stop_timerxPKc
.LCPI5_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z10stop_timerxPKc
	.type	_Z10stop_timerxPKc,@function
_Z10stop_timerxPKc:                     # @_Z10stop_timerxPKc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movq	%rsp, %r15
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%r15), %rax          # imm = 0xF4240
	movq	8(%r15), %r15
	subq	%r14, %r15
	addq	%rax, %r15
	cvtsi2ss	%r15, %xmm0
	divss	.LCPI5_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.13, %edi
	movq	%rbx, %rsi
	movb	$1, %al
	callq	printf
	movq	%r15, %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z10stop_timerxPKc, .Lfunc_end5-_Z10stop_timerxPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__mult_matrix_baselinePfS_S_iii # -- Begin function _Z35__device_stub__mult_matrix_baselinePfS_S_iii
	.type	_Z35__device_stub__mult_matrix_baselinePfS_S_iii,@function
_Z35__device_stub__mult_matrix_baselinePfS_S_iii: # @_Z35__device_stub__mult_matrix_baselinePfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20mult_matrix_baselinePfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z35__device_stub__mult_matrix_baselinePfS_S_iii, .Lfunc_end6-_Z35__device_stub__mult_matrix_baselinePfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__mult_matrix_sharedPfS_S_iii # -- Begin function _Z33__device_stub__mult_matrix_sharedPfS_S_iii
	.type	_Z33__device_stub__mult_matrix_sharedPfS_S_iii,@function
_Z33__device_stub__mult_matrix_sharedPfS_S_iii: # @_Z33__device_stub__mult_matrix_sharedPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18mult_matrix_sharedPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z33__device_stub__mult_matrix_sharedPfS_S_iii, .Lfunc_end7-_Z33__device_stub__mult_matrix_sharedPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z17copyMatricesToGPUv          # -- Begin function _Z17copyMatricesToGPUv
	.type	_Z17copyMatricesToGPUv,@function
_Z17copyMatricesToGPUv:                 # @_Z17copyMatricesToGPUv
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%r14), %rbx          # imm = 0xF4240
	addq	8(%r14), %rbx
	movslq	A_MD(%rip), %rax
	movslq	A_MD+4(%rip), %r14
	imulq	%rax, %r14
	shlq	$2, %r14
	movl	$A_GPU, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	A_GPU(%rip), %rdi
	movq	A_CPU(%rip), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movslq	B_MD(%rip), %rax
	movslq	B_MD+4(%rip), %r14
	imulq	%rax, %r14
	shlq	$2, %r14
	movl	$B_GPU, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movq	B_GPU(%rip), %rdi
	movq	B_CPU(%rip), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movslq	C_MD(%rip), %rax
	movslq	C_MD+4(%rip), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	movl	$C_GPU, %edi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movl	$.L.str.6, %esi
	movq	%rbx, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z10stop_timerxPKc              # TAILCALL
.Lfunc_end8:
	.size	_Z17copyMatricesToGPUv, .Lfunc_end8-_Z17copyMatricesToGPUv
	.cfi_endproc
                                        # -- End function
	.globl	_Z17copyResultFromGPUv          # -- Begin function _Z17copyResultFromGPUv
	.type	_Z17copyResultFromGPUv,@function
_Z17copyResultFromGPUv:                 # @_Z17copyResultFromGPUv
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imulq	$1000000, (%rbx), %r14          # imm = 0xF4240
	addq	8(%rbx), %r14
	movslq	C_MD(%rip), %rax
	movslq	C_MD+4(%rip), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	C_GPU_result(%rip), %rdi
	movq	C_GPU(%rip), %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z11check_error10hipError_t
	movl	$.L.str.7, %esi
	movq	%r14, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z10stop_timerxPKc              # TAILCALL
.Lfunc_end9:
	.size	_Z17copyResultFromGPUv, .Lfunc_end9-_Z17copyResultFromGPUv
	.cfi_endproc
                                        # -- End function
	.globl	_Z11check_error10hipError_t     # -- Begin function _Z11check_error10hipError_t
	.type	_Z11check_error10hipError_t,@function
_Z11check_error10hipError_t:            # @_Z11check_error10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB10_2
# %bb.1:
	retq
.LBB10_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movl	$.L.str.12, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end10:
	.size	_Z11check_error10hipError_t, .Lfunc_end10-_Z11check_error10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z13computeCpuMMMv              # -- Begin function _Z13computeCpuMMMv
	.type	_Z13computeCpuMMMv,@function
_Z13computeCpuMMMv:                     # @_Z13computeCpuMMMv
	.cfi_startproc
# %bb.0:
	movl	A_MD(%rip), %eax
	testl	%eax, %eax
	jle	.LBB11_10
# %bb.1:                                # %.lr.ph27
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movslq	A_MD+4(%rip), %rcx
	movslq	C_MD+4(%rip), %rdx
	movl	B_MD+4(%rip), %esi
	movq	C_CPU(%rip), %rdi
	movl	B_MD(%rip), %r8d
	movslq	%esi, %r9
	shlq	$2, %rcx
	shlq	$2, %r9
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
.LBB11_2:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_4 Depth 2
                                        #       Child Loop BB11_6 Depth 3
	testl	%esi, %esi
	jle	.LBB11_8
# %bb.3:                                # %.lr.ph23
                                        #   in Loop: Header=BB11_2 Depth=1
	movq	%r11, %r14
	imulq	%rdx, %r14
	movq	B_CPU(%rip), %rbx
	leaq	(%rdi,%r14,4), %r14
	movq	A_CPU(%rip), %r15
	addq	%r10, %r15
	xorl	%r12d, %r12d
.LBB11_4:                               #   Parent Loop BB11_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB11_6 Depth 3
	movl	$0, (%r14,%r12,4)
	testl	%r8d, %r8d
	jle	.LBB11_7
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB11_4 Depth=2
	xorps	%xmm0, %xmm0
	movq	%rbx, %r13
	xorl	%ebp, %ebp
.LBB11_6:                               #   Parent Loop BB11_2 Depth=1
                                        #     Parent Loop BB11_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r15,%rbp,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r13), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%rbp
	addq	%r9, %r13
	cmpq	%rbp, %r8
	jne	.LBB11_6
.LBB11_7:                               # %._crit_edge
                                        #   in Loop: Header=BB11_4 Depth=2
	incq	%r12
	addq	$4, %rbx
	cmpq	%rsi, %r12
	jne	.LBB11_4
.LBB11_8:                               # %._crit_edge24
                                        #   in Loop: Header=BB11_2 Depth=1
	incq	%r11
	addq	%rcx, %r10
	cmpq	%rax, %r11
	jne	.LBB11_2
# %bb.9:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB11_10:                              # %._crit_edge28
	retq
.Lfunc_end11:
	.size	_Z13computeCpuMMMv, .Lfunc_end11-_Z13computeCpuMMMv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z23compareHostAndGpuOutputv
.LCPI12_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI12_1:
	.quad	0x3f847ae147ae147b              # double 0.01
	.text
	.globl	_Z23compareHostAndGpuOutputv
	.type	_Z23compareHostAndGpuOutputv,@function
_Z23compareHostAndGpuOutputv:           # @_Z23compareHostAndGpuOutputv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	C_MD+4(%rip), %eax
	imull	C_MD(%rip), %eax
	testl	%eax, %eax
	jle	.LBB12_7
# %bb.1:                                # %.lr.ph.preheader
	movl	%eax, %r14d
	movq	C_GPU_result(%rip), %rax
	xorl	%ebx, %ebx
	movq	C_CPU(%rip), %rcx
	movaps	.LCPI12_0(%rip), %xmm3          # xmm3 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI12_1(%rip), %xmm4          # xmm4 = mem[0],zero
	xorl	%ebp, %ebp
.LBB12_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rbx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	movss	(%rcx,%rbx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm1, %xmm2
	subss	%xmm0, %xmm2
	andps	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	ucomisd	%xmm4, %xmm2
	jbe	.LBB12_4
# %bb.3:                                #   in Loop: Header=BB12_2 Depth=1
	incl	%ebp
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.8, %edi
	movl	%ebx, %esi
	movb	$2, %al
	callq	printf
	movsd	.LCPI12_1(%rip), %xmm4          # xmm4 = mem[0],zero
	movaps	.LCPI12_0(%rip), %xmm3          # xmm3 = [NaN,NaN,NaN,NaN]
	movq	C_GPU_result(%rip), %rax
	movq	C_CPU(%rip), %rcx
.LBB12_4:                               #   in Loop: Header=BB12_2 Depth=1
	incq	%rbx
	cmpq	%rbx, %r14
	jne	.LBB12_2
# %bb.5:                                # %._crit_edge
	testl	%ebp, %ebp
	jle	.LBB12_7
# %bb.6:
	movl	$.L.str.9, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB12_7:                               # %._crit_edge.thread
	.cfi_def_cfa_offset 32
	movl	$.Lstr, %edi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end12:
	.size	_Z23compareHostAndGpuOutputv, .Lfunc_end12-_Z23compareHostAndGpuOutputv
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20mult_matrix_baselinePfS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18mult_matrix_sharedPfS_S_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	A_MD,@object                    # @A_MD
	.bss
	.globl	A_MD
	.p2align	2, 0x0
A_MD:
	.zero	8
	.size	A_MD, 8

	.type	B_MD,@object                    # @B_MD
	.globl	B_MD
	.p2align	2, 0x0
B_MD:
	.zero	8
	.size	B_MD, 8

	.type	C_MD,@object                    # @C_MD
	.globl	C_MD
	.p2align	2, 0x0
C_MD:
	.zero	8
	.size	C_MD, 8

	.type	A_CPU,@object                   # @A_CPU
	.globl	A_CPU
	.p2align	3, 0x0
A_CPU:
	.quad	0
	.size	A_CPU, 8

	.type	B_CPU,@object                   # @B_CPU
	.globl	B_CPU
	.p2align	3, 0x0
B_CPU:
	.quad	0
	.size	B_CPU, 8

	.type	C_CPU,@object                   # @C_CPU
	.globl	C_CPU
	.p2align	3, 0x0
C_CPU:
	.quad	0
	.size	C_CPU, 8

	.type	C_GPU_result,@object            # @C_GPU_result
	.globl	C_GPU_result
	.p2align	3, 0x0
C_GPU_result:
	.quad	0
	.size	C_GPU_result, 8

	.type	A_GPU,@object                   # @A_GPU
	.globl	A_GPU
	.p2align	3, 0x0
A_GPU:
	.quad	0
	.size	A_GPU, 8

	.type	B_GPU,@object                   # @B_GPU
	.globl	B_GPU
	.p2align	3, 0x0
B_GPU:
	.quad	0
	.size	B_GPU, 8

	.type	C_GPU,@object                   # @C_GPU
	.globl	C_GPU
	.p2align	3, 0x0
C_GPU:
	.quad	0
	.size	C_GPU, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Matrix A is %d-by-%d\n"
	.size	.L.str, 22

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Matrix B is %d-by-%d\n"
	.size	.L.str.1, 22

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Matrix C is %d-by-%d\n"
	.size	.L.str.2, 22

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Dimension inconsistent for two matrices"
	.size	.L.str.3, 40

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\tTotal"
	.size	.L.str.4, 7

	.type	_Z20mult_matrix_baselinePfS_S_iii,@object # @_Z20mult_matrix_baselinePfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z20mult_matrix_baselinePfS_S_iii
	.p2align	3, 0x0
_Z20mult_matrix_baselinePfS_S_iii:
	.quad	_Z35__device_stub__mult_matrix_baselinePfS_S_iii
	.size	_Z20mult_matrix_baselinePfS_S_iii, 8

	.type	_Z18mult_matrix_sharedPfS_S_iii,@object # @_Z18mult_matrix_sharedPfS_S_iii
	.globl	_Z18mult_matrix_sharedPfS_S_iii
	.p2align	3, 0x0
_Z18mult_matrix_sharedPfS_S_iii:
	.quad	_Z33__device_stub__mult_matrix_sharedPfS_S_iii
	.size	_Z18mult_matrix_sharedPfS_S_iii, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"\tkernal excution time"
	.size	.L.str.5, 22

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nGPU:\tTransfer to GPU"
	.size	.L.str.6, 22

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\tTransfer from GPU"
	.size	.L.str.7, 19

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"mismatch at index %i: %f\t%f\n"
	.size	.L.str.8, 29

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Computation is incorrect: outputs do not match in %d indexes\n"
	.size	.L.str.9, 62

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"%s"
	.size	.L.str.11, 3

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"\nCUDA error: %s\n"
	.size	.L.str.12, 17

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"%s: %.5f sec\n"
	.size	.L.str.13, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20mult_matrix_baselinePfS_S_iii"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18mult_matrix_sharedPfS_S_iii"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Computation is correct: CPU and GPU outputs match"
	.size	.Lstr, 50

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__mult_matrix_baselinePfS_S_iii
	.addrsig_sym _Z33__device_stub__mult_matrix_sharedPfS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym A_GPU
	.addrsig_sym B_GPU
	.addrsig_sym C_GPU
	.addrsig_sym _Z20mult_matrix_baselinePfS_S_iii
	.addrsig_sym _Z18mult_matrix_sharedPfS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20mult_matrix_baselinePfS_S_iii ; -- Begin function _Z20mult_matrix_baselinePfS_S_iii
	.globl	_Z20mult_matrix_baselinePfS_S_iii
	.p2align	8
	.type	_Z20mult_matrix_baselinePfS_S_iii,@function
_Z20mult_matrix_baselinePfS_S_iii:      ; @_Z20mult_matrix_baselinePfS_S_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, s14, 5, v1
	v_lshl_add_u32 v0, s15, 5, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v5
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v1, v5, s4
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
	s_mov_b32 s2, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v4, v[1:2], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v4, v7
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %Flow52
	v_mad_u64_u32 v[1:2], null, v5, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20mult_matrix_baselinePfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20mult_matrix_baselinePfS_S_iii, .Lfunc_end0-_Z20mult_matrix_baselinePfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18mult_matrix_sharedPfS_S_iii ; -- Begin function _Z18mult_matrix_sharedPfS_S_iii
	.globl	_Z18mult_matrix_sharedPfS_S_iii
	.p2align	8
	.type	_Z18mult_matrix_sharedPfS_S_iii,@function
_Z18mult_matrix_sharedPfS_S_iii:        ; @_Z18mult_matrix_sharedPfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s15, 5, v2
	v_lshl_add_u32 v0, s14, 5, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	v_cmp_gt_i32_e64 s0, s6, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s7, vcc_lo, s0
	s_cmpk_lt_i32 s5, 0xffe2
	s_cbranch_scc1 .LBB1_11
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v4, 2, v3
	s_add_i32 s1, s5, -1
	v_lshlrev_b32_e32 v5, 7, v2
	s_ashr_i32 s12, s1, 31
	v_mul_lo_u32 v7, v1, s4
	v_or_b32_e32 v6, 0x1000, v4
	s_lshr_b32 s4, s12, 27
	v_add_nc_u32_e32 v8, v5, v4
	v_mov_b32_e32 v4, 0
	s_add_i32 s1, s1, s4
	v_add_nc_u32_e32 v9, v6, v5
	s_ashr_i32 s4, s1, 5
	s_mov_b32 s12, 0
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_8 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s13, s12, 5
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s5, v11
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v10, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s8, v10
	v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
	global_load_b32 v10, v[10:11], off
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s13, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10
	v_cmp_gt_i32_e64 s1, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s10, v10
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v12, v[10:11], off
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s7
	s_cbranch_execz .LBB1_9
; %bb.7:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v10, v6
	s_mov_b32 s13, 0
.LBB1_8:                                ; %.preheader
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v11, s13, v5
	s_add_i32 s13, s13, 4
	ds_load_b32 v12, v10
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v10, 0x80, v10
	s_cmpk_lg_i32 s13, 0x80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v4, v11, v12
	s_cbranch_scc1 .LBB1_8
.LBB1_9:                                ; %Flow92
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s12, 1
	s_cmp_eq_u32 s12, s4
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s12, s1
	s_branch .LBB1_2
.LBB1_11:                               ; %Flow94
	s_and_saveexec_b32 s0, s7
	s_cbranch_execz .LBB1_13
; %bb.12:
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB1_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18mult_matrix_sharedPfS_S_iii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18mult_matrix_sharedPfS_S_iii, .Lfunc_end1-_Z18mult_matrix_sharedPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20mult_matrix_baselinePfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20mult_matrix_baselinePfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18mult_matrix_sharedPfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18mult_matrix_sharedPfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
