#include "includes.h"
__global__ void pcr_k(float a, float b, float c, float* y, int n) {
// Identifies the thread working within a group
int tidx = threadIdx.x % n;
// Identifies the data concerned by the computations
int Qt = (threadIdx.x - tidx) / n;
// The global memory access index
int gb_index_x = Qt + blockIdx.x * (blockDim.x / n);
// Local integers
int i, nt, lL, d, tL, tR;
// Local floats
float aL, bL, cL, yL, aLp, bLp, cLp, yLp;
// Shared memory
extern __shared__ float sAds[];

nt = 5 * Qt * n;
d = (n / 2 + (n % 2)) * (tidx % 2) + (int)tidx / 2;
float* sa = (float*)&sAds[nt];
float* sb = (float*)&sa[n];
float* sc = (float*)&sb[n];
float* sy = (float*)&sc[n];
int* sl = (int*)&sy[n];

sa[tidx] = a;
sb[tidx] = b;
sc[tidx] = c;
sy[tidx] = y[gb_index_x * n + tidx];
sl[tidx] = tidx;
__syncthreads();

//Left/Right indices of the reduction
tL = tidx - 1;
if (tL < 0) tL = 0;
tR = tidx + 1;
if (tR >= n) tR = 0;

for (i = 0; i < (int)log2((float)n) + 1; i++) {
lL = (int)sl[tidx];
aL = sa[tidx];
bL = sb[tidx];
cL = sc[tidx];
yL = sy[tidx];

bLp = sb[tL];
//Reduction phase
if (fabsf(aL) > EPS) {
aLp = sa[tL];
cLp = sc[tL];
yLp = sy[tL];

//bL = b[tidx] - a[tidx]*c[tidx]/b[tidx-1];
bL -= aL * cL / bLp;
//yL = y[tidx] - a[tidx]*y[tidx-1]/b[tidx-1];
yL -= aL * yLp / bLp;
//aL = -a[tidx]*a[tidx-1]/b[tidx-1];
aL = -aL * aLp / bLp;

//aL = -aL * aLp / bLp;
}

aLp = sa[tR];
bLp = sb[tR];
cLp = sc[tR];
if (fabsf(aLp) > EPS) {
yLp = sy[tR];
//bL -= c[tidx+1]*a[tidx+1]/b[tidx+1];
bL -= cLp * aLp / bLp;
//yL -= c[tidx+1]*y[tidx+1]/b[tidx+1];
yL -= cLp * yLp / bLp;

cL = -cL * cLp / bLp;
}
__syncthreads();
//Permutation phase
if (i < (int)log2((float)n)) {
sa[d] = aL;
sb[d] = bL;
sc[d] = cL;
sy[d] = yL;
sl[d] = (int)lL;
__syncthreads();
}
}

sy[(int)tidx] = yL / bL;
__syncthreads();
y[gb_index_x * n + sl[tidx]] = sy[tidx];
}
	.file	"tmpxft_0027b2f6_00000000-6_pcr_k.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z5pcr_kfffPfifffPfi
	.type	_Z28__device_stub__Z5pcr_kfffPfifffPfi, @function
_Z28__device_stub__Z5pcr_kfffPfifffPfi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 8(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movl	%esi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5pcr_kfffPfi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z28__device_stub__Z5pcr_kfffPfifffPfi, .-_Z28__device_stub__Z5pcr_kfffPfifffPfi
	.globl	_Z5pcr_kfffPfi
	.type	_Z5pcr_kfffPfi, @function
_Z5pcr_kfffPfi:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5pcr_kfffPfifffPfi
	.cfi_endproc
.LFE2033:
	.size	_Z5pcr_kfffPfi, .-_Z5pcr_kfffPfi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5pcr_kfffPfi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5pcr_kfffPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pcr_k(float a, float b, float c, float* y, int n) {
// Identifies the thread working within a group
int tidx = threadIdx.x % n;
// Identifies the data concerned by the computations
int Qt = (threadIdx.x - tidx) / n;
// The global memory access index
int gb_index_x = Qt + blockIdx.x * (blockDim.x / n);
// Local integers
int i, nt, lL, d, tL, tR;
// Local floats
float aL, bL, cL, yL, aLp, bLp, cLp, yLp;
// Shared memory
extern __shared__ float sAds[];

nt = 5 * Qt * n;
d = (n / 2 + (n % 2)) * (tidx % 2) + (int)tidx / 2;
float* sa = (float*)&sAds[nt];
float* sb = (float*)&sa[n];
float* sc = (float*)&sb[n];
float* sy = (float*)&sc[n];
int* sl = (int*)&sy[n];

sa[tidx] = a;
sb[tidx] = b;
sc[tidx] = c;
sy[tidx] = y[gb_index_x * n + tidx];
sl[tidx] = tidx;
__syncthreads();

//Left/Right indices of the reduction
tL = tidx - 1;
if (tL < 0) tL = 0;
tR = tidx + 1;
if (tR >= n) tR = 0;

for (i = 0; i < (int)log2((float)n) + 1; i++) {
lL = (int)sl[tidx];
aL = sa[tidx];
bL = sb[tidx];
cL = sc[tidx];
yL = sy[tidx];

bLp = sb[tL];
//Reduction phase
if (fabsf(aL) > EPS) {
aLp = sa[tL];
cLp = sc[tL];
yLp = sy[tL];

//bL = b[tidx] - a[tidx]*c[tidx]/b[tidx-1];
bL -= aL * cL / bLp;
//yL = y[tidx] - a[tidx]*y[tidx-1]/b[tidx-1];
yL -= aL * yLp / bLp;
//aL = -a[tidx]*a[tidx-1]/b[tidx-1];
aL = -aL * aLp / bLp;

//aL = -aL * aLp / bLp;
}

aLp = sa[tR];
bLp = sb[tR];
cLp = sc[tR];
if (fabsf(aLp) > EPS) {
yLp = sy[tR];
//bL -= c[tidx+1]*a[tidx+1]/b[tidx+1];
bL -= cLp * aLp / bLp;
//yL -= c[tidx+1]*y[tidx+1]/b[tidx+1];
yL -= cLp * yLp / bLp;

cL = -cL * cLp / bLp;
}
__syncthreads();
//Permutation phase
if (i < (int)log2((float)n)) {
sa[d] = aL;
sb[d] = bL;
sc[d] = cL;
sy[d] = yL;
sl[d] = (int)lL;
__syncthreads();
}
}

sy[(int)tidx] = yL / bL;
__syncthreads();
y[gb_index_x * n + sl[tidx]] = sy[tidx];
}
	.text
	.file	"pcr_k.hip"
	.globl	_Z20__device_stub__pcr_kfffPfi  # -- Begin function _Z20__device_stub__pcr_kfffPfi
	.type	_Z20__device_stub__pcr_kfffPfi,@function
_Z20__device_stub__pcr_kfffPfi:         # @_Z20__device_stub__pcr_kfffPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	16(%rsp), %rcx
	movss	%xmm1, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm2, (%rdx)
	leaq	40(%rsp), %r8
	movq	%rdi, (%r8)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rdi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5pcr_kfffPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__pcr_kfffPfi, .Lfunc_end0-_Z20__device_stub__pcr_kfffPfi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5pcr_kfffPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5pcr_kfffPfi,@object          # @_Z5pcr_kfffPfi
	.section	.rodata,"a",@progbits
	.globl	_Z5pcr_kfffPfi
	.p2align	3, 0x0
_Z5pcr_kfffPfi:
	.quad	_Z20__device_stub__pcr_kfffPfi
	.size	_Z5pcr_kfffPfi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5pcr_kfffPfi"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__pcr_kfffPfi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5pcr_kfffPfi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5pcr_kfffPfi          ; -- Begin function _Z5pcr_kfffPfi
	.globl	_Z5pcr_kfffPfi
	.p2align	8
	.type	_Z5pcr_kfffPfi,@function
_Z5pcr_kfffPfi:                         ; @_Z5pcr_kfffPfi
; %bb.0:
	s_clause 0x2
	s_load_b32 s6, s[0:1], 0x18
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[8:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s6
	s_sub_i32 s4, 0, s6
	s_and_b32 s2, s2, 0xffff
	v_mov_b32_e32 v10, s9
	v_mov_b32_e32 v12, s10
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s3
	s_mul_hi_u32 s4, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s4
	v_mul_hi_u32 v1, v0, s3
	s_mul_hi_u32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s3, s6
	s_sub_i32 s2, s2, s4
	s_add_i32 s4, s3, 1
	s_sub_i32 s5, s2, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v2, v1, s6
	v_add_nc_u32_e32 v3, 1, v1
	s_cmp_ge_u32 s2, s6
	s_cselect_b32 s3, s4, s3
	s_cselect_b32 s2, s5, s2
	s_add_i32 s4, s3, 1
	s_cmp_ge_u32 s2, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	s_cselect_b32 s2, s4, s3
	s_mov_b32 s4, 0
	v_subrev_nc_u32_e32 v4, s6, v2
	v_cmp_le_u32_e32 vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s6, v2
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s2, s15, v[1:2]
	v_mul_lo_u32 v3, v1, s6
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshl_b32 s0, s6, 2
	v_mul_lo_u32 v2, v2, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v0, v3
	v_lshlrev_b32_e32 v11, 2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v2, v7
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v8, v[0:1], off
	v_cvt_f32_i32_e32 v0, s6
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v1
	v_log_f32_e32 v5, v0
	v_mad_u64_u32 v[0:1], null, v3, 20, s[4:5]
	v_mov_b32_e32 v9, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, s0, v0
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v1, v5, v4 :: v_dual_add_nc_u32 v4, v0, v11
	v_add_nc_u32_e32 v17, s0, v15
	v_cvt_i32_f32_e32 v1, v1
	v_add_nc_u32_e32 v5, v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, s0, v17
	v_cmp_gt_i32_e32 vcc_lo, 0, v1
	v_readfirstlane_b32 s5, v1
	v_add_nc_u32_e32 v6, v17, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, s0, v18
	v_add_nc_u32_e32 v1, v18, v11
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	v_add_nc_u32_e32 v3, v19, v11
	ds_store_b32 v4, v9
	ds_store_b32 v5, v10
	ds_store_b32 v6, v12
	ds_store_b32 v3, v7
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_10
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v8, 1, v7
	s_lshr_b32 s0, s6, 31
	v_max_i32_e32 v9, 1, v7
	s_add_i32 s0, s6, s0
	v_bfe_i32 v10, v7, 0, 1
	s_and_b32 s1, s0, 0x3ffffffe
	v_cmp_gt_i32_e32 vcc_lo, s6, v8
	s_lshr_b32 s0, s0, 1
	s_sub_i32 s1, s6, s1
	v_lshl_add_u32 v9, v9, 2, -4
	s_add_i32 s0, s0, s1
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_and_b32_e32 v10, s0, v10
	v_lshrrev_b32_e32 v11, 1, v7
	v_add_nc_u32_e32 v7, v15, v9
	s_add_i32 s6, s5, 1
	v_lshlrev_b32_e32 v13, 2, v8
	v_add_nc_u32_e32 v8, v0, v9
	v_add_lshl_u32 v20, v10, v11, 2
	v_add_nc_u32_e32 v9, v18, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v0, v13
	v_add_nc_u32_e32 v11, v17, v13
	v_add_nc_u32_e32 v12, v15, v13
	v_add_nc_u32_e32 v13, v18, v13
	v_add_nc_u32_e32 v14, v0, v20
	v_add_nc_u32_e32 v16, v15, v20
	v_add_nc_u32_e32 v17, v17, v20
	v_add_nc_u32_e32 v18, v18, v20
	v_add_nc_u32_e32 v19, v19, v20
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v21, v4
	ds_load_b32 v0, v5
	ds_load_b32 v22, v6
	ds_load_b32 v20, v3
	ds_load_b32 v15, v1
	s_mov_b32 s7, exec_lo
	s_waitcnt lgkmcnt(4)
	v_cmpx_lt_f32_e64 0x33d6bf95, |v21|
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v23, v9
	ds_load_b32 v24, v7
	ds_load_b32 v25, v8
	s_waitcnt lgkmcnt(5)
	v_mul_f32_e32 v26, v21, v22
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v27, null, v24, v24, v26
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v27, v28, 1.0
	v_mul_f32_e32 v23, v21, v23
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v21, v25, -v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v32, v28
	v_div_scale_f32 v25, null, v24, v24, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v29, null, v24, v24, v21
	v_div_scale_f32 v35, s0, v23, v24, v23
	v_rcp_f32_e32 v30, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v25, v30, 1.0
	v_fma_f32 v32, -v29, v31, 1.0
	v_dual_fmac_f32 v30, v34, v30 :: v_dual_fmac_f32 v31, v32, v31
	v_div_scale_f32 v33, vcc_lo, v26, v24, v26
	v_div_scale_f32 v34, s1, v21, v24, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v32, v35, v30
	v_mul_f32_e32 v36, v33, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v38, v34, v31
	v_fma_f32 v39, -v25, v32, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v27, v36, v33
	v_fmac_f32_e32 v32, v39, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v36, v37, v28
	v_fma_f32 v37, -v29, v38, v34
	v_fma_f32 v25, -v25, v32, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v27, -v27, v36, v33
	v_fmac_f32_e32 v38, v37, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v27, v27, v28, v36
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v28, -v29, v38, v34
	v_div_fmas_f32 v25, v25, v30, v32
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v26, v27, v24, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v23, v25, v24, v23
	v_div_fmas_f32 v25, v28, v31, v38
	v_dual_sub_f32 v0, v0, v26 :: v_dual_sub_f32 v15, v15, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v21, v25, v24, v21
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	ds_load_b32 v23, v10
	s_mov_b32 s7, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_f32_e64 0x33d6bf95, |v23|
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v24, v11
	ds_load_b32 v25, v13
	ds_load_b32 v26, v12
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v23, v23, v24
	s_waitcnt lgkmcnt(1)
	v_mul_f32_e32 v25, v24, v25
	v_mul_f32_e64 v22, v24, -v22
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v24, null, v26, v26, v25
	v_div_scale_f32 v29, null, v26, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v30, v24
	v_rcp_f32_e32 v31, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v24, v30, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v34, v30
	v_div_scale_f32 v27, null, v26, v26, v23
	v_div_scale_f32 v33, vcc_lo, v23, v26, v23
	v_div_scale_f32 v34, s1, v22, v26, v22
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v27, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v32, v28
	v_fma_f32 v32, -v29, v31, 1.0
	v_mul_f32_e32 v36, v33, v28
	v_div_scale_f32 v35, s0, v25, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v31, v32, v31
	v_fma_f32 v37, -v27, v36, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v32, v35, v30
	v_fmac_f32_e32 v36, v37, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v24, v32, v35
	v_fma_f32 v27, -v27, v36, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v39, v30
	v_div_fmas_f32 v27, v27, v28, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v24, v32, v35
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v23, v27, v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v24, v24, v30, v32
	s_mov_b32 vcc_lo, s1
	v_sub_f32_e32 v0, v0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v24, v24, v26, v25
	v_dual_mul_f32 v38, v34, v31 :: v_dual_sub_f32 v15, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, -v29, v38, v34
	v_fmac_f32_e32 v38, v37, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, -v29, v38, v34
	v_div_fmas_f32 v25, v28, v31, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v22, v25, v26, v22
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmp_ge_i32 s4, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_store_b32 v14, v21
	ds_store_b32 v16, v0
	ds_store_b32 v17, v22
	ds_store_b32 v18, v15
	ds_store_b32 v19, v20
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s6, s4
	s_cbranch_scc1 .LBB0_2
; %bb.9:                                ; %._crit_edge.loopexit
	v_div_scale_f32 v4, null, v0, v0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v15, v0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v0, v4, v0, v15
	s_branch .LBB0_11
.LBB0_10:
                                        ; implicit-def: $vgpr0
.LBB0_11:                               ; %._crit_edge
	ds_store_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v0, v2
	ds_load_b32 v2, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5pcr_kfffPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5pcr_kfffPfi, .Lfunc_end0-_Z5pcr_kfffPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1744
; NumSgprs: 18
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5pcr_kfffPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5pcr_kfffPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
