#include <stdio.h>
#include <cuda.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width) 
{
    int i = blockIdx.x*blockDim.x + threadIdx.x;
    __shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
    int n = Mask_Width/2;
    /******************************************************************/
    /* Your TODO-1 starts here:                                       */ 
    /* Load the data with halo from N to the shared memory N_ds       */ 
    /*  remember that you need to load:                               */
    /*  + the left halo                                               */
    /*  + the data                                                    */    
    /*  + the right halo                                              */    
    /******************************************************************/
    int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
    int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
    if(threadIdx.x>=blockDim.x-n)
        N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
    N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
    if(threadIdx.x<n)
        N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
    __syncthreads();
    /***********************/
    /*Your TODO-1 ends here*/               
    /***********************/
    /******************************************************************/
    /* Your TODO-2 starts here:                                       */ 
    /* Calculate the value coresponding to each thread                */ 
    /* The result is saved into the array P                           */
    /* It should be noted that the mask M is already copy to the      */                                                  
    /* constant memory                                                */    
    /******************************************************************/
    float Pvalue = 0;
    for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
    P[i] = Pvalue;
    /***********************/
    /*Your TODO-2 ends here*/               
    /***********************/   
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
    int i;
    /*******************/
    /** READING INPUT **/
    /*******************/
    /* dimension of mask */
    int size_m = 0;
    scanf("%d", &size_m);
    int full_size_m = size_m*sizeof(float);
    float* h_M = (float*)malloc(full_size_m);
    for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
    /* dimension of array */
    int size = 0; 
    scanf("%d", &size);
    int full_size = sizeof(float)*size;
    /* Allocate host memory */
    float* h_N = (float*)malloc(full_size);
    float* h_P = (float*)malloc(full_size);
    for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
    /********************/
    /** FINISHED INPUT **/
    /********************/
    /*************************/
    /* allocate device memory */
    /*************************/
    float* d_N,*d_P;
    cudaMalloc(&d_N, full_size);
    cudaMalloc(&d_P, full_size);
    /******************************/
    /* copy array & mask to device */
    /******************************/
    cudaMemcpy(d_N,h_N,full_size,cudaMemcpyHostToDevice);
    cudaMemcpyToSymbol(M,h_M,full_size_m);
    /****************/
    /** CALL KERNEL */ 
    /****************/
    int threadsPerBlock = size;
    Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
    checkCUDAError("Kernel Invoking");
    /**************************/
    /*   copy result back     */
    /**************************/
    cudaMemcpy(h_P, d_P, full_size, cudaMemcpyDeviceToHost);
    /*******************************************/
    /*  Testing output, don't change anything! */
    /*******************************************/
    test(h_P, size);
    free(h_N);
    free(h_P);
    cudaFree(d_N);
    cudaFree(d_P);
    return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
    int i=0;
    for(i=0;i<length;++i){
        printf("%.1f ", C[i]);
    }
    printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
    cudaError_t err = cudaGetLastError();
    if( cudaSuccess != err) 
    {
        fprintf(stderr, "Cuda error: %s: %s.\n", msg, 
        cudaGetErrorString( err) );
        exit(EXIT_FAILURE);
    }                         
}

	.file	"tmpxft_003955d2_00000000-6_cuda1DCovolution.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%.1f "
.LC1:
	.string	"\n"
	.text
	.globl	_Z4testPfi
	.type	_Z4testPfi, @function
_Z4testPfi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
.L3:
	cmpl	%ebx, %ebp
	jle	.L7
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC1(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z4testPfi, .-_Z4testPfi
	.section	.rodata.str1.1
.LC2:
	.string	"Cuda error: %s: %s.\n"
	.text
	.globl	_Z14checkCUDAErrorPKc
	.type	_Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L8
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	leaq	.LC2(%rip), %rdx
	movq	%rax, %r8
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
	.globl	_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
	.type	_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, @function
_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6Conv1DPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, .-_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
	.globl	_Z6Conv1DPfS_ii
	.type	_Z6Conv1DPfS_ii, @function
_Z6Conv1DPfS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
	.cfi_endproc
.LFE2055:
	.size	_Z6Conv1DPfS_ii, .-_Z6Conv1DPfS_ii
	.section	.rodata.str1.1
.LC3:
	.string	"%d"
.LC4:
	.string	"%f"
.LC5:
	.string	"Kernel Invoking"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edx, %edx
	leaq	.LC4(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	.LC3(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r13, %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rsi
	movl	%edx, 24(%rsp)
	call	__isoc23_scanf@PLT
	movl	24(%rsp), %eax
	leal	0(,%rax,4), %ebp
	movslq	%ebp, %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rax, %r14
	movq	%rax, %r12
.L17:
	cmpl	%ebx, 24(%rsp)
	jle	.L24
	movq	%r12, %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	incl	%ebx
	call	__isoc23_scanf@PLT
	addq	$4, %r12
	jmp	.L17
.L24:
	xorl	%eax, %eax
	leaq	28(%rsp), %rsi
	movq	%r13, %rdi
	xorl	%r12d, %r12d
	movl	%eax, 28(%rsp)
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	28(%rsp), %eax
	leal	0(,%rax,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%r13, %r15
	movq	%rax, 8(%rsp)
.L19:
	cmpl	%r12d, 28(%rsp)
	jle	.L25
	movq	%r15, %rsi
	leaq	.LC4(%rip), %rdi
	xorl	%eax, %eax
	incl	%r12d
	call	__isoc23_scanf@PLT
	addq	$4, %r15
	jmp	.L19
.L25:
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbp, %rdx
	movq	%r14, %rsi
	leaq	_ZL1M(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	28(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	movl	%eax, 60(%rsp)
	movq	60(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movl	28(%rsp), %ecx
	movl	24(%rsp), %edx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
.L21:
	leaq	.LC5(%rip), %rdi
	call	_Z14checkCUDAErrorPKc
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %esi
	movq	8(%rsp), %rdi
	call	_Z4testPfi
	movq	%r13, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z6Conv1DPfS_ii"
.LC7:
	.string	"M"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6Conv1DPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movl	$44, %r9d
	leaq	_ZL1M(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL1M
	.comm	_ZL1M,44,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width) 
{
    int i = blockIdx.x*blockDim.x + threadIdx.x;
    __shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
    int n = Mask_Width/2;
    /******************************************************************/
    /* Your TODO-1 starts here:                                       */ 
    /* Load the data with halo from N to the shared memory N_ds       */ 
    /*  remember that you need to load:                               */
    /*  + the left halo                                               */
    /*  + the data                                                    */    
    /*  + the right halo                                              */    
    /******************************************************************/
    int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
    int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
    if(threadIdx.x>=blockDim.x-n)
        N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
    N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
    if(threadIdx.x<n)
        N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
    __syncthreads();
    /***********************/
    /*Your TODO-1 ends here*/               
    /***********************/
    /******************************************************************/
    /* Your TODO-2 starts here:                                       */ 
    /* Calculate the value coresponding to each thread                */ 
    /* The result is saved into the array P                           */
    /* It should be noted that the mask M is already copy to the      */                                                  
    /* constant memory                                                */    
    /******************************************************************/
    float Pvalue = 0;
    for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
    P[i] = Pvalue;
    /***********************/
    /*Your TODO-2 ends here*/               
    /***********************/   
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
    int i;
    /*******************/
    /** READING INPUT **/
    /*******************/
    /* dimension of mask */
    int size_m = 0;
    scanf("%d", &size_m);
    int full_size_m = size_m*sizeof(float);
    float* h_M = (float*)malloc(full_size_m);
    for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
    /* dimension of array */
    int size = 0; 
    scanf("%d", &size);
    int full_size = sizeof(float)*size;
    /* Allocate host memory */
    float* h_N = (float*)malloc(full_size);
    float* h_P = (float*)malloc(full_size);
    for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
    /********************/
    /** FINISHED INPUT **/
    /********************/
    /*************************/
    /* allocate device memory */
    /*************************/
    float* d_N,*d_P;
    hipMalloc(&d_N, full_size);
    hipMalloc(&d_P, full_size);
    /******************************/
    /* copy array & mask to device */
    /******************************/
    hipMemcpy(d_N,h_N,full_size,hipMemcpyHostToDevice);
    hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,full_size_m);
    /****************/
    /** CALL KERNEL */ 
    /****************/
    int threadsPerBlock = size;
    Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
    checkCUDAError("Kernel Invoking");
    /**************************/
    /*   copy result back     */
    /**************************/
    hipMemcpy(h_P, d_P, full_size, hipMemcpyDeviceToHost);
    /*******************************************/
    /*  Testing output, don't change anything! */
    /*******************************************/
    test(h_P, size);
    free(h_N);
    free(h_P);
    hipFree(d_N);
    hipFree(d_P);
    return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
    int i=0;
    for(i=0;i<length;++i){
        printf("%.1f ", C[i]);
    }
    printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
    hipError_t err = hipGetLastError();
    if( hipSuccess != err) 
    {
        fprintf(stderr, "Cuda error: %s: %s.\n", msg, 
        hipGetErrorString( err) );
        exit(EXIT_FAILURE);
    }                         
}

	.text
	.file	"cuda1DCovolution.hip"
	.globl	_Z21__device_stub__Conv1DPfS_ii # -- Begin function _Z21__device_stub__Conv1DPfS_ii
	.type	_Z21__device_stub__Conv1DPfS_ii,@function
_Z21__device_stub__Conv1DPfS_ii:        # @_Z21__device_stub__Conv1DPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6Conv1DPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__Conv1DPfS_ii, .Lfunc_end0-_Z21__device_stub__Conv1DPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %rbx
	movl	$0, (%rbx)
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %ebx
	leal	(,%rbx,4), %eax
	movslq	%eax, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r12
	testl	%ebx, %ebx
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%r12, %rbx
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r15
	movslq	12(%rsp), %rax
	addq	$4, %rbx
	cmpq	%rax, %r15
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	%r12, 32(%rsp)                  # 8-byte Spill
	leaq	8(%rsp), %rbx
	movl	$0, (%rbx)
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %r13d
	leal	(,%r13,4), %eax
	movslq	%eax, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	testl	%r13d, %r13d
	jle	.LBB1_6
# %bb.4:                                # %.lr.ph30.preheader
	movq	%rbx, %rbp
	xorl	%r13d, %r13d
.LBB1_5:                                # %.lr.ph30
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.1, %edi
	movq	%rbp, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r13
	movslq	8(%rsp), %rax
	addq	$4, %rbp
	cmpq	%rax, %r13
	jl	.LBB1_5
.LBB1_6:                                # %._crit_edge31
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$M, %edi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	8(%rsp), %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	12(%rsp), %edx
	movl	8(%rsp), %ecx
	callq	_Z21__device_stub__Conv1DPfS_ii
.LBB1_8:
	movl	$.L.str.2, %edi
	callq	_Z14checkCUDAErrorPKc
	movq	16(%rsp), %rsi
	movq	%r15, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	8(%rsp), %esi
	movq	%r15, %rdi
	callq	_Z4testPfi
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCUDAErrorPKc           # -- Begin function _Z14checkCUDAErrorPKc
	.type	_Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc:                  # @_Z14checkCUDAErrorPKc
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 32
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z4testPfi                      # -- Begin function _Z4testPfi
	.type	_Z4testPfi,@function
_Z4testPfi:                             # @_Z4testPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB3_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB3_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB3_4:                                # %._crit_edge
	movl	$10, %edi
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end3:
	.size	_Z4testPfi, .Lfunc_end3-_Z4testPfi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6Conv1DPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$M, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$44, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	M,@object                       # @M
	.local	M
	.comm	M,44,16
	.type	_Z6Conv1DPfS_ii,@object         # @_Z6Conv1DPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z6Conv1DPfS_ii
	.p2align	3, 0x0
_Z6Conv1DPfS_ii:
	.quad	_Z21__device_stub__Conv1DPfS_ii
	.size	_Z6Conv1DPfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%f"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Kernel Invoking"
	.size	.L.str.2, 16

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%.1f "
	.size	.L.str.3, 6

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Cuda error: %s: %s.\n"
	.size	.L.str.5, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6Conv1DPfS_ii"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"M"
	.size	.L__unnamed_2, 2

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__Conv1DPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym M
	.addrsig_sym _Z6Conv1DPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6Conv1DPfS_ii         ; -- Begin function _Z6Conv1DPfS_ii
	.globl	_Z6Conv1DPfS_ii
	.p2align	8
	.type	_Z6Conv1DPfS_ii,@function
_Z6Conv1DPfS_ii:                        ; @_Z6Conv1DPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b32 s6, s[0:1], 0x24
	s_load_b128 s[0:3], s[0:1], 0x0
                                        ; implicit-def: $vgpr3
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s4, 31
	s_and_b32 s6, s6, 0xffff
	s_add_i32 s7, s4, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s8, s7, 1
	s_sub_i32 s7, s6, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s7, v0
	s_add_i32 s7, s15, 1
	s_mul_i32 s7, s7, s6
	s_and_saveexec_b32 s9, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_lshl_b32 s10, s6, 1
	v_mov_b32_e32 v2, 0
	s_sub_i32 s10, s7, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s10, v0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v3, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v1, s6, v3
	v_lshlrev_b32_e32 v1, 2, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
.LBB0_4:                                ; %Flow50
	s_and_not1_saveexec_b32 s9, s9
; %bb.5:                                ; %._crit_edge32
	v_add_nc_u32_e32 v3, s8, v0
; %bb.6:
	s_or_b32 exec_lo, exec_lo, s9
	v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v0
	global_load_b32 v4, v[4:5], off
	v_lshlrev_b32_e32 v5, 2, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.7:
	v_add_nc_u32_e32 v3, s7, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s5, v3
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v3, s6, 2, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v2
.LBB0_10:                               ; %Flow49
	s_or_b32 exec_lo, exec_lo, s8
	s_cmp_lt_i32 s4, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_13
; %bb.11:                               ; %.lr.ph.preheader
	v_lshlrev_b32_e32 v2, 2, v0
	v_mov_b32_e32 v0, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, M@rel32@lo+4
	s_addc_u32 s1, s1, M@rel32@hi+12
.LBB0_12:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v3, v2
	s_load_b32 s5, s[0:1], 0x0
	s_add_i32 s4, s4, -1
	v_add_nc_u32_e32 v2, 4, v2
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s4, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v0, s5, v3
	s_cbranch_scc0 .LBB0_12
	s_branch .LBB0_14
.LBB0_13:
	v_mov_b32_e32 v0, 0
.LBB0_14:                               ; %Flow48
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6Conv1DPfS_ii
		.amdhsa_group_segment_fixed_size 168
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6Conv1DPfS_ii, .Lfunc_end0-_Z6Conv1DPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 532
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 168 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	M                       ; @M
	.type	M,@object
	.section	.bss,"aw",@nobits
	.globl	M
	.p2align	4, 0x0
M:
	.zero	44
	.size	M, 44

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym M
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 168
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6Conv1DPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6Conv1DPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
