#include "../image_headers/hough.cuh"
#include <iostream>
#include <cmath>
#include <cstdio>

__global__ void hough_kernel(int* line_matrix, int* image, int width, int height, int diag) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i = idx / width;
	int j = idx % width;

	if (idx < width * height) {
		for (int r = 0; r <= diag; r++) {
			for (float theta = 0; theta < 360; theta = theta + 1) {
				if (r == (int)(i * cosf(theta) + j * sinf(theta))) {
					//printf("Doing an add!!!");
					if (image[i * width + j] == 255) {
						atomicAdd(line_matrix + r * 360 + (int)theta, 1);
					}
				}
			}
		}
	}
}

void hough(int* line_matrix, int* image, int width, int height, int diag, unsigned int threads_per_block) {
	size_t number_of_blocks = (width * height + threads_per_block - 1) / threads_per_block;
	hough_kernel<<<number_of_blocks, threads_per_block>>>(line_matrix, image, width, height, diag);
	cudaDeviceSynchronize();
}
	.file	"tmpxft_002b866e_00000000-6_hough.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii
	.type	_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii, @function
_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12hough_kernelPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii, .-_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii
	.globl	_Z12hough_kernelPiS_iii
	.type	_Z12hough_kernelPiS_iii, @function
_Z12hough_kernelPiS_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii
	.cfi_endproc
.LFE3661:
	.size	_Z12hough_kernelPiS_iii, .-_Z12hough_kernelPiS_iii
	.globl	_Z5houghPiS_iiij
	.type	_Z5houghPiS_iiij, @function
_Z5houghPiS_iiij:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%edx, %eax
	movl	%ecx, %r14d
	movabsq	$4294967297, %rcx
	imull	%r14d, %eax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%r8d, %r13d
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leal	-1(%r9,%rax), %eax
	movl	%edx, %ebx
	xorl	%edx, %edx
	divl	%r9d
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movq	%rcx, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%r9d, 20(%rsp)
	xorl	%r9d, %r9d
	movq	%rcx, 24(%rsp)
	movl	28(%rsp), %ecx
	movq	20(%rsp), %rdx
	movl	%eax, 8(%rsp)
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movl	%r13d, %r8d
	movl	%r14d, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z37__device_stub__Z12hough_kernelPiS_iiiPiS_iii
.L9:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z5houghPiS_iiij, .-_Z5houghPiS_iiij
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12hough_kernelPiS_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12hough_kernelPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "../image_headers/hough.cuh"
#include <iostream>
#include <cmath>
#include <cstdio>

__global__ void hough_kernel(int* line_matrix, int* image, int width, int height, int diag) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int i = idx / width;
	int j = idx % width;

	if (idx < width * height) {
		for (int r = 0; r <= diag; r++) {
			for (float theta = 0; theta < 360; theta = theta + 1) {
				if (r == (int)(i * cosf(theta) + j * sinf(theta))) {
					//printf("Doing an add!!!");
					if (image[i * width + j] == 255) {
						atomicAdd(line_matrix + r * 360 + (int)theta, 1);
					}
				}
			}
		}
	}
}

void hough(int* line_matrix, int* image, int width, int height, int diag, unsigned int threads_per_block) {
	size_t number_of_blocks = (width * height + threads_per_block - 1) / threads_per_block;
	hough_kernel<<<number_of_blocks, threads_per_block>>>(line_matrix, image, width, height, diag);
	hipDeviceSynchronize();
}
	.text
	.file	"hough.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__hough_kernelPiS_iii # -- Begin function _Z27__device_stub__hough_kernelPiS_iii
	.type	_Z27__device_stub__hough_kernelPiS_iii,@function
_Z27__device_stub__hough_kernelPiS_iii: # @_Z27__device_stub__hough_kernelPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12hough_kernelPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__hough_kernelPiS_iii, .Lfunc_end0-_Z27__device_stub__hough_kernelPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5houghPiS_iiij                # -- Begin function _Z5houghPiS_iiij
	.type	_Z5houghPiS_iiij,@function
_Z5houghPiS_iiij:                       # @_Z5houghPiS_iiij
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
	movl	%r8d, %ebx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	%ecx, %eax
	imull	%edx, %eax
	addl	%r9d, %eax
	decl	%eax
	xorl	%edx, %edx
	divl	%r9d
                                        # kill: def $eax killed $eax def $rax
	btsq	$32, %rax
	movl	%r9d, %edx
	btsq	$32, %rdx
	movq	%rax, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	callq	_Z27__device_stub__hough_kernelPiS_iii
.LBB1_2:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	_Z5houghPiS_iiij, .Lfunc_end1-_Z5houghPiS_iiij
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12hough_kernelPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12hough_kernelPiS_iii,@object # @_Z12hough_kernelPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z12hough_kernelPiS_iii
	.p2align	3, 0x0
_Z12hough_kernelPiS_iii:
	.quad	_Z27__device_stub__hough_kernelPiS_iii
	.size	_Z12hough_kernelPiS_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12hough_kernelPiS_iii"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__hough_kernelPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12hough_kernelPiS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12hough_kernelPiS_iii ; -- Begin function _Z12hough_kernelPiS_iii
	.globl	_Z12hough_kernelPiS_iii
	.p2align	8
	.type	_Z12hough_kernelPiS_iii,@function
_Z12hough_kernelPiS_iii:                ; @_Z12hough_kernelPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_gt_i32 s6, -1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_19
; %bb.1:                                ; %.preheader.lr.ph
	s_ashr_i32 s2, s4, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s3, s4, s2
	s_mov_b32 s7, 0xb94c1982
	s_xor_b32 s3, s3, s2
	s_mov_b32 s8, 0x37d75334
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s5, 0, s3
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v4, v4, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s5, v0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s9, s5
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s3
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v5
	v_mul_lo_u32 v0, v4, s4
	s_mov_b32 s4, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v1, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	v_cvt_f32_i32_e32 v2, v4
	v_cvt_f32_i32_e32 v3, v5
	v_mov_b32_e32 v4, 0
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_lshl_b64 s[2:3], s[4:5], 2
	s_mov_b32 s10, 0
	s_add_u32 s2, s0, s2
	s_addc_u32 s3, s1, s3
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cvt_f32_i32_e32 v5, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e64 s12, 0x48000000, |v5|
	v_readfirstlane_b32 s11, v5
	s_and_b32 vcc_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_bitset0_b32 s11, 31
	s_cbranch_vccz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	s_and_b32 s13, s11, 0x7fffff
	s_lshr_b32 s14, s11, 23
	s_bitset1_b32 s13, 23
	s_addk_i32 s14, 0xff88
	s_mul_hi_u32 s15, s13, 0xfe5163ab
	s_mul_i32 s16, s13, 0x3c439041
	s_mul_hi_u32 s17, s13, 0x3c439041
	s_add_u32 s15, s15, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s13, 0xdb629599
	s_mul_hi_u32 s18, s13, 0xdb629599
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s13, 0xf534ddc0
	s_mul_hi_u32 s19, s13, 0xf534ddc0
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s13, 0xfc2757d1
	s_mul_hi_u32 s20, s13, 0xfc2757d1
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_mul_i32 s20, s13, 0x4e441529
	s_mul_hi_u32 s21, s13, 0x4e441529
	s_add_u32 s19, s19, s20
	s_addc_u32 s20, 0, s21
	s_cmp_gt_u32 s14, 63
	s_mul_i32 s21, s13, 0xfe5163ab
	s_mul_hi_u32 s22, s13, 0xa2f9836e
	s_mul_i32 s13, s13, 0xa2f9836e
	s_cselect_b32 s23, s16, s18
	s_cselect_b32 s15, s15, s17
	s_cselect_b32 s16, s21, s16
	s_add_u32 s13, s20, s13
	s_addc_u32 s20, 0, s22
	s_cmp_gt_u32 s14, 63
	s_cselect_b32 s21, 0xffffffc0, 0
	s_cselect_b32 s17, s17, s19
	s_cselect_b32 s13, s18, s13
	s_cselect_b32 s18, s19, s20
	s_add_i32 s21, s21, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s21, 31
	s_cselect_b32 s14, 0xffffffe0, 0
	s_cselect_b32 s19, s17, s13
	s_cselect_b32 s13, s13, s18
	s_cselect_b32 s17, s23, s17
	s_cselect_b32 s18, s15, s23
	s_cselect_b32 s15, s16, s15
	s_add_i32 s14, s14, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s14, 31
	s_cselect_b32 s16, 0xffffffe0, 0
	s_cselect_b32 s13, s19, s13
	s_cselect_b32 s19, s17, s19
	s_cselect_b32 s17, s18, s17
	s_cselect_b32 s15, s15, s18
	s_add_i32 s16, s16, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s14, 32, s16
	s_cmp_eq_u32 s16, 0
	v_mov_b32_e32 v6, s14
	s_cselect_b32 s16, -1, 0
	v_alignbit_b32 v7, s13, s19, v6
	v_alignbit_b32 v8, s19, s17, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s14, v7
	v_cndmask_b32_e64 v7, v8, s19, s16
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s13, s13, s14
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, s13, v7, 30
	s_bfe_u32 s14, s13, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s18, 0, s14
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s18, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v8
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 23, v9
	v_alignbit_b32 v6, s17, s15, v6
	v_sub_nc_u32_e32 v10, 31, v9
	v_cndmask_b32_e64 v6, v6, s17, s16
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v6, v6, s15, 30
	s_lshr_b32 s15, s13, 29
	s_lshr_b32 s13, s13, 30
	s_lshl_b32 s15, s15, 31
	v_xor_b32_e32 v7, s18, v7
	v_xor_b32_e32 v6, s18, v6
	s_or_b32 s16, s15, 0.5
	s_add_i32 s14, s14, s13
	v_sub_nc_u32_e32 v11, s16, v11
	v_alignbit_b32 v8, v8, v7, v10
	v_alignbit_b32 v6, v7, v6, v10
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v8, v6, 9
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v12, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v7, v6, v12
	v_or_b32_e32 v7, v8, v11
	v_add_nc_u32_e32 v9, v10, v9
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, 0x3fc90fda, v7 :: v_dual_lshlrev_b32 v8, 23, v9
	v_sub_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v7, -v9
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, 0x33a22168, v7
	v_or_b32_e32 v6, s15, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v6
	v_add_f32_e32 v6, v9, v8
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s13, -1
                                        ; implicit-def: $sgpr14
                                        ; implicit-def: $vgpr6
.LBB0_6:                                ; %Flow59
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_mul_f32_e64 v8, 0x3f22f983, |v5|
	v_mov_b32_e32 v7, s14
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_delay_alu instid0(VALU_DEP_2)
	v_rndne_f32_e32 v8, v8
	s_cbranch_vccnz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0xbfc90fda, v8, |v5|
	v_cvt_i32_f32_e32 v7, v8
	v_fmac_f32_e32 v6, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0xa7c234c4, v8
.LBB0_8:                                ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=2
	s_and_b32 s12, s11, 0x7fffff
	s_lshr_b32 s13, s11, 23
	s_bitset1_b32 s12, 23
	s_addk_i32 s13, 0xff88
	s_mul_hi_u32 s14, s12, 0xfe5163ab
	s_mul_i32 s15, s12, 0x3c439041
	s_mul_hi_u32 s16, s12, 0x3c439041
	s_add_u32 s14, s14, s15
	s_addc_u32 s15, 0, s16
	s_mul_i32 s16, s12, 0xdb629599
	s_mul_hi_u32 s17, s12, 0xdb629599
	s_add_u32 s15, s15, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s12, 0xf534ddc0
	s_mul_hi_u32 s18, s12, 0xf534ddc0
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s12, 0xfc2757d1
	s_mul_hi_u32 s19, s12, 0xfc2757d1
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s12, 0x4e441529
	s_mul_hi_u32 s20, s12, 0x4e441529
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_cmp_gt_u32 s13, 63
	s_mul_i32 s20, s12, 0xfe5163ab
	s_mul_hi_u32 s21, s12, 0xa2f9836e
	s_mul_i32 s12, s12, 0xa2f9836e
	s_cselect_b32 s22, s15, s17
	s_cselect_b32 s14, s14, s16
	s_cselect_b32 s15, s20, s15
	s_add_u32 s12, s19, s12
	s_addc_u32 s19, 0, s21
	s_cmp_gt_u32 s13, 63
	s_cselect_b32 s20, 0xffffffc0, 0
	s_cselect_b32 s16, s16, s18
	s_cselect_b32 s12, s17, s12
	s_cselect_b32 s17, s18, s19
	s_add_i32 s20, s20, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s20, 31
	s_cselect_b32 s13, 0xffffffe0, 0
	s_cselect_b32 s18, s16, s12
	s_cselect_b32 s12, s12, s17
	s_cselect_b32 s16, s22, s16
	s_cselect_b32 s17, s14, s22
	s_cselect_b32 s14, s15, s14
	s_add_i32 s13, s13, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s13, 31
	s_cselect_b32 s15, 0xffffffe0, 0
	s_cselect_b32 s12, s18, s12
	s_cselect_b32 s18, s16, s18
	s_cselect_b32 s16, s17, s16
	s_cselect_b32 s14, s14, s17
	s_add_i32 s15, s15, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s13, 32, s15
	s_cmp_eq_u32 s15, 0
	v_mov_b32_e32 v9, s13
	s_cselect_b32 s15, -1, 0
	v_alignbit_b32 v10, s12, s18, v9
	v_alignbit_b32 v11, s18, s16, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s13, v10
	v_cndmask_b32_e64 v10, v11, s18, s15
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s12, s12, s13
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v11, s12, v10, 30
	s_bfe_u32 s13, s12, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s17, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v11, s17, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v11
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v14, 23, v12
	v_alignbit_b32 v9, s16, s14, v9
	v_sub_nc_u32_e32 v13, 31, v12
	v_cndmask_b32_e64 v9, v9, s16, s15
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v10, v10, v9, 30
	v_alignbit_b32 v9, v9, s14, 30
	s_lshr_b32 s14, s12, 29
	s_lshr_b32 s12, s12, 30
	s_lshl_b32 s14, s14, 31
	v_xor_b32_e32 v10, s17, v10
	v_xor_b32_e32 v9, s17, v9
	s_or_b32 s15, s14, 0.5
	s_add_i32 s13, s13, s12
	v_sub_nc_u32_e32 v14, s15, v14
	v_alignbit_b32 v11, v11, v10, v13
	v_alignbit_b32 v9, v10, v9, v13
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v11, v9, 9
	v_lshrrev_b32_e32 v11, 9, v11
	v_clz_i32_u32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v13, 32, v13
	v_sub_nc_u32_e32 v15, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v10, v9, v15
	v_or_b32_e32 v10, v11, v14
	v_add_nc_u32_e32 v12, v13, v12
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, 0x3fc90fda, v10 :: v_dual_lshlrev_b32 v11, 23, v12
	v_sub_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3fc90fda, v10, -v12
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 0x33a22168, v10
	v_or_b32_e32 v9, s14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0x3fc90fda, v9
	v_add_f32_e32 v9, v12, v11
	s_branch .LBB0_11
.LBB0_10:                               ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $vgpr9
.LBB0_11:                               ; %Flow58
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_mov_b32_e32 v10, s13
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=2
	v_fma_f32 v9, 0xbfc90fda, v8, |v5|
	v_cvt_i32_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0xb3a22168, v8
	v_fmac_f32_e32 v9, 0xa7c234c4, v8
.LBB0_13:                               ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v8, v9, v9 :: v_dual_mul_f32 v11, v6, v6
	v_and_b32_e32 v12, 1, v7
	v_lshlrev_b32_e32 v7, 30, v7
	v_and_b32_e32 v15, 1, v10
	v_dual_fmaak_f32 v13, s7, v8, 0x3c0881c4 :: v_dual_fmaak_f32 v16, s7, v11, 0x3c0881c4
	v_dual_fmaak_f32 v14, s8, v8, 0xbab64f3b :: v_dual_fmaak_f32 v17, s8, v11, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v13, v8, v13, 0xbe2aaa9d :: v_dual_lshlrev_b32 v10, 30, v10
	v_fmaak_f32 v16, v11, v16, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v14, v8, v14, 0x3d2aabf7 :: v_dual_fmaak_f32 v17, v11, v17, 0x3d2aabf7
	v_xor_b32_e32 v5, s11, v5
	v_dual_mul_f32 v13, v8, v13 :: v_dual_mul_f32 v16, v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v14, v8, v14, 0xbf000004 :: v_dual_fmaak_f32 v17, v11, v17, 0xbf000004
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_dual_fmac_f32 v9, v9, v13 :: v_dual_and_b32 v10, 0x80000000, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v8, v8, v14, 1.0
	v_dual_fmac_f32 v6, v6, v16 :: v_dual_and_b32 v7, 0x80000000, v7
	v_fma_f32 v11, v11, v17, 1.0
	v_xor_b32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	s_mov_b32 s11, exec_lo
	v_xor_b32_e32 v5, v5, v8
	v_cndmask_b32_e64 v6, -v6, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, v5, v3
	v_xor_b32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v2
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e64 s9, v5
	s_cbranch_execz .LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0xff, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.15:                               ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v5, s12, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_and_b32 s13, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s13
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s12
	global_atomic_add_u32 v4, v5, s[2:3]
.LBB0_17:                               ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_add_i32 s10, s10, 1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s10, 0x168
	s_cbranch_scc0 .LBB0_3
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s2, s9, 1
	s_addk_i32 s4, 0x168
	s_cmp_eq_u32 s9, s6
	s_mov_b32 s9, s2
	s_cbranch_scc0 .LBB0_2
.LBB0_19:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12hough_kernelPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12hough_kernelPiS_iii, .Lfunc_end0-_Z12hough_kernelPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2192
; NumSgprs: 26
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12hough_kernelPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z12hough_kernelPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
