#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <vector>
#include "vector_types.h"
#include <unistd.h>
#include <time.h>
#include "device_functions.h"
#include "cuda.h"
#include <cuda_runtime.h>

#define fix1 3.14 / (60 * 180)

using namespace std;

__global__ void angles(volatile float *a0, volatile float *b0, volatile float *a1, volatile float*b1, volatile int *hist, volatile int* hist_r, volatile int* hist_s)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	float ac, bb0, sb1, sb0, cb0, k, bb1, ssb1, cb1, ccb1, pom, minus, factorial, factorials, fb, fsb, k1, pom1, ccd;
	int angle;
	float fix2 = 57;

	bb0 = b0[idx];
	bb1 = b1[idx];
	ssb1 = sin(bb1);
	sb0 = sin(bb0);
	cb0 = cos(bb0);
	cb1 = cos(bb1);

	__shared__ int mn[720], r[720], s[720];

	if (threadIdx.x == 0) {
		for (int i = 0; i < 720; i++) {
			mn[i] = 0;
			r[i] = 0;
			s[i] = 0;
		}
	}

	__syncthreads();

	if (idx < 100000) {
		for (int i = 0; i < 100000; i++) {
			k = b1[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) { 
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf(sb0 * sb1 + cb0 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);

			angle = (int)ac;
			atomicAdd(&mn[angle], 1);
		}

		for (int i = idx + 1; i < 100000; i++) {
			k = b0[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) {
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf(sb0 * sb1 + cb0 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);
			angle = (int)ac;
			atomicAdd(&r[angle], 2);

			k = b1[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) {
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf((ssb1 * sb1) + cb1 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);
			angle = (int)ac;
			atomicAdd(&s[angle], 2);
		}
	}

	__syncthreads();

	if (threadIdx.x == 0) {
		for (int i = 0; i < 720; i++) {  
			hist[i + (blockIdx.x * 720)] = mn[i];
			hist_r[i + (blockIdx.x * 720)] = r[i];
			hist_s[i + (blockIdx.x * 720)] = s[i];
		}
	}
}

int main(int argc, char *argv[]) {
	FILE *real_g;
	FILE *synthetic_g;
	int galaxies_r, galaxies_s;
	clock_t start, end;

	start = clock();
	real_g = fopen("data_100k_arcmin.txt", "r");
	synthetic_g = fopen("flat_100k_arcmin.txt", "r");
	fscanf(real_g, "%d", &galaxies_r);
	fscanf(synthetic_g, "%d", &galaxies_s);

	int N = 100000;
	int xx = 782;
	size_t arraybytes = N * sizeof(float);
	size_t arraybytes1 = xx * 720 * sizeof(int);
	size_t arraybytes11 = xx * 720 * sizeof(float);
	size_t l = 720 * sizeof(int);
	size_t l1 = 720  * sizeof(float); // Check this

	// Allocate input vectors h_A and h_B in host memory
	float* h_A = (float*)malloc(arraybytes);
	float* h_B = (float*)malloc(arraybytes);
	float* h_A1 = (float*)malloc(arraybytes);
	float* h_B1 = (float*)malloc(arraybytes);
	int* h_C = (int*)malloc(arraybytes1);
	int* h_D = (int*)malloc(arraybytes1);
	int* h_E = (int*)malloc(arraybytes1);

	int* result = (int*)malloc(l);
	int* result_r = (int*)malloc(l);
	int* result_s = (int*)malloc(l);
	float* final = (float*)malloc(l1);

	for(int i = 0; i < galaxies_r; i++) {
		fscanf(real_g, "%e %e", &h_A[i], &h_B[i]);
		fscanf(synthetic_g, "%e %e", &h_A1[i], &h_B1[i]);

		h_A[i] = h_A[i] * fix1;
		h_A1[i] = h_A1[i] * fix1;
		h_B[i] = h_B[i] * fix1;
		h_B1[i] = h_B1[i] * fix1;
	}

	fclose(real_g);
	fclose(synthetic_g);

	float* d_A; cudaMalloc(&d_A, arraybytes);
	float* d_B; cudaMalloc(&d_B, arraybytes);
	float* d_A1; cudaMalloc(&d_A1, arraybytes);
	float* d_B1; cudaMalloc(&d_B1, arraybytes);
	int* d_C; cudaMalloc(&d_C, arraybytes1);
	int* d_D; cudaMalloc(&d_D, arraybytes1);
	int* d_E; cudaMalloc(&d_E, arraybytes1);
	int* d_result; cudaMalloc(&d_result, l);
	int* d_result_r; cudaMalloc(&d_result_r, l);
	int* d_result_s; cudaMalloc(&d_result_s, l);

	// Copy arrays from host memory to device memory
	cudaMemcpy(d_A, h_A, arraybytes, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B, h_B, arraybytes, cudaMemcpyHostToDevice);
	cudaMemcpy(d_A1, h_A1, arraybytes, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B1, h_B1, arraybytes, cudaMemcpyHostToDevice);

	// Invoke kernel
	dim3 threadsPerBlock(128);
	dim3 threadsPerBlock1(736);
	dim3 blocksize2(1);
	dim3 blocksPerGrid(xx);

	double cpu_time_used;

	cudaMemset(d_C, 0, arraybytes1);
	cudaMemset(d_D, 0, arraybytes1);
	cudaMemset(d_E, 0, arraybytes1);

	angles<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_A1, d_B1, d_C, d_D, d_E);

	cudaMemcpy(h_C, d_C, arraybytes1, cudaMemcpyDeviceToHost);
	cudaMemcpy(h_D, d_D, arraybytes1, cudaMemcpyDeviceToHost);
	cudaMemcpy(h_E, d_E, arraybytes1, cudaMemcpyDeviceToHost);

	for (int i = 0; i < 720 * xx; i++) {
		result[i % 720] += h_C[i];
		result_r[i % 720] += h_D[i];
		result_s[i % 720] += h_E[i];
	}

	result_r[0] = result_r[0] + 100000;
	result_s[0] = result_s[0] + 100000;

	final[0] = (float) ((float)(result_r[0] - 2 * result[0] + result_s[0] + 200000) / (float)(100000 + result_s[0]));
	for(int i = 1; i < 720; i++) {
		final[i] = (float) ((float)(result_r[i] - 2 * result[i] + result_s[i]) / (float) result_s[i]);
	}

	end = clock();
	cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;

	double brk = 0;
	printf("%f\n", cpu_time_used);

	for(int i = 0; i < 720; i++) {
		printf( "%f ", final[i]);
	}

	cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
	cudaFree(h_A); cudaFree(h_B); cudaFree(h_C);
	cudaFree(d_D); cudaFree(h_D); cudaFree(d_E); cudaFree(h_E);
	cudaFree(d_A1); cudaFree(h_A1); cudaFree(d_B1); cudaFree(h_B1);
}

	.file	"tmpxft_002e6dd1_00000000-6_new.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2912:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2912:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB3057:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE3057:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.globl	_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_
	.type	_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_, @function
_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_:
.LFB2934:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z6anglesPVfS0_S0_S0_PViS2_S2_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L3:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2934:
	.size	_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_, .-_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_
	.globl	_Z6anglesPVfS0_S0_S0_PViS2_S2_
	.type	_Z6anglesPVfS0_S0_S0_PViS2_S2_, @function
_Z6anglesPVfS0_S0_S0_PViS2_S2_:
.LFB2935:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_
	.cfi_endproc
.LFE2935:
	.size	_Z6anglesPVfS0_S0_S0_PViS2_S2_, .-_Z6anglesPVfS0_S0_S0_PViS2_S2_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"data_100k_arcmin.txt"
.LC2:
	.string	"flat_100k_arcmin.txt"
.LC3:
	.string	"%d"
.LC4:
	.string	"%e %e"
.LC8:
	.string	"%f\n"
.LC9:
	.string	"%f "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2909:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	.LC0(%rip), %rbx
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	call	clock@PLT
	movq	%rbx, %rsi
	leaq	.LC1(%rip), %rdi
	movq	%rax, 80(%rsp)
	call	fopen@PLT
	movq	%rbx, %rsi
	leaq	.LC2(%rip), %rdi
	leaq	.LC3(%rip), %rbx
	movq	%rax, 8(%rsp)
	call	fopen@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	leaq	120(%rsp), %rdx
	movq	%rax, 16(%rsp)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	leaq	124(%rsp), %rdx
	call	__isoc23_fscanf@PLT
	movl	$400000, %edi
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	movl	$2252160, %edi
	movq	%rax, 48(%rsp)
	call	malloc@PLT
	movl	$2252160, %edi
	movq	%rax, 56(%rsp)
	call	malloc@PLT
	movl	$2252160, %edi
	movq	%rax, 64(%rsp)
	call	malloc@PLT
	movl	$2880, %edi
	movq	%rax, 72(%rsp)
	call	malloc@PLT
	movl	$2880, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$2880, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$2880, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	24(%rsp), %r10
	movq	32(%rsp), %r9
	xorl	%r11d, %r11d
	movq	40(%rsp), %r13
	movq	48(%rsp), %r15
	movq	%rax, %r14
.L10:
	cmpl	%r11d, 120(%rsp)
	jle	.L21
	movq	8(%rsp), %rdi
	movq	%r9, %rcx
	movq	%r10, %rdx
	xorl	%eax, %eax
	leaq	.LC4(%rip), %rsi
	movl	%r11d, 108(%rsp)
	movq	%r9, 96(%rsp)
	movq	%r10, 88(%rsp)
	call	__isoc23_fscanf@PLT
	movq	16(%rsp), %rdi
	movq	%r15, %rcx
	movq	%r13, %rdx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	addq	$4, %r13
	addq	$4, %r15
	call	__isoc23_fscanf@PLT
	movq	88(%rsp), %r10
	movq	96(%rsp), %r9
	movsd	.LC5(%rip), %xmm2
	movsd	.LC6(%rip), %xmm1
	cvtss2sd	(%r10), %xmm0
	movl	108(%rsp), %r11d
	addq	$4, %r10
	addq	$4, %r9
	mulsd	%xmm2, %xmm0
	incl	%r11d
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, -4(%r10)
	cvtss2sd	-4(%r13), %xmm0
	mulsd	%xmm2, %xmm0
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, -4(%r13)
	cvtss2sd	-4(%r9), %xmm0
	mulsd	%xmm2, %xmm0
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, -4(%r9)
	cvtss2sd	-4(%r15), %xmm0
	mulsd	%xmm2, %xmm0
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, -4(%r15)
	jmp	.L10
.L21:
	movq	8(%rsp), %rdi
	call	fclose@PLT
	movq	16(%rsp), %rdi
	call	fclose@PLT
	leaq	128(%rsp), %rdi
	movl	$400000, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	136(%rsp), %rdi
	movl	$400000, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	144(%rsp), %rdi
	movl	$400000, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	152(%rsp), %rdi
	movl	$400000, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	160(%rsp), %rdi
	movl	$2252160, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	168(%rsp), %rdi
	movl	$2252160, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	176(%rsp), %rdi
	movl	$2252160, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	184(%rsp), %rdi
	movl	$2880, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	192(%rsp), %rdi
	movl	$2880, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	200(%rsp), %rdi
	movl	$2880, %esi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	152(%rsp), %rdi
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %eax
	xorl	%esi, %esi
	movq	160(%rsp), %rdi
	salq	$7, %rax
	movl	$2252160, %edx
	movl	$1, 216(%rsp)
	movq	%rax, 208(%rsp)
	addq	$654, %rax
	movq	%rax, 220(%rsp)
	movl	$1, 228(%rsp)
	call	cudaMemset@PLT
	movq	168(%rsp), %rdi
	xorl	%esi, %esi
	movl	$2252160, %edx
	call	cudaMemset@PLT
	movq	176(%rsp), %rdi
	xorl	%esi, %esi
	movl	$2252160, %edx
	call	cudaMemset@PLT
	movl	216(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	208(%rsp), %rdx
	movq	220(%rsp), %rdi
	movl	228(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rax
	.cfi_def_cfa_offset 312
	pushq	184(%rsp)
	.cfi_def_cfa_offset 320
	movq	184(%rsp), %r9
	movq	176(%rsp), %r8
	movq	168(%rsp), %rcx
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z44__device_stub__Z6anglesPVfS0_S0_S0_PViS2_S2_PVfS0_S0_S0_PViS2_S2_
	popq	%rdx
	.cfi_def_cfa_offset 312
	popq	%rcx
	.cfi_def_cfa_offset 304
.L12:
	movq	56(%rsp), %rdi
	movl	$2, %ecx
	movl	$2252160, %edx
	movq	160(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$2, %ecx
	movq	168(%rsp), %rsi
	movl	$2252160, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movl	$2, %ecx
	movq	176(%rsp), %rsi
	movl	$2252160, %edx
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	movl	$720, %esi
.L13:
	movl	%ecx, %eax
	cltd
	idivl	%esi
	movq	56(%rsp), %rax
	movl	(%rax,%rcx,4), %eax
	movslq	%edx, %rdx
	salq	$2, %rdx
	addl	%eax, (%r12,%rdx)
	movq	64(%rsp), %rax
	movl	(%rax,%rcx,4), %eax
	addl	%eax, (%rbx,%rdx)
	movq	72(%rsp), %rax
	movl	(%rax,%rcx,4), %eax
	incq	%rcx
	addl	%eax, 0(%rbp,%rdx)
	cmpq	$563040, %rcx
	jne	.L13
	movl	(%rbx), %eax
	movl	(%r12), %ecx
	movl	0(%rbp), %edx
	addl	$100000, %eax
	addl	%ecx, %ecx
	leal	100000(%rdx), %esi
	movl	%eax, (%rbx)
	subl	%ecx, %eax
	addl	$200000, %edx
	cvtsi2ssl	%edx, %xmm1
	leal	200000(%rsi,%rax), %eax
	movl	%esi, 0(%rbp)
	cvtsi2ssl	%eax, %xmm0
	movl	$4, %eax
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r14)
.L14:
	movl	0(%rbp,%rax), %esi
	movl	(%r12,%rax), %ecx
	movl	(%rbx,%rax), %edx
	addl	%ecx, %ecx
	cvtsi2ssl	%esi, %xmm1
	addl	%esi, %edx
	subl	%ecx, %edx
	cvtsi2ssl	%edx, %xmm0
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%rax)
	addq	$4, %rax
	cmpq	$2880, %rax
	jne	.L14
	call	clock@PLT
	movq	80(%rsp), %rbx
	leaq	.LC8(%rip), %rsi
	xorl	%ebp, %ebp
	movl	$2, %edi
	subq	%rbx, %rax
	leaq	.LC9(%rip), %rbx
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
.L15:
	cvtss2sd	(%r14,%rbp,4), %xmm0
	movq	%rbx, %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%rbp
	cmpq	$720, %rbp
	jne	.L15
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2909:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z6anglesPVfS0_S0_S0_PViS2_S2_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2937:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6anglesPVfS0_S0_S0_PViS2_S2_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2937:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	1374389535
	.long	1074339512
	.align 8
.LC6:
	.long	0
	.long	1086658560
	.align 8
.LC7:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <vector>
#include "hip/hip_vector_types.h"
#include <unistd.h>
#include <time.h>
#include "hip/device_functions.h"
#include "hip/hip_runtime.h"


#define fix1 3.14 / (60 * 180)

using namespace std;

__global__ void angles(volatile float *a0, volatile float *b0, volatile float *a1, volatile float*b1, volatile int *hist, volatile int* hist_r, volatile int* hist_s)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	float ac, bb0, sb1, sb0, cb0, k, bb1, ssb1, cb1, ccb1, pom, minus, factorial, factorials, fb, fsb, k1, pom1, ccd;
	int angle;
	float fix2 = 57;

	bb0 = b0[idx];
	bb1 = b1[idx];
	ssb1 = sin(bb1);
	sb0 = sin(bb0);
	cb0 = cos(bb0);
	cb1 = cos(bb1);

	__shared__ int mn[720], r[720], s[720];

	if (threadIdx.x == 0) {
		for (int i = 0; i < 720; i++) {
			mn[i] = 0;
			r[i] = 0;
			s[i] = 0;
		}
	}

	__syncthreads();

	if (idx < 100000) {
		for (int i = 0; i < 100000; i++) {
			k = b1[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) { 
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf(sb0 * sb1 + cb0 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);

			angle = (int)ac;
			atomicAdd(&mn[angle], 1);
		}

		for (int i = idx + 1; i < 100000; i++) {
			k = b0[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) {
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf(sb0 * sb1 + cb0 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);
			angle = (int)ac;
			atomicAdd(&r[angle], 2);

			k = b1[i];
			k1 = a0[i] - a0[idx];
			pom = k * k;
			pom1 = k1 * k1;
			minus = -1;
			sb1 = k;
			ccb1 = 1;
			ccd = 1;
			fb = 3;
			fsb = 4;
			factorial = 2;
			factorials = 6;

			for (int i = 0; i < 5; i++) {
				ccb1 = ccb1 + minus * pom / factorial;
				sb1 = sb1 + minus * k * pom / factorials;
				ccd = ccd + minus * pom1 / factorial;
				factorial = factorial * fb * (fb + 1);
				fb += 2;
				factorials = factorials * fsb * (fsb + 1);
				fsb += 2;
				minus = minus * (-1);
				pom = pom * k * k;
			}

			ac = acosf((ssb1 * sb1) + cb1 * ccb1 * ccd);
			ac = (ac * fix2 / 0.25);
			angle = (int)ac;
			atomicAdd(&s[angle], 2);
		}
	}

	__syncthreads();

	if (threadIdx.x == 0) {
		for (int i = 0; i < 720; i++) {  
			hist[i + (blockIdx.x * 720)] = mn[i];
			hist_r[i + (blockIdx.x * 720)] = r[i];
			hist_s[i + (blockIdx.x * 720)] = s[i];
		}
	}
}

int main(int argc, char *argv[]) {
	FILE *real_g;
	FILE *synthetic_g;
	int galaxies_r, galaxies_s;
	clock_t start, end;

	start = clock();
	real_g = fopen("data_100k_arcmin.txt", "r");
	synthetic_g = fopen("flat_100k_arcmin.txt", "r");
	fscanf(real_g, "%d", &galaxies_r);
	fscanf(synthetic_g, "%d", &galaxies_s);

	int N = 100000;
	int xx = 782;
	size_t arraybytes = N * sizeof(float);
	size_t arraybytes1 = xx * 720 * sizeof(int);
	size_t arraybytes11 = xx * 720 * sizeof(float);
	size_t l = 720 * sizeof(int);
	size_t l1 = 720  * sizeof(float); // Check this

	// Allocate input vectors h_A and h_B in host memory
	float* h_A = (float*)malloc(arraybytes);
	float* h_B = (float*)malloc(arraybytes);
	float* h_A1 = (float*)malloc(arraybytes);
	float* h_B1 = (float*)malloc(arraybytes);
	int* h_C = (int*)malloc(arraybytes1);
	int* h_D = (int*)malloc(arraybytes1);
	int* h_E = (int*)malloc(arraybytes1);

	int* result = (int*)malloc(l);
	int* result_r = (int*)malloc(l);
	int* result_s = (int*)malloc(l);
	float* final = (float*)malloc(l1);

	for(int i = 0; i < galaxies_r; i++) {
		fscanf(real_g, "%e %e", &h_A[i], &h_B[i]);
		fscanf(synthetic_g, "%e %e", &h_A1[i], &h_B1[i]);

		h_A[i] = h_A[i] * fix1;
		h_A1[i] = h_A1[i] * fix1;
		h_B[i] = h_B[i] * fix1;
		h_B1[i] = h_B1[i] * fix1;
	}

	fclose(real_g);
	fclose(synthetic_g);

	float* d_A; hipMalloc(&d_A, arraybytes);
	float* d_B; hipMalloc(&d_B, arraybytes);
	float* d_A1; hipMalloc(&d_A1, arraybytes);
	float* d_B1; hipMalloc(&d_B1, arraybytes);
	int* d_C; hipMalloc(&d_C, arraybytes1);
	int* d_D; hipMalloc(&d_D, arraybytes1);
	int* d_E; hipMalloc(&d_E, arraybytes1);
	int* d_result; hipMalloc(&d_result, l);
	int* d_result_r; hipMalloc(&d_result_r, l);
	int* d_result_s; hipMalloc(&d_result_s, l);

	// Copy arrays from host memory to device memory
	hipMemcpy(d_A, h_A, arraybytes, hipMemcpyHostToDevice);
	hipMemcpy(d_B, h_B, arraybytes, hipMemcpyHostToDevice);
	hipMemcpy(d_A1, h_A1, arraybytes, hipMemcpyHostToDevice);
	hipMemcpy(d_B1, h_B1, arraybytes, hipMemcpyHostToDevice);

	// Invoke kernel
	dim3 threadsPerBlock(128);
	dim3 threadsPerBlock1(736);
	dim3 blocksize2(1);
	dim3 blocksPerGrid(xx);

	double cpu_time_used;

	hipMemset(d_C, 0, arraybytes1);
	hipMemset(d_D, 0, arraybytes1);
	hipMemset(d_E, 0, arraybytes1);

	angles<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_A1, d_B1, d_C, d_D, d_E);

	hipMemcpy(h_C, d_C, arraybytes1, hipMemcpyDeviceToHost);
	hipMemcpy(h_D, d_D, arraybytes1, hipMemcpyDeviceToHost);
	hipMemcpy(h_E, d_E, arraybytes1, hipMemcpyDeviceToHost);

	for (int i = 0; i < 720 * xx; i++) {
		result[i % 720] += h_C[i];
		result_r[i % 720] += h_D[i];
		result_s[i % 720] += h_E[i];
	}

	result_r[0] = result_r[0] + 100000;
	result_s[0] = result_s[0] + 100000;

	final[0] = (float) ((float)(result_r[0] - 2 * result[0] + result_s[0] + 200000) / (float)(100000 + result_s[0]));
	for(int i = 1; i < 720; i++) {
		final[i] = (float) ((float)(result_r[i] - 2 * result[i] + result_s[i]) / (float) result_s[i]);
	}

	end = clock();
	cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;

	double brk = 0;
	printf("%f\n", cpu_time_used);

	for(int i = 0; i < 720; i++) {
		printf( "%f ", final[i]);
	}

	hipFree(d_A); hipFree(d_B); hipFree(d_C);
	hipFree(h_A); hipFree(h_B); hipFree(h_C);
	hipFree(d_D); hipFree(h_D); hipFree(d_E); hipFree(h_E);
	hipFree(d_A1); hipFree(h_A1); hipFree(d_B1); hipFree(h_B1);
}

	.text
	.file	"new.hip"
	.globl	_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_ # -- Begin function _Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
	.type	_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_,@function
_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_: # @_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6anglesPVfS0_S0_S0_PViS2_S2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_, .Lfunc_end0-_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x40091eb851eb851f              # double 3.1400000000000001
.LCPI1_1:
	.quad	0x40c5180000000000              # double 10800
.LCPI1_2:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	callq	clock
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.2, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	60(%rsp), %r15
	movl	$.L.str.3, %esi
	movq	%rbx, 104(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	188(%rsp), %rdx
	movl	$.L.str.3, %esi
	movq	%r14, 96(%rsp)                  # 8-byte Spill
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	$2252160, %edi                  # imm = 0x225D80
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$2252160, %edi                  # imm = 0x225D80
	callq	malloc
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movl	$2252160, %edi                  # imm = 0x225D80
	callq	malloc
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movl	$2880, %edi                     # imm = 0xB40
	callq	malloc
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movl	$2880, %edi                     # imm = 0xB40
	callq	malloc
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movl	$2880, %edi                     # imm = 0xB40
	callq	malloc
	movq	%rax, %rbp
	movl	$2880, %edi                     # imm = 0xB40
	callq	malloc
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	cmpl	$0, (%r15)
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movq	64(%rsp), %r13                  # 8-byte Reload
	movq	40(%rsp), %rbx                  # 8-byte Reload
	movq	48(%rsp), %r14                  # 8-byte Reload
	movq	72(%rsp), %r15                  # 8-byte Reload
	xorl	%r12d, %r12d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	104(%rsp), %rdi                 # 8-byte Reload
	movq	%r13, %rdx
	movq	%rbx, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	$.L.str.4, %esi
	movq	96(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movq	%r15, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13), %xmm0
	movsd	.LCPI1_0(%rip), %xmm2           # xmm2 = mem[0],zero
	mulsd	%xmm2, %xmm0
	movsd	.LCPI1_1(%rip), %xmm3           # xmm3 = mem[0],zero
	divsd	%xmm3, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r13)
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	mulsd	%xmm2, %xmm0
	divsd	%xmm3, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%rbx), %xmm1
	mulsd	%xmm2, %xmm1
	divsd	%xmm3, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm0, (%r14)
	movss	%xmm1, (%rbx)
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	mulsd	%xmm2, %xmm0
	divsd	%xmm3, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15)
	incq	%r12
	movslq	60(%rsp), %rax
	addq	$4, %r15
	addq	$4, %r14
	addq	$4, %rbx
	addq	$4, %r13
	cmpq	%rax, %r12
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	104(%rsp), %rdi                 # 8-byte Reload
	callq	fclose
	movq	96(%rsp), %rdi                  # 8-byte Reload
	callq	fclose
	leaq	136(%rsp), %r15
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	128(%rsp), %r14
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	120(%rsp), %rbx
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	112(%rsp), %r13
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$2252160, %esi                  # imm = 0x225D80
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$2252160, %esi                  # imm = 0x225D80
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$2252160, %esi                  # imm = 0x225D80
	callq	hipMalloc
	leaq	208(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	callq	hipMalloc
	leaq	200(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	callq	hipMalloc
	leaq	192(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	64(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	72(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movl	$2252160, %edx                  # imm = 0x225D80
	xorl	%esi, %esi
	callq	hipMemset
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$2252160, %edx                  # imm = 0x225D80
	xorl	%esi, %esi
	callq	hipMemset
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$2252160, %edx                  # imm = 0x225D80
	xorl	%esi, %esi
	callq	hipMemset
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	654(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	136(%rsp), %rdi
	movq	128(%rsp), %rsi
	movq	120(%rsp), %rdx
	movq	112(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	24(%rsp), %r9
	movq	16(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
.LBB1_5:
	movq	32(%rsp), %rsi
	movl	$2252160, %edx                  # imm = 0x225D80
	movq	80(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movl	$2252160, %edx                  # imm = 0x225D80
	movq	88(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$2252160, %edx                  # imm = 0x225D80
	movq	168(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%esi, %esi
	movabsq	$3279421168659475843, %rdi      # imm = 0x2D82D82D82D82D83
	xorl	%ecx, %ecx
	movq	152(%rsp), %r10                 # 8-byte Reload
	movq	144(%rsp), %r11                 # 8-byte Reload
.LBB1_6:                                # =>This Inner Loop Header: Depth=1
	movq	%rcx, %rax
	mulq	%rdi
	shrq	$7, %rdx
	imulq	$-2880, %rdx, %rax              # imm = 0xF4C0
	leaq	(%r10,%rax), %rdx
	leaq	(%r11,%rax), %r8
	addq	%rbp, %rax
	movl	(%r15,%rsi), %r9d
	addl	%r9d, (%rsi,%rdx)
	movl	(%rbx,%rsi), %edx
	addl	%edx, (%rsi,%r8)
	movl	(%r13,%rsi), %edx
	addl	%edx, (%rsi,%rax)
	incq	%rcx
	addq	$4, %rsi
	cmpq	$2252160, %rsi                  # imm = 0x225D80
	jne	.LBB1_6
# %bb.7:
	movl	(%rbp), %eax
	movl	(%r10), %ecx
	movl	(%r11), %edx
	addl	%eax, %edx
	addl	%ecx, %ecx
	subl	%ecx, %edx
	addl	$400000, %edx                   # imm = 0x61A80
	cvtsi2ss	%edx, %xmm0
	addl	$200000, %eax                   # imm = 0x30D40
	cvtsi2ss	%eax, %xmm1
	divss	%xmm1, %xmm0
	movq	160(%rsp), %r15                 # 8-byte Reload
	movss	%xmm0, (%r15)
	movl	$1, %eax
.LBB1_8:                                # =>This Inner Loop Header: Depth=1
	movl	(%r11,%rax,4), %ecx
	movl	(%r10,%rax,4), %edx
	addl	%edx, %edx
	subl	%edx, %ecx
	movl	(%rbp,%rax,4), %edx
	addl	%edx, %ecx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%edx, %xmm1
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r15,%rax,4)
	incq	%rax
	cmpq	$720, %rax                      # imm = 0x2D0
	jne	.LBB1_8
# %bb.9:
	callq	clock
	subq	176(%rsp), %rax                 # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI1_2(%rip), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	xorl	%ebx, %ebx
.LBB1_10:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%rbx,4), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$720, %rbx                      # imm = 0x2D0
	jne	.LBB1_10
# %bb.11:
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	%r12, %rdi
	callq	hipFree
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%r13, %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6anglesPVfS0_S0_S0_PViS2_S2_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6anglesPVfS0_S0_S0_PViS2_S2_,@object # @_Z6anglesPVfS0_S0_S0_PViS2_S2_
	.section	.rodata,"a",@progbits
	.globl	_Z6anglesPVfS0_S0_S0_PViS2_S2_
	.p2align	3, 0x0
_Z6anglesPVfS0_S0_S0_PViS2_S2_:
	.quad	_Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
	.size	_Z6anglesPVfS0_S0_S0_PViS2_S2_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"data_100k_arcmin.txt"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"flat_100k_arcmin.txt"
	.size	.L.str.2, 21

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%e %e"
	.size	.L.str.4, 6

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%f\n"
	.size	.L.str.5, 4

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%f "
	.size	.L.str.6, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6anglesPVfS0_S0_S0_PViS2_S2_"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__anglesPVfS0_S0_S0_PViS2_S2_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6anglesPVfS0_S0_S0_PViS2_S2_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6anglesPVfS0_S0_S0_PViS2_S2_ ; -- Begin function _Z6anglesPVfS0_S0_S0_PViS2_S2_
	.globl	_Z6anglesPVfS0_S0_S0_PViS2_S2_
	.p2align	8
	.type	_Z6anglesPVfS0_S0_S0_PViS2_S2_,@function
_Z6anglesPVfS0_S0_S0_PViS2_S2_:         ; @_Z6anglesPVfS0_S0_S0_PViS2_S2_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x18
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s18, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s19, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v7, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 23, v7
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v5, v7, s0, 0x800000
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, v9
	v_add_nc_u32_e32 v9, 0xffffff88, v10
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v5, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v9
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v18, v9
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v5, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v9
	v_mov_b32_e32 v11, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v8, v14, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v5, v[11:12]
	v_add_nc_u32_e32 v9, v19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v9
	v_mov_b32_e32 v11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v5, v[11:12]
	v_mov_b32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v5, v[11:12]
	v_mov_b32_e32 v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v5, v[11:12]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v11, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v12, v18, v16 :: v_dual_add_nc_u32 v5, v5, v9
	v_dual_cndmask_b32 v17, v19, v17 :: v_dual_cndmask_b32 v16, v16, v14
	v_cndmask_b32_e32 v9, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v15, 32, v5
	v_cndmask_b32_e64 v13, v12, v11, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v17, v12, s0
	v_cndmask_b32_e64 v11, v11, v16, s0
	v_cndmask_b32_e64 v16, v16, v9, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v8, v9, v8, s0
	v_cndmask_b32_e64 v12, v12, v13, s1
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v11, v11, v16, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v16, v8, s1
	v_alignbit_b32 v17, v12, v13, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v13, v11, v15
	v_alignbit_b32 v15, v11, v8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v17, v12, vcc_lo
	v_cndmask_b32_e32 v9, v14, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v15, v11, vcc_lo
	v_bfe_u32 v12, v5, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v5, v9, 30
	v_alignbit_b32 v9, v9, v11, 30
	v_alignbit_b32 v8, v11, v8, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 0, v12
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v14
	v_xor_b32_e32 v8, v8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v15, v13
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	v_alignbit_b32 v13, v13, v9, v11
	v_alignbit_b32 v8, v9, v8, v11
	v_lshrrev_b32_e32 v11, 29, v5
	v_lshrrev_b32_e32 v5, 30, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v13, v8, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v14, v9
	v_or_b32_e32 v16, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v8, v9, v8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v9, v13, v16
	v_add_lshl_u32 v13, v14, v15, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v9
	v_sub_nc_u32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3fc90fda, v9, -v14
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v9, v9, 0x33a22168, v13
	v_or_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	v_add_f32_e32 v8, v14, v9
	v_add_nc_u32_e32 v9, v12, v5
.LBB0_2:                                ; %Flow384
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v15, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v15
	v_fma_f32 v8, 0xbfc90fda, v5, |v6|
	v_cvt_i32_f32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v5, 0xb3a22168, v8
	v_fmamk_f32 v8, v5, 0xa7c234c4, v8
; %bb.4:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v5, 0x7fffffff, v4
	v_cmp_ngt_f32_e64 s3, 0x48000000, |v4|
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v13, 23, v5
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v14, v5, s0, 0x800000
	v_mad_u64_u32 v[11:12], null, 0xfe5163ab, v14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, v12
	v_add_nc_u32_e32 v12, 0xffffff88, v13
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v14, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v12
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v16, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v23, v12
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v14, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v12
	v_mov_b32_e32 v16, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v11, v19, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v14, v[16:17]
	v_add_nc_u32_e32 v12, v24, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v12
	v_mov_b32_e32 v16, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v14, v[16:17]
	v_mov_b32_e32 v16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v14, v[16:17]
	v_mov_b32_e32 v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v14, v[16:17]
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v16, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v17, v23, v21 :: v_dual_add_nc_u32 v12, v14, v12
	v_dual_cndmask_b32 v22, v24, v22 :: v_dual_cndmask_b32 v21, v21, v19
	v_cndmask_b32_e32 v14, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v20, 32, v12
	v_cndmask_b32_e64 v18, v17, v16, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v22, v17, s0
	v_cndmask_b32_e64 v16, v16, v21, s0
	v_cndmask_b32_e64 v21, v21, v14, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e64 v11, v14, v11, s0
	v_cndmask_b32_e64 v17, v17, v18, s1
	v_cndmask_b32_e64 v18, v18, v16, s1
	v_cndmask_b32_e64 v16, v16, v21, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v21, v11, s1
	v_alignbit_b32 v22, v17, v18, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v18, v16, v20
	v_alignbit_b32 v20, v16, v11, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v22, v17, vcc_lo
	v_cndmask_b32_e32 v14, v19, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v20, v16, vcc_lo
	v_bfe_u32 v17, v12, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v12, v14, 30
	v_alignbit_b32 v14, v14, v16, 30
	v_alignbit_b32 v11, v16, v11, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, 0, v17
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v14, v19
	v_xor_b32_e32 v11, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	v_alignbit_b32 v18, v18, v14, v16
	v_alignbit_b32 v11, v14, v11, v16
	v_lshrrev_b32_e32 v16, 29, v12
	v_lshrrev_b32_e32 v12, 30, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v18, v11, 9
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v12, v17, v12
	v_clz_i32_u32_e32 v19, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v14, v11, v23
	v_or_b32_e32 v14, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v11, 9, v11
	v_mul_f32_e32 v19, 0x3fc90fda, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v18
	v_fma_f32 v18, 0x3fc90fda, v14, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 0x33000000, v11
	v_fmamk_f32 v14, v14, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v11, v11, v16
	v_fmac_f32_e32 v14, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v11, v19, v14
.LBB0_6:                                ; %Flow383
	s_or_saveexec_b32 s0, s12
	v_mul_f32_e64 v14, 0x3f22f983, |v4|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.7:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v12, v14
	v_fma_f32 v11, 0xbfc90fda, v12, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v11, v12, 0xb3a22168, v11
	v_fmamk_f32 v11, v12, 0xa7c234c4, v11
	v_cvt_i32_f32_e32 v12, v12
; %bb.8:                                ; %_ZL3sinf.exit218
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v18, 0
	v_and_or_b32 v25, v5, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfe5163ab, v25, 0
	v_mad_u64_u32 v[19:20], null, 0x3c439041, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v20
	v_mad_u64_u32 v[20:21], null, 0xdb629599, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v21
	v_mad_u64_u32 v[21:22], null, 0xf534ddc0, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v17, v22 :: v_dual_add_nc_u32 v22, 0xffffff88, v13
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v17, v14 :: v_dual_cndmask_b32 v16, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v23, v22
	v_cmp_lt_u32_e64 s0, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v14, v24, v14
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v14
	v_mov_b32_e32 v17, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[17:18]
	v_cndmask_b32_e32 v18, v22, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v23, v23, v13 :: v_dual_add_nc_u32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v22, v24, v22 :: v_dual_cndmask_b32 v17, v21, v19
	v_cndmask_b32_e64 v19, v23, v18, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v22, v23, s0
	v_sub_nc_u32_e32 v22, 32, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v17, v16, s0
	v_cndmask_b32_e64 v21, v21, v19, s1
	v_cndmask_b32_e32 v13, v13, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v13, s0
	v_cndmask_b32_e64 v19, v19, v18, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v23, v21, v19, v22
	v_cndmask_b32_e32 v14, v23, v21, vcc_lo
	v_cndmask_b32_e64 v13, v13, v17, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v13, s1
	v_cndmask_b32_e64 v13, v13, v16, s1
	v_alignbit_b32 v20, v19, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v18, v13, v22
	v_cndmask_b32_e32 v17, v20, v19, vcc_lo
	v_bfe_u32 v19, v14, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v21, v18, vcc_lo
	v_alignbit_b32 v16, v14, v17, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v19
	v_xor_b32_e32 v16, v16, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v16
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v17, v17, v18, 30
	v_alignbit_b32 v13, v18, v13, 30
	v_sub_nc_u32_e32 v18, 31, v21
	v_xor_b32_e32 v17, v17, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v13, v13, v20
	v_alignbit_b32 v16, v16, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v13, v17, v13, v18
	v_lshrrev_b32_e32 v18, 29, v14
	v_alignbit_b32 v17, v16, v13, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v18, 31, v18
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v22, 0.5, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v23
	v_sub_nc_u32_e32 v24, 31, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v16, v16, v22
	v_alignbit_b32 v13, v17, v13, v24
	v_add_lshl_u32 v17, v20, v21, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, v13, v17
	v_fma_f32 v17, 0x3fc90fda, v16, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, 0x33000000, v13
	v_fmamk_f32 v16, v16, 0x33a22168, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v13, v13, v18
	v_fmac_f32_e32 v16, 0x3fc90fda, v13
	v_lshrrev_b32_e32 v13, 30, v14
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v16, v20, v16 :: v_dual_add_nc_u32 v17, v19, v13
.LBB0_10:                               ; %Flow382
	s_and_not1_saveexec_b32 s0, s3
; %bb.11:
	v_rndne_f32_e32 v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0xbfc90fda, v13, |v4|
	v_cvt_i32_f32_e32 v17, v13
	v_fmamk_f32 v14, v13, 0xb3a22168, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v16, v13, 0xa7c234c4, v14
; %bb.12:                               ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v15, 0
	v_and_or_b32 v25, v7, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0xfe5163ab, v25, 0
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v19
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[14:15]
	v_add_nc_u32_e32 v10, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v10
	v_mov_b32_e32 v14, v20
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[14:15]
	v_cndmask_b32_e32 v13, v19, v13, vcc_lo
	v_add_nc_u32_e32 v10, v23, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v21
	v_cmp_lt_u32_e64 s0, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[14:15]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v24, v10
	v_mov_b32_e32 v14, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v10
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v15, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_add_nc_u32 v10, v14, v10
	v_dual_cndmask_b32 v22, v24, v22 :: v_dual_cndmask_b32 v21, v21, v19
	v_cndmask_b32_e32 v14, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v18, v23, v15, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v22, v23, s0
	v_cndmask_b32_e64 v15, v15, v21, s0
	v_sub_nc_u32_e32 v22, 32, v10
	v_cndmask_b32_e64 v21, v21, v14, s0
	v_cndmask_b32_e64 v13, v14, v13, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v15, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v21, s1
	v_cndmask_b32_e64 v13, v21, v13, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v15, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v15, v13, v22
	v_cndmask_b32_e32 v10, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v19, v18 :: v_dual_cndmask_b32 v15, v21, v15
	v_bfe_u32 v18, v10, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v10, v14, 30
	v_alignbit_b32 v14, v14, v15, 30
	v_alignbit_b32 v13, v15, v13, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v14, v20
	v_xor_b32_e32 v13, v13, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v14, v15
	v_alignbit_b32 v13, v14, v13, v15
	v_lshrrev_b32_e32 v15, 29, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v14, v19, v13, 9
	v_lshlrev_b32_e32 v15, 31, v15
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v14
	v_or_b32_e32 v22, 0.5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v13, v14, v13, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v14, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v14
	v_sub_nc_u32_e32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v14, -v20
	v_add_nc_u32_e32 v13, 0x33000000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v14, v14, 0x33a22168, v19
	v_or_b32_e32 v13, v13, v15
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0x3fc90fda, v13
	v_add_f32_e32 v13, v20, v14
	v_lshrrev_b32_e32 v10, 30, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v18, v10
.LBB0_14:                               ; %Flow380
	s_and_not1_saveexec_b32 s0, s2
; %bb.15:
	v_rndne_f32_e32 v10, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0xbfc90fda, v10, |v6|
	v_cvt_i32_f32_e32 v14, v10
	v_fmamk_f32 v13, v10, 0xb3a22168, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v13, v10, 0xa7c234c4, v13
; %bb.16:                               ; %_ZL3cosf.exit229
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e64 s0, 0, v0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_19
; %bb.17:                               ; %.preheader240.preheader
	v_mov_b32_e32 v0, 0
.LBB0_18:                               ; %.preheader240
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v10, s2
	s_add_i32 s2, s2, 4
	ds_store_b32 v10, v0
	ds_store_b32 v10, v0 offset:5760
	ds_store_b32 v10, v0 offset:2880
	s_cmpk_lg_i32 s2, 0xb40
	s_cbranch_scc1 .LBB0_18
.LBB0_19:                               ; %Flow379
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e32 0x186a0, v1
	s_cbranch_execz .LBB0_31
; %bb.20:                               ; %.preheader239
	v_dual_mul_f32 v0, v16, v16 :: v_dual_and_b32 v19, 1, v17
	s_mov_b32 s1, 0xb94c1982
	s_mov_b32 s2, 0x37d75334
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v10, v11, v11 :: v_dual_fmaak_f32 v15, s1, v0, 0x3c0881c4
	v_dual_fmaak_f32 v18, s2, v0, 0xbab64f3b :: v_dual_lshlrev_b32 v17, 30, v17
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_fmaak_f32 v21, s2, v10, 0xbab64f3b
	v_fmaak_f32 v20, s1, v10, 0x3c0881c4
	v_fmaak_f32 v15, v0, v15, 0xbe2aaa9d
	v_fmaak_f32 v18, v0, v18, 0x3d2aabf7
	v_xor_b32_e32 v5, v5, v4
	v_fmaak_f32 v21, v10, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v20, v10, v20, 0xbe2aaa9d :: v_dual_mul_f32 v15, v0, v15
	v_and_b32_e32 v22, 1, v12
	v_dual_fmaak_f32 v18, v0, v18, 0xbf000004 :: v_dual_fmaak_f32 v21, v10, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v20, v10, v20
	v_fmac_f32_e32 v16, v16, v15
	v_lshlrev_b32_e32 v12, 30, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v0, v0, v18, 1.0
	v_fma_f32 v10, v10, v21, 1.0
	v_and_b32_e32 v15, 0x80000000, v17
	v_fmac_f32_e32 v11, v11, v20
	s_mov_b32 s13, 0
	v_cndmask_b32_e64 v0, -v16, v0, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v22
	s_mov_b32 s14, 0x3d1c21a7
	s_mov_b32 s12, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v15, v0
	v_dual_cndmask_b32 v10, v10, v11 :: v_dual_and_b32 v11, 0x80000000, v12
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	v_xor3_b32 v5, v5, v11, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_cndmask_b32_e32 v10, 0x7fc00000, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
	v_mov_b32_e32 v2, 1
.LBB0_21:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_22 Depth 2
	s_lshl_b64 s[20:21], s[12:13], 2
	v_mov_b32_e32 v18, 1.0
	s_add_u32 s22, s4, s20
	s_addc_u32 s23, s5, s21
	s_add_u32 s20, s16, s20
	s_addc_u32 s21, s17, s21
	v_dual_mov_b32 v11, s22 :: v_dual_mov_b32 v12, s23
	v_dual_mov_b32 v15, s20 :: v_dual_mov_b32 v16, s21
	flat_load_b32 v3, v[11:12] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[15:16] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v12, 0x40400000 :: v_dual_mov_b32 v11, 4.0
	v_mov_b32_e32 v16, 0x40c00000
	s_mov_b32 s20, -1.0
	s_mov_b32 s21, 5
	s_waitcnt lgkmcnt(2)
	v_mov_b32_e32 v21, v3
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v19, v15, v17
	v_mov_b32_e32 v17, 2.0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v15, 1.0 :: v_dual_mul_f32 v20, v19, v19
	v_mov_b32_e32 v19, v3
.LBB0_22:                               ;   Parent Loop BB0_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v23, s20, v20 :: v_dual_mul_f32 v26, v16, v11
	v_dual_mul_f32 v21, v3, v21 :: v_dual_mul_f32 v22, s20, v3
	v_add_f32_e32 v25, 1.0, v12
	v_div_scale_f32 v29, null, v17, v17, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, s20, v21
	v_div_scale_f32 v30, s1, v23, v17, v23
	v_rcp_f32_e32 v33, v29
	v_dual_mul_f32 v24, v17, v12 :: v_dual_add_f32 v27, 1.0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v31, null, v17, v17, v28
	v_div_scale_f32 v36, vcc_lo, v28, v17, v28
	v_dual_add_f32 v12, 2.0, v12 :: v_dual_add_f32 v11, 2.0, v11
	v_rcp_f32_e32 v34, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v38, -v29, v33, 1.0
	v_dual_mul_f32 v22, v21, v22 :: v_dual_mul_f32 v21, v3, v21
	s_add_i32 s21, s21, -1
	s_xor_b32 s20, s20, 0x80000000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, v38, v33
	v_div_scale_f32 v32, null, v16, v16, v22
	v_div_scale_f32 v37, s2, v22, v16, v22
	v_fma_f32 v39, -v31, v34, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v35, v32
	s_cmp_eq_u32 s21, 0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v32, v35, 1.0
	v_dual_fmac_f32 v34, v39, v34 :: v_dual_fmac_f32 v35, v40, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v38, v30, v33 :: v_dual_mul_f32 v39, v36, v34
	v_fma_f32 v41, -v29, v38, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v42, -v31, v39, v36
	v_mul_f32_e32 v40, v37, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v38, v41, v33 :: v_dual_fmac_f32 v39, v42, v34
	v_fma_f32 v43, -v32, v40, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v29, v38, v30
	v_fma_f32 v30, -v31, v39, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v40, v43, v35
	v_div_fmas_f32 v30, v30, v34, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v32, v40, v37
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v28, v30, v17, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v31, v31, v35, v40
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v22, v31, v16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, v26, v27 :: v_dual_add_f32 v19, v19, v22
	v_div_fmas_f32 v29, v29, v33, v38
	v_div_fixup_f32 v23, v29, v17, v23
	v_dual_mul_f32 v17, v24, v25 :: v_dual_add_f32 v18, v18, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v15, v23, v15
	s_cbranch_scc0 .LBB0_22
; %bb.23:                               ;   in Loop: Header=BB0_21 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_f32_e32 v3, v0, v18
	s_add_i32 s12, s12, 1
	s_cmp_eq_u32 s12, 0x186a0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v3, v15
	v_fmac_f32_e32 v3, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v11, |v3|, -0.5, 0.5
	v_mul_f32_e32 v12, v3, v3
	v_cmp_gt_f32_e64 vcc_lo, |v3|, 0.5
	v_cndmask_b32_e32 v11, v12, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, s14, v11, 0x3c5fc5da
	v_sqrt_f32_e32 v15, v11
	v_fmaak_f32 v12, v11, v12, 0x3d034c3c
	v_cmp_gt_f32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, v11, v12, 0x3d3641b1
	v_fmaak_f32 v12, v11, v12, 0x3d999bc8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, v11, v12, 0x3e2aaaac
	v_mul_f32_e32 v11, v11, v12
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v15, v11
	v_fmac_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v15, v15
	v_sub_f32_e32 v3, 0x3fc90fdb, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, 0x40490fdb, v12
	v_cndmask_b32_e64 v11, v12, v15, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_mul_f32_e32 v3, 0x42640000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 4.0, v3
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_add_u32 v3, v2 offset:5760
	s_cbranch_scc0 .LBB0_21
; %bb.24:                               ; %.preheader237
	v_cmp_ne_u32_e32 vcc_lo, 0x1869f, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_31
; %bb.25:                               ; %.lr.ph.preheader
	v_dual_mul_f32 v2, v13, v13 :: v_dual_mul_f32 v3, v8, v8
	s_mov_b32 s1, 0xb94c1982
	s_mov_b32 s2, 0x37d75334
	v_xor_b32_e32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v11, s1, v2, 0x3c0881c4 :: v_dual_fmaak_f32 v16, s1, v3, 0x3c0881c4
	v_dual_fmaak_f32 v12, s2, v2, 0xbab64f3b :: v_dual_fmaak_f32 v17, s2, v3, 0xbab64f3b
	v_and_b32_e32 v15, 1, v14
	v_dual_fmaak_f32 v11, v2, v11, 0xbe2aaa9d :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v16, v3, v16, 0xbe2aaa9d
	v_fmaak_f32 v12, v2, v12, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_dual_mul_f32 v11, v2, v11 :: v_dual_and_b32 v18, 1, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v16, v3, v16 :: v_dual_lshlrev_b32 v9, 30, v9
	v_fmaak_f32 v17, v3, v17, 0x3d2aabf7
	v_fmac_f32_e32 v13, v13, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v8, v8, v16 :: v_dual_and_b32 v11, 0x80000000, v14
	v_dual_fmaak_f32 v12, v2, v12, 0xbf000004 :: v_dual_fmaak_f32 v17, v3, v17, 0xbf000004
	s_add_u32 s13, s18, 4
	s_addc_u32 s14, s19, 0
	s_add_u32 s16, s16, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v2, v2, v12, 1.0
	v_fma_f32 v3, v3, v17, 1.0
	s_addc_u32 s17, s17, 0
	s_add_u32 s4, s4, 4
	s_mov_b32 s12, 0
	v_cndmask_b32_e64 v2, -v13, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_addc_u32 s5, s5, 0
	s_mov_b32 s18, 0x3d1c21a7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v11, v2
	v_dual_cndmask_b32 v3, v3, v8 :: v_dual_and_b32 v8, 0x80000000, v9
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	v_mov_b32_e32 v11, 2
	v_xor3_b32 v3, v7, v8, v3
	v_cndmask_b32_e32 v8, 0x7fc00000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v9, 0x7fc00000, v3, vcc_lo
.LBB0_26:                               ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_27 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s19, -1.0
	s_mov_b32 s20, 5
	v_mov_b32_e32 v16, 0x40c00000
	v_mov_b32_e32 v18, 1.0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s13, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s14, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v3, vcc_lo
	flat_load_b32 v12, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v14, 0x40400000 :: v_dual_mov_b32 v13, 4.0
	s_waitcnt lgkmcnt(2)
	v_mov_b32_e32 v21, v12
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v19, v15, v17
	v_mov_b32_e32 v17, 2.0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v15, 1.0 :: v_dual_mul_f32 v20, v19, v19
	v_mov_b32_e32 v19, v12
.LBB0_27:                               ;   Parent Loop BB0_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mul_f32 v21, v12, v21 :: v_dual_mul_f32 v22, s19, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v23, s19, v20 :: v_dual_mul_f32 v24, v17, v14
	v_dual_add_f32 v25, 1.0, v14 :: v_dual_mul_f32 v26, v16, v13
	v_dual_add_f32 v14, 2.0, v14 :: v_dual_add_f32 v27, 1.0, v13
	v_dual_add_f32 v13, 2.0, v13 :: v_dual_mul_f32 v22, v21, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v29, null, v17, v17, v23
	v_div_scale_f32 v30, s1, v23, v17, v23
	v_div_scale_f32 v32, null, v16, v16, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v33, v29
	v_div_scale_f32 v37, s2, v22, v16, v22
	v_rcp_f32_e32 v35, v32
	s_add_i32 s20, s20, -1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v38, -v29, v33, 1.0
	v_fma_f32 v40, -v32, v35, 1.0
	v_mul_f32_e32 v28, s19, v21
	s_xor_b32 s19, s19, 0x80000000
	s_cmp_eq_u32 s20, 0
	v_mul_f32_e32 v21, v12, v21
	v_fmac_f32_e32 v35, v40, v35
	v_div_scale_f32 v31, null, v17, v17, v28
	v_div_scale_f32 v36, vcc_lo, v28, v17, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v34, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v39, -v31, v34, 1.0
	v_dual_fmac_f32 v33, v38, v33 :: v_dual_fmac_f32 v34, v39, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v38, v30, v33 :: v_dual_mul_f32 v39, v36, v34
	v_fma_f32 v41, -v29, v38, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v42, -v31, v39, v36
	v_mul_f32_e32 v40, v37, v35
	v_dual_fmac_f32 v38, v41, v33 :: v_dual_fmac_f32 v39, v42, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v43, -v32, v40, v37
	v_fma_f32 v29, -v29, v38, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v31, v39, v36
	v_fmac_f32_e32 v40, v43, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v34, v39
	v_fma_f32 v31, -v32, v40, v37
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v28, v30, v17, v28
	v_div_fmas_f32 v31, v31, v35, v40
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v22, v31, v16, v22
	v_dual_mul_f32 v16, v26, v27 :: v_dual_add_f32 v19, v19, v22
	v_div_fmas_f32 v29, v29, v33, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v23, v29, v17, v23
	v_dual_mul_f32 v17, v24, v25 :: v_dual_add_f32 v18, v18, v28
	v_add_f32_e32 v15, v23, v15
	s_cbranch_scc0 .LBB0_27
; %bb.28:                               ;   in Loop: Header=BB0_26 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v0, v18
	s_mov_b32 s19, -1.0
	s_mov_b32 s20, 5
	v_mul_f32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v10, v19
	v_fma_f32 v13, |v12|, -0.5, 0.5
	v_mul_f32_e32 v14, v12, v12
	v_cmp_gt_f32_e64 vcc_lo, |v12|, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_fmaak_f32 v14, s18, v13, 0x3c5fc5da
	v_sqrt_f32_e32 v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0x3d034c3c
	v_fmaak_f32 v14, v13, v14, 0x3d3641b1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0x3d999bc8
	v_fmaak_f32 v14, v13, v14, 0x3e2aaaac
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v13, v13, v14
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v15, v15, v13
	v_cmp_gt_f32_e64 s1, 0, v12
	v_fmac_f32_e32 v12, v12, v13
	v_add_f32_e32 v14, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, 0x3fc90fdb, v12
	v_sub_f32_e32 v15, 0x40490fdb, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v14, v15, s1
	v_mov_b32_e32 v14, 1.0
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0x42640000, v12
	v_mul_f32_e32 v12, 4.0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v12, v12
	v_lshlrev_b32_e32 v12, 2, v12
	ds_add_u32 v12, v11
	flat_load_b32 v2, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, 4.0 :: v_dual_mov_b32 v12, 0x40c00000
	v_mov_b32_e32 v7, 0x40400000
	s_waitcnt lgkmcnt(2)
	v_mov_b32_e32 v17, v2
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v15, v6, v13
	v_dual_mov_b32 v13, 2.0 :: v_dual_mov_b32 v6, 1.0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mul_f32 v16, v15, v15 :: v_dual_mov_b32 v15, v2
.LBB0_29:                               ;   Parent Loop BB0_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v19, s19, v16 :: v_dual_mul_f32 v20, v13, v7
	v_dual_mul_f32 v17, v2, v17 :: v_dual_mul_f32 v18, s19, v2
	v_add_f32_e32 v21, 1.0, v7
	v_div_scale_f32 v25, null, v13, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v24, s19, v17 :: v_dual_add_f32 v7, 2.0, v7
	v_mul_f32_e32 v18, v17, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v29, v25
	v_div_scale_f32 v26, s1, v19, v13, v19
	v_div_scale_f32 v27, null, v13, v13, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v28, null, v12, v12, v18
	v_div_scale_f32 v32, vcc_lo, v24, v13, v24
	v_rcp_f32_e32 v30, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v25, v29, 1.0
	v_rcp_f32_e32 v31, v28
	v_mul_f32_e32 v22, v12, v3
	v_div_scale_f32 v33, s2, v18, v12, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v29, v34, v29
	s_add_i32 s20, s20, -1
	s_xor_b32 s19, s19, 0x80000000
	s_cmp_eq_u32 s20, 0
	v_fma_f32 v35, -v27, v30, 1.0
	v_add_f32_e32 v23, 1.0, v3
	v_dual_add_f32 v3, 2.0, v3 :: v_dual_mul_f32 v34, v26, v29
	v_fma_f32 v36, -v28, v31, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v35, v30
	v_fma_f32 v37, -v25, v34, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v31, v36, v31 :: v_dual_fmac_f32 v34, v37, v29
	v_dual_mul_f32 v35, v32, v30 :: v_dual_mul_f32 v36, v33, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v25, v34, v26
	v_fma_f32 v38, -v27, v35, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v39, -v28, v36, v33
	v_dual_fmac_f32 v35, v38, v30 :: v_dual_fmac_f32 v36, v39, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v27, v35, v32
	v_fma_f32 v27, -v28, v36, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v26, v26, v30, v35
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v27, v27, v31, v36
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v24, v26, v13, v24
	v_div_fmas_f32 v25, v25, v29, v34
	v_div_fixup_f32 v18, v27, v12, v18
	v_mul_f32_e32 v12, v22, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v14, v14, v24
	v_div_fixup_f32 v19, v25, v13, v19
	v_mul_f32_e32 v17, v2, v17
	v_mul_f32_e32 v13, v20, v21
	v_add_f32_e32 v15, v15, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v6, v19, v6
	s_cbranch_scc0 .LBB0_29
; %bb.30:                               ;   in Loop: Header=BB0_26 Depth=1
	v_mul_f32_e32 v2, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v6
	v_fmac_f32_e32 v2, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v3, |v2|, -0.5, 0.5
	v_mul_f32_e32 v6, v2, v2
	v_cmp_gt_f32_e64 vcc_lo, |v2|, 0.5
	v_cndmask_b32_e32 v3, v6, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, s18, v3, 0x3c5fc5da
	v_sqrt_f32_e32 v7, v3
	v_fmaak_f32 v6, v3, v6, 0x3d034c3c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, v3, v6, 0x3d3641b1
	v_fmaak_f32 v6, v3, v6, 0x3d999bc8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, v3, v6, 0x3e2aaaac
	v_mul_f32_e32 v3, v3, v6
	v_cmp_gt_f32_e64 s1, 0, v2
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v7, v3
	v_fmac_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v7, v7
	v_sub_f32_e32 v2, 0x3fc90fdb, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, 0x40490fdb, v6
	v_cndmask_b32_e64 v3, v6, v7, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0x1869d, v1
	v_mul_f32_e32 v2, 0x42640000, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 4.0, v2
	v_cvt_i32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 2, v2
	ds_add_u32 v2, v11 offset:2880
	v_add_nc_u32_e32 v2, 1, v1
	v_mov_b32_e32 v1, v2
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_26
.LBB0_31:                               ; %Flow377
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_34
; %bb.32:                               ; %.preheader
	s_mov_b32 s1, 0
	s_mul_i32 s0, s15, 0x2d0
	s_mov_b32 s2, s1
.LBB0_33:                               ; =>This Inner Loop Header: Depth=1
	s_lshl_b64 s[4:5], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s6, s4
	s_addc_u32 s13, s7, s5
	v_mov_b32_e32 v2, s2
	v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
	s_add_u32 s12, s8, s4
	s_addc_u32 s13, s9, s5
	ds_load_b32 v3, v2 offset:5760
	s_add_u32 s4, s10, s4
	s_addc_u32 s5, s11, s5
	s_add_i32 s2, s2, 4
	s_add_i32 s0, s0, 1
	s_cmpk_lg_i32 s2, 0xb40
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[0:1], v3 dlc
	s_waitcnt_vscnt null, 0x0
	ds_load_b32 v3, v2
	v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[0:1], v3 dlc
	s_waitcnt_vscnt null, 0x0
	ds_load_b32 v2, v2 offset:2880
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[0:1], v2 dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_scc1 .LBB0_33
.LBB0_34:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6anglesPVfS0_S0_S0_PViS2_S2_
		.amdhsa_group_segment_fixed_size 8640
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 44
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6anglesPVfS0_S0_S0_PViS2_S2_, .Lfunc_end0-_Z6anglesPVfS0_S0_S0_PViS2_S2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6288
; NumSgprs: 26
; NumVgprs: 44
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8640 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 44
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8640
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6anglesPVfS0_S0_S0_PViS2_S2_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z6anglesPVfS0_S0_S0_PViS2_S2_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     44
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
