/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <iostream>
#include <cuda_runtime_api.h>
namespace nvinfer1
{
namespace plugin
{
__global__ void generateVoxels_kernel(
        int max_num_points,
        float *points, unsigned int* points_size,
        float min_x_range, float max_x_range,
        float min_y_range, float max_y_range,
        float min_z_range, float max_z_range,
        float pillar_x_size, float pillar_y_size, float pillar_z_size,
        int grid_y_size, int grid_x_size, int num_point_values,
        int max_points_per_voxel,
        unsigned int *mask, float *voxels)
{
  int point_idx = blockIdx.x * blockDim.x + threadIdx.x;
  int batch_idx = point_idx / max_num_points;
  int point_idx_in_frame = point_idx % max_num_points;
  if(point_idx_in_frame >= points_size[batch_idx]) return;
  float px = points[num_point_values * point_idx];
  float py = points[num_point_values * point_idx + 1];
  float pz = points[num_point_values * point_idx + 2];
  float pw = points[num_point_values * point_idx + 3];
  float pt;
  if (num_point_values == 5) {
    pt = points[num_point_values * point_idx + 4];
  }
  if(px<min_x_range||px>=max_x_range
    || py<min_y_range||py>=max_y_range
    || pz<min_z_range||pz>=max_z_range) return;
  int voxel_idx = floorf((px - min_x_range)/pillar_x_size);
  int voxel_idy = floorf((py - min_y_range)/pillar_y_size);
  unsigned int voxel_index = (batch_idx * grid_y_size + voxel_idy) * grid_x_size + voxel_idx;
  unsigned int point_id = atomicAdd(&(mask[voxel_index]), 1);
  if(point_id >= max_points_per_voxel) return;
  float *address = voxels + (voxel_index*max_points_per_voxel + point_id)*num_point_values;
  atomicExch(address+0, px);
  atomicExch(address+1, py);
  atomicExch(address+2, pz);
  atomicExch(address+3, pw);
  if (num_point_values == 5) {
    atomicExch(address+4, pt);
  }
}

__global__ void generateBaseFeatures_kernel(
        int batch_size,
        unsigned int *mask, float *voxels,
        int grid_y_size, int grid_x_size,
        unsigned int *pillar_num,
        int max_pillar_num,
        int max_points_per_voxel,
        int num_point_values,
        float *voxel_features,
        unsigned int *voxel_num_points,
        unsigned int *coords)
{
  int voxel_id = blockIdx.x * blockDim.x + threadIdx.x;
  int voxel_idx = voxel_id % grid_x_size;
  int voxel_idy = (voxel_id / grid_x_size) % grid_y_size;
  int batch_id = voxel_id / (grid_y_size * grid_x_size);
  if (batch_id >= batch_size) return;
  unsigned int count = mask[voxel_id];
  if( !(count>0) ) return;
  count = count<max_points_per_voxel?count:max_points_per_voxel;
  int current_pillarId = 0;
  current_pillarId = atomicAdd(pillar_num + batch_id, 1);
  voxel_num_points[batch_id * grid_y_size * grid_x_size + current_pillarId] = count;
  int4 coord = {0, 0, voxel_idy, voxel_idx};
  ((int4*)coords)[batch_id * max_pillar_num + current_pillarId] = coord;
  for (int i=0; i<count; i++){
    int inIndex = voxel_id*max_points_per_voxel + i;
    int outIndex = (batch_id * grid_x_size * grid_y_size + current_pillarId)*max_points_per_voxel + i;
    if (num_point_values == 4) {
      ((float4*)voxel_features)[outIndex] = ((float4*)voxels)[inIndex];
    }
    else if (num_point_values == 5) {
      for(int k=0; k<5;k++)
          voxel_features[5 * outIndex + k] = voxels[5 * inIndex + k];
    }
  }
}

void generateVoxels_launch(
        int batch_size, int max_num_points,
        float *points, unsigned int* points_size,
        float min_x_range, float max_x_range,
        float min_y_range, float max_y_range,
        float min_z_range, float max_z_range,
        float pillar_x_size, float pillar_y_size, float pillar_z_size,
        int grid_y_size, int grid_x_size, int num_point_values,
        int max_points_per_voxel,
        unsigned int *mask, float *voxels,
        cudaStream_t stream)
{
  int threadNum = 256;
  dim3 blocks((batch_size * max_num_points + threadNum - 1) / threadNum);
  dim3 threads(threadNum);
  generateVoxels_kernel<<<blocks, threads, 0, stream>>>
      (max_num_points,
        points, points_size,
        min_x_range, max_x_range,
        min_y_range, max_y_range,
        min_z_range, max_z_range,
        pillar_x_size, pillar_y_size, pillar_z_size,
        grid_y_size, grid_x_size, num_point_values,
        max_points_per_voxel,
        mask, voxels);
}

void generateBaseFeatures_launch(
        int batch_size,
        unsigned int *mask, float *voxels,
        int grid_y_size, int grid_x_size,
        unsigned int *pillar_num,
        int max_pillar_num,
        int max_points_per_voxel,
        int num_point_values,
        float *voxel_features,
        unsigned int *voxel_num_points,
        unsigned int *coords,
        cudaStream_t stream)
{
  int blockSize = 1024;
  dim3 threads(blockSize);
  dim3 blocks((batch_size * grid_y_size * grid_x_size + blockSize - 1) / blockSize);
  generateBaseFeatures_kernel<<<blocks, threads, 0, stream>>>
      (
        batch_size,
        mask, voxels, grid_y_size, grid_x_size,
        pillar_num,
        max_pillar_num,
        max_points_per_voxel,
        num_point_values,
        voxel_features,
        voxel_num_points,
        coords
      );
}

__global__ void generateFeatures_kernel(
    int batch_size,
    int dense_pillar_num,
    float* voxel_features,
    unsigned int* voxel_num_points,
    unsigned int* coords, unsigned int *params,
    float voxel_x, float voxel_y, float voxel_z,
    float range_min_x, float range_min_y, float range_min_z,
    unsigned int voxel_features_size, unsigned int max_points,
    unsigned int max_voxels,
    float* features)
{
    int warp_size = max_points;
    int pillar_idx = blockIdx.x * 4 + threadIdx.x/warp_size;
    int point_idx = threadIdx.x % warp_size;
    // In case the actual number of points is less than warp_size
    // E.g., warp_size=32, max_points=20
    if (point_idx >= max_points) return;
    int batch_idx = pillar_idx / max_voxels;
    if (batch_idx >= batch_size) return;
    int pillar_idx_in_frame = pillar_idx % max_voxels;
    int dense_pillar_idx = pillar_idx_in_frame + dense_pillar_num * batch_idx;
    int pillar_idx_inBlock = threadIdx.x/warp_size;
    // Limit number of voxels to max_voxels
    unsigned int num_pillars = params[batch_idx] > max_voxels ? max_voxels : params[batch_idx];
    // Update max_voxel to actual number
    if (pillar_idx_in_frame == 0 && point_idx == 0) {
      params[batch_idx] = num_pillars;
    }
    if (pillar_idx_in_frame >= num_pillars) return;

    //load src
    __shared__ float pillarSM[4][64][5]; // up to 64 points per pillar
    __shared__ float4 pillarSumSM[4]; //4*4
    __shared__ int4 cordsSM[4]; //4*4
    __shared__ int pointsNumSM[4]; //4
    __shared__ float pillarOutSM[4][64][11]; // up to 11 features per point

    if (point_idx == 0) {
      pointsNumSM[pillar_idx_inBlock] = voxel_num_points[dense_pillar_idx];
      cordsSM[pillar_idx_inBlock] = ((int4*)coords)[dense_pillar_idx];
      pillarSumSM[pillar_idx_inBlock] = {0,0,0,0};
    }
    for(int k=0; k<5; k++) {
      pillarSM[pillar_idx_inBlock][point_idx][k] = voxel_features[5 * (dense_pillar_idx*max_points + point_idx) + k];
    }
    __syncthreads();
    //calculate sm
    if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].x),  pillarSM[pillar_idx_inBlock][point_idx][0]);
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].y),  pillarSM[pillar_idx_inBlock][point_idx][1]);
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].z),  pillarSM[pillar_idx_inBlock][point_idx][2]);
    }
    __syncthreads();
    //feature-mean
    float4 mean;
    float validPoints = pointsNumSM[pillar_idx_inBlock];
    mean.x = pillarSumSM[pillar_idx_inBlock].x / validPoints;
    mean.y = pillarSumSM[pillar_idx_inBlock].y / validPoints;
    mean.z = pillarSumSM[pillar_idx_inBlock].z / validPoints;
    mean.x  = pillarSM[pillar_idx_inBlock][point_idx][0] - mean.x;
    mean.y  = pillarSM[pillar_idx_inBlock][point_idx][1] - mean.y;
    mean.z  = pillarSM[pillar_idx_inBlock][point_idx][2] - mean.z;
    //calculate offset
    float x_offset = voxel_x / 2.0f + cordsSM[pillar_idx_inBlock].w * voxel_x + range_min_x;
    float y_offset = voxel_y / 2.0f + cordsSM[pillar_idx_inBlock].z * voxel_y + range_min_y;
    float z_offset = voxel_z / 2.0f + cordsSM[pillar_idx_inBlock].y * voxel_z + range_min_z;
    //feature-offset
    float4 center;
    center.x  = pillarSM[pillar_idx_inBlock][point_idx][0] - x_offset;
    center.y  = pillarSM[pillar_idx_inBlock][point_idx][1] - y_offset;
    center.z  = pillarSM[pillar_idx_inBlock][point_idx][2] - z_offset;
    //store output
    if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
      for(int k=0; k<5; k++)
        pillarOutSM[pillar_idx_inBlock][point_idx][k] = pillarSM[pillar_idx_inBlock][point_idx][k];
      pillarOutSM[pillar_idx_inBlock][point_idx][5] = mean.x;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 1] = mean.y;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 2] = mean.z;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 3] = center.x;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 4] = center.y;
      if (5 + 5 < voxel_features_size)
        pillarOutSM[pillar_idx_inBlock][point_idx][warp_size + 5] = center.z;
    } else {
      for (int k = 0; k < voxel_features_size; k++)
        pillarOutSM[pillar_idx_inBlock][point_idx][k] = 0;
    }
    __syncthreads();
    for(int i = 0; i < voxel_features_size; i ++) {
      int outputSMId = pillar_idx_inBlock*64*11 + point_idx * 11 + i;
      int outputId = pillar_idx*max_points*voxel_features_size + point_idx * voxel_features_size + i;
      features[outputId] = ((float*)pillarOutSM)[outputSMId] ;
    }

}

__global__ void generateFeatures_kernel_4x(
  int batch_size,
  int dense_pillar_num,
  float* voxel_features,
  unsigned int* voxel_num_points, unsigned int* coords,
  unsigned int *params,
  float voxel_x, float voxel_y, float voxel_z,
  float range_min_x, float range_min_y, float range_min_z,
  unsigned int voxel_features_size, unsigned int max_points,
  unsigned int max_voxels,
  float* features)
{
  int warp_size = max_points;
  int pillar_idx = blockIdx.x * 4 + threadIdx.x / warp_size;
  int point_idx = threadIdx.x % warp_size;
  // In case the actual number of points is less than warp_size
  // E.g., warp_size=32, max_points=20
  if (point_idx >= max_points) return;
  int batch_idx = pillar_idx / max_voxels;
  if (batch_idx >= batch_size) return;
  int pillar_idx_in_frame = pillar_idx % max_voxels;
  int dense_pillar_idx = pillar_idx_in_frame + dense_pillar_num * batch_idx;
  int pillar_idx_inBlock = threadIdx.x / warp_size;
  // Limit number of voxels to max_voxels
  unsigned int num_pillars = params[batch_idx] > max_voxels ? max_voxels : params[batch_idx];
  // Update max_voxel to actual number
  if (pillar_idx_in_frame == 0 && point_idx == 0) {
    params[batch_idx] = num_pillars;
  }
  if (pillar_idx_in_frame >= num_pillars) return;
  //load src
  __shared__ float4 pillarSM[4][64]; // up to 64 points per pillar
  __shared__ float4 pillarSumSM[4]; //4*4
  __shared__ int4 cordsSM[4]; //4*4
  __shared__ int pointsNumSM[4]; //4
  __shared__ float pillarOutSM[4][64][11]; // up to 11 output features per point

  if (point_idx == 0) {
    pointsNumSM[pillar_idx_inBlock] = voxel_num_points[dense_pillar_idx];
    cordsSM[pillar_idx_inBlock] = ((int4*)coords)[pillar_idx];
    pillarSumSM[pillar_idx_inBlock] = {0,0,0,0};
  }
  pillarSM[pillar_idx_inBlock][point_idx] = ((float4*)voxel_features)[dense_pillar_idx*max_points + point_idx];
  __syncthreads();
  //calculate sm
  if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].x),  pillarSM[pillar_idx_inBlock][point_idx].x);
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].y),  pillarSM[pillar_idx_inBlock][point_idx].y);
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].z),  pillarSM[pillar_idx_inBlock][point_idx].z);
  }
  __syncthreads();
  //feature-mean
  float4 mean;
  float validPoints = pointsNumSM[pillar_idx_inBlock];
  mean.x = pillarSumSM[pillar_idx_inBlock].x / validPoints;
  mean.y = pillarSumSM[pillar_idx_inBlock].y / validPoints;
  mean.z = pillarSumSM[pillar_idx_inBlock].z / validPoints;
  mean.x  = pillarSM[pillar_idx_inBlock][point_idx].x - mean.x;
  mean.y  = pillarSM[pillar_idx_inBlock][point_idx].y - mean.y;
  mean.z  = pillarSM[pillar_idx_inBlock][point_idx].z - mean.z;
  //calculate offset
  float x_offset = voxel_x / 2.0f + cordsSM[pillar_idx_inBlock].w * voxel_x + range_min_x;
  float y_offset = voxel_y / 2.0f + cordsSM[pillar_idx_inBlock].z * voxel_y + range_min_y;
  float z_offset = voxel_z / 2.0f + cordsSM[pillar_idx_inBlock].y * voxel_z + range_min_z;
  //feature-offset
  float4 center;
  center.x  = pillarSM[pillar_idx_inBlock][point_idx].x - x_offset;
  center.y  = pillarSM[pillar_idx_inBlock][point_idx].y - y_offset;
  center.z  = pillarSM[pillar_idx_inBlock][point_idx].z - z_offset;
  //store output
  if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
    pillarOutSM[pillar_idx_inBlock][point_idx][0] = pillarSM[pillar_idx_inBlock][point_idx].x;
    pillarOutSM[pillar_idx_inBlock][point_idx][1] = pillarSM[pillar_idx_inBlock][point_idx].y;
    pillarOutSM[pillar_idx_inBlock][point_idx][2] = pillarSM[pillar_idx_inBlock][point_idx].z;
    pillarOutSM[pillar_idx_inBlock][point_idx][3] = pillarSM[pillar_idx_inBlock][point_idx].w;
    pillarOutSM[pillar_idx_inBlock][point_idx][4] = mean.x;
    pillarOutSM[pillar_idx_inBlock][point_idx][5] = mean.y;
    pillarOutSM[pillar_idx_inBlock][point_idx][6] = mean.z;
    pillarOutSM[pillar_idx_inBlock][point_idx][7] = center.x;
    pillarOutSM[pillar_idx_inBlock][point_idx][8] = center.y;
    pillarOutSM[pillar_idx_inBlock][point_idx][9] = center.z;

  } else {
    pillarOutSM[pillar_idx_inBlock][point_idx][0] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][1] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][2] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][3] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][4] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][5] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][6] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][7] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][8] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][9] = 0;
  }
  __syncthreads();
  for(int i = 0; i < voxel_features_size; i ++) {
    int outputSMId = pillar_idx_inBlock*64*11 + point_idx * 11 + i;
    int outputId = pillar_idx*max_points*voxel_features_size + point_idx * voxel_features_size + i;
    features[outputId] = ((float*)pillarOutSM)[outputSMId] ;
  }

}

int generateFeatures_launch(
    int batch_size,
    int dense_pillar_num,
    float* voxel_features,
    unsigned int* voxel_num_points,
    unsigned int* coords,
    unsigned int *params,
    float voxel_x, float voxel_y, float voxel_z,
    float range_min_x, float range_min_y, float range_min_z,
    unsigned int voxel_features_size, unsigned int max_points,
    unsigned int max_voxels, unsigned int num_point_values,
    float* features,
    cudaStream_t stream)
{
    unsigned int warp_size = max_points;
    dim3 blocks((batch_size * max_voxels + 3) / 4);
    dim3 threads(4*warp_size);
    if (num_point_values == 4) {
      generateFeatures_kernel_4x<<<blocks, threads, 0, stream>>>
      (batch_size,
      dense_pillar_num,
      voxel_features,
      voxel_num_points,
      coords,
      params,
      voxel_x, voxel_y, voxel_z,
      range_min_x, range_min_y, range_min_z,
      voxel_features_size, max_points,
      max_voxels, 
      features);
    }
    else {
      generateFeatures_kernel<<<blocks, threads, 0, stream>>>
      (batch_size,
      dense_pillar_num,
      voxel_features,
      voxel_num_points,
      coords,
      params,
      voxel_x, voxel_y, voxel_z,
      range_min_x, range_min_y, range_min_z,
      voxel_features_size, max_points,
      max_voxels, 
      features);
    }
    auto err = cudaGetLastError();
    if (cudaSuccess != err) {
        fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
        exit(-1);
    }
    return err;
}
} // namespace plugin
} // namespace nvinfer1

	.file	"tmpxft_00302e80_00000000-6_voxelGeneratorKernels.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_
	.type	_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_, @function
_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	336(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	96(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movl	%r9d, 16(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 72(%rsp)
	movss	%xmm1, 52(%rsp)
	movss	%xmm2, 48(%rsp)
	movss	%xmm3, 44(%rsp)
	movss	%xmm4, 40(%rsp)
	movss	%xmm5, 36(%rsp)
	movss	%xmm6, 32(%rsp)
	movss	%xmm7, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	%rsp, %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 336
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L2:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_, .-_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_
	.globl	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.type	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, @function
_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_
	.cfi_endproc
.LFE3663:
	.size	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, .-_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.globl	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P11CUstream_st
	.type	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P11CUstream_st, @function
_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P11CUstream_st:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	imull	%esi, %edi
	movl	%esi, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leal	255(%rdi), %eax
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdx, 8(%rsp)
	cltd
	movss	160(%rsp), %xmm8
	movq	%rcx, 16(%rsp)
	movl	$256, %ecx
	movl	168(%rsp), %ebx
	idivl	%ecx
	movss	%xmm0, 60(%rsp)
	movl	176(%rsp), %r14d
	movq	184(%rsp), %r13
	movss	%xmm1, 56(%rsp)
	movq	192(%rsp), %r12
	movss	%xmm2, 52(%rsp)
	movss	%xmm3, 48(%rsp)
	movss	%xmm4, 44(%rsp)
	movss	%xmm5, 40(%rsp)
	movss	%xmm6, 36(%rsp)
	movss	%xmm7, 32(%rsp)
	movss	%xmm8, 28(%rsp)
	movl	%r8d, 24(%rsp)
	movl	$16777217, %edx
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$8, %rdx
	movl	%eax, 72(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 76(%rsp)
	movq	200(%rsp), %r9
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm8
	movss	32(%rsp), %xmm7
	testl	%eax, %eax
	movss	36(%rsp), %xmm6
	movss	40(%rsp), %xmm5
	movss	44(%rsp), %xmm4
	movss	48(%rsp), %xmm3
	movss	52(%rsp), %xmm2
	movss	56(%rsp), %xmm1
	movss	60(%rsp), %xmm0
	jne	.L8
	movl	24(%rsp), %ecx
	movq	16(%rsp), %rdx
	movl	%ebx, %r9d
	movl	%ebp, %r8d
	movq	%r12, 184(%rsp)
	movq	8(%rsp), %rsi
	movl	%r15d, %edi
	movq	%r13, 176(%rsp)
	movl	%r14d, 168(%rsp)
	movss	%xmm8, 160(%rsp)
	addq	$104, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z81__device_stub__ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_iPfPjfffffffffiiiiS0_S_
.L8:
	.cfi_restore_state
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P11CUstream_st, .-_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P11CUstream_st
	.globl	_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_
	.type	_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_, @function
_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	280(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	288(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	296(%rsp), %rax
	movl	%ecx, 56(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L11:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_, .-_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_
	.globl	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.type	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, @function
_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_
	.cfi_endproc
.LFE3665:
	.size	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, .-_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.globl	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P11CUstream_st
	.type	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P11CUstream_st, @function
_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P11CUstream_st:
.LFB3636:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	imull	%edi, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%r8d, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	xorl	%r8d, %r8d
	addl	$1023, %eax
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdx, 16(%rsp)
	cltd
	movq	176(%rsp), %r10
	movl	%ecx, 4(%rsp)
	movl	$1024, %ecx
	movq	184(%rsp), %r11
	idivl	%ecx
	movq	%rsi, 8(%rsp)
	movl	144(%rsp), %r12d
	movq	%r9, 24(%rsp)
	movq	192(%rsp), %r9
	movq	%r10, 40(%rsp)
	movl	152(%rsp), %r13d
	movq	%r11, 32(%rsp)
	movl	160(%rsp), %r14d
	movq	168(%rsp), %r15
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 68(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	68(%rsp), %rdi
	movl	76(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movq	32(%rsp), %r11
	movq	40(%rsp), %r10
	testl	%eax, %eax
	jne	.L16
	movq	%r15, 168(%rsp)
	movq	24(%rsp), %r9
	movl	%ebx, %r8d
	movl	%ebp, %edi
	movl	%r14d, 160(%rsp)
	movl	4(%rsp), %ecx
	movl	%r13d, 152(%rsp)
	movq	16(%rsp), %rdx
	movl	%r12d, 144(%rsp)
	movq	8(%rsp), %rsi
	movq	%r11, 184(%rsp)
	movq	%r10, 176(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z85__device_stub__ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_iPjPfiiS_iiiS0_S_S_
.L16:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P11CUstream_st, .-_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P11CUstream_st
	.globl	_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.type	_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_, @function
_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	328(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 64(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 56(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 48(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movss	%xmm1, 32(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm5, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	96(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 320
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L19:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_, .-_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.globl	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.type	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, @function
_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.cfi_endproc
.LFE3667:
	.size	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, .-_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.globl	_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.type	_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_, @function
_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	328(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 64(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 56(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 48(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movss	%xmm1, 32(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm5, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	96(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 320
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L24:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_, .-_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.globl	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.type	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, @function
_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	.cfi_endproc
.LFE3669:
	.size	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, .-_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA kernel failed : %s\n"
	.text
	.globl	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P11CUstream_st
	.type	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P11CUstream_st, @function
_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P11CUstream_st:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	movl	$0, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	160(%rsp), %r14d
	movl	152(%rsp), %r13d
	movq	%rdx, 8(%rsp)
	movl	%esi, 4(%rsp)
	movq	176(%rsp), %r15
	imull	%r14d, %eax
	leal	0(,%r13,4), %edx
	movq	%rcx, 16(%rsp)
	movl	%edx, 68(%rsp)
	movss	%xmm0, 24(%rsp)
	addl	$3, %eax
	movss	%xmm5, 44(%rsp)
	shrl	$2, %eax
	cmpl	$4, 168(%rsp)
	movss	%xmm4, 40(%rsp)
	movl	%eax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	56(%rsp), %rdi
	movq	%rax, 72(%rsp)
	movl	64(%rsp), %esi
	movq	68(%rsp), %rdx
	movl	76(%rsp), %ecx
	movss	%xmm3, 36(%rsp)
	movq	184(%rsp), %r9
	movss	%xmm2, 32(%rsp)
	movss	%xmm1, 28(%rsp)
	jne	.L30
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm1
	movss	32(%rsp), %xmm2
	testl	%eax, %eax
	movss	36(%rsp), %xmm3
	movss	40(%rsp), %xmm4
	movss	44(%rsp), %xmm5
	jne	.L32
	pushq	%r15
	.cfi_remember_state
	.cfi_def_cfa_offset 152
	movq	%r12, %r9
	movq	%rbp, %r8
	movl	%ebx, %edi
	pushq	%r14
	.cfi_def_cfa_offset 160
	pushq	%r13
	.cfi_def_cfa_offset 168
	movl	168(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movss	56(%rsp), %xmm0
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movl	36(%rsp), %esi
	call	_Z86__device_stub__ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
	jmp	.L36
.L30:
	.cfi_restore_state
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm1
	movss	32(%rsp), %xmm2
	testl	%eax, %eax
	movss	36(%rsp), %xmm3
	movss	40(%rsp), %xmm4
	movss	44(%rsp), %xmm5
	jne	.L32
	pushq	%r15
	.cfi_def_cfa_offset 152
	movq	%r12, %r9
	movq	%rbp, %r8
	movl	%ebx, %edi
	pushq	%r14
	.cfi_def_cfa_offset 160
	pushq	%r13
	.cfi_def_cfa_offset 168
	movl	168(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movss	56(%rsp), %xmm0
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movl	36(%rsp), %esi
	call	_Z83__device_stub__ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_iiPfPjS0_S0_ffffffjjjS_
.L36:
	addq	$32, %rsp
	.cfi_def_cfa_offset 144
.L32:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L34
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L34:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P11CUstream_st, .-_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P11CUstream_st
	.section	.rodata.str1.1
.LC1:
	.string	"_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_"
.LC2:
	.string	"_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_"
.LC3:
	.string	"_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_"
.LC4:
	.string	"_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3671:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3671:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include <hip/hip_runtime.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
namespace nvinfer1
{
namespace plugin
{
__global__ void generateVoxels_kernel(
        int max_num_points,
        float *points, unsigned int* points_size,
        float min_x_range, float max_x_range,
        float min_y_range, float max_y_range,
        float min_z_range, float max_z_range,
        float pillar_x_size, float pillar_y_size, float pillar_z_size,
        int grid_y_size, int grid_x_size, int num_point_values,
        int max_points_per_voxel,
        unsigned int *mask, float *voxels)
{
  int point_idx = blockIdx.x * blockDim.x + threadIdx.x;
  int batch_idx = point_idx / max_num_points;
  int point_idx_in_frame = point_idx % max_num_points;
  if(point_idx_in_frame >= points_size[batch_idx]) return;
  float px = points[num_point_values * point_idx];
  float py = points[num_point_values * point_idx + 1];
  float pz = points[num_point_values * point_idx + 2];
  float pw = points[num_point_values * point_idx + 3];
  float pt;
  if (num_point_values == 5) {
    pt = points[num_point_values * point_idx + 4];
  }
  if(px<min_x_range||px>=max_x_range
    || py<min_y_range||py>=max_y_range
    || pz<min_z_range||pz>=max_z_range) return;
  int voxel_idx = floorf((px - min_x_range)/pillar_x_size);
  int voxel_idy = floorf((py - min_y_range)/pillar_y_size);
  unsigned int voxel_index = (batch_idx * grid_y_size + voxel_idy) * grid_x_size + voxel_idx;
  unsigned int point_id = atomicAdd(&(mask[voxel_index]), 1);
  if(point_id >= max_points_per_voxel) return;
  float *address = voxels + (voxel_index*max_points_per_voxel + point_id)*num_point_values;
  atomicExch(address+0, px);
  atomicExch(address+1, py);
  atomicExch(address+2, pz);
  atomicExch(address+3, pw);
  if (num_point_values == 5) {
    atomicExch(address+4, pt);
  }
}

__global__ void generateBaseFeatures_kernel(
        int batch_size,
        unsigned int *mask, float *voxels,
        int grid_y_size, int grid_x_size,
        unsigned int *pillar_num,
        int max_pillar_num,
        int max_points_per_voxel,
        int num_point_values,
        float *voxel_features,
        unsigned int *voxel_num_points,
        unsigned int *coords)
{
  int voxel_id = blockIdx.x * blockDim.x + threadIdx.x;
  int voxel_idx = voxel_id % grid_x_size;
  int voxel_idy = (voxel_id / grid_x_size) % grid_y_size;
  int batch_id = voxel_id / (grid_y_size * grid_x_size);
  if (batch_id >= batch_size) return;
  unsigned int count = mask[voxel_id];
  if( !(count>0) ) return;
  count = count<max_points_per_voxel?count:max_points_per_voxel;
  int current_pillarId = 0;
  current_pillarId = atomicAdd(pillar_num + batch_id, 1);
  voxel_num_points[batch_id * grid_y_size * grid_x_size + current_pillarId] = count;
  int4 coord = {0, 0, voxel_idy, voxel_idx};
  ((int4*)coords)[batch_id * max_pillar_num + current_pillarId] = coord;
  for (int i=0; i<count; i++){
    int inIndex = voxel_id*max_points_per_voxel + i;
    int outIndex = (batch_id * grid_x_size * grid_y_size + current_pillarId)*max_points_per_voxel + i;
    if (num_point_values == 4) {
      ((float4*)voxel_features)[outIndex] = ((float4*)voxels)[inIndex];
    }
    else if (num_point_values == 5) {
      for(int k=0; k<5;k++)
          voxel_features[5 * outIndex + k] = voxels[5 * inIndex + k];
    }
  }
}

void generateVoxels_launch(
        int batch_size, int max_num_points,
        float *points, unsigned int* points_size,
        float min_x_range, float max_x_range,
        float min_y_range, float max_y_range,
        float min_z_range, float max_z_range,
        float pillar_x_size, float pillar_y_size, float pillar_z_size,
        int grid_y_size, int grid_x_size, int num_point_values,
        int max_points_per_voxel,
        unsigned int *mask, float *voxels,
        hipStream_t stream)
{
  int threadNum = 256;
  dim3 blocks((batch_size * max_num_points + threadNum - 1) / threadNum);
  dim3 threads(threadNum);
  generateVoxels_kernel<<<blocks, threads, 0, stream>>>
      (max_num_points,
        points, points_size,
        min_x_range, max_x_range,
        min_y_range, max_y_range,
        min_z_range, max_z_range,
        pillar_x_size, pillar_y_size, pillar_z_size,
        grid_y_size, grid_x_size, num_point_values,
        max_points_per_voxel,
        mask, voxels);
}

void generateBaseFeatures_launch(
        int batch_size,
        unsigned int *mask, float *voxels,
        int grid_y_size, int grid_x_size,
        unsigned int *pillar_num,
        int max_pillar_num,
        int max_points_per_voxel,
        int num_point_values,
        float *voxel_features,
        unsigned int *voxel_num_points,
        unsigned int *coords,
        hipStream_t stream)
{
  int blockSize = 1024;
  dim3 threads(blockSize);
  dim3 blocks((batch_size * grid_y_size * grid_x_size + blockSize - 1) / blockSize);
  generateBaseFeatures_kernel<<<blocks, threads, 0, stream>>>
      (
        batch_size,
        mask, voxels, grid_y_size, grid_x_size,
        pillar_num,
        max_pillar_num,
        max_points_per_voxel,
        num_point_values,
        voxel_features,
        voxel_num_points,
        coords
      );
}

__global__ void generateFeatures_kernel(
    int batch_size,
    int dense_pillar_num,
    float* voxel_features,
    unsigned int* voxel_num_points,
    unsigned int* coords, unsigned int *params,
    float voxel_x, float voxel_y, float voxel_z,
    float range_min_x, float range_min_y, float range_min_z,
    unsigned int voxel_features_size, unsigned int max_points,
    unsigned int max_voxels,
    float* features)
{
    int warp_size = max_points;
    int pillar_idx = blockIdx.x * 4 + threadIdx.x/warp_size;
    int point_idx = threadIdx.x % warp_size;
    // In case the actual number of points is less than warp_size
    // E.g., warp_size=32, max_points=20
    if (point_idx >= max_points) return;
    int batch_idx = pillar_idx / max_voxels;
    if (batch_idx >= batch_size) return;
    int pillar_idx_in_frame = pillar_idx % max_voxels;
    int dense_pillar_idx = pillar_idx_in_frame + dense_pillar_num * batch_idx;
    int pillar_idx_inBlock = threadIdx.x/warp_size;
    // Limit number of voxels to max_voxels
    unsigned int num_pillars = params[batch_idx] > max_voxels ? max_voxels : params[batch_idx];
    // Update max_voxel to actual number
    if (pillar_idx_in_frame == 0 && point_idx == 0) {
      params[batch_idx] = num_pillars;
    }
    if (pillar_idx_in_frame >= num_pillars) return;

    //load src
    __shared__ float pillarSM[4][64][5]; // up to 64 points per pillar
    __shared__ float4 pillarSumSM[4]; //4*4
    __shared__ int4 cordsSM[4]; //4*4
    __shared__ int pointsNumSM[4]; //4
    __shared__ float pillarOutSM[4][64][11]; // up to 11 features per point

    if (point_idx == 0) {
      pointsNumSM[pillar_idx_inBlock] = voxel_num_points[dense_pillar_idx];
      cordsSM[pillar_idx_inBlock] = ((int4*)coords)[dense_pillar_idx];
      pillarSumSM[pillar_idx_inBlock] = {0,0,0,0};
    }
    for(int k=0; k<5; k++) {
      pillarSM[pillar_idx_inBlock][point_idx][k] = voxel_features[5 * (dense_pillar_idx*max_points + point_idx) + k];
    }
    __syncthreads();
    //calculate sm
    if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].x),  pillarSM[pillar_idx_inBlock][point_idx][0]);
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].y),  pillarSM[pillar_idx_inBlock][point_idx][1]);
      atomicAdd(&(pillarSumSM[pillar_idx_inBlock].z),  pillarSM[pillar_idx_inBlock][point_idx][2]);
    }
    __syncthreads();
    //feature-mean
    float4 mean;
    float validPoints = pointsNumSM[pillar_idx_inBlock];
    mean.x = pillarSumSM[pillar_idx_inBlock].x / validPoints;
    mean.y = pillarSumSM[pillar_idx_inBlock].y / validPoints;
    mean.z = pillarSumSM[pillar_idx_inBlock].z / validPoints;
    mean.x  = pillarSM[pillar_idx_inBlock][point_idx][0] - mean.x;
    mean.y  = pillarSM[pillar_idx_inBlock][point_idx][1] - mean.y;
    mean.z  = pillarSM[pillar_idx_inBlock][point_idx][2] - mean.z;
    //calculate offset
    float x_offset = voxel_x / 2.0f + cordsSM[pillar_idx_inBlock].w * voxel_x + range_min_x;
    float y_offset = voxel_y / 2.0f + cordsSM[pillar_idx_inBlock].z * voxel_y + range_min_y;
    float z_offset = voxel_z / 2.0f + cordsSM[pillar_idx_inBlock].y * voxel_z + range_min_z;
    //feature-offset
    float4 center;
    center.x  = pillarSM[pillar_idx_inBlock][point_idx][0] - x_offset;
    center.y  = pillarSM[pillar_idx_inBlock][point_idx][1] - y_offset;
    center.z  = pillarSM[pillar_idx_inBlock][point_idx][2] - z_offset;
    //store output
    if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
      for(int k=0; k<5; k++)
        pillarOutSM[pillar_idx_inBlock][point_idx][k] = pillarSM[pillar_idx_inBlock][point_idx][k];
      pillarOutSM[pillar_idx_inBlock][point_idx][5] = mean.x;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 1] = mean.y;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 2] = mean.z;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 3] = center.x;
      pillarOutSM[pillar_idx_inBlock][point_idx][5 + 4] = center.y;
      if (5 + 5 < voxel_features_size)
        pillarOutSM[pillar_idx_inBlock][point_idx][warp_size + 5] = center.z;
    } else {
      for (int k = 0; k < voxel_features_size; k++)
        pillarOutSM[pillar_idx_inBlock][point_idx][k] = 0;
    }
    __syncthreads();
    for(int i = 0; i < voxel_features_size; i ++) {
      int outputSMId = pillar_idx_inBlock*64*11 + point_idx * 11 + i;
      int outputId = pillar_idx*max_points*voxel_features_size + point_idx * voxel_features_size + i;
      features[outputId] = ((float*)pillarOutSM)[outputSMId] ;
    }

}

__global__ void generateFeatures_kernel_4x(
  int batch_size,
  int dense_pillar_num,
  float* voxel_features,
  unsigned int* voxel_num_points, unsigned int* coords,
  unsigned int *params,
  float voxel_x, float voxel_y, float voxel_z,
  float range_min_x, float range_min_y, float range_min_z,
  unsigned int voxel_features_size, unsigned int max_points,
  unsigned int max_voxels,
  float* features)
{
  int warp_size = max_points;
  int pillar_idx = blockIdx.x * 4 + threadIdx.x / warp_size;
  int point_idx = threadIdx.x % warp_size;
  // In case the actual number of points is less than warp_size
  // E.g., warp_size=32, max_points=20
  if (point_idx >= max_points) return;
  int batch_idx = pillar_idx / max_voxels;
  if (batch_idx >= batch_size) return;
  int pillar_idx_in_frame = pillar_idx % max_voxels;
  int dense_pillar_idx = pillar_idx_in_frame + dense_pillar_num * batch_idx;
  int pillar_idx_inBlock = threadIdx.x / warp_size;
  // Limit number of voxels to max_voxels
  unsigned int num_pillars = params[batch_idx] > max_voxels ? max_voxels : params[batch_idx];
  // Update max_voxel to actual number
  if (pillar_idx_in_frame == 0 && point_idx == 0) {
    params[batch_idx] = num_pillars;
  }
  if (pillar_idx_in_frame >= num_pillars) return;
  //load src
  __shared__ float4 pillarSM[4][64]; // up to 64 points per pillar
  __shared__ float4 pillarSumSM[4]; //4*4
  __shared__ int4 cordsSM[4]; //4*4
  __shared__ int pointsNumSM[4]; //4
  __shared__ float pillarOutSM[4][64][11]; // up to 11 output features per point

  if (point_idx == 0) {
    pointsNumSM[pillar_idx_inBlock] = voxel_num_points[dense_pillar_idx];
    cordsSM[pillar_idx_inBlock] = ((int4*)coords)[pillar_idx];
    pillarSumSM[pillar_idx_inBlock] = {0,0,0,0};
  }
  pillarSM[pillar_idx_inBlock][point_idx] = ((float4*)voxel_features)[dense_pillar_idx*max_points + point_idx];
  __syncthreads();
  //calculate sm
  if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].x),  pillarSM[pillar_idx_inBlock][point_idx].x);
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].y),  pillarSM[pillar_idx_inBlock][point_idx].y);
    atomicAdd(&(pillarSumSM[pillar_idx_inBlock].z),  pillarSM[pillar_idx_inBlock][point_idx].z);
  }
  __syncthreads();
  //feature-mean
  float4 mean;
  float validPoints = pointsNumSM[pillar_idx_inBlock];
  mean.x = pillarSumSM[pillar_idx_inBlock].x / validPoints;
  mean.y = pillarSumSM[pillar_idx_inBlock].y / validPoints;
  mean.z = pillarSumSM[pillar_idx_inBlock].z / validPoints;
  mean.x  = pillarSM[pillar_idx_inBlock][point_idx].x - mean.x;
  mean.y  = pillarSM[pillar_idx_inBlock][point_idx].y - mean.y;
  mean.z  = pillarSM[pillar_idx_inBlock][point_idx].z - mean.z;
  //calculate offset
  float x_offset = voxel_x / 2.0f + cordsSM[pillar_idx_inBlock].w * voxel_x + range_min_x;
  float y_offset = voxel_y / 2.0f + cordsSM[pillar_idx_inBlock].z * voxel_y + range_min_y;
  float z_offset = voxel_z / 2.0f + cordsSM[pillar_idx_inBlock].y * voxel_z + range_min_z;
  //feature-offset
  float4 center;
  center.x  = pillarSM[pillar_idx_inBlock][point_idx].x - x_offset;
  center.y  = pillarSM[pillar_idx_inBlock][point_idx].y - y_offset;
  center.z  = pillarSM[pillar_idx_inBlock][point_idx].z - z_offset;
  //store output
  if (point_idx < pointsNumSM[pillar_idx_inBlock]) {
    pillarOutSM[pillar_idx_inBlock][point_idx][0] = pillarSM[pillar_idx_inBlock][point_idx].x;
    pillarOutSM[pillar_idx_inBlock][point_idx][1] = pillarSM[pillar_idx_inBlock][point_idx].y;
    pillarOutSM[pillar_idx_inBlock][point_idx][2] = pillarSM[pillar_idx_inBlock][point_idx].z;
    pillarOutSM[pillar_idx_inBlock][point_idx][3] = pillarSM[pillar_idx_inBlock][point_idx].w;
    pillarOutSM[pillar_idx_inBlock][point_idx][4] = mean.x;
    pillarOutSM[pillar_idx_inBlock][point_idx][5] = mean.y;
    pillarOutSM[pillar_idx_inBlock][point_idx][6] = mean.z;
    pillarOutSM[pillar_idx_inBlock][point_idx][7] = center.x;
    pillarOutSM[pillar_idx_inBlock][point_idx][8] = center.y;
    pillarOutSM[pillar_idx_inBlock][point_idx][9] = center.z;

  } else {
    pillarOutSM[pillar_idx_inBlock][point_idx][0] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][1] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][2] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][3] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][4] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][5] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][6] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][7] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][8] = 0;
    pillarOutSM[pillar_idx_inBlock][point_idx][9] = 0;
  }
  __syncthreads();
  for(int i = 0; i < voxel_features_size; i ++) {
    int outputSMId = pillar_idx_inBlock*64*11 + point_idx * 11 + i;
    int outputId = pillar_idx*max_points*voxel_features_size + point_idx * voxel_features_size + i;
    features[outputId] = ((float*)pillarOutSM)[outputSMId] ;
  }

}

int generateFeatures_launch(
    int batch_size,
    int dense_pillar_num,
    float* voxel_features,
    unsigned int* voxel_num_points,
    unsigned int* coords,
    unsigned int *params,
    float voxel_x, float voxel_y, float voxel_z,
    float range_min_x, float range_min_y, float range_min_z,
    unsigned int voxel_features_size, unsigned int max_points,
    unsigned int max_voxels, unsigned int num_point_values,
    float* features,
    hipStream_t stream)
{
    unsigned int warp_size = max_points;
    dim3 blocks((batch_size * max_voxels + 3) / 4);
    dim3 threads(4*warp_size);
    if (num_point_values == 4) {
      generateFeatures_kernel_4x<<<blocks, threads, 0, stream>>>
      (batch_size,
      dense_pillar_num,
      voxel_features,
      voxel_num_points,
      coords,
      params,
      voxel_x, voxel_y, voxel_z,
      range_min_x, range_min_y, range_min_z,
      voxel_features_size, max_points,
      max_voxels, 
      features);
    }
    else {
      generateFeatures_kernel<<<blocks, threads, 0, stream>>>
      (batch_size,
      dense_pillar_num,
      voxel_features,
      voxel_num_points,
      coords,
      params,
      voxel_x, voxel_y, voxel_z,
      range_min_x, range_min_y, range_min_z,
      voxel_features_size, max_points,
      max_voxels, 
      features);
    }
    auto err = hipGetLastError();
    if (hipSuccess != err) {
        fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
        exit(-1);
    }
    return err;
}
} // namespace plugin
} // namespace nvinfer1

	.text
	.file	"voxelGeneratorKernels.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_ # -- Begin function _ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.type	_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_,@function
_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_: # @_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$264, %rsp                      # imm = 0x108
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsp, %rax
	movl	%edi, (%rax)
	leaq	72(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	64(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	44(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	36(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	32(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	28(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	24(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	20(%rsp), %r13
	movss	%xmm6, (%r13)
	leaq	16(%rsp), %rbp
	movss	%xmm7, (%rbp)
	leaq	12(%rsp), %rax
	movl	%ecx, (%rax)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rsp, %r9
	movq	%r9, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%r14, 48(%rbx)
	movq	%r15, 56(%rbx)
	movq	%r12, 64(%rbx)
	movq	%r13, 72(%rbx)
	movq	%rbp, 80(%rbx)
	leaq	320(%rsp), %rdx
	movq	%rdx, 88(%rbx)
	movq	%rax, 96(%rbx)
	movq	%rcx, 104(%rbx)
	movq	%r8, 112(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$280, %rsp                      # imm = 0x118
	.cfi_adjust_cfa_offset -280
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, .Lfunc_end0-_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_ # -- Begin function _ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.type	_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_,@function
_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_: # @_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, .Lfunc_end1-_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t # -- Begin function _ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t
	.type	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t,@function
_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t: # @_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movss	%xmm7, 60(%rsp)                 # 4-byte Spill
	movss	%xmm6, 56(%rsp)                 # 4-byte Spill
	movss	%xmm5, 52(%rsp)                 # 4-byte Spill
	movss	%xmm4, 48(%rsp)                 # 4-byte Spill
	movss	%xmm3, 44(%rsp)                 # 4-byte Spill
	movss	%xmm2, 40(%rsp)                 # 4-byte Spill
	movss	%xmm1, 36(%rsp)                 # 4-byte Spill
	movss	%xmm0, 32(%rsp)                 # 4-byte Spill
	movq	%rcx, %r14
	movq	%rdx, %r15
	movl	%esi, %r12d
                                        # kill: def $edi killed $edi def $rdi
	movq	152(%rsp), %r9
	imull	%esi, %edi
	leal	255(%rdi), %eax
	addl	$510, %edi                      # imm = 0x1FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$8, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	144(%rsp), %rax
	movq	136(%rsp), %rcx
	movl	128(%rsp), %edx
	movl	120(%rsp), %r9d
	movss	112(%rsp), %xmm0                # xmm0 = mem[0],zero,zero,zero
	movq	%rax, 24(%rsp)
	movq	%rcx, 16(%rsp)
	movl	%edx, 8(%rsp)
	movss	%xmm0, (%rsp)
	movl	%r12d, %edi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movss	32(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	36(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	40(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	44(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	48(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	52(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	movss	56(%rsp), %xmm6                 # 4-byte Reload
                                        # xmm6 = mem[0],zero,zero,zero
	movss	60(%rsp), %xmm7                 # 4-byte Reload
                                        # xmm7 = mem[0],zero,zero,zero
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	callq	_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
.LBB2_2:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t, .Lfunc_end2-_ZN8nvinfer16plugin21generateVoxels_launchEiiPfPjfffffffffiiiiS2_S1_P12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t # -- Begin function _ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t
	.type	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t,@function
_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t: # @_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movq	%rdx, %r15
	movq	%rsi, %r12
	movl	%edi, %r13d
	movq	112(%rsp), %r9
	movl	%ecx, %edi
	imull	%r13d, %edi
	imull	%r8d, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_ # TAILCALL
.Lfunc_end3:
	.size	_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t, .Lfunc_end3-_ZN8nvinfer16plugin27generateBaseFeatures_launchEiPjPfiiS1_iiiS2_S1_S1_P12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_ # -- Begin function _ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.type	_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_,@function
_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_: # @_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	20(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	4(%rsp), %r15
	movss	%xmm4, (%r15)
	movq	%rsp, %r12
	movss	%xmm5, (%r12)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	movq	%r15, 80(%rbx)
	movq	%r12, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, .Lfunc_end4-_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_ # -- Begin function _ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.type	_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_,@function
_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_: # @_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	20(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	4(%rsp), %r15
	movss	%xmm4, (%r15)
	movq	%rsp, %r12
	movss	%xmm5, (%r12)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	movq	%r15, 80(%rbx)
	movq	%r12, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, .Lfunc_end5-_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.cfi_endproc
                                        # -- End function
	.globl	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t # -- Begin function _ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t
	.type	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t,@function
_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t: # @_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm5, 28(%rsp)                 # 4-byte Spill
	movss	%xmm4, 24(%rsp)                 # 4-byte Spill
	movss	%xmm3, 20(%rsp)                 # 4-byte Spill
	movss	%xmm2, 16(%rsp)                 # 4-byte Spill
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	%r9, 32(%rsp)                   # 8-byte Spill
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movl	%esi, %ebp
	movl	%edi, %r13d
	movl	112(%rsp), %edi
	movl	104(%rsp), %eax
	movl	120(%rsp), %ebx
	movq	136(%rsp), %r9
                                        # kill: def $edi killed $edi killed $rdi def $rdi
	imull	%r13d, %edi
	addl	$3, %edi
	shrl	$2, %edi
	btsq	$32, %rdi
	leal	(,%rax,4), %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	cmpl	$4, %ebx
	jne	.LBB6_3
# %bb.1:
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.2:
	movl	%r13d, %edi
	movl	%ebp, %esi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	32(%rsp), %r9                   # 8-byte Reload
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	28(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	jmp	.LBB6_5
.LBB6_3:
	.cfi_def_cfa_offset 96
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.4:
	movl	%r13d, %edi
	movl	%ebp, %esi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	32(%rsp), %r9                   # 8-byte Reload
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	28(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
.LBB6_5:
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_6:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB6_8
# %bb.7:
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_8:
	.cfi_def_cfa_offset 96
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end6:
	.size	_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t, .Lfunc_end6-_ZN8nvinfer16plugin23generateFeatures_launchEiiPfPjS2_S2_ffffffjjjjS1_P12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_,@object # @_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.section	.rodata,"a",@progbits
	.globl	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.p2align	3, 0x0
_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_:
	.quad	_ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.size	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, 8

	.type	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_,@object # @_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.globl	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.p2align	3, 0x0
_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_:
	.quad	_ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.size	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, 8

	.type	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_,@object # @_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.globl	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.p2align	3, 0x0
_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_:
	.quad	_ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.size	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, 8

	.type	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_,@object # @_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.globl	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.p2align	3, 0x0
_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_:
	.quad	_ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.size	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA kernel failed : %s\n"
	.size	.L.str, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_"
	.size	.L__unnamed_1, 68

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_"
	.size	.L__unnamed_2, 72

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_"
	.size	.L__unnamed_3, 70

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_"
	.size	.L__unnamed_4, 73

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN8nvinfer16plugin36__device_stub__generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.addrsig_sym _ZN8nvinfer16plugin42__device_stub__generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.addrsig_sym _ZN8nvinfer16plugin38__device_stub__generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.addrsig_sym _ZN8nvinfer16plugin41__device_stub__generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.addrsig_sym _ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.addrsig_sym _ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.addrsig_sym _ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_ ; -- Begin function _ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.globl	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
	.p2align	8
	.type	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_,@function
_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_: ; @_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x6c
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s2, s8
	s_and_b32 s3, s3, 0xffff
	s_xor_b32 s9, s9, s8
	v_cvt_f32_u32_e32 v1, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_sub_i32 s3, 0, s9
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s9
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s9, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	v_mul_lo_u32 v2, v4, s2
	s_mov_b32 s2, exec_lo
	v_sub_nc_u32_e32 v2, v1, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v2, v0
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_load_b128 s[16:19], s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v0, v1, s18
	s_cmp_eq_u32 s18, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	s_cselect_b32 s5, -1, 0
	s_cmp_lg_u32 s18, 5
	global_load_b128 v[0:3], v[5:6], off
	s_cbranch_scc1 .LBB0_3
; %bb.2:
	global_load_b32 v7, v[5:6], off offset:16
	s_branch .LBB0_4
.LBB0_3:
                                        ; implicit-def: $vgpr7
.LBB0_4:
	s_load_b256 s[8:15], s[0:1], 0x18
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, s8, v0
	v_cmp_ngt_f32_e64 s2, s10, v1
	v_cmp_nle_f32_e64 s3, s9, v0
	v_cmp_nle_f32_e64 s4, s11, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	s_and_b32 s2, vcc_lo, s2
	v_cmp_ngt_f32_e32 vcc_lo, s12, v2
	s_and_b32 s3, s2, s3
	v_cmp_nle_f32_e64 s2, s13, v2
	s_and_b32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_8
; %bb.5:
	v_dual_subrev_f32 v5, s8, v0 :: v_dual_subrev_f32 v6, s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v8, null, s14, s14, v5
	v_div_scale_f32 v9, null, s15, s15, v6
	v_div_scale_f32 v14, vcc_lo, v5, s14, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v10, v8
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v10, 1.0
	v_fma_f32 v13, -v9, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v10, v12, v10 :: v_dual_fmac_f32 v11, v13, v11
	v_div_scale_f32 v12, s2, v6, s15, v6
	v_mul_f32_e32 v13, v14, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v12, v11
	v_fma_f32 v16, -v8, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v9, v15, v12
	v_fmac_f32_e32 v13, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v17, v11
	v_fma_f32 v8, -v8, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v9, v15, v12
	v_div_fmas_f32 v8, v8, v10, v13
	s_mov_b32 vcc_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v9, v11, v15
	v_div_fixup_f32 v8, v8, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v6, v9, s15, v6
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v5, v6
	v_floor_f32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, s16, v[5:6]
	v_cvt_i32_f32_e32 v6, v6
	v_mad_u64_u32 v[4:5], null, v8, s17, v[6:7]
	v_dual_mov_b32 v6, 1 :: v_dual_mov_b32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s0, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_atomic_add_u32 v6, v[8:9], v6, off glc
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s19, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.6:
	v_mad_u64_u32 v[8:9], null, v4, s19, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v8, s18
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_clause 0x3
	global_atomic_swap_b32 v[4:5], v0, off
	global_atomic_swap_b32 v[4:5], v1, off offset:4
	global_atomic_swap_b32 v[4:5], v2, off offset:8
	global_atomic_swap_b32 v[4:5], v3, off offset:12
	s_cbranch_vccnz .LBB0_8
; %bb.7:
	global_atomic_swap_b32 v[4:5], v7, off offset:16
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_, .Lfunc_end0-_ZN8nvinfer16plugin21generateVoxels_kernelEiPfPjfffffffffiiiiS2_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 22
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_ ; -- Begin function _ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.globl	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
	.p2align	8
	.type	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_,@function
_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_: ; @_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x5c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s16, s3, s2
	s_and_b32 s4, s4, 0xffff
	s_ashr_i32 s5, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s16, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s6
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_sub_i32 s4, 0, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s4, v3
	s_load_b32 s4, s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v5, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s6
	v_sub_nc_u32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_add_nc_u32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v6, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v6
	v_sub_nc_u32_e32 v3, v0, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v3
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_13
; %bb.1:
	s_load_b128 s[12:15], s[0:1], 0x8
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	global_load_b32 v0, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_13
; %bb.2:
	s_load_b64 s[4:5], s[0:1], 0x20
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[3:4]
	v_mov_b32_e32 v4, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_ashr_i32 s4, s3, 31
	s_add_i32 s5, s3, s4
	global_atomic_add_u32 v7, v[6:7], v4, off glc
	s_xor_b32 s5, s5, s4
	v_xor_b32_e32 v2, s4, v2
	v_cvt_f32_u32_e32 v4, s5
	s_sub_i32 s6, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v6, s6, v4
	s_ashr_i32 s6, s2, 31
	s_add_i32 s2, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s6
	v_cvt_f32_u32_e32 v8, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v4, v6
	s_sub_i32 s4, 0, s2
	v_rcp_iflag_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v6
	v_mul_hi_u32 v4, v5, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x4f7ffffe, v8
	v_mul_lo_u32 v6, v4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v6
	v_add_nc_u32_e32 v6, 1, v4
	v_subrev_nc_u32_e32 v9, s5, v5
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v9
	v_add_nc_u32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	v_cvt_u32_f32_e32 v5, v8
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, s4, v5
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x28
	s_load_b64 s[0:1], s[0:1], 0x48
	v_xor_b32_e32 v4, v4, v2
	v_sub_nc_u32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v5, v6
	v_ashrrev_i32_e32 v8, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_add_nc_u32_e32 v6, v2, v8
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v6, v8
	v_mov_b32_e32 v6, 0
	v_mul_hi_u32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, s2
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s2, v4
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	v_cndmask_b32_e32 v9, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, s16, v3, v[7:8]
	v_subrev_nc_u32_e32 v5, s2, v9
	v_mad_u64_u32 v[10:11], null, v3, s4, v[7:8]
	v_mov_b32_e32 v7, v6
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v9, v5, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_mul_lo_u32 v9, v2, s3
	v_ashrrev_i32_e32 v11, 31, v10
	v_xor_b32_e32 v12, v3, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_min_u32_e32 v5, s5, v0
	v_lshlrev_b64 v[10:11], 4, v[10:11]
	v_sub_nc_u32_e32 v9, v1, v9
	v_sub_nc_u32_e32 v8, v12, v8
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	global_store_b32 v[2:3], v5, off
	global_store_b128 v[10:11], v[6:9], off
	s_cbranch_scc1 .LBB1_13
; %bb.3:                                ; %.lr.ph
	v_mul_lo_u32 v4, v4, s5
	v_mul_lo_u32 v6, v1, s5
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v4, 2, v4
	v_lshl_add_u32 v2, v6, 2, v6
.LBB1_4:                                ; %NodeBlock
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	s_cmp_lt_i32 s6, 5
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB1_9
; %bb.5:                                ; %LeafBlock112
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_cmp_eq_u32 s6, 5
	s_cbranch_scc0 .LBB1_8
; %bb.6:                                ; %.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s14, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v10, vcc_lo
.LBB1_7:                                ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, s0
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v11, v[9:10], off
	v_add_co_u32 v9, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v3, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 20
	s_waitcnt vmcnt(0)
	global_store_b32 v[9:10], v11, off
	s_cbranch_scc1 .LBB1_7
.LBB1_8:                                ; %Flow114
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_9:                                ; %Flow116
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_12
; %bb.10:                               ; %LeafBlock
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_cmp_eq_u32 s6, 4
	s_cbranch_scc0 .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_4 Depth=1
	v_add_nc_u32_e32 v7, s3, v6
	v_add_nc_u32_e32 v11, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 4, v[7:8]
	v_lshlrev_b64 v[11:12], 4, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	global_load_b128 v[7:10], v[7:8], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[11:12], v[7:10], off
.LBB1_12:                               ; %.loopexit
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_add_i32 s3, s3, 1
	v_add_nc_u32_e32 v0, 5, v0
	v_cmp_eq_u32_e32 vcc_lo, s3, v5
	v_add_nc_u32_e32 v2, 5, v2
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_4
.LBB1_13:                               ; %.loopexit67
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_, .Lfunc_end1-_ZN8nvinfer16plugin27generateBaseFeatures_kernelEiPjPfiiS1_iiiS2_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1180
; NumSgprs: 19
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_ ; -- Begin function _ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.globl	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
	.p2align	8
	.type	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_,@function
_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_: ; @_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x28
	s_load_b32 s20, s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s2, 0, s11
	v_cvt_f32_u32_e32 v3, s20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v1
	s_sub_i32 s2, 0, s20
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_rcp_iflag_f32_e32 v2, v3
	v_mul_hi_u32 v1, v0, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mul_lo_u32 v3, v1, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v5, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	s_load_b64 s[2:3], s[0:1], 0x0
	v_subrev_nc_u32_e32 v6, s11, v3
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_add_nc_u32_e32 v4, 1, v1
	v_mul_hi_u32 v5, v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v1, v4, vcc_lo
	v_add_nc_u32_e32 v1, v2, v5
	v_lshl_add_u32 v10, s15, 2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v10, v1
	v_mul_lo_u32 v2, v1, s20
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v10, v2
	v_subrev_nc_u32_e32 v4, s20, v2
	v_cmp_le_u32_e32 vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s20, v2
	v_cndmask_b32_e32 v3, v1, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_22
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x8
	v_ashrrev_i32_e32 v4, 31, v3
	v_mul_lo_u32 v5, v3, s20
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	v_mul_lo_u32 v4, v9, s11
	v_sub_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_or_b32_e32 v7, v5, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v2, vcc_lo
	global_load_b32 v6, v[1:2], off
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB2_3
; %bb.2:
	s_waitcnt vmcnt(0)
	v_min_u32_e32 v7, s20, v6
	global_store_b32 v[1:2], v7, off
.LBB2_3:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, v6, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_22
; %bb.4:
	v_mad_u64_u32 v[1:2], null, v3, s3, v[5:6]
	v_lshlrev_b32_e32 v11, 4, v9
	v_lshlrev_b32_e32 v3, 2, v9
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB2_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[5:6], 4, v[1:2]
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v8, vcc_lo
	global_load_b128 v[5:8], v[5:6], off
	global_load_b32 v2, v[12:13], off
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v13, v12
	v_mov_b32_e32 v14, v12
	v_mov_b32_e32 v15, v12
	s_waitcnt vmcnt(1)
	ds_store_b128 v11, v[5:8] offset:16448
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v2 offset:16512
	ds_store_b128 v11, v[12:15] offset:16384
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_mul_i32 s2, s11, 20
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_sub_i32 s2, 0x500, s2
	v_mul_u32_u24_e32 v6, 20, v0
	v_mul_lo_u32 v2, v9, s2
	s_movk_i32 s2, 0xffec
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, v5, 2, v5
	v_add3_u32 v13, v2, v6, 0x2c00
	v_mov_b32_e32 v2, 0
.LBB2_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	v_add_nc_u32_e32 v6, s2, v13
	s_add_i32 s2, s2, 4
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5 offset:20
	s_cbranch_scc0 .LBB2_7
; %bb.8:
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v5, v3 offset:16512
	v_mul_lo_u32 v1, v4, 20
	v_add_nc_u32_e32 v2, 0x4080, v3
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v4, v5
	s_cbranch_execz .LBB2_10
; %bb.9:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v3, 0x500, v9, v1
	v_add_nc_u32_e32 v5, 0x2c00, v3
	ds_load_2addr_b32 v[5:6], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	ds_add_f32 v11, v5 offset:16384
	ds_add_f32 v11, v6 offset:16388
	ds_load_b32 v3, v3 offset:11272
	s_waitcnt lgkmcnt(0)
	ds_add_f32 v11, v3 offset:16392
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v14, v2
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_ge_i32_e64 v4, v14
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_14
; %bb.11:                               ; %.preheader155
	s_cmp_eq_u32 s10, 0
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr1
	s_cbranch_scc1 .LBB2_14
; %bb.12:                               ; %.lr.ph.preheader
	s_mul_i32 s3, s11, 44
	v_mov_b32_e32 v3, 0
	s_sub_i32 s3, 0xb00, s3
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v9, s3
	s_mov_b32 s3, s10
	v_mad_u32_u24 v2, v0, 44, v1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr0
.LBB2_13:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_store_b32 v2, v3
	v_add_nc_u32_e32 v2, 4, v2
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB2_13
.LBB2_14:                               ; %Flow239
	s_and_not1_saveexec_b32 s12, s2
	s_cbranch_execz .LBB2_19
; %bb.15:                               ; %.preheader.preheader
	v_mad_u32_u24 v12, 0x500, v9, v1
	v_add_nc_u32_e32 v5, 0x4044, v11
	s_mul_i32 s2, s11, 44
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_sub_i32 s2, 0xb00, s2
	v_add_nc_u32_e32 v7, 0x2c00, v12
	v_mul_lo_u32 v15, v9, s2
	s_mov_b32 s2, 0
	ds_load_b96 v[1:3], v11 offset:16384
	ds_load_2addr_b32 v[5:6], v5 offset1:1
	ds_load_2addr_b32 v[7:8], v7 offset1:1
	ds_load_b32 v12, v12 offset:11272
	ds_load_b32 v11, v11 offset:16460
	v_mad_u32_u24 v0, v0, 44, v15
.LBB2_16:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v15, s2, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v16, s2, v0
	s_add_i32 s2, s2, 4
	s_cmp_eq_u32 s2, 20
	ds_load_b32 v15, v15
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v16, v15
	s_cbranch_scc0 .LBB2_16
; %bb.17:
	v_cvt_f32_i32_e32 v13, v14
	v_cvt_f32_i32_e32 v6, v6
	v_cvt_f32_i32_e32 v11, v11
	s_cmp_gt_u32 s10, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v14, null, v13, v13, v1
	v_div_scale_f32 v15, null, v13, v13, v2
	v_div_scale_f32 v16, null, v13, v13, v3
	v_rcp_f32_e32 v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v18, v15
	v_div_scale_f32 v20, vcc_lo, v1, v13, v1
	v_rcp_f32_e32 v19, v16
	v_div_scale_f32 v21, s2, v2, v13, v2
	v_div_scale_f32 v24, s3, v3, v13, v3
	v_mul_f32_e32 v6, s5, v6
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_fma_f32 v0, -v14, v17, 1.0
	v_fma_f32 v22, -v15, v18, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v16, v19, 1.0
	v_dual_fmac_f32 v17, v0, v17 :: v_dual_fmac_f32 v18, v22, v18
	v_mul_lo_u32 v0, v4, 44
	v_fmac_f32_e64 v6, s5, 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v19, v23, v19 :: v_dual_mul_f32 v22, v20, v17
	v_dual_mul_f32 v11, s4, v11 :: v_dual_add_f32 v6, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v25, v24, v19
	v_fma_f32 v26, -v14, v22, v20
	v_mul_f32_e32 v23, v21, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e64 v11, s4, 0.5
	v_sub_f32_e32 v6, v8, v6
	v_fma_f32 v28, -v16, v25, v24
	v_fmac_f32_e32 v22, v26, v17
	v_fma_f32 v27, -v15, v23, v21
	v_mad_u32_u24 v26, 0xb00, v9, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v25, v28, v19
	v_fma_f32 v14, -v14, v22, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v23, v27, v18
	v_fma_f32 v16, -v16, v25, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v14, v14, v17, v22
	v_fma_f32 v15, -v15, v23, v21
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v14, v13, v1
	v_div_fmas_f32 v15, v15, v18, v23
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v16, v16, v19, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v7, v1
	v_div_fixup_f32 v2, v15, v13, v2
	v_add_f32_e32 v11, s7, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v16, v13, v3
	v_dual_sub_f32 v2, v8, v2 :: v_dual_sub_f32 v11, v7, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_f32_e32 v3, v12, v3
	ds_store_2addr_b32 v26, v1, v2 offset0:5 offset1:6
	ds_store_2addr_b32 v26, v3, v11 offset0:7 offset1:8
	ds_store_b32 v26, v6 offset:36
	s_cbranch_scc0 .LBB2_19
; %bb.18:
	v_cvt_f32_i32_e32 v1, v5
	v_mul_u32_u24_e32 v2, 0xb00, v9
	s_lshl_b32 s2, s11, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, s6, v1
	v_add3_u32 v0, v2, v0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e64 v1, s6, 0.5
	v_add_f32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v1, v12, v1
	ds_store_b32 v0, v1 offset:20
.LBB2_19:                               ; %Flow240
	s_or_b32 exec_lo, exec_lo, s12
	s_cmp_eq_u32 s10, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_22
; %bb.20:                               ; %.lr.ph161
	s_load_b64 s[0:1], s[0:1], 0x50
	v_mad_u64_u32 v[0:1], null, v10, s11, v[4:5]
	v_mul_lo_u32 v1, v4, 44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s10
	v_mad_u32_u24 v2, 0xb00, v9, v1
.LBB2_21:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, 4, v2
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s10, 0
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, 1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc1 .LBB2_21
.LBB2_22:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
		.amdhsa_group_segment_fixed_size 16528
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 88
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_, .Lfunc_end2-_ZN8nvinfer16plugin23generateFeatures_kernelEiiPfPjS2_S2_ffffffjjjS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1764
; NumSgprs: 23
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16528 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_ ; -- Begin function _ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.globl	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
	.p2align	8
	.type	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_,@function
_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_: ; @_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x28
	s_load_b32 s20, s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s2, 0, s11
	v_cvt_f32_u32_e32 v3, s20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s2, v1
	s_sub_i32 s2, 0, s20
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_rcp_iflag_f32_e32 v2, v3
	v_mul_hi_u32 v1, v0, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mul_lo_u32 v3, v1, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v5, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	s_load_b64 s[2:3], s[0:1], 0x0
	v_subrev_nc_u32_e32 v6, s11, v3
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_add_nc_u32_e32 v4, 1, v1
	v_mul_hi_u32 v5, v2, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v1, v4, vcc_lo
	v_add_nc_u32_e32 v1, v2, v5
	v_lshl_add_u32 v4, s15, 2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v4, v1
	v_mul_lo_u32 v2, v1, s20
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v4, v2
	v_subrev_nc_u32_e32 v5, s20, v2
	v_cmp_le_u32_e32 vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s20, v2
	v_cndmask_b32_e32 v2, v1, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_13
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x8
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_mul_lo_u32 v3, v9, s11
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v6, vcc_lo
	v_mul_lo_u32 v5, v2, s20
	v_sub_nc_u32_e32 v6, v0, v3
	global_load_b32 v1, v[7:8], off
	v_sub_nc_u32_e32 v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v3, v6
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_3
; %bb.2:
	s_waitcnt vmcnt(0)
	v_min_u32_e32 v0, s20, v1
	global_store_b32 v[7:8], v0, off
.LBB3_3:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, v1, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_13
; %bb.4:
	v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
	v_lshlrev_b32_e32 v2, 2, v9
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB3_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_dual_mov_b32 v14, 0 :: v_dual_lshlrev_b32 v3, 4, v9
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 4, v[4:5]
	v_mov_b32_e32 v15, v14
	v_mov_b32_e32 v16, v14
	v_mov_b32_e32 v17, v14
	v_add_co_u32 v7, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	v_add_co_u32 v10, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v11, vcc_lo
	global_load_b32 v1, v[7:8], off
	global_load_b128 v[10:13], v[10:11], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v2, v1 offset:15488
	s_waitcnt vmcnt(0)
	ds_store_b128 v3, v[10:13] offset:15424
	ds_store_b128 v3, v[14:17] offset:15360
.LBB3_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v0, s11, v[6:7]
	v_mov_b32_e32 v8, 0
	s_mov_b32 s2, exec_lo
	v_lshlrev_b64 v[0:1], 4, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b128 v[10:13], v[0:1], off
	v_add_nc_u32_e32 v1, 0x3c80, v2
	v_lshlrev_b32_e32 v0, 4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v9, 10, v0
	s_waitcnt vmcnt(0)
	ds_store_b128 v0, v[10:13] offset:11264
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v2 offset:15488
	v_add_nc_u32_e32 v0, 0x2c00, v0
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v6, v3
	s_cbranch_execz .LBB3_8
; %bb.7:
	ds_load_b96 v[10:12], v0
	v_lshlrev_b32_e32 v2, 4, v9
	s_waitcnt lgkmcnt(0)
	ds_add_f32 v2, v10 offset:15360
	ds_add_f32 v2, v11 offset:15364
	ds_add_f32 v2, v12 offset:15368
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v5, v1
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, 0
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v6, v5
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_lshlrev_b32_e32 v1, 4, v9
	v_cvt_f32_i32_e32 v5, v5
	ds_load_b96 v[10:12], v1 offset:15360
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v15, null, v5, v5, v11
	v_div_scale_f32 v16, null, v5, v5, v10
	v_div_scale_f32 v14, null, v5, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v18, v15
	v_rcp_f32_e32 v19, v16
	v_div_scale_f32 v21, s2, v11, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v17, v14
	v_div_scale_f32 v20, vcc_lo, v12, v5, v12
	v_div_scale_f32 v22, s3, v10, v5, v10
	v_fma_f32 v24, -v15, v18, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v16, v19, 1.0
	v_fma_f32 v23, -v14, v17, 1.0
	v_fmac_f32_e32 v18, v24, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v19, v25, v19 :: v_dual_add_nc_u32 v2, 0x3c44, v1
	ds_load_2addr_b32 v[7:8], v2 offset1:1
	ds_load_b32 v13, v1 offset:15436
	ds_load_b128 v[0:3], v0
	v_mul_f32_e32 v24, v21, v18
	v_fma_f32 v27, -v15, v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v27, v18
	v_fma_f32 v15, -v15, v24, v21
	s_waitcnt lgkmcnt(2)
	v_cvt_f32_i32_e32 v7, v7
	v_cvt_f32_i32_e32 v8, v8
	v_fmac_f32_e32 v17, v23, v17
	s_waitcnt lgkmcnt(1)
	v_cvt_f32_i32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v7, s6, v7 :: v_dual_mul_f32 v8, s5, v8
	v_mul_f32_e32 v23, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e64 v7, s6, 0.5
	v_fmac_f32_e64 v8, s5, 0.5
	v_mul_f32_e32 v25, v22, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v14, v23, v20
	v_add_f32_e32 v8, s8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v16, v25, v22
	v_fmac_f32_e32 v23, v26, v17
	v_mul_f32_e32 v13, s4, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, v28, v19
	v_fma_f32 v14, -v14, v23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, -v16, v25, v22
	v_div_fmas_f32 v14, v14, v17, v23
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v15, v15, v18, v24
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v14, v14, v5, v12
	v_div_fmas_f32 v16, v16, v19, v25
	v_div_fixup_f32 v15, v15, v5, v11
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v2, v14
	v_div_fixup_f32 v5, v16, v5, v10
	v_sub_f32_e32 v10, v1, v8
	v_fmac_f32_e64 v13, s4, 0.5
	v_mov_b32_e32 v8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v1, v15 :: v_dual_add_f32 v13, s7, v13
	v_dual_add_f32 v7, s9, v7 :: v_dual_sub_f32 v12, v0, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v7, v2, v7
	v_sub_f32_e32 v13, v0, v5
.LBB3_10:
	s_or_b32 exec_lo, exec_lo, s12
	v_mul_lo_u32 v0, v6, 44
	s_cmp_eq_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v5, 0xb00, v9, v0
	ds_store_2addr_b32 v5, v8, v1 offset1:1
	ds_store_2addr_b32 v5, v2, v3 offset0:2 offset1:3
	ds_store_2addr_b32 v5, v13, v14 offset0:4 offset1:5
	ds_store_2addr_b32 v5, v11, v12 offset0:6 offset1:7
	ds_store_2addr_b32 v5, v10, v7 offset0:8 offset1:9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_13
; %bb.11:                               ; %.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x50
	v_mad_u64_u32 v[0:1], null, v4, s11, v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s10
.LBB3_12:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v3, v5
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s10, 0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v0, 1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v3, off
	s_cbranch_scc1 .LBB3_12
.LBB3_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
		.amdhsa_group_segment_fixed_size 15504
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 88
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_, .Lfunc_end3-_ZN8nvinfer16plugin26generateFeatures_kernel_4xEiiPfPjS2_S2_ffffffjjjS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1496
; NumSgprs: 23
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 15504 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
