#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>

#define PREFIX_LENGTH 4
#define MAX_PASSWORD_LENGTH 6
#define ALPHABET_SIZE 26


/* F, G and H are basic MD5 functions: selection, majority, parity */
#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
#define H(x, y, z) ((x) ^ (y) ^ (z))
#define I(x, y, z) ((y) ^ ((x) | (~z)))

/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))

/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
/* Rotation is separate from addition to prevent recomputation */
#define FF(a, b, c, d, x, s, ac) \
  {(a) += F ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define GG(a, b, c, d, x, s, ac) \
  {(a) += G ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define HH(a, b, c, d, x, s, ac) \
  {(a) += H ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define II(a, b, c, d, x, s, ac) \
  {(a) += I ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }

__host__ __device__ void md5_vfy(unsigned char* data, unsigned int length, unsigned int *a1, unsigned int *b1, unsigned int *c1, unsigned int *d1)
{

	const unsigned int a0 = 0x67452301;
	const unsigned int b0 = 0xEFCDAB89;
	const unsigned int c0 = 0x98BADCFE;
	const unsigned int d0 = 0x10325476;

	unsigned int a = 0;
	unsigned int b = 0;
	unsigned int c = 0;
	unsigned int d = 0;

	unsigned int vals[14] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0 };

	int i = 0;

	for (i = 0; i < length; i++)
	{
		vals[i / 4] |= data[i] << ((i % 4) * 8);
	}
	vals[i / 4] |= 0x80 << ((i % 4) * 8);

	unsigned int bitlen = length * 8;

#define in0  (vals[0])//x
#define in1  (vals[1])//y
#define in2  (vals[2])//z
#define in3  (vals[3])
#define in4  (vals[4])
#define in5  (vals[5])
#define in6  (vals[6])
#define in7  (vals[7])
#define in8  (vals[8])
#define in9  (vals[9])
#define in10 (vals[10])
#define in11 (vals[11])
#define in12 (vals[12])
#define in13 (vals[13])
#define in14 (bitlen) //w = bit length
#define in15 (0)

	//Initialize hash value for this chunk:
	a = a0;
	b = b0;
	c = c0;
	d = d0;


	/* Round 1 */
#define S11 7
#define S12 12
#define S13 17
#define S14 22
	FF(a, b, c, d, in0, S11, 3614090360); /* 1 */
	FF(d, a, b, c, in1, S12, 3905402710); /* 2 */
	FF(c, d, a, b, in2, S13, 606105819); /* 3 */
	FF(b, c, d, a, in3, S14, 3250441966); /* 4 */
	FF(a, b, c, d, in4, S11, 4118548399); /* 5 */
	FF(d, a, b, c, in5, S12, 1200080426); /* 6 */
	FF(c, d, a, b, in6, S13, 2821735955); /* 7 */
	FF(b, c, d, a, in7, S14, 4249261313); /* 8 */
	FF(a, b, c, d, in8, S11, 1770035416); /* 9 */
	FF(d, a, b, c, in9, S12, 2336552879); /* 10 */
	FF(c, d, a, b, in10, S13, 4294925233); /* 11 */
	FF(b, c, d, a, in11, S14, 2304563134); /* 12 */
	FF(a, b, c, d, in12, S11, 1804603682); /* 13 */
	FF(d, a, b, c, in13, S12, 4254626195); /* 14 */
	FF(c, d, a, b, in14, S13, 2792965006); /* 15 */
	FF(b, c, d, a, in15, S14, 1236535329); /* 16 */

										   /* Round 2 */
#define S21 5
#define S22 9
#define S23 14
#define S24 20
	GG(a, b, c, d, in1, S21, 4129170786); /* 17 */
	GG(d, a, b, c, in6, S22, 3225465664); /* 18 */
	GG(c, d, a, b, in11, S23, 643717713); /* 19 */
	GG(b, c, d, a, in0, S24, 3921069994); /* 20 */
	GG(a, b, c, d, in5, S21, 3593408605); /* 21 */
	GG(d, a, b, c, in10, S22, 38016083); /* 22 */
	GG(c, d, a, b, in15, S23, 3634488961); /* 23 */
	GG(b, c, d, a, in4, S24, 3889429448); /* 24 */
	GG(a, b, c, d, in9, S21, 568446438); /* 25 */
	GG(d, a, b, c, in14, S22, 3275163606); /* 26 */
	GG(c, d, a, b, in3, S23, 4107603335); /* 27 */
	GG(b, c, d, a, in8, S24, 1163531501); /* 28 */
	GG(a, b, c, d, in13, S21, 2850285829); /* 29 */
	GG(d, a, b, c, in2, S22, 4243563512); /* 30 */
	GG(c, d, a, b, in7, S23, 1735328473); /* 31 */
	GG(b, c, d, a, in12, S24, 2368359562); /* 32 */

										   /* Round 3 */
#define S31 4
#define S32 11
#define S33 16
#define S34 23
	HH(a, b, c, d, in5, S31, 4294588738); /* 33 */
	HH(d, a, b, c, in8, S32, 2272392833); /* 34 */
	HH(c, d, a, b, in11, S33, 1839030562); /* 35 */
	HH(b, c, d, a, in14, S34, 4259657740); /* 36 */
	HH(a, b, c, d, in1, S31, 2763975236); /* 37 */
	HH(d, a, b, c, in4, S32, 1272893353); /* 38 */
	HH(c, d, a, b, in7, S33, 4139469664); /* 39 */
	HH(b, c, d, a, in10, S34, 3200236656); /* 40 */
	HH(a, b, c, d, in13, S31, 681279174); /* 41 */
	HH(d, a, b, c, in0, S32, 3936430074); /* 42 */
	HH(c, d, a, b, in3, S33, 3572445317); /* 43 */
	HH(b, c, d, a, in6, S34, 76029189); /* 44 */
	HH(a, b, c, d, in9, S31, 3654602809); /* 45 */
	HH(d, a, b, c, in12, S32, 3873151461); /* 46 */
	HH(c, d, a, b, in15, S33, 530742520); /* 47 */
	HH(b, c, d, a, in2, S34, 3299628645); /* 48 */

										  /* Round 4 */
#define S41 6
#define S42 10
#define S43 15
#define S44 21
	II(a, b, c, d, in0, S41, 4096336452); /* 49 */
	II(d, a, b, c, in7, S42, 1126891415); /* 50 */
	II(c, d, a, b, in14, S43, 2878612391); /* 51 */
	II(b, c, d, a, in5, S44, 4237533241); /* 52 */
	II(a, b, c, d, in12, S41, 1700485571); /* 53 */
	II(d, a, b, c, in3, S42, 2399980690); /* 54 */
	II(c, d, a, b, in10, S43, 4293915773); /* 55 */
	II(b, c, d, a, in1, S44, 2240044497); /* 56 */
	II(a, b, c, d, in8, S41, 1873313359); /* 57 */
	II(d, a, b, c, in15, S42, 4264355552); /* 58 */
	II(c, d, a, b, in6, S43, 2734768916); /* 59 */
	II(b, c, d, a, in13, S44, 1309151649); /* 60 */
	II(a, b, c, d, in4, S41, 4149444226); /* 61 */
	II(d, a, b, c, in11, S42, 3174756917); /* 62 */
	II(c, d, a, b, in2, S43, 718787259); /* 63 */
	II(b, c, d, a, in9, S44, 3951481745); /* 64 */

	a += a0;
	b += b0;
	c += c0;
	d += d0;

	*a1 = a;
	*b1 = b;
	*c1 = c;
	*d1 = d;
}

unsigned int unhex(unsigned char x)
{
	if (x <= 'F' && x >= 'A')
	{
		return  (unsigned int)(x - 'A' + 10);
	}
	else if (x <= 'f' && x >= 'a')
	{
		return (unsigned int)(x - 'a' + 10);
	}
	else if (x <= '9' && x >= '0')
	{
		return (unsigned int)(x - '0');
	}
	return 0;
}

void md5_to_ints(unsigned char* md5, unsigned int *r0, unsigned int *r1, unsigned int *r2, unsigned int *r3)
{
	unsigned int v0 = 0, v1 = 0, v2 = 0, v3 = 0;
	int i = 0;
	for (i = 0; i < 32; i += 2)
	{
		unsigned int first = unhex(md5[i]);
		unsigned int second = unhex(md5[i + 1]);
		unsigned int both = first * 16 + second;
		both = both << 24;
		if (i < 8)
		{
			v0 = (v0 >> 8) | both;
		}
		else if (i < 16)
		{
			v1 = (v1 >> 8) | both;
		}
		else if (i < 24)
		{
			v2 = (v2 >> 8) | both;
		}
		else if (i < 32)
		{
			v3 = (v3 >> 8) | both;
		}
	}

	*r0 = v0;
	*r1 = v1;
	*r2 = v2;
	*r3 = v3;
}

/*
* This method is given a test password and the unsigned int of the orginal password and will check
* to see if it is the original passowrd
*
*/
__host__ __device__ int myencrypt(unsigned char * test, unsigned int length, unsigned int a, unsigned int b, unsigned int c, unsigned int d)
{
	unsigned int v1 = 0, v2 = 0, v3 = 0, v4 = 0;
	md5_vfy(test, length, &v1, &v2, &v3, &v4);
	if (v1 == a && v2 == b && v3 == c && v4 == d)
	{
		return 1;
	}
	else
		return 0;
}//end of crypt method

__device__ bool Compare(unsigned char* guess, unsigned int* hash) {
	return myencrypt(guess, MAX_PASSWORD_LENGTH, hash[0], hash[1], hash[2], hash[3]);
}

__global__ void square_array(char* a, unsigned int* hash) {
	int idx = threadIdx.x + blockDim.x * blockIdx.x;

	unsigned char guess[MAX_PASSWORD_LENGTH];

	if (idx < pow((double)ALPHABET_SIZE, (double)PREFIX_LENGTH)) {
		for (unsigned int i = 0; i < PREFIX_LENGTH; i++) {
			if (i == PREFIX_LENGTH - 1) {
				guess[i] = 'a' + idx % ALPHABET_SIZE;
			}
			else {
				unsigned int offset = PREFIX_LENGTH - i - 1;
				unsigned int t = idx % (int)(pow((double)ALPHABET_SIZE, (double)(offset + 1)));
				guess[i] = 'a' + t / (unsigned long long int)(pow((double)ALPHABET_SIZE, (double)offset));
			}
		}
	}
	int remainingLetters = MAX_PASSWORD_LENGTH - PREFIX_LENGTH;
	unsigned long i = 1;
	for (int j = 0; j < remainingLetters; j++) {
		i *= 26;
	}
	for (int pos = PREFIX_LENGTH; pos < MAX_PASSWORD_LENGTH; pos++) {
		guess[pos] = 'a';
	}
	while (true) {
		int tail;
		for (tail = MAX_PASSWORD_LENGTH - 1; tail >= PREFIX_LENGTH && guess[tail] == 'z'; tail--);
		if (tail < PREFIX_LENGTH) {
			break;
		}
		else {
			for (int j = MAX_PASSWORD_LENGTH - 1; j > tail; j--) {
				guess[j] = 'a';
			}
			guess[tail] += 1;
		}
		if (Compare(guess, hash)) {
			for (unsigned int jj = 0; jj < MAX_PASSWORD_LENGTH; jj++)
				a[jj] = guess[jj];
			break;
		}
	}
}

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
	if (code != cudaSuccess)
	{
		fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
		if (abort) exit(code);
	}
}

int main() {
	unsigned char password[MAX_PASSWORD_LENGTH] = { 'p', 'a', 's', 's', 'w', 'o' };
	char* a_h, *a_d;
	size_t size = MAX_PASSWORD_LENGTH * sizeof(char);
	unsigned int* hash_h, *hash_d;
	hash_h = (unsigned int*)malloc(4 * sizeof(unsigned int));

	// calculate hash and verify it works
	md5_vfy(password, MAX_PASSWORD_LENGTH, &hash_h[0], &hash_h[1], &hash_h[2], &hash_h[3]);
	printf("hash: 0x%08X 0x%08X 0x%08X 0x%08X\n", hash_h[0], hash_h[1], hash_h[2], hash_h[3]);
	int res = myencrypt((unsigned char*)"password", MAX_PASSWORD_LENGTH, hash_h[0], hash_h[1], hash_h[2], hash_h[3]);
	printf("%d\n", res);

	// set array to a default value
	a_h = (char*)malloc(size + 1);
	for (unsigned int i = 0; i < size; i++) {
		a_h[i] = 'a' - 1;
	}
	a_h[size] = '\0';
	cudaMalloc((void**)&a_d, size);	
	cudaMalloc((void**)&hash_d, 4 * sizeof(unsigned int));
	cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
	cudaMemcpy(hash_d, hash_h, 4 * sizeof(unsigned int), cudaMemcpyHostToDevice);

	int threadsPerBlock = 1024;
	int numBlocks = ceil(pow(ALPHABET_SIZE, PREFIX_LENGTH) / threadsPerBlock);

	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);

	cudaEventRecord(start);
	square_array<<<numBlocks, threadsPerBlock>>>(a_d, hash_d);
	cudaEventRecord(stop);

	cudaMemcpy(a_h, a_d, size, cudaMemcpyDeviceToHost);

	printf("password: %s\n", a_h);

	cudaEventSynchronize(stop);
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);
	printf("Done in: %f milliseconds\n", milliseconds);

	free(a_h);
	cudaFree(a_d);
}

	.file	"tmpxft_00239aa8_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7md5_vfyPhjPjS0_S0_S0_
	.type	_Z7md5_vfyPhjPjS0_S0_S0_, @function
_Z7md5_vfyPhjPjS0_S0_S0_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r10
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%rcx, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	$14, %ecx
	movq	%rdx, 16(%rsp)
	movq	%r8, 32(%rsp)
	movq	%r9, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	rep stosl
	xorl	%eax, %eax
.L3:
	movl	%eax, %edx
	movl	%eax, %ecx
	sarl	$2, %edx
	andl	$3, %ecx
	movslq	%edx, %rdx
	sall	$3, %ecx
	movl	48(%rsp,%rdx,4), %r8d
	cmpl	%esi, %eax
	jnb	.L8
	movzbl	(%r10,%rax), %edi
	incq	%rax
	sall	%cl, %edi
	orl	%r8d, %edi
	movl	%edi, 48(%rsp,%rdx,4)
	jmp	.L3
.L8:
	movl	$128, %eax
	sall	%cl, %eax
	orl	%r8d, %eax
	leal	0(,%rsi,8), %r8d
	movl	%eax, 48(%rsp,%rdx,4)
	movl	48(%rsp), %r14d
	movl	52(%rsp), %ebx
	movl	64(%rsp), %edi
	leal	-680876937(%r14), %eax
	movl	68(%rsp), %r12d
	movl	76(%rsp), %r13d
	roll	$7, %eax
	movl	84(%rsp), %r15d
	movl	88(%rsp), %r11d
	subl	$271733879, %eax
	movl	92(%rsp), %r9d
	movl	96(%rsp), %ebp
	movl	%eax, %edx
	movl	%eax, %ecx
	movl	%eax, %esi
	movl	100(%rsp), %r10d
	andl	$2004318071, %edx
	xorl	$-271733879, %ecx
	leal	-176418897(%rdi,%rax), %edi
	xorl	$-1732584194, %edx
	leal	-117830708(%rbx,%rdx), %edx
	movl	56(%rsp), %ebx
	roll	$12, %edx
	addl	%eax, %edx
	andl	%edx, %ecx
	xorl	%edx, %esi
	xorl	$-271733879, %ecx
	leal	-1126478375(%rbx,%rcx), %ecx
	movl	60(%rsp), %ebx
	rorl	$15, %ecx
	addl	%edx, %ecx
	andl	%ecx, %esi
	xorl	%eax, %esi
	movl	%edx, %eax
	leal	-1316259209(%rbx,%rsi), %esi
	xorl	%ecx, %eax
	rorl	$10, %esi
	addl	%ecx, %esi
	andl	%esi, %eax
	xorl	%edx, %eax
	addl	%edi, %eax
	leal	1200080426(%r12,%rdx), %edi
	movl	%ecx, %edx
	roll	$7, %eax
	xorl	%esi, %edx
	addl	%esi, %eax
	andl	%eax, %edx
	xorl	%ecx, %edx
	addl	%edi, %edx
	movl	72(%rsp), %edi
	roll	$12, %edx
	leal	-1473231341(%rdi,%rcx), %edi
	movl	%esi, %ecx
	addl	%eax, %edx
	xorl	%eax, %ecx
	andl	%edx, %ecx
	xorl	%esi, %ecx
	addl	%edi, %ecx
	leal	-45705983(%r13,%rsi), %edi
	movl	%eax, %esi
	rorl	$15, %ecx
	xorl	%edx, %esi
	addl	%edx, %ecx
	andl	%ecx, %esi
	xorl	%eax, %esi
	addl	%edi, %esi
	movl	80(%rsp), %edi
	rorl	$10, %esi
	leal	1770035416(%rdi,%rax), %edi
	movl	%edx, %eax
	addl	%ecx, %esi
	xorl	%ecx, %eax
	andl	%esi, %eax
	xorl	%edx, %eax
	addl	%edi, %eax
	leal	-1958414417(%r15,%rdx), %edi
	movl	%ecx, %edx
	roll	$7, %eax
	xorl	%esi, %edx
	addl	%esi, %eax
	andl	%eax, %edx
	xorl	%ecx, %edx
	addl	%edi, %edx
	leal	-42063(%r11,%rcx), %edi
	movl	%esi, %ecx
	roll	$12, %edx
	xorl	%eax, %ecx
	addl	%eax, %edx
	andl	%edx, %ecx
	xorl	%esi, %ecx
	addl	%edi, %ecx
	leal	-1990404162(%r9,%rsi), %edi
	movl	%eax, %esi
	rorl	$15, %ecx
	xorl	%edx, %esi
	addl	%edx, %ecx
	andl	%ecx, %esi
	xorl	%eax, %esi
	addl	%edi, %esi
	leal	1804603682(%rbp,%rax), %edi
	movl	%edx, %eax
	rorl	$10, %esi
	xorl	%ecx, %eax
	addl	%ecx, %esi
	andl	%esi, %eax
	xorl	%edx, %eax
	addl	%edi, %eax
	leal	-40341101(%r10,%rdx), %edi
	movl	%ecx, %edx
	roll	$7, %eax
	xorl	%esi, %edx
	addl	%esi, %eax
	andl	%eax, %edx
	xorl	%ecx, %edx
	addl	%edi, %edx
	leal	-1502002290(%r8,%rcx), %edi
	movl	%esi, %ecx
	roll	$12, %edx
	xorl	%eax, %ecx
	addl	%eax, %edx
	andl	%edx, %ecx
	xorl	%esi, %ecx
	addl	%edi, %ecx
	movl	%eax, %edi
	rorl	$15, %ecx
	xorl	%edx, %edi
	addl	%edx, %ecx
	andl	%ecx, %edi
	xorl	%eax, %edi
	leal	1236535329(%rsi,%rdi), %esi
	movl	52(%rsp), %edi
	rorl	$10, %esi
	addl	%ecx, %esi
	leal	-165796510(%rdi,%rax), %edi
	movl	%ecx, %eax
	xorl	%esi, %eax
	andl	%edx, %eax
	xorl	%ecx, %eax
	addl	%edi, %eax
	movl	72(%rsp), %edi
	roll	$5, %eax
	addl	%esi, %eax
	leal	-1069501632(%rdi,%rdx), %edi
	movl	%esi, %edx
	xorl	%eax, %edx
	andl	%ecx, %edx
	xorl	%esi, %edx
	addl	%edi, %edx
	leal	643717713(%r9,%rcx), %edi
	movl	%eax, %ecx
	roll	$9, %edx
	addl	%eax, %edx
	xorl	%edx, %ecx
	andl	%esi, %ecx
	xorl	%eax, %ecx
	addl	%edi, %ecx
	leal	-373897302(%r14,%rsi), %edi
	movl	%edx, %esi
	roll	$14, %ecx
	addl	%edx, %ecx
	xorl	%ecx, %esi
	andl	%eax, %esi
	xorl	%edx, %esi
	addl	%edi, %esi
	leal	-701558691(%r12,%rax), %edi
	movl	%ecx, %eax
	rorl	$12, %esi
	addl	%ecx, %esi
	xorl	%esi, %eax
	andl	%edx, %eax
	xorl	%ecx, %eax
	addl	%edi, %eax
	leal	38016083(%r11,%rdx), %edi
	movl	%esi, %edx
	roll	$5, %eax
	addl	%esi, %eax
	xorl	%eax, %edx
	andl	%ecx, %edx
	xorl	%esi, %edx
	addl	%edi, %edx
	movl	%eax, %edi
	roll	$9, %edx
	addl	%eax, %edx
	xorl	%edx, %edi
	andl	%esi, %edi
	xorl	%eax, %edi
	leal	-660478335(%rcx,%rdi), %ecx
	movl	64(%rsp), %edi
	roll	$14, %ecx
	addl	%edx, %ecx
	leal	-405537848(%rdi,%rsi), %edi
	movl	%edx, %esi
	xorl	%ecx, %esi
	andl	%eax, %esi
	xorl	%edx, %esi
	addl	%edi, %esi
	leal	568446438(%r15,%rax), %edi
	movl	%ecx, %eax
	rorl	$12, %esi
	addl	%ecx, %esi
	xorl	%esi, %eax
	andl	%edx, %eax
	xorl	%ecx, %eax
	addl	%edi, %eax
	leal	-1019803690(%r8,%rdx), %edi
	movl	%esi, %edx
	roll	$5, %eax
	addl	%esi, %eax
	xorl	%eax, %edx
	andl	%ecx, %edx
	xorl	%esi, %edx
	addl	%edi, %edx
	leal	-187363961(%rbx,%rcx), %edi
	movl	%eax, %ecx
	roll	$9, %edx
	addl	%eax, %edx
	xorl	%edx, %ecx
	andl	%esi, %ecx
	xorl	%eax, %ecx
	addl	%edi, %ecx
	movl	80(%rsp), %edi
	roll	$14, %ecx
	addl	%edx, %ecx
	leal	1163531501(%rdi,%rsi), %esi
	movl	%edx, %edi
	xorl	%ecx, %edi
	andl	%eax, %edi
	xorl	%edx, %edi
	addl	%esi, %edi
	leal	-1444681467(%r10,%rax), %esi
	movl	%ecx, %eax
	rorl	$12, %edi
	addl	%ecx, %edi
	xorl	%edi, %eax
	andl	%edx, %eax
	xorl	%ecx, %eax
	addl	%esi, %eax
	movl	56(%rsp), %esi
	roll	$5, %eax
	addl	%edi, %eax
	leal	-51403784(%rsi,%rdx), %esi
	movl	%edi, %edx
	xorl	%eax, %edx
	andl	%ecx, %edx
	leal	1735328473(%r13,%rcx), %ecx
	xorl	%edi, %edx
	addl	%esi, %edx
	movl	%eax, %esi
	roll	$9, %edx
	addl	%eax, %edx
	xorl	%edx, %esi
	andl	%edi, %esi
	leal	-1926607734(%rbp,%rdi), %edi
	xorl	%eax, %esi
	movl	%edi, 12(%rsp)
	movl	%eax, %edi
	leal	-378558(%r12,%rax), %eax
	addl	%ecx, %esi
	movl	%edx, %ecx
	roll	$14, %esi
	addl	%edx, %esi
	xorl	%esi, %ecx
	movl	%ecx, 8(%rsp)
	andl	%ecx, %edi
	movl	12(%rsp), %ecx
	xorl	%edx, %edi
	addl	%ecx, %edi
	movl	8(%rsp), %ecx
	rorl	$12, %edi
	addl	%esi, %edi
	xorl	%edi, %ecx
	addl	%eax, %ecx
	movl	80(%rsp), %eax
	roll	$4, %ecx
	leal	-2022574463(%rax,%rdx), %eax
	movl	%esi, %edx
	addl	%edi, %ecx
	xorl	%edi, %edx
	xorl	%ecx, %edx
	addl	%eax, %edx
	leal	1839030562(%r9,%rsi), %eax
	movl	%edi, %esi
	roll	$11, %edx
	leal	-35309556(%r8,%rdi), %edi
	addl	%ecx, %edx
	xorl	%ecx, %esi
	xorl	%edx, %esi
	addl	%eax, %esi
	movl	%ecx, %eax
	roll	$16, %esi
	xorl	%edx, %eax
	addl	%edx, %esi
	xorl	%esi, %eax
	addl	%edi, %eax
	movl	52(%rsp), %edi
	rorl	$9, %eax
	leal	-1530992060(%rdi,%rcx), %edi
	movl	%edx, %ecx
	addl	%esi, %eax
	xorl	%esi, %ecx
	xorl	%eax, %ecx
	addl	%edi, %ecx
	movl	64(%rsp), %edi
	roll	$4, %ecx
	leal	1272893353(%rdi,%rdx), %edx
	movl	%esi, %edi
	addl	%eax, %ecx
	xorl	%eax, %edi
	leal	-155497632(%r13,%rsi), %esi
	xorl	%ecx, %edi
	addl	%edx, %edi
	movl	%eax, %edx
	leal	-1094730640(%r11,%rax), %eax
	roll	$11, %edi
	xorl	%ecx, %edx
	addl	%ecx, %edi
	xorl	%edi, %edx
	addl	%esi, %edx
	movl	%ecx, %esi
	roll	$16, %edx
	xorl	%edi, %esi
	addl	%edi, %edx
	xorl	%edx, %esi
	addl	%eax, %esi
	leal	681279174(%r10,%rcx), %eax
	movl	%edi, %ecx
	rorl	$9, %esi
	xorl	%edx, %ecx
	leal	-358537222(%r14,%rdi), %edi
	addl	%edx, %esi
	xorl	%esi, %ecx
	addl	%eax, %ecx
	movl	%edx, %eax
	leal	-722521979(%rbx,%rdx), %edx
	roll	$4, %ecx
	xorl	%esi, %eax
	addl	%esi, %ecx
	xorl	%ecx, %eax
	addl	%edi, %eax
	movl	%esi, %edi
	roll	$11, %eax
	xorl	%ecx, %edi
	addl	%ecx, %eax
	xorl	%eax, %edi
	addl	%edx, %edi
	movl	72(%rsp), %edx
	roll	$16, %edi
	leal	76029189(%rdx,%rsi), %edx
	movl	%ecx, %esi
	addl	%eax, %edi
	xorl	%eax, %esi
	leal	-640364487(%r15,%rcx), %ecx
	xorl	%edi, %esi
	addl	%edx, %esi
	movl	%eax, %edx
	leal	-421815835(%rbp,%rax), %eax
	rorl	$9, %esi
	xorl	%edi, %edx
	addl	%edi, %esi
	xorl	%esi, %edx
	addl	%ecx, %edx
	movl	%edi, %ecx
	roll	$4, %edx
	xorl	%esi, %ecx
	addl	%esi, %edx
	xorl	%edx, %ecx
	addl	%eax, %ecx
	movl	%esi, %eax
	roll	$11, %ecx
	xorl	%edx, %eax
	addl	%edx, %ecx
	xorl	%ecx, %eax
	leal	530742520(%rdi,%rax), %edi
	movl	56(%rsp), %eax
	roll	$16, %edi
	leal	-995338651(%rax,%rsi), %esi
	movl	%edx, %eax
	addl	%ecx, %edi
	xorl	%ecx, %eax
	xorl	%edi, %eax
	addl	%esi, %eax
	leal	-198630844(%r14,%rdx), %esi
	movl	%ecx, %edx
	rorl	$9, %eax
	notl	%edx
	addl	%edi, %eax
	orl	%eax, %edx
	xorl	%edi, %edx
	addl	%esi, %edx
	leal	1126891415(%r13,%rcx), %esi
	movl	%edi, %ecx
	roll	$6, %edx
	notl	%ecx
	leal	-1416354905(%r8,%rdi), %edi
	addl	%eax, %edx
	orl	%edx, %ecx
	xorl	%eax, %ecx
	addl	%esi, %ecx
	movl	%eax, %esi
	roll	$10, %ecx
	notl	%esi
	addl	%edx, %ecx
	orl	%ecx, %esi
	xorl	%edx, %esi
	addl	%edi, %esi
	leal	-57434055(%r12,%rax), %edi
	movl	%edx, %eax
	roll	$15, %esi
	notl	%eax
	addl	%ecx, %esi
	orl	%esi, %eax
	xorl	%ecx, %eax
	addl	%edi, %eax
	leal	1700485571(%rbp,%rdx), %edi
	movl	%ecx, %edx
	rorl	$11, %eax
	notl	%edx
	addl	%esi, %eax
	orl	%eax, %edx
	xorl	%esi, %edx
	addl	%edi, %edx
	leal	-1894986606(%rbx,%rcx), %edi
	movl	%esi, %ecx
	movl	52(%rsp), %ebx
	roll	$6, %edx
	notl	%ecx
	addl	%eax, %edx
	orl	%edx, %ecx
	xorl	%eax, %ecx
	addl	%edi, %ecx
	leal	-1051523(%r11,%rsi), %edi
	movl	%eax, %esi
	roll	$10, %ecx
	notl	%esi
	addl	%edx, %ecx
	orl	%ecx, %esi
	xorl	%edx, %esi
	addl	%edi, %esi
	leal	-2054922799(%rbx,%rax), %edi
	movl	%edx, %eax
	movl	80(%rsp), %ebx
	roll	$15, %esi
	notl	%eax
	addl	%ecx, %esi
	orl	%esi, %eax
	xorl	%ecx, %eax
	addl	%edi, %eax
	leal	1873313359(%rbx,%rdx), %edi
	movl	%ecx, %edx
	movl	72(%rsp), %ebx
	rorl	$11, %eax
	notl	%edx
	addl	%esi, %eax
	orl	%eax, %edx
	xorl	%esi, %edx
	addl	%edi, %edx
	movl	%esi, %edi
	roll	$6, %edx
	notl	%edi
	addl	%eax, %edx
	orl	%edx, %edi
	xorl	%eax, %edi
	leal	-30611744(%rcx,%rdi), %ecx
	leal	-1560198380(%rbx,%rsi), %edi
	movl	%eax, %esi
	roll	$10, %ecx
	notl	%esi
	leal	1309151649(%r10,%rax), %eax
	addl	%edx, %ecx
	orl	%ecx, %esi
	xorl	%edx, %esi
	addl	%edi, %esi
	movl	%edx, %edi
	roll	$15, %esi
	notl	%edi
	addl	%ecx, %esi
	orl	%esi, %edi
	xorl	%ecx, %edi
	addl	%eax, %edi
	movl	64(%rsp), %eax
	movl	56(%rsp), %ebx
	rorl	$11, %edi
	leal	-145523070(%rax,%rdx), %edx
	movl	%ecx, %eax
	addl	%esi, %edi
	notl	%eax
	leal	-1120210379(%r9,%rcx), %ecx
	orl	%edi, %eax
	xorl	%esi, %eax
	addl	%edx, %eax
	movl	%esi, %edx
	leal	718787259(%rbx,%rsi), %esi
	movq	16(%rsp), %rbx
	roll	$6, %eax
	notl	%edx
	addl	%edi, %eax
	orl	%eax, %edx
	xorl	%edi, %edx
	addl	%ecx, %edx
	movl	%edi, %ecx
	leal	-343485551(%r15,%rdi), %edi
	roll	$10, %edx
	notl	%ecx
	addl	%eax, %edx
	orl	%edx, %ecx
	xorl	%eax, %ecx
	addl	%esi, %ecx
	movl	%eax, %esi
	addl	$1732584193, %eax
	roll	$15, %ecx
	notl	%esi
	movl	%eax, (%rbx)
	movq	24(%rsp), %rbx
	addl	%edx, %ecx
	orl	%ecx, %esi
	xorl	%edx, %esi
	addl	$271733878, %edx
	addl	%edi, %esi
	rorl	$11, %esi
	leal	-271733879(%rcx,%rsi), %eax
	subl	$1732584194, %ecx
	movl	%eax, (%rbx)
	movq	32(%rsp), %rax
	movl	%ecx, (%rax)
	movq	40(%rsp), %rax
	movl	%edx, (%rax)
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7md5_vfyPhjPjS0_S0_S0_, .-_Z7md5_vfyPhjPjS0_S0_S0_
	.globl	_Z5unhexh
	.type	_Z5unhexh, @function
_Z5unhexh:
.LFB2028:
	.cfi_startproc
	endbr64
	leal	-65(%rdi), %eax
	cmpb	$5, %al
	ja	.L10
	movzbl	%dil, %edi
	leal	-55(%rdi), %eax
	ret
.L10:
	leal	-97(%rdi), %eax
	cmpb	$5, %al
	ja	.L12
	movzbl	%dil, %edi
	leal	-87(%rdi), %eax
	ret
.L12:
	leal	-48(%rdi), %edx
	xorl	%eax, %eax
	cmpb	$9, %dl
	ja	.L9
	movzbl	%dil, %edi
	leal	-48(%rdi), %eax
.L9:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z5unhexh, .-_Z5unhexh
	.globl	_Z11md5_to_intsPhPjS0_S0_S0_
	.type	_Z11md5_to_intsPhPjS0_S0_S0_, @function
_Z11md5_to_intsPhPjS0_S0_S0_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%r9d, %r9d
	movq	%rcx, %r14
	xorl	%r10d, %r10d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r11d, %r11d
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	xorl	%esi, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
.L19:
	movzbl	0(%rbp,%rsi), %edi
	call	_Z5unhexh
	movzbl	1(%rbp,%rsi), %edi
	movl	%eax, %ecx
	call	_Z5unhexh
	sall	$4, %ecx
	addl	%ecx, %eax
	sall	$24, %eax
	cmpq	$7, %rsi
	ja	.L15
	shrl	$8, %ebx
	orl	%eax, %ebx
	jmp	.L16
.L15:
	cmpq	$15, %rsi
	ja	.L17
	shrl	$8, %r11d
	orl	%eax, %r11d
	jmp	.L16
.L17:
	cmpq	$23, %rsi
	ja	.L18
	shrl	$8, %r10d
	orl	%eax, %r10d
	jmp	.L16
.L18:
	shrl	$8, %r9d
	orl	%eax, %r9d
.L16:
	addq	$2, %rsi
	cmpq	$32, %rsi
	jne	.L19
	movl	%ebx, (%r12)
	movl	%r11d, 0(%r13)
	movl	%r10d, (%r14)
	popq	%rbx
	.cfi_def_cfa_offset 40
	movl	%r9d, (%r8)
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z11md5_to_intsPhPjS0_S0_S0_, .-_Z11md5_to_intsPhPjS0_S0_S0_
	.globl	_Z9myencryptPhjjjjj
	.type	_Z9myencryptPhjjjjj, @function
_Z9myencryptPhjjjjj:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%r9d, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	leaq	12(%rsp), %rcx
	leaq	8(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	20(%rsp), %r9
	leaq	16(%rsp), %r8
	call	_Z7md5_vfyPhjPjS0_S0_S0_
	xorl	%eax, %eax
	cmpl	%r13d, 8(%rsp)
	jne	.L22
	cmpl	%r12d, 12(%rsp)
	jne	.L22
	cmpl	%ebp, 16(%rsp)
	jne	.L22
	xorl	%eax, %eax
	cmpl	%ebx, 20(%rsp)
	sete	%al
.L22:
	movq	24(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z9myencryptPhjjjjj, .-_Z9myencryptPhjjjjj
	.globl	_Z7ComparePhPj
	.type	_Z7ComparePhPj, @function
_Z7ComparePhPj:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z7ComparePhPj, .-_Z7ComparePhPj
	.globl	_Z34__device_stub__Z12square_arrayPcPjPcPj
	.type	_Z34__device_stub__Z12square_arrayPcPjPcPj, @function
_Z34__device_stub__Z12square_arrayPcPjPcPj:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12square_arrayPcPj(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L31:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z34__device_stub__Z12square_arrayPcPjPcPj, .-_Z34__device_stub__Z12square_arrayPcPjPcPj
	.globl	_Z12square_arrayPcPj
	.type	_Z12square_arrayPcPj, @function
_Z12square_arrayPcPj:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z12square_arrayPcPjPcPj
	.cfi_endproc
.LFE2060:
	.size	_Z12square_arrayPcPj, .-_Z12square_arrayPcPj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"hash: 0x%08X 0x%08X 0x%08X 0x%08X\n"
.LC1:
	.string	"password"
.LC2:
	.string	"%d\n"
.LC3:
	.string	"password: %s\n"
.LC5:
	.string	"Done in: %f milliseconds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$16, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movl	$1936941424, 66(%rsp)
	movw	$28535, 70(%rsp)
	call	malloc@PLT
	leaq	66(%rsp), %rdi
	movl	$6, %esi
	movq	%rax, %rbx
	leaq	4(%rax), %rcx
	leaq	12(%rax), %r9
	movq	%rax, %rdx
	leaq	8(%rax), %r8
	call	_Z7md5_vfyPhjPjS0_S0_S0_
	movl	4(%rbx), %ecx
	movl	12(%rbx), %r9d
	xorl	%eax, %eax
	movl	8(%rbx), %r8d
	movl	(%rbx), %edx
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
	movl	12(%rbx), %r9d
	movl	(%rbx), %edx
	movl	$6, %esi
	movl	8(%rbx), %r8d
	movl	4(%rbx), %ecx
	leaq	.LC1(%rip), %rdi
	call	_Z9myencryptPhjjjjj
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movl	%eax, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$7, %edi
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$6, %esi
	movl	$1616928864, (%rax)
	movq	%rax, %rbp
	movw	$24672, 4(%rax)
	movb	$0, 6(%rax)
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$6, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$16, %edx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movabsq	$4294967743, %rdi
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z34__device_stub__Z12square_arrayPcPjPcPj
.L37:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$6, %edx
	call	cudaMemcpy@PLT
	movq	%rbp, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	52(%rsp), %rdi
	movl	$0x00000000, 52(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	52(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z12square_arrayPcPj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12square_arrayPcPj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>

#define PREFIX_LENGTH 4
#define MAX_PASSWORD_LENGTH 6
#define ALPHABET_SIZE 26


/* F, G and H are basic MD5 functions: selection, majority, parity */
#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
#define H(x, y, z) ((x) ^ (y) ^ (z))
#define I(x, y, z) ((y) ^ ((x) | (~z)))

/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))

/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
/* Rotation is separate from addition to prevent recomputation */
#define FF(a, b, c, d, x, s, ac) \
  {(a) += F ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define GG(a, b, c, d, x, s, ac) \
  {(a) += G ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define HH(a, b, c, d, x, s, ac) \
  {(a) += H ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }
#define II(a, b, c, d, x, s, ac) \
  {(a) += I ((b), (c), (d)) + (x) + (unsigned int)(ac); \
   (a) = ROTATE_LEFT ((a), (s)); \
   (a) += (b); \
  }

__host__ __device__ void md5_vfy(unsigned char* data, unsigned int length, unsigned int *a1, unsigned int *b1, unsigned int *c1, unsigned int *d1)
{

	const unsigned int a0 = 0x67452301;
	const unsigned int b0 = 0xEFCDAB89;
	const unsigned int c0 = 0x98BADCFE;
	const unsigned int d0 = 0x10325476;

	unsigned int a = 0;
	unsigned int b = 0;
	unsigned int c = 0;
	unsigned int d = 0;

	unsigned int vals[14] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0 };

	int i = 0;

	for (i = 0; i < length; i++)
	{
		vals[i / 4] |= data[i] << ((i % 4) * 8);
	}
	vals[i / 4] |= 0x80 << ((i % 4) * 8);

	unsigned int bitlen = length * 8;

#define in0  (vals[0])//x
#define in1  (vals[1])//y
#define in2  (vals[2])//z
#define in3  (vals[3])
#define in4  (vals[4])
#define in5  (vals[5])
#define in6  (vals[6])
#define in7  (vals[7])
#define in8  (vals[8])
#define in9  (vals[9])
#define in10 (vals[10])
#define in11 (vals[11])
#define in12 (vals[12])
#define in13 (vals[13])
#define in14 (bitlen) //w = bit length
#define in15 (0)

	//Initialize hash value for this chunk:
	a = a0;
	b = b0;
	c = c0;
	d = d0;


	/* Round 1 */
#define S11 7
#define S12 12
#define S13 17
#define S14 22
	FF(a, b, c, d, in0, S11, 3614090360); /* 1 */
	FF(d, a, b, c, in1, S12, 3905402710); /* 2 */
	FF(c, d, a, b, in2, S13, 606105819); /* 3 */
	FF(b, c, d, a, in3, S14, 3250441966); /* 4 */
	FF(a, b, c, d, in4, S11, 4118548399); /* 5 */
	FF(d, a, b, c, in5, S12, 1200080426); /* 6 */
	FF(c, d, a, b, in6, S13, 2821735955); /* 7 */
	FF(b, c, d, a, in7, S14, 4249261313); /* 8 */
	FF(a, b, c, d, in8, S11, 1770035416); /* 9 */
	FF(d, a, b, c, in9, S12, 2336552879); /* 10 */
	FF(c, d, a, b, in10, S13, 4294925233); /* 11 */
	FF(b, c, d, a, in11, S14, 2304563134); /* 12 */
	FF(a, b, c, d, in12, S11, 1804603682); /* 13 */
	FF(d, a, b, c, in13, S12, 4254626195); /* 14 */
	FF(c, d, a, b, in14, S13, 2792965006); /* 15 */
	FF(b, c, d, a, in15, S14, 1236535329); /* 16 */

										   /* Round 2 */
#define S21 5
#define S22 9
#define S23 14
#define S24 20
	GG(a, b, c, d, in1, S21, 4129170786); /* 17 */
	GG(d, a, b, c, in6, S22, 3225465664); /* 18 */
	GG(c, d, a, b, in11, S23, 643717713); /* 19 */
	GG(b, c, d, a, in0, S24, 3921069994); /* 20 */
	GG(a, b, c, d, in5, S21, 3593408605); /* 21 */
	GG(d, a, b, c, in10, S22, 38016083); /* 22 */
	GG(c, d, a, b, in15, S23, 3634488961); /* 23 */
	GG(b, c, d, a, in4, S24, 3889429448); /* 24 */
	GG(a, b, c, d, in9, S21, 568446438); /* 25 */
	GG(d, a, b, c, in14, S22, 3275163606); /* 26 */
	GG(c, d, a, b, in3, S23, 4107603335); /* 27 */
	GG(b, c, d, a, in8, S24, 1163531501); /* 28 */
	GG(a, b, c, d, in13, S21, 2850285829); /* 29 */
	GG(d, a, b, c, in2, S22, 4243563512); /* 30 */
	GG(c, d, a, b, in7, S23, 1735328473); /* 31 */
	GG(b, c, d, a, in12, S24, 2368359562); /* 32 */

										   /* Round 3 */
#define S31 4
#define S32 11
#define S33 16
#define S34 23
	HH(a, b, c, d, in5, S31, 4294588738); /* 33 */
	HH(d, a, b, c, in8, S32, 2272392833); /* 34 */
	HH(c, d, a, b, in11, S33, 1839030562); /* 35 */
	HH(b, c, d, a, in14, S34, 4259657740); /* 36 */
	HH(a, b, c, d, in1, S31, 2763975236); /* 37 */
	HH(d, a, b, c, in4, S32, 1272893353); /* 38 */
	HH(c, d, a, b, in7, S33, 4139469664); /* 39 */
	HH(b, c, d, a, in10, S34, 3200236656); /* 40 */
	HH(a, b, c, d, in13, S31, 681279174); /* 41 */
	HH(d, a, b, c, in0, S32, 3936430074); /* 42 */
	HH(c, d, a, b, in3, S33, 3572445317); /* 43 */
	HH(b, c, d, a, in6, S34, 76029189); /* 44 */
	HH(a, b, c, d, in9, S31, 3654602809); /* 45 */
	HH(d, a, b, c, in12, S32, 3873151461); /* 46 */
	HH(c, d, a, b, in15, S33, 530742520); /* 47 */
	HH(b, c, d, a, in2, S34, 3299628645); /* 48 */

										  /* Round 4 */
#define S41 6
#define S42 10
#define S43 15
#define S44 21
	II(a, b, c, d, in0, S41, 4096336452); /* 49 */
	II(d, a, b, c, in7, S42, 1126891415); /* 50 */
	II(c, d, a, b, in14, S43, 2878612391); /* 51 */
	II(b, c, d, a, in5, S44, 4237533241); /* 52 */
	II(a, b, c, d, in12, S41, 1700485571); /* 53 */
	II(d, a, b, c, in3, S42, 2399980690); /* 54 */
	II(c, d, a, b, in10, S43, 4293915773); /* 55 */
	II(b, c, d, a, in1, S44, 2240044497); /* 56 */
	II(a, b, c, d, in8, S41, 1873313359); /* 57 */
	II(d, a, b, c, in15, S42, 4264355552); /* 58 */
	II(c, d, a, b, in6, S43, 2734768916); /* 59 */
	II(b, c, d, a, in13, S44, 1309151649); /* 60 */
	II(a, b, c, d, in4, S41, 4149444226); /* 61 */
	II(d, a, b, c, in11, S42, 3174756917); /* 62 */
	II(c, d, a, b, in2, S43, 718787259); /* 63 */
	II(b, c, d, a, in9, S44, 3951481745); /* 64 */

	a += a0;
	b += b0;
	c += c0;
	d += d0;

	*a1 = a;
	*b1 = b;
	*c1 = c;
	*d1 = d;
}

unsigned int unhex(unsigned char x)
{
	if (x <= 'F' && x >= 'A')
	{
		return  (unsigned int)(x - 'A' + 10);
	}
	else if (x <= 'f' && x >= 'a')
	{
		return (unsigned int)(x - 'a' + 10);
	}
	else if (x <= '9' && x >= '0')
	{
		return (unsigned int)(x - '0');
	}
	return 0;
}

void md5_to_ints(unsigned char* md5, unsigned int *r0, unsigned int *r1, unsigned int *r2, unsigned int *r3)
{
	unsigned int v0 = 0, v1 = 0, v2 = 0, v3 = 0;
	int i = 0;
	for (i = 0; i < 32; i += 2)
	{
		unsigned int first = unhex(md5[i]);
		unsigned int second = unhex(md5[i + 1]);
		unsigned int both = first * 16 + second;
		both = both << 24;
		if (i < 8)
		{
			v0 = (v0 >> 8) | both;
		}
		else if (i < 16)
		{
			v1 = (v1 >> 8) | both;
		}
		else if (i < 24)
		{
			v2 = (v2 >> 8) | both;
		}
		else if (i < 32)
		{
			v3 = (v3 >> 8) | both;
		}
	}

	*r0 = v0;
	*r1 = v1;
	*r2 = v2;
	*r3 = v3;
}

/*
* This method is given a test password and the unsigned int of the orginal password and will check
* to see if it is the original passowrd
*
*/
__host__ __device__ int myencrypt(unsigned char * test, unsigned int length, unsigned int a, unsigned int b, unsigned int c, unsigned int d)
{
	unsigned int v1 = 0, v2 = 0, v3 = 0, v4 = 0;
	md5_vfy(test, length, &v1, &v2, &v3, &v4);
	if (v1 == a && v2 == b && v3 == c && v4 == d)
	{
		return 1;
	}
	else
		return 0;
}//end of crypt method

__device__ bool Compare(unsigned char* guess, unsigned int* hash) {
	return myencrypt(guess, MAX_PASSWORD_LENGTH, hash[0], hash[1], hash[2], hash[3]);
}

__global__ void square_array(char* a, unsigned int* hash) {
	int idx = threadIdx.x + blockDim.x * blockIdx.x;

	unsigned char guess[MAX_PASSWORD_LENGTH];

	if (idx < pow((double)ALPHABET_SIZE, (double)PREFIX_LENGTH)) {
		for (unsigned int i = 0; i < PREFIX_LENGTH; i++) {
			if (i == PREFIX_LENGTH - 1) {
				guess[i] = 'a' + idx % ALPHABET_SIZE;
			}
			else {
				unsigned int offset = PREFIX_LENGTH - i - 1;
				unsigned int t = idx % (int)(pow((double)ALPHABET_SIZE, (double)(offset + 1)));
				guess[i] = 'a' + t / (unsigned long long int)(pow((double)ALPHABET_SIZE, (double)offset));
			}
		}
	}
	int remainingLetters = MAX_PASSWORD_LENGTH - PREFIX_LENGTH;
	unsigned long i = 1;
	for (int j = 0; j < remainingLetters; j++) {
		i *= 26;
	}
	for (int pos = PREFIX_LENGTH; pos < MAX_PASSWORD_LENGTH; pos++) {
		guess[pos] = 'a';
	}
	while (true) {
		int tail;
		for (tail = MAX_PASSWORD_LENGTH - 1; tail >= PREFIX_LENGTH && guess[tail] == 'z'; tail--);
		if (tail < PREFIX_LENGTH) {
			break;
		}
		else {
			for (int j = MAX_PASSWORD_LENGTH - 1; j > tail; j--) {
				guess[j] = 'a';
			}
			guess[tail] += 1;
		}
		if (Compare(guess, hash)) {
			for (unsigned int jj = 0; jj < MAX_PASSWORD_LENGTH; jj++)
				a[jj] = guess[jj];
			break;
		}
	}
}

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
	if (code != hipSuccess)
	{
		fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
		if (abort) exit(code);
	}
}

int main() {
	unsigned char password[MAX_PASSWORD_LENGTH] = { 'p', 'a', 's', 's', 'w', 'o' };
	char* a_h, *a_d;
	size_t size = MAX_PASSWORD_LENGTH * sizeof(char);
	unsigned int* hash_h, *hash_d;
	hash_h = (unsigned int*)malloc(4 * sizeof(unsigned int));

	// calculate hash and verify it works
	md5_vfy(password, MAX_PASSWORD_LENGTH, &hash_h[0], &hash_h[1], &hash_h[2], &hash_h[3]);
	printf("hash: 0x%08X 0x%08X 0x%08X 0x%08X\n", hash_h[0], hash_h[1], hash_h[2], hash_h[3]);
	int res = myencrypt((unsigned char*)"password", MAX_PASSWORD_LENGTH, hash_h[0], hash_h[1], hash_h[2], hash_h[3]);
	printf("%d\n", res);

	// set array to a default value
	a_h = (char*)malloc(size + 1);
	for (unsigned int i = 0; i < size; i++) {
		a_h[i] = 'a' - 1;
	}
	a_h[size] = '\0';
	hipMalloc((void**)&a_d, size);	
	hipMalloc((void**)&hash_d, 4 * sizeof(unsigned int));
	hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
	hipMemcpy(hash_d, hash_h, 4 * sizeof(unsigned int), hipMemcpyHostToDevice);

	int threadsPerBlock = 1024;
	int numBlocks = ceil(pow(ALPHABET_SIZE, PREFIX_LENGTH) / threadsPerBlock);

	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);

	hipEventRecord(start);
	square_array<<<numBlocks, threadsPerBlock>>>(a_d, hash_d);
	hipEventRecord(stop);

	hipMemcpy(a_h, a_d, size, hipMemcpyDeviceToHost);

	printf("password: %s\n", a_h);

	hipEventSynchronize(stop);
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);
	printf("Done in: %f milliseconds\n", milliseconds);

	free(a_h);
	hipFree(a_d);
}

	.text
	.file	"main.hip"
	.globl	_Z7md5_vfyPhjPjS0_S0_S0_        # -- Begin function _Z7md5_vfyPhjPjS0_S0_S0_
	.type	_Z7md5_vfyPhjPjS0_S0_S0_,@function
_Z7md5_vfyPhjPjS0_S0_S0_:               # @_Z7md5_vfyPhjPjS0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 64(%rsp)                   # 8-byte Spill
	movq	%r8, 56(%rsp)                   # 8-byte Spill
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
                                        # kill: def $esi killed $esi def $rsi
	xorps	%xmm0, %xmm0
	movaps	%xmm0, -32(%rsp)
	movaps	%xmm0, -48(%rsp)
	movaps	%xmm0, -64(%rsp)
	movq	$0, -16(%rsp)
	testl	%esi, %esi
	je	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorl	%edx, %edx
	xorl	%r9d, %r9d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movzbl	(%rdi,%r9), %r8d
	movl	%edx, %ecx
	andb	$24, %cl
	shll	%cl, %r8d
	movl	%r9d, %ecx
	andl	$-4, %ecx
	orl	%r8d, -64(%rsp,%rcx)
	incq	%r9
	addl	$8, %edx
	cmpq	%r9, %rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	leal	(,%rsi,8), %ecx
	movl	$128, %eax
                                        # kill: def $cl killed $cl killed $ecx
	shll	%cl, %eax
	movl	%esi, %ecx
	andl	$-4, %ecx
	orl	%eax, -64(%rsp,%rcx)
	movl	-64(%rsp), %ecx
	movl	-60(%rsp), %r10d
	leal	-680876937(%rcx), %eax
	movq	%rcx, %r12
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	roll	$7, %eax
	movq	%rsi, %r11
	movl	$-271733879, %r9d               # imm = 0xEFCDAB89
	leal	(%rax,%r9), %ecx
	movl	%ecx, %edx
	andl	%r9d, %edx
	movl	$271733878, %esi                # imm = 0x10325476
	subl	%eax, %esi
	movl	$-1732584194, %edi              # imm = 0x98BADCFE
	andl	%edi, %esi
	orl	%edx, %esi
	leal	(%r10,%rsi), %edx
	addl	$-117830708, %edx               # imm = 0xF8FA0BCC
	movq	%r10, -72(%rsp)                 # 8-byte Spill
	roll	$12, %edx
	addl	%eax, %edx
	addl	$-271733879, %edx               # imm = 0xEFCDAB89
	movl	%ecx, %esi
	xorl	%r9d, %esi
	andl	%edx, %esi
	xorl	%r9d, %esi
	movl	-56(%rsp), %edi
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	addl	%edi, %esi
	addl	$-1126478375, %esi              # imm = 0xBCDB4DD9
	roll	$17, %esi
	addl	%edx, %esi
	movl	%edx, %edi
	xorl	%ecx, %edi
	andl	%esi, %edi
	xorl	%ecx, %edi
	movl	-52(%rsp), %ecx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	addl	%edi, %ecx
	addl	$-1316259209, %ecx              # imm = 0xB18B7A77
	roll	$22, %ecx
	addl	%esi, %ecx
	movl	%esi, %edi
	xorl	%edx, %edi
	andl	%ecx, %edi
	xorl	%edx, %edi
	movl	-48(%rsp), %r8d
	movq	%r8, -96(%rsp)                  # 8-byte Spill
	addl	%r8d, %eax
	addl	%edi, %eax
	addl	$-448152776, %eax               # imm = 0xE549BB38
	roll	$7, %eax
	addl	%ecx, %eax
	movl	%ecx, %edi
	xorl	%esi, %edi
	andl	%eax, %edi
	xorl	%esi, %edi
	movl	-44(%rsp), %r8d
	movl	%r8d, -116(%rsp)                # 4-byte Spill
	addl	%r8d, %edx
	addl	%edi, %edx
	addl	$1200080426, %edx               # imm = 0x4787C62A
	roll	$12, %edx
	addl	%eax, %edx
	movl	%eax, %edi
	xorl	%ecx, %edi
	andl	%edx, %edi
	xorl	%ecx, %edi
	movl	-40(%rsp), %r8d
	addl	%r8d, %esi
	movq	%r8, %r15
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	leal	(%rdi,%rsi), %r8d
	addl	$-1473231341, %r8d              # imm = 0xA8304613
	roll	$17, %r8d
	addl	%edx, %r8d
	movl	%edx, %esi
	xorl	%eax, %esi
	andl	%r8d, %esi
	xorl	%eax, %esi
	movl	-36(%rsp), %edi
	movl	%edi, -100(%rsp)                # 4-byte Spill
	addl	%edi, %ecx
	addl	%esi, %ecx
	addl	$-45705983, %ecx                # imm = 0xFD469501
	roll	$22, %ecx
	addl	%r8d, %ecx
	movl	%r8d, %esi
	xorl	%edx, %esi
	andl	%ecx, %esi
	xorl	%edx, %esi
	movl	-32(%rsp), %edi
	movl	%edi, -112(%rsp)                # 4-byte Spill
	addl	%edi, %eax
	addl	%esi, %eax
	addl	$1770035416, %eax               # imm = 0x698098D8
	roll	$7, %eax
	addl	%ecx, %eax
	movl	%ecx, %esi
	xorl	%r8d, %esi
	andl	%eax, %esi
	xorl	%r8d, %esi
	movl	-28(%rsp), %r13d
	addl	%r13d, %edx
	addl	%esi, %edx
	addl	$-1958414417, %edx              # imm = 0x8B44F7AF
	roll	$12, %edx
	addl	%eax, %edx
	movl	%eax, %esi
	xorl	%ecx, %esi
	andl	%edx, %esi
	xorl	%ecx, %esi
	movl	-24(%rsp), %edi
	addl	%edi, %r8d
	movl	%edi, %ebp
	movl	%edi, -108(%rsp)                # 4-byte Spill
	addl	%r8d, %esi
	addl	$-42063, %esi                   # imm = 0xFFFF5BB1
	roll	$17, %esi
	addl	%edx, %esi
	movl	%edx, %edi
	xorl	%eax, %edi
	andl	%esi, %edi
	xorl	%eax, %edi
	movl	-20(%rsp), %r8d
	addl	%r8d, %ecx
	movq	%r8, %rbx
	movq	%r8, -80(%rsp)                  # 8-byte Spill
	addl	%edi, %ecx
	addl	$-1990404162, %ecx              # imm = 0x895CD7BE
	roll	$22, %ecx
	addl	%esi, %ecx
	movl	%esi, %edi
	xorl	%edx, %edi
	andl	%ecx, %edi
	xorl	%edx, %edi
	movl	-16(%rsp), %r8d
	movl	%r8d, -104(%rsp)                # 4-byte Spill
	addl	%r8d, %eax
	addl	%eax, %edi
	addl	$1804603682, %edi               # imm = 0x6B901122
	roll	$7, %edi
	addl	%ecx, %edi
	movl	%ecx, %eax
	xorl	%esi, %eax
	andl	%edi, %eax
	xorl	%esi, %eax
	movl	-12(%rsp), %r8d
	movq	%r8, (%rsp)                     # 8-byte Spill
	addl	%r8d, %edx
	addl	%edx, %eax
	addl	$-40341101, %eax                # imm = 0xFD987193
	roll	$12, %eax
	addl	%edi, %eax
	movl	%eax, %edx
	andl	%edi, %edx
	movl	%eax, %r14d
	notl	%r14d
	movl	%ecx, %r8d
	andl	%r14d, %r8d
	orl	%edx, %r8d
	leal	(%rsi,%r11,8), %edx
	addl	%r8d, %edx
	addl	$-1502002290, %edx              # imm = 0xA679438E
	roll	$17, %edx
	addl	%eax, %edx
	movl	%edx, %esi
	andl	%eax, %esi
	movl	%edx, %r8d
	notl	%r8d
	leal	(%r10,%rdi), %r9d
	andl	%r8d, %edi
	orl	%esi, %edi
	leal	(%rcx,%rdi), %esi
	addl	$1236535329, %esi               # imm = 0x49B40821
	roll	$22, %esi
	addl	%edx, %esi
	movl	%esi, %ecx
	andl	%eax, %ecx
	andl	%edx, %r14d
	orl	%ecx, %r14d
	leal	(%r9,%r14), %ecx
	addl	$-165796510, %ecx               # imm = 0xF61E2562
	roll	$5, %ecx
	addl	%esi, %ecx
	movl	%ecx, %edi
	andl	%edx, %edi
	andl	%esi, %r8d
	orl	%edi, %r8d
	addl	%r15d, %eax
	addl	%r8d, %eax
	addl	$-1069501632, %eax              # imm = 0xC040B340
	roll	$9, %eax
	addl	%ecx, %eax
	movl	%eax, %edi
	xorl	%ecx, %edi
	andl	%esi, %edi
	xorl	%ecx, %edi
	addl	%ebx, %edx
	addl	%edi, %edx
	addl	$643717713, %edx                # imm = 0x265E5A51
	roll	$14, %edx
	addl	%eax, %edx
	movl	%edx, %edi
	xorl	%eax, %edi
	andl	%ecx, %edi
	xorl	%eax, %edi
	addl	%r12d, %esi
	addl	%edi, %esi
	addl	$-373897302, %esi               # imm = 0xE9B6C7AA
	roll	$20, %esi
	addl	%edx, %esi
	movl	%esi, %edi
	xorl	%edx, %edi
	andl	%eax, %edi
	xorl	%edx, %edi
	movl	-116(%rsp), %r15d               # 4-byte Reload
	addl	%r15d, %ecx
	leal	(%rdi,%rcx), %r14d
	addl	$-701558691, %r14d              # imm = 0xD62F105D
	roll	$5, %r14d
	addl	%esi, %r14d
	movl	%r14d, %ecx
	xorl	%esi, %ecx
	andl	%edx, %ecx
	xorl	%esi, %ecx
	addl	%ebp, %eax
	leal	(%rcx,%rax), %edi
	addl	$38016083, %edi                 # imm = 0x2441453
	roll	$9, %edi
	addl	%r14d, %edi
	movl	%edi, %eax
	xorl	%r14d, %eax
	andl	%esi, %eax
	xorl	%r14d, %eax
	addl	%edx, %eax
	addl	$-660478335, %eax               # imm = 0xD8A1E681
	roll	$14, %eax
	addl	%edi, %eax
	movl	%eax, %ecx
	xorl	%edi, %ecx
	andl	%r14d, %ecx
	xorl	%edi, %ecx
	movq	-96(%rsp), %r9                  # 8-byte Reload
	addl	%r9d, %esi
	addl	%esi, %ecx
	addl	$-405537848, %ecx               # imm = 0xE7D3FBC8
	roll	$20, %ecx
	addl	%eax, %ecx
	movl	%ecx, %edx
	xorl	%eax, %edx
	andl	%edi, %edx
	xorl	%eax, %edx
	movq	%r13, -88(%rsp)                 # 8-byte Spill
	addl	%r13d, %r14d
	addl	%r14d, %edx
	addl	$568446438, %edx                # imm = 0x21E1CDE6
	roll	$5, %edx
	addl	%ecx, %edx
	movl	%edx, %esi
	xorl	%ecx, %esi
	andl	%eax, %esi
	xorl	%ecx, %esi
	leal	(%rdi,%r11,8), %edi
	movq	%r11, %r8
	movq	%r11, -8(%rsp)                  # 8-byte Spill
	addl	%edi, %esi
	addl	$-1019803690, %esi              # imm = 0xC33707D6
	roll	$9, %esi
	addl	%edx, %esi
	movl	%esi, %edi
	xorl	%edx, %edi
	andl	%ecx, %edi
	xorl	%edx, %edi
	movq	16(%rsp), %rbp                  # 8-byte Reload
	addl	%ebp, %eax
	addl	%edi, %eax
	addl	$-187363961, %eax               # imm = 0xF4D50D87
	roll	$14, %eax
	addl	%esi, %eax
	movl	%eax, %edi
	xorl	%esi, %edi
	andl	%edx, %edi
	xorl	%esi, %edi
	movl	-112(%rsp), %r10d               # 4-byte Reload
	addl	%r10d, %ecx
	addl	%edi, %ecx
	addl	$1163531501, %ecx               # imm = 0x455A14ED
	roll	$20, %ecx
	addl	%eax, %ecx
	movl	%ecx, %edi
	xorl	%eax, %edi
	andl	%esi, %edi
	xorl	%eax, %edi
	movq	(%rsp), %r11                    # 8-byte Reload
	addl	%r11d, %edx
	addl	%edi, %edx
	addl	$-1444681467, %edx              # imm = 0xA9E3E905
	roll	$5, %edx
	addl	%ecx, %edx
	movl	%edx, %edi
	xorl	%ecx, %edi
	andl	%eax, %edi
	xorl	%ecx, %edi
	movq	32(%rsp), %rbx                  # 8-byte Reload
	addl	%ebx, %esi
	addl	%edi, %esi
	addl	$-51403784, %esi                # imm = 0xFCEFA3F8
	roll	$9, %esi
	addl	%edx, %esi
	movl	%esi, %edi
	xorl	%edx, %edi
	andl	%ecx, %edi
	xorl	%edx, %edi
	movl	-100(%rsp), %r12d               # 4-byte Reload
	addl	%r12d, %eax
	addl	%edi, %eax
	addl	$1735328473, %eax               # imm = 0x676F02D9
	roll	$14, %eax
	addl	%esi, %eax
	movl	%eax, %edi
	xorl	%esi, %edi
	andl	%edx, %edi
	xorl	%esi, %edi
	movl	-104(%rsp), %r13d               # 4-byte Reload
	addl	%r13d, %ecx
	leal	(%rdi,%rcx), %r14d
	addl	$-1926607734, %r14d             # imm = 0x8D2A4C8A
	roll	$20, %r14d
	addl	%eax, %r14d
	movl	%r14d, %ecx
	xorl	%eax, %ecx
	movl	%ecx, %edi
	xorl	%esi, %edi
	addl	%r15d, %edx
	addl	%edx, %edi
	addl	$-378558, %edi                  # imm = 0xFFFA3942
	roll	$4, %edi
	addl	%r14d, %edi
	xorl	%edi, %ecx
	addl	%r10d, %esi
	addl	%esi, %ecx
	addl	$-2022574463, %ecx              # imm = 0x8771F681
	roll	$11, %ecx
	addl	%edi, %ecx
	movl	%edi, %edx
	xorl	%r14d, %edx
	xorl	%ecx, %edx
	addl	-80(%rsp), %eax                 # 4-byte Folded Reload
	addl	%edx, %eax
	addl	$1839030562, %eax               # imm = 0x6D9D6122
	roll	$16, %eax
	addl	%ecx, %eax
	movl	%ecx, %edx
	xorl	%edi, %edx
	xorl	%eax, %edx
	leal	(%r14,%r8,8), %esi
	addl	%esi, %edx
	addl	$-35309556, %edx                # imm = 0xFDE5380C
	roll	$23, %edx
	addl	%eax, %edx
	movl	%eax, %esi
	xorl	%ecx, %esi
	xorl	%edx, %esi
	addl	-72(%rsp), %edi                 # 4-byte Folded Reload
	addl	%edi, %esi
	addl	$-1530992060, %esi              # imm = 0xA4BEEA44
	roll	$4, %esi
	addl	%edx, %esi
	movl	%edx, %edi
	xorl	%eax, %edi
	xorl	%esi, %edi
	addl	%r9d, %ecx
	addl	%edi, %ecx
	addl	$1272893353, %ecx               # imm = 0x4BDECFA9
	roll	$11, %ecx
	addl	%esi, %ecx
	movl	%esi, %edi
	xorl	%edx, %edi
	xorl	%ecx, %edi
	addl	%r12d, %eax
	addl	%edi, %eax
	addl	$-155497632, %eax               # imm = 0xF6BB4B60
	roll	$16, %eax
	addl	%ecx, %eax
	movl	%ecx, %edi
	xorl	%esi, %edi
	xorl	%eax, %edi
	movl	-108(%rsp), %r15d               # 4-byte Reload
	addl	%r15d, %edx
	addl	%edi, %edx
	addl	$-1094730640, %edx              # imm = 0xBEBFBC70
	roll	$23, %edx
	addl	%eax, %edx
	movl	%eax, %edi
	xorl	%ecx, %edi
	xorl	%edx, %edi
	addl	%r11d, %esi
	addl	%edi, %esi
	addl	$681279174, %esi                # imm = 0x289B7EC6
	roll	$4, %esi
	addl	%edx, %esi
	movl	%edx, %edi
	xorl	%eax, %edi
	xorl	%esi, %edi
	movq	8(%rsp), %r9                    # 8-byte Reload
	addl	%r9d, %ecx
	addl	%edi, %ecx
	addl	$-358537222, %ecx               # imm = 0xEAA127FA
	roll	$11, %ecx
	addl	%esi, %ecx
	movl	%esi, %edi
	xorl	%edx, %edi
	xorl	%ecx, %edi
	addl	%ebp, %eax
	addl	%eax, %edi
	addl	$-722521979, %edi               # imm = 0xD4EF3085
	roll	$16, %edi
	addl	%ecx, %edi
	movl	%ecx, %eax
	xorl	%esi, %eax
	xorl	%edi, %eax
	movq	24(%rsp), %r10                  # 8-byte Reload
	addl	%r10d, %edx
	leal	(%rax,%rdx), %r14d
	addl	$76029189, %r14d                # imm = 0x4881D05
	roll	$23, %r14d
	addl	%edi, %r14d
	movl	%edi, %eax
	xorl	%ecx, %eax
	xorl	%r14d, %eax
	addl	-88(%rsp), %esi                 # 4-byte Folded Reload
	addl	%eax, %esi
	addl	$-640364487, %esi               # imm = 0xD9D4D039
	roll	$4, %esi
	addl	%r14d, %esi
	movl	%r14d, %eax
	xorl	%edi, %eax
	xorl	%esi, %eax
	movl	%r13d, %r8d
	addl	%r13d, %ecx
	addl	%ecx, %eax
	addl	$-421815835, %eax               # imm = 0xE6DB99E5
	roll	$11, %eax
	addl	%esi, %eax
	movl	%esi, %ecx
	xorl	%r14d, %ecx
	xorl	%eax, %ecx
	leal	(%rcx,%rdi), %edx
	addl	$530742520, %edx                # imm = 0x1FA27CF8
	roll	$16, %edx
	addl	%eax, %edx
	movl	%eax, %ecx
	xorl	%esi, %ecx
	xorl	%edx, %ecx
	addl	%ebx, %r14d
	addl	%r14d, %ecx
	addl	$-995338651, %ecx               # imm = 0xC4AC5665
	addl	%r9d, %esi
	roll	$23, %ecx
	addl	%edx, %ecx
	movl	%eax, %edi
	notl	%edi
	orl	%ecx, %edi
	xorl	%edx, %edi
	leal	(%rdi,%rsi), %r13d
	addl	$-198630844, %r13d              # imm = 0xF4292244
	addl	%r12d, %eax
	roll	$6, %r13d
	addl	%ecx, %r13d
	movq	-8(%rsp), %rsi                  # 8-byte Reload
	leal	(%rdx,%rsi,8), %esi
                                        # kill: def $edx killed $edx killed $rdx def $rdx
	notl	%edx
	orl	%r13d, %edx
	xorl	%ecx, %edx
	leal	(%rdx,%rax), %r9d
	addl	$1126891415, %r9d               # imm = 0x432AFF97
	roll	$10, %r9d
	addl	%r13d, %r9d
	movl	%ecx, %eax
	notl	%eax
	orl	%r9d, %eax
	xorl	%r13d, %eax
	addl	%eax, %esi
	addl	$-1416354905, %esi              # imm = 0xAB9423A7
	roll	$15, %esi
	addl	-116(%rsp), %ecx                # 4-byte Folded Reload
	addl	%r9d, %esi
	movl	%r13d, %eax
	notl	%eax
	orl	%esi, %eax
	xorl	%r9d, %eax
	addl	%ecx, %eax
	addl	$-57434055, %eax                # imm = 0xFC93A039
	addl	%r8d, %r13d
	roll	$21, %eax
	addl	%esi, %eax
	movl	%r9d, %ecx
	notl	%ecx
	orl	%eax, %ecx
	xorl	%esi, %ecx
	leal	(%rcx,%r13), %edx
	addl	$1700485571, %edx               # imm = 0x655B59C3
	addl	%ebp, %r9d
	roll	$6, %edx
	addl	%eax, %edx
	movl	%esi, %ecx
	notl	%ecx
	orl	%edx, %ecx
	xorl	%eax, %ecx
	addl	%r9d, %ecx
	addl	$-1894986606, %ecx              # imm = 0x8F0CCC92
	addl	%r15d, %esi
	roll	$10, %ecx
	addl	%edx, %ecx
	movl	%eax, %edi
	notl	%edi
	orl	%ecx, %edi
	xorl	%edx, %edi
	addl	%edi, %esi
	addl	$-1051523, %esi                 # imm = 0xFFEFF47D
	roll	$15, %esi
	addl	-72(%rsp), %eax                 # 4-byte Folded Reload
	addl	%ecx, %esi
	movl	%edx, %edi
	notl	%edi
	orl	%esi, %edi
	xorl	%ecx, %edi
	addl	%edi, %eax
	addl	$-2054922799, %eax              # imm = 0x85845DD1
	addl	-112(%rsp), %edx                # 4-byte Folded Reload
	roll	$21, %eax
	addl	%esi, %eax
	movl	%ecx, %edi
	notl	%edi
	orl	%eax, %edi
	xorl	%esi, %edi
	addl	%edx, %edi
	addl	$1873313359, %edi               # imm = 0x6FA87E4F
	roll	$6, %edi
	addl	%eax, %edi
	addl	%esi, %r10d
	notl	%esi
	orl	%edi, %esi
	xorl	%eax, %esi
	addl	%esi, %ecx
	addl	$-30611744, %ecx                # imm = 0xFE2CE6E0
	roll	$10, %ecx
	addl	%edi, %ecx
	addl	%eax, %r11d
	notl	%eax
	orl	%ecx, %eax
	xorl	%edi, %eax
	leal	(%rax,%r10), %edx
	addl	$-1560198380, %edx              # imm = 0xA3014314
	roll	$15, %edx
	addl	%ecx, %edx
	movq	-96(%rsp), %rsi                 # 8-byte Reload
	addl	%edi, %esi
	notl	%edi
	orl	%edx, %edi
	xorl	%ecx, %edi
	leal	(%rdi,%r11), %eax
	addl	$1309151649, %eax               # imm = 0x4E0811A1
	roll	$21, %eax
	addl	%edx, %eax
	movq	-80(%rsp), %r9                  # 8-byte Reload
	addl	%ecx, %r9d
	notl	%ecx
	orl	%eax, %ecx
	xorl	%edx, %ecx
	addl	%esi, %ecx
	addl	$-145523070, %ecx               # imm = 0xF7537E82
	roll	$6, %ecx
	leal	(%rcx,%rax), %esi
	addl	$1732584193, %esi               # imm = 0x67452301
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	%esi, (%rdi)
	addl	%eax, %ecx
	addl	%edx, %ebx
	notl	%edx
	orl	%ecx, %edx
	xorl	%eax, %edx
	addl	%r9d, %edx
	addl	$-1120210379, %edx              # imm = 0xBD3AF235
	roll	$10, %edx
	addl	%ecx, %edx
	movl	%eax, %esi
	notl	%esi
	orl	%edx, %esi
	xorl	%ecx, %esi
	addl	%ebx, %esi
	addl	$718787259, %esi                # imm = 0x2AD7D2BB
	roll	$15, %esi
	movq	-88(%rsp), %rdi                 # 8-byte Reload
	addl	%eax, %edi
	addl	%edx, %esi
	notl	%ecx
	orl	%esi, %ecx
	xorl	%edx, %ecx
	leal	(%rcx,%rdi), %eax
	addl	$-343485551, %eax               # imm = 0xEB86D391
	roll	$21, %eax
	movl	$-271733879, %ecx               # imm = 0xEFCDAB89
	addl	%esi, %ecx
	addl	%eax, %ecx
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	%ecx, (%rax)
	movl	$-1732584194, %eax              # imm = 0x98BADCFE
	addl	%eax, %esi
	movq	56(%rsp), %rax                  # 8-byte Reload
	movl	%esi, (%rax)
	movl	$271733878, %eax                # imm = 0x10325476
	addl	%eax, %edx
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	%edx, (%rax)
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7md5_vfyPhjPjS0_S0_S0_, .Lfunc_end0-_Z7md5_vfyPhjPjS0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z5unhexh                       # -- Begin function _Z5unhexh
	.type	_Z5unhexh,@function
_Z5unhexh:                              # @_Z5unhexh
	.cfi_startproc
# %bb.0:
	movl	%edi, %eax
	leal	-65(%rax), %ecx
	cmpb	$5, %cl
	ja	.LBB1_3
# %bb.1:
	addl	$-55, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.LBB1_3:
	leal	-97(%rax), %ecx
	cmpb	$5, %cl
	ja	.LBB1_5
# %bb.4:
	addl	$-87, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.LBB1_5:
	leal	-48(%rax), %ecx
	addl	$-48, %eax
	xorl	%edx, %edx
	cmpb	$10, %cl
	cmovbl	%eax, %edx
	movl	%edx, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end1:
	.size	_Z5unhexh, .Lfunc_end1-_Z5unhexh
	.cfi_endproc
                                        # -- End function
	.globl	_Z11md5_to_intsPhPjS0_S0_S0_    # -- Begin function _Z11md5_to_intsPhPjS0_S0_S0_
	.type	_Z11md5_to_intsPhPjS0_S0_S0_,@function
_Z11md5_to_intsPhPjS0_S0_S0_:           # @_Z11md5_to_intsPhPjS0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%eax, %eax
	xorl	%r10d, %r10d
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	xorl	%r9d, %r9d
	xorl	%r11d, %r11d
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movzbl	(%rdi,%r10), %r14d
	leal	-65(%r14), %r15d
	cmpb	$5, %r15b
	ja	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	addl	$-55, %r14d
	jmp	.LBB2_6
.LBB2_3:                                #   in Loop: Header=BB2_1 Depth=1
	leal	-97(%r14), %r15d
	cmpb	$5, %r15b
	ja	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_1 Depth=1
	addl	$-87, %r14d
	jmp	.LBB2_6
.LBB2_5:                                #   in Loop: Header=BB2_1 Depth=1
	leal	-48(%r14), %r15d
	addl	$-48, %r14d
	cmpb	$10, %r15b
	cmovael	%eax, %r14d
.LBB2_6:                                # %_Z5unhexh.exit
                                        #   in Loop: Header=BB2_1 Depth=1
	movzbl	1(%rdi,%r10), %r15d
	leal	-65(%r15), %r12d
	cmpb	$5, %r12b
	ja	.LBB2_8
# %bb.7:                                #   in Loop: Header=BB2_1 Depth=1
	addl	$-55, %r15d
	jmp	.LBB2_11
.LBB2_8:                                #   in Loop: Header=BB2_1 Depth=1
	leal	-97(%r15), %r12d
	cmpb	$5, %r12b
	ja	.LBB2_10
# %bb.9:                                #   in Loop: Header=BB2_1 Depth=1
	addl	$-87, %r15d
	jmp	.LBB2_11
.LBB2_10:                               #   in Loop: Header=BB2_1 Depth=1
	leal	-48(%r15), %r12d
	addl	$-48, %r15d
	cmpb	$10, %r12b
	cmovael	%eax, %r15d
.LBB2_11:                               # %_Z5unhexh.exit40
                                        #   in Loop: Header=BB2_1 Depth=1
	shll	$28, %r14d
	shll	$24, %r15d
	addl	%r14d, %r15d
	cmpq	$7, %r10
	ja	.LBB2_13
# %bb.12:                               #   in Loop: Header=BB2_1 Depth=1
	shrl	$8, %ebp
	orl	%ebp, %r15d
	movl	%r15d, %ebp
	jmp	.LBB2_18
.LBB2_13:                               #   in Loop: Header=BB2_1 Depth=1
	cmpq	$15, %r10
	ja	.LBB2_15
# %bb.14:                               #   in Loop: Header=BB2_1 Depth=1
	shrl	$8, %ebx
	orl	%ebx, %r15d
	movl	%r15d, %ebx
	jmp	.LBB2_18
.LBB2_15:                               #   in Loop: Header=BB2_1 Depth=1
	cmpq	$23, %r10
	ja	.LBB2_17
# %bb.16:                               #   in Loop: Header=BB2_1 Depth=1
	shrl	$8, %r11d
	orl	%r11d, %r15d
	movl	%r15d, %r11d
	jmp	.LBB2_18
.LBB2_17:                               #   in Loop: Header=BB2_1 Depth=1
	shrl	$8, %r9d
	orl	%r9d, %r15d
	movl	%r15d, %r9d
.LBB2_18:                               #   in Loop: Header=BB2_1 Depth=1
	leaq	2(%r10), %r14
	cmpq	$30, %r10
	movq	%r14, %r10
	jb	.LBB2_1
# %bb.19:
	movl	%ebp, (%rsi)
	movl	%ebx, (%rdx)
	movl	%r11d, (%rcx)
	movl	%r9d, (%r8)
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z11md5_to_intsPhPjS0_S0_S0_, .Lfunc_end2-_Z11md5_to_intsPhPjS0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z9myencryptPhjjjjj             # -- Begin function _Z9myencryptPhjjjjj
	.type	_Z9myencryptPhjjjjj,@function
_Z9myencryptPhjjjjj:                    # @_Z9myencryptPhjjjjj
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	xorl	%eax, %eax
	leaq	20(%rsp), %r12
	movl	%eax, (%r12)
	leaq	16(%rsp), %r13
	movl	%eax, (%r13)
	leaq	12(%rsp), %r8
	movl	%eax, (%r8)
	leaq	8(%rsp), %r9
	movl	%eax, (%r9)
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	_Z7md5_vfyPhjPjS0_S0_S0_
	xorl	(%r12), %r15d
	xorl	(%r13), %r14d
	leaq	12(%rsp), %rax
	xorl	(%rax), %ebp
	orl	%r15d, %r14d
	orl	%r14d, %ebp
	leaq	8(%rsp), %rax
	xorl	(%rax), %ebx
	xorl	%eax, %eax
	orl	%ebp, %ebx
	sete	%al
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z9myencryptPhjjjjj, .Lfunc_end3-_Z9myencryptPhjjjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__square_arrayPcPj # -- Begin function _Z27__device_stub__square_arrayPcPj
	.type	_Z27__device_stub__square_arrayPcPj,@function
_Z27__device_stub__square_arrayPcPj:    # @_Z27__device_stub__square_arrayPcPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12square_arrayPcPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z27__device_stub__square_arrayPcPj, .Lfunc_end4-_Z27__device_stub__square_arrayPcPj
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	42(%rsp), %rbx
	movl	$1936941424, (%rbx)             # imm = 0x73736170
	movw	$28535, 4(%rbx)                 # imm = 0x6F77
	movl	$16, %edi
	callq	malloc
	movq	%rax, %r14
	leaq	4(%rax), %rcx
	leaq	8(%rax), %r8
	leaq	12(%rax), %r9
	movq	%rbx, %rdi
	movl	$6, %esi
	movq	%rax, %rdx
	callq	_Z7md5_vfyPhjPjS0_S0_S0_
	movl	(%r14), %ebx
	movl	4(%r14), %ebp
	movl	8(%r14), %r15d
	movl	12(%r14), %r12d
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%ebp, %edx
	movl	%r15d, %ecx
	movl	%r12d, %r8d
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	$6, %esi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	movl	%r15d, %r8d
	movl	%r12d, %r9d
	callq	_Z9myencryptPhjjjjj
	movl	$.L.str.2, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$7, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$1616928864, (%rax)             # imm = 0x60606060
	movw	$24672, 4(%rax)                 # imm = 0x6060
	movb	$0, 6(%rax)
	leaq	8(%rsp), %r15
	movl	$6, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r12
	movl	$16, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$6, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$16, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967743, %rdi               # imm = 0x1000001BF
	leaq	577(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z27__device_stub__square_arrayPcPj
.LBB5_2:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rsi
	movl	$6, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.3, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	36(%rsp), %r14
	movl	$0, (%r14)
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12square_arrayPcPj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12square_arrayPcPj,@object    # @_Z12square_arrayPcPj
	.section	.rodata,"a",@progbits
	.globl	_Z12square_arrayPcPj
	.p2align	3, 0x0
_Z12square_arrayPcPj:
	.quad	_Z27__device_stub__square_arrayPcPj
	.size	_Z12square_arrayPcPj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hash: 0x%08X 0x%08X 0x%08X 0x%08X\n"
	.size	.L.str, 35

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"password"
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d\n"
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"password: %s\n"
	.size	.L.str.3, 14

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Done in: %f milliseconds\n"
	.size	.L.str.4, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12square_arrayPcPj"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__square_arrayPcPj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12square_arrayPcPj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12square_arrayPcPj    ; -- Begin function _Z12square_arrayPcPj
	.globl	_Z12square_arrayPcPj
	.p2align	8
	.type	_Z12square_arrayPcPj,@function
_Z12square_arrayPcPj:                   ; @_Z12square_arrayPcPj
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_mov_b32 s33, exec_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr11
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmpx_gt_i32_e32 0x6f910, v1
	s_cbranch_execz .LBB0_9
; %bb.1:                                ; %.preheader59
	v_mul_hi_i32 v2, 0x4ec4ec4f, v1
	v_ashrrev_i32_e32 v0, 31, v1
	s_mov_b32 s8, 0xeaf01acd
	s_mov_b32 s10, 0x70df5b1b
	s_mov_b32 s14, 0x652b82fe
	s_mov_b32 s16, 0xfefa39ef
	s_mov_b32 s18, 0x3b39803f
	s_mov_b32 s20, 0xfca7ab0c
	v_lshrrev_b32_e32 v3, 31, v2
	v_lshrrev_b32_e32 v2, 3, v2
	s_mov_b32 s22, 0x6a5dcb37
	s_mov_b32 s24, 0x623fde64
	s_mov_b32 s26, 0x7c89e6b0
	s_mov_b32 s28, 0x14761f6e
	v_add_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, v1, v0
	s_mov_b32 s30, 0x1852b7b0
	s_mov_b32 s34, 0x11122322
	s_mov_b32 s36, 0x555502a1
	v_mul_lo_u32 v2, v2, 26
	s_mov_b32 s38, 0x55555511
	s_mov_b32 s40, 11
	s_mov_b32 s42, 0x55555555
	s_mov_b32 s44, 0x968915a9
	s_mov_b32 s46, 0x4222de17
	s_mov_b32 s48, 0x3abe935a
	s_mov_b32 s50, 0x47e6c9c2
	v_sub_nc_u32_e32 v2, v1, v2
	v_xor_b32_e32 v1, v3, v0
	s_mov_b32 s52, 0xcfa74449
	s_mov_b32 s54, 0x71bf3c30
	s_mov_b32 s56, 0x1c7792ce
	v_add_nc_u16 v2, v2, 0x61
	s_mov_b32 s58, 0x924920da
	s_mov_b32 s60, 0x9999999c
	s_mov_b32 s62, 0xd5df274d
	s_mov_b32 s68, 4
	s_mov_b64 s[6:7], 0
	s_mov_b32 s9, 0x400a1094
	s_mov_b32 s11, 0xbc9a0d94
	s_mov_b32 s12, 0
	s_mov_b32 s15, 0x3ff71547
	s_mov_b32 s17, 0xbfe62e42
	s_mov_b32 s19, 0xbc7abc9e
	s_mov_b32 s21, 0x3e928af3
	s_mov_b32 s23, 0x3e5ade15
	s_mov_b32 s25, 0x3ec71dee
	s_mov_b32 s27, 0x3efa0199
	s_mov_b32 s29, 0x3f2a01a0
	s_mov_b32 s31, 0x3f56c16c
	s_mov_b32 s35, 0x3f811111
	s_mov_b32 s37, 0x3fa55555
	s_mov_b32 s39, 0x3fc55555
	s_mov_b32 s41, 0x3fe00000
	s_mov_b32 s43, 0x3fe55555
	s_mov_b32 s45, 0x3fba6564
	s_mov_b32 s47, 0x3fbdee67
	s_mov_b32 s49, 0x3fbe25e4
	s_mov_b32 s51, 0x3fc110ef
	s_mov_b32 s53, 0x3fc3b13b
	s_mov_b32 s55, 0x3fc745d1
	s_mov_b32 s57, 0x3fcc71c7
	s_mov_b32 s59, 0x3fd24924
	s_mov_b32 s61, 0x3fd99999
	s_mov_b32 s63, 0x3c8543b0
	s_mov_b32 s69, 0x3ff00000
	s_mov_b32 s5, 0x3fe62e42
	s_mov_b32 s65, 0x3c7abc9e
	s_mov_b32 s67, 0xbfe55555
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr4
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_and_b32_e32 v5, 0xff, v8
	v_lshlrev_b16 v6, 8, v11
	v_and_b32_e32 v9, 0xff, v9
	s_cmp_lg_u32 s68, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v5, v5, v6
	v_lshlrev_b16 v6, 8, v10
	v_lshlrev_b32_e32 v8, 16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v7, 0xffff, v6
	v_or_b32_e32 v6, v9, v6
	v_or_b32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 8, v7
	s_cbranch_scc0 .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_u32_e32 v[9:10], s68
	s_xor_b32 s3, s6, 3
	s_mov_b32 s66, s42
	s_mov_b32 s4, s16
	s_mov_b32 s64, s18
	v_lshrrev_b32_e32 v8, 24, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b16 v8, 8, v8
	v_mul_f64 v[11:12], v[9:10], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[9:10], s[8:9], -v[11:12]
	v_cmp_eq_f64_e32 vcc_lo, 0x7ff00000, v[11:12]
	v_fma_f64 v[9:10], v[9:10], s[10:11], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[11:12], v[9:10]
	v_dual_cndmask_b32 v16, v14, v12 :: v_dual_cndmask_b32 v15, v13, v11
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f64 v[17:18], v[15:16], s[14:15]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[15:16]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[17:18], v[17:18]
	v_fma_f64 v[19:20], v[17:18], s[16:17], v[15:16]
	v_cvt_i32_f64_e32 v23, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], s[18:19], v[19:20]
	v_fma_f64 v[21:22], v[19:20], s[22:23], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[24:25]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[28:29]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[34:35]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[38:39]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], 1.0
	v_fma_f64 v[17:18], v[19:20], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[17:18], v[17:18], v23
	v_cndmask_b32_e32 v18, 0x7ff00000, v18, vcc_lo
	s_and_b32 vcc_lo, s2, vcc_lo
	s_cmp_eq_u32 s3, 0
	s_cselect_b32 s13, s69, 0x403a0000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, 0, v18, s2
	v_frexp_mant_f64_e32 v[19:20], s[12:13]
	v_cndmask_b32_e32 v17, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x204
	v_cmp_gt_f64_e64 s2, s[42:43], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, 1, s2
	v_ldexp_f64 v[19:20], v[19:20], v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[19:20], 1.0
	v_add_f64 v[27:28], v[19:20], -1.0
	v_rcp_f64_e32 v[23:24], v[21:22]
	v_add_f64 v[29:30], v[21:22], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], -v[29:30]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
	v_fma_f64 v[23:24], v[25:26], v[23:24], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
	v_fma_f64 v[23:24], v[25:26], v[23:24], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[25:26], v[27:28], v[23:24]
	v_mul_f64 v[31:32], v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[25:26], v[21:22], -v[31:32]
	v_fma_f64 v[19:20], v[25:26], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[31:32], v[19:20]
	v_add_f64 v[29:30], v[27:28], -v[21:22]
	v_add_f64 v[31:32], v[21:22], -v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[27:28], -v[29:30]
	v_add_f64 v[19:20], v[31:32], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[27:28], -v[21:22]
	v_add_f64 v[19:20], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[29:30], v[19:20]
	v_mul_f64 v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[25:26], v[19:20]
	v_add_f64 v[23:24], v[21:22], -v[25:26]
	v_mul_f64 v[25:26], v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], -v[23:24]
	v_fma_f64 v[23:24], v[21:22], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[19:20], v[19:20]
	v_fma_f64 v[23:24], v[21:22], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[25:26], v[23:24]
	v_fma_f64 v[29:30], v[27:28], s[46:47], s[44:45]
	v_add_f64 v[25:26], v[27:28], -v[25:26]
	v_mul_f64 v[35:36], v[21:22], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[48:49]
	v_add_f64 v[23:24], v[23:24], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[50:51]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[54:55]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[58:59]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[31:32], v[27:28], v[29:30]
	v_fma_f64 v[25:26], v[27:28], v[29:30], -v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[23:24], v[29:30], v[25:26]
	v_add_f64 v[29:30], v[31:32], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[29:30], s[42:43]
	v_add_f64 v[31:32], v[29:30], -v[31:32]
	v_add_f64 v[37:38], v[33:34], s[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[25:26], -v[31:32]
	v_fma_f64 v[31:32], v[27:28], v[21:22], -v[35:36]
	v_add_f64 v[29:30], v[29:30], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[25:26], s[62:63]
	v_fma_f64 v[27:28], v[27:28], v[19:20], v[31:32]
	v_ldexp_f64 v[19:20], v[19:20], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[25:26], v[29:30]
	v_fma_f64 v[23:24], v[23:24], v[21:22], v[27:28]
	v_ldexp_f64 v[21:22], v[21:22], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[33:34], v[25:26]
	v_add_f64 v[29:30], v[35:36], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[33:34], -v[27:28]
	v_mul_f64 v[33:34], v[29:30], v[27:28]
	v_add_f64 v[35:36], v[29:30], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[25:26], v[31:32]
	v_fma_f64 v[31:32], v[29:30], v[27:28], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[23:24], -v[35:36]
	v_fma_f64 v[25:26], v[29:30], v[25:26], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[25:26]
	v_frexp_exp_i32_f64_e32 v27, s[12:13]
	v_add_f64 v[25:26], v[33:34], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v27, s2, 0, v27, s2
	v_cvt_f64_i32_e32 v[27:28], v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[21:22], v[25:26]
	v_add_f64 v[31:32], v[25:26], -v[33:34]
	v_mul_f64 v[33:34], v[27:28], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[29:30], -v[21:22]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[31:32], v[27:28], s[4:5], -v[33:34]
	v_add_f64 v[21:22], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[23:24]
	v_fma_f64 v[23:24], v[27:28], s[64:65], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], v[21:22]
	v_add_f64 v[21:22], v[33:34], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[29:30], v[19:20]
	v_add_f64 v[33:34], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[21:22], v[25:26]
	v_add_f64 v[29:30], v[25:26], -v[29:30]
	v_add_f64 v[23:24], v[23:24], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[27:28], -v[21:22]
	v_add_f64 v[19:20], v[19:20], -v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[27:28], -v[31:32]
	v_add_f64 v[25:26], v[25:26], -v[31:32]
	v_add_f64 v[29:30], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	v_add_f64 v[21:22], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[29:30], -v[23:24]
	v_add_f64 v[21:22], v[29:30], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[29:30], -v[25:26]
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_add_f64 v[31:32], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[23:24], -v[29:30]
	v_add_f64 v[25:26], v[31:32], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], v[23:24]
	v_cvt_f64_u32_e32 v[23:24], s3
	v_add_f64 v[21:22], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], v[21:22]
	v_add_f64 v[21:22], v[31:32], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[21:22], -v[31:32]
	v_mul_f64 v[27:28], v[21:22], v[23:24]
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[23:24], v[21:22], -v[27:28]
	v_cmp_class_f64_e64 s2, v[27:28], 0x204
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[27:28], v[19:20]
	v_cndmask_b32_e64 v24, v22, v28, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, v21, v27, s2
	v_add_f64 v[21:22], v[21:22], -v[27:28]
	v_mul_f64 v[25:26], v[23:24], s[14:15]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[23:24]
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[23:24]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[23:24]
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	v_rndne_f64_e32 v[25:26], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, 0, v20, s2
	v_cndmask_b32_e64 v19, 0, v19, s2
	s_and_b32 s2, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], s[16:17], v[23:24]
	v_cvt_i32_f64_e32 v33, v[25:26]
	v_fma_f64 v[29:30], v[25:26], s[18:19], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], s[22:23], s[20:21]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[26:27]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[30:31]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[36:37]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[40:41]
	v_fma_f64 v[31:32], v[29:30], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], v[29:30], v[31:32], 1.0
	v_ldexp_f64 v[25:26], v[25:26], v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0x7ff00000, v26, s3
	v_cndmask_b32_e64 v22, 0, v21, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, v25, s2
	v_fma_f64 v[19:20], v[21:22], v[19:20], v[21:22]
	v_cmp_class_f64_e64 s2, v[21:22], 0x204
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v20, v22, s2
	v_cndmask_b32_e64 v19, v19, v21, s2
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[15:16]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f64_e64 v[19:20], |v[19:20]|
	v_cndmask_b32_e64 v10, 0, v10, s2
	v_cndmask_b32_e64 v9, 0, v9, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[13:14], v[19:20], 0xffffffe0
	v_fma_f64 v[9:10], v[17:18], v[9:10], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[11:12], v[13:14]
	v_dual_cndmask_b32 v10, v10, v18 :: v_dual_cndmask_b32 v9, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e64 v9, |v[9:10]|
	v_fma_f64 v[13:14], 0xc1f00000, v[11:12], v[19:20]
	v_cvt_u32_f64_e32 v15, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v9
	v_add_nc_u32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v12
	v_cvt_u32_f64_e32 v13, v[13:14]
	v_cvt_f32_u32_e32 v10, v15
	v_sub_nc_u32_e32 v14, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v11, v13
	v_sub_co_u32 v16, vcc_lo, 0, v13
	v_sub_co_ci_u32_e32 v17, vcc_lo, 0, v15, vcc_lo
	v_fmac_f32_e32 v11, 0x4f800000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v11
	v_cvt_f32_u32_e32 v11, v9
	v_rcp_iflag_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x5f7ffffc, v10
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v11, v11
	v_mul_lo_u32 v14, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v1, v11
	v_mul_lo_u32 v11, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v1, v11
	v_mul_f32_e32 v12, 0x2f800000, v10
	v_trunc_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, 0xcf800000, v12
	v_cvt_u32_f32_e32 v12, v12
	v_cvt_u32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v18, v16, v12
	v_mul_hi_u32 v19, v16, v10
	v_mul_lo_u32 v20, v17, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v18, v19, v18
	v_mul_lo_u32 v19, v16, v10
	v_add_nc_u32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v14, v10, v19
	v_mul_lo_u32 v20, v10, v18
	v_mul_hi_u32 v21, v10, v18
	v_mul_hi_u32 v22, v12, v19
	v_mul_lo_u32 v19, v12, v19
	v_mul_hi_u32 v23, v12, v18
	v_mul_lo_u32 v18, v12, v18
	v_add_co_u32 v14, vcc_lo, v14, v20
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v14, v19
	v_add_co_ci_u32_e32 v14, vcc_lo, v20, v22, vcc_lo
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v14, v18
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v19, vcc_lo
	v_sub_nc_u32_e32 v19, v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v10, v14
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v18, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v14, v16, v10
	v_mul_lo_u32 v17, v17, v10
	v_mul_lo_u32 v18, v16, v12
	v_mul_lo_u32 v16, v16, v10
	v_cndmask_b32_e32 v11, v11, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_u32_e32 vcc_lo, v11, v9
	v_add_nc_u32_e32 v14, v14, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v18, v10, v16
	v_add_nc_u32_e32 v14, v14, v17
	v_sub_nc_u32_e32 v17, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v19, v10, v14
	v_mul_hi_u32 v20, v10, v14
	v_cndmask_b32_e32 v9, v11, v17, vcc_lo
	v_mul_hi_u32 v11, v12, v16
	v_mul_lo_u32 v16, v12, v16
	v_mul_hi_u32 v17, v12, v14
	v_mul_lo_u32 v14, v12, v14
	v_xor_b32_e32 v9, v9, v0
	v_add_co_u32 v18, vcc_lo, v18, v19
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v18, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, v19, v11, vcc_lo
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v16, vcc_lo
	v_sub_nc_u32_e32 v16, v9, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, v12, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v16, v9
	v_mad_u64_u32 v[9:10], null, v16, v11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v12, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, v14, 0
	v_mad_u64_u32 v[11:12], null, v15, v14, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v9, vcc_lo, v16, v9
	v_sub_nc_u32_e32 v10, 0, v11
	v_sub_co_ci_u32_e64 v11, s2, 0, v11, vcc_lo
	s_lshl_b32 s2, s6, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v15, vcc_lo
	v_sub_co_u32 v12, vcc_lo, v9, v13
	s_lshl_b64 s[2:3], 0xff, s2
	v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v12, v13
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v10, v15
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v10, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v16, v12, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v9, v13
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v11, v15
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v10, 1, 2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v11, v15
	v_lshlrev_b16 v11, 8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v9 :: v_dual_add_nc_u32 v10, v14, v10
	v_and_b32_e32 v12, 0xff, v5
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or_b32_e32 v8, v12, v8
	v_dual_cndmask_b32 v9, v14, v10 :: v_dual_and_b32 v12, 0xff, v3
	v_and_b32_e32 v10, 0xff, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v8, 16, v8
	v_lshlrev_b16 v14, 8, v4
	v_add_nc_u16 v9, v9, 0x61
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, v10, v11
	v_lshlrev_b16 v13, 8, v9
	v_and_b32_e32 v9, 0xff, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v10, 0xffff, v10
	v_or_b32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v8, v10, v8
	v_and_b32_e32 v11, 0xffff, v9
	v_lshlrev_b32_e32 v9, 16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, v11, v9
	v_bfi_b32 v10, s2, v9, v8
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v8, 24, v10
	v_lshrrev_b32_e32 v11, 16, v10
	v_lshrrev_b32_e32 v13, 8, v10
	v_and_b32_e32 v10, 0xff, v10
	v_lshlrev_b16 v8, 8, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v11, 0xff, v11
	v_lshlrev_b16 v13, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v8, v11, v8
	v_or_b32_e32 v11, v12, v14
	v_and_b32_e32 v12, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 16, v8
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, v12, v14
	v_bfi_b32 v12, s3, v9, v11
	v_or_b32_e32 v9, v10, v13
	v_lshrrev_b32_e32 v11, 24, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v10, 8, v15
	v_lshrrev_b32_e32 v13, 8, v12
	s_branch .LBB0_5
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr11
.LBB0_5:                                ; %Flow127
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v7
	v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v11, v2
	v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v13, v4
.LBB0_7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s68, s68, -1
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s68, 0
	s_cbranch_scc0 .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v3, v12 :: v_dual_mov_b32 v4, v13
	s_branch .LBB0_2
.LBB0_9:                                ; %Flow129
	s_or_b32 exec_lo, exec_lo, s33
	v_dual_mov_b32 v25, 0 :: v_dual_and_b32 v0, 0xff, v8
	v_lshlrev_b16 v1, 8, v11
	v_lshlrev_b16 v2, 8, v10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v21, 0x61
	v_and_b32_e32 v3, 0xff, v9
	v_or_b32_e32 v26, v0, v1
	v_and_b32_e32 v0, 0xffff, v2
	s_mov_b32 s3, 0
	v_mov_b32_e32 v28, v21
	v_or_b32_e32 v20, v3, v2
	v_lshlrev_b32_e32 v1, 16, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v0, v0, v1
	v_lshrrev_b32_e32 v22, 24, v1
	v_lshrrev_b32_e32 v27, 8, v0
.LBB0_10:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
                                        ;     Child Loop BB0_17 Depth 2
	v_and_b32_e32 v0, 0xff, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b16 v1, 8, v27
	v_and_b32_e32 v2, 0xff, v26
	v_lshlrev_b16 v3, 8, v22
	v_and_b32_e32 v5, 0xff, v21
	s_mov_b64 s[0:1], 5
	v_or_b32_e32 v0, v0, v1
	s_mov_b32 s2, 0
	v_or_b32_e32 v1, v2, v3
	v_lshlrev_b16 v2, 8, v28
	s_mov_b32 s8, 6
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v1, 16, v1
	v_or_b32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v0, v0, v1
	v_and_b32_e32 v1, 0xffff, v2
.LBB0_11:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_lt_u32 s0, 4
	s_cselect_b32 s9, -1, 0
	s_lshl_b32 s10, s0, 3
	s_add_i32 s8, s8, -1
	v_lshrrev_b64 v[2:3], s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xff, v2
	v_cmp_ne_u16_e32 vcc_lo, 0x7a, v3
	v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
	v_mov_b32_e32 v4, s8
	s_or_b32 s9, s9, vcc_lo
	s_add_u32 s0, s0, -1
	s_addc_u32 s1, s1, -1
	s_and_b32 s9, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s9, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_11
; %bb.12:                               ; %.critedge
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s0, 0
	s_mov_b32 s8, exec_lo
	v_cmpx_lt_i32_e32 3, v4
	s_cbranch_execz .LBB0_20
; %bb.13:                               ; %.preheader56
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b128 v[16:19], v25, s[6:7]
	v_or_b32_e32 v5, 0x6100, v5
	v_cmp_eq_u32_e32 vcc_lo, 4, v4
	s_mov_b64 s[0:1], 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v0 :: v_dual_and_b32 v6, 0xffff, v5
	v_lshlrev_b32_e32 v3, 3, v3
	v_lshrrev_b64 v[7:8], v3, v[5:6]
	v_cndmask_b32_e32 v6, v1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v7, vcc_lo
	v_add_nc_u16 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b16 v4, 8, v2
	v_and_b32_e32 v2, 0xff, v2
	v_or_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, 0xffff, v2
	v_lshlrev_b32_e32 v5, 16, v2
	v_lshlrev_b64 v[1:2], v3, 0xff
	v_or_b32_e32 v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v20, v1, v3, v0
	v_bfi_b32 v21, v2, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v27, 8, v20
	v_and_b32_e32 v0, 0xff, v20
	v_lshrrev_b64 v[22:23], 24, v[20:21]
	v_lshrrev_b32_e32 v26, 16, v20
	v_lshrrev_b32_e32 v28, 8, v21
	v_lshlrev_b16 v1, 8, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b16 v3, 8, v22
	v_or_b32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xffff, v0
	v_mov_b32_e32 v0, 0
	v_dual_mov_b32 v5, v0 :: v_dual_and_b32 v2, 0xff, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_or_b32_e32 v1, v2, v3
	v_dual_mov_b32 v7, v0 :: v_dual_and_b32 v2, 0xff, v21
	v_lshlrev_b16 v3, 8, v28
	v_dual_mov_b32 v6, v0 :: v_dual_lshlrev_b32 v1, 16, v1
	v_mov_b32_e32 v8, v0
	v_mov_b32_e32 v9, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v2, v2, v3
	v_mov_b32_e32 v3, v0
	v_or_b32_e32 v23, v4, v1
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v4, v0
	v_dual_mov_b32 v11, v0 :: v_dual_and_b32 v24, 0xffff, v2
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v10, v0
	v_mov_b32_e32 v12, v0
	v_mov_b32_e32 v13, v0
.LBB0_14:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s9, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b64 v[14:15], s9, v[23:24]
	s_lshr_b32 s9, s0, 2
	s_mov_b32 m0, s9
	s_and_b32 s9, s2, 24
	v_movrels_b32_e32 v15, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_and_b32_e32 v14, 0xff, v14
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_add_i32 s2, s2, 8
	s_cmp_lg_u32 s0, 6
	v_lshl_or_b32 v14, v14, s9, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_movreld_b32_e32 v0, v14
	s_cbranch_scc1 .LBB0_14
; %bb.15:                               ; %_Z7ComparePhPj.exit
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_add_nc_u32_e32 v14, 0xd76aa477, v0
	v_or_b32_e32 v1, 0x800000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v14, v14, v14, 25
	v_sub_nc_u32_e32 v15, 0x10325476, v14
	v_add_nc_u32_e32 v29, 0xefcdab89, v14
	v_add_nc_u32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v15, 0x98badcfe, v15
	v_and_or_b32 v15, 0xefcdab89, v29, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v1, v15, 0xf8fa0bcc
	v_alignbit_b32 v15, v15, v15, 20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v29
	v_bfi_b32 v30, v15, v29, 0xefcdab89
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v2, v30, 0xbcdb4dd9
	v_alignbit_b32 v30, v30, v30, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v29, v30, v15, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v3, v29, 0xb18b7a77
	v_alignbit_b32 v29, v29, v29, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v29, v30, v15
	v_add_nc_u32_e32 v15, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0xe549bb38
	v_alignbit_b32 v14, v14, v14, 25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v14, v29, v30
	v_add_nc_u32_e32 v30, v6, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0x4787c62a
	v_alignbit_b32 v15, v15, v15, 20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v15, v14, v29
	v_add_nc_u32_e32 v29, v7, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xa8304613
	v_alignbit_b32 v30, v30, v30, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v30, v15, v14
	v_add_nc_u32_e32 v14, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0xfd469501
	v_alignbit_b32 v29, v29, v29, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v29, v30, v15
	v_add_nc_u32_e32 v15, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0x698098d8
	v_alignbit_b32 v14, v14, v14, 25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v14, v29, v30
	v_add_nc_u32_e32 v30, v10, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0x8b44f7af
	v_alignbit_b32 v15, v15, v15, 20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v15, v14, v29
	v_add_nc_u32_e32 v29, v11, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xffff5bb1
	v_alignbit_b32 v30, v30, v30, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v30, v15, v14
	v_add_nc_u32_e32 v14, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0x895cd7be
	v_alignbit_b32 v29, v29, v29, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v29, v30, v15
	v_add_nc_u32_e32 v15, v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0x6b901122
	v_alignbit_b32 v14, v14, v14, 25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v14, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xfd987193
	v_alignbit_b32 v15, v15, v15, 20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v15, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xa67943be
	v_alignbit_b32 v30, v30, v30, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v30, v15, v14
	v_add_nc_u32_e32 v14, v1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0x49b40821
	v_alignbit_b32 v29, v29, v29, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v15, v29, v30
	v_add_nc_u32_e32 v15, v6, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0xf61e2562
	v_alignbit_b32 v14, v14, v14, 27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v30, v14, v29
	v_add_nc_u32_e32 v30, v11, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xc040b340
	v_alignbit_b32 v15, v15, v15, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v29, v15, v14
	v_add_nc_u32_e32 v29, v0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0x265e5a51
	v_alignbit_b32 v30, v30, v30, 18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v14, v30, v15
	v_add_nc_u32_e32 v14, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0xe9b6c7aa
	v_alignbit_b32 v29, v29, v29, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v15, v29, v30
	v_add_nc_u32_e32 v15, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0xd62f105d
	v_alignbit_b32 v14, v14, v14, 27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v30, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0x2441453
	v_alignbit_b32 v15, v15, v15, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v29, v15, v14
	v_add_nc_u32_e32 v29, v4, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xd8a1e681
	v_alignbit_b32 v30, v30, v30, 18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v14, v30, v15
	v_add_nc_u32_e32 v14, v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0xe7d3fbc8
	v_alignbit_b32 v29, v29, v29, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v15, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0x21e1cde6
	v_alignbit_b32 v14, v14, v14, 27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v30, v14, v29
	v_add_nc_u32_e32 v30, v3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xc3370806
	v_alignbit_b32 v15, v15, v15, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v29, v15, v14
	v_add_nc_u32_e32 v29, v8, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xf4d50d87
	v_alignbit_b32 v30, v30, v30, 18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v14, v30, v15
	v_add_nc_u32_e32 v14, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0x455a14ed
	v_alignbit_b32 v29, v29, v29, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_bfi_b32 v31, v15, v29, v30
	v_add_nc_u32_e32 v15, v2, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0xa9e3e905
	v_alignbit_b32 v14, v14, v14, 27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_bfi_b32 v31, v30, v14, v29
	v_add_nc_u32_e32 v30, v7, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xfcefa3f8
	v_alignbit_b32 v15, v15, v15, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_bfi_b32 v31, v29, v15, v14
	v_add_nc_u32_e32 v29, v12, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0x676f02d9
	v_alignbit_b32 v30, v30, v30, 18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_bfi_b32 v31, v14, v30, v15
	v_add_nc_u32_e32 v14, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0x8d2a4c8a
	v_alignbit_b32 v29, v29, v29, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_xor_b32_e32 v31, v29, v30
	v_add_nc_u32_e32 v30, v11, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v32, v31, v15
	v_add_nc_u32_e32 v15, v8, v15
	v_add3_u32 v14, v14, v32, 0xfffa3942
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v14, v14, v14, 28
	v_add_nc_u32_e32 v14, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v31, v14, v31
	v_add3_u32 v15, v15, v31, 0x8771f681
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v15, v15, v15, 21
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v31, v15, v14
	v_add_nc_u32_e32 v14, v1, v14
	v_xor_b32_e32 v32, v31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v32, 0x6d9d6122
	v_alignbit_b32 v30, v30, v30, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_xor_b32_e32 v31, v30, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0xfde5383c
	v_alignbit_b32 v29, v29, v29, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_xor_b32_e32 v31, v29, v30
	v_add_nc_u32_e32 v30, v7, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v32, v31, v15
	v_add_nc_u32_e32 v15, v4, v15
	v_add3_u32 v14, v14, v32, 0xa4beea44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v14, v14, v14, 28
	v_add_nc_u32_e32 v14, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v31, v14, v31
	v_add3_u32 v15, v15, v31, 0x4bdecfa9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v15, v15, v15, 21
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v31, v15, v14
	v_add_nc_u32_e32 v14, v13, v14
	v_xor_b32_e32 v32, v31, v29
	v_add_nc_u32_e32 v29, v10, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v32, 0xf6bb4b60
	v_alignbit_b32 v30, v30, v30, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_xor_b32_e32 v31, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0xbebfbc70
	v_alignbit_b32 v29, v29, v29, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_xor3_b32 v31, v30, v15, v29
	v_add_nc_u32_e32 v15, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0x289b7ec6
	v_alignbit_b32 v14, v14, v14, 28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_xor3_b32 v31, v29, v30, v14
	v_add_nc_u32_e32 v30, v3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xeaa127fa
	v_alignbit_b32 v15, v15, v15, 21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_xor3_b32 v31, v14, v29, v15
	v_add_nc_u32_e32 v29, v6, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0xd4ef3085
	v_alignbit_b32 v30, v30, v30, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_xor3_b32 v31, v15, v14, v30
	v_add_nc_u32_e32 v14, v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v29, v31, 0x4881d05
	v_alignbit_b32 v29, v29, v29, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_xor3_b32 v31, v30, v15, v29
	v_add_nc_u32_e32 v15, v12, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v31, 0xd9d4d039
	v_alignbit_b32 v14, v14, v14, 28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v29
	v_xor3_b32 v31, v29, v30, v14
	v_add_nc_u32_e32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v31, 0xe6db99e5
	v_alignbit_b32 v15, v15, v15, 21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v14
	v_xor3_b32 v31, v14, v29, v15
	v_add_nc_u32_e32 v29, v2, v29
	v_add_nc_u32_e32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v30, v30, v31, 0x1fa27cf8
	v_alignbit_b32 v30, v30, v30, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v30, v30, v15
	v_xor3_b32 v31, v15, v14, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v29, v29, v31, 0xc4ac5665
	v_not_b32_e32 v31, v15
	v_alignbit_b32 v29, v29, v29, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v29, v30
	v_or_b32_e32 v31, v29, v31
	v_add_nc_u32_e32 v5, v5, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v31, v30
	v_add3_u32 v0, v0, v14, 0xf4292244
	v_not_b32_e32 v14, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v0, v0, v0, 26
	v_add_nc_u32_e32 v0, v0, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, v0, v14
	v_not_b32_e32 v15, v0
	v_xor_b32_e32 v14, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v7, v7, v14, 0x432aff97
	v_not_b32_e32 v14, v29
	v_alignbit_b32 v7, v7, v7, 22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v7, v0
	v_or_b32_e32 v14, v7, v14
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v14, v0
	v_add_nc_u32_e32 v0, v12, v0
	v_add3_u32 v14, v30, v14, 0xab9423d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v14, v14, v14, 17
	v_add_nc_u32_e32 v14, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, v14, v15
	v_add_nc_u32_e32 v10, v10, v14
	v_xor_b32_e32 v15, v15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v5, v5, v15, 0xfc93a039
	v_not_b32_e32 v15, v7
	v_alignbit_b32 v5, v5, v5, 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v14
	v_or_b32_e32 v15, v5, v15
	v_add_nc_u32_e32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v12, v15, v14
	v_add3_u32 v0, v0, v12, 0x655b59c3
	v_not_b32_e32 v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v0, v0, v0, 26
	v_add_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, v0, v12
	v_xor_b32_e32 v7, v12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v3, v7, 0x8f0ccc92
	v_not_b32_e32 v7, v5
	v_alignbit_b32 v3, v3, v3, 22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v0
	v_or_b32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v7, v7, v0
	v_add3_u32 v7, v10, v7, 0xffeff47d
	v_not_b32_e32 v10, v0
	v_add_nc_u32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v7, v7, v7, 17
	v_add_nc_u32_e32 v7, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, v7, v10
	v_add_nc_u32_e32 v6, v6, v7
	v_xor_b32_e32 v5, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v1, v5, 0x85845dd1
	v_not_b32_e32 v5, v3
	v_alignbit_b32 v1, v1, v1, 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v7
	v_or_b32_e32 v5, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v7
	v_add3_u32 v0, v0, v5, 0x6fa87e4f
	v_not_b32_e32 v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v0, v0, v0, 26
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v0, v5
	v_xor_b32_e32 v5, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v3, v5, 0xfe2ce6e0
	v_not_b32_e32 v5, v1
	v_add_nc_u32_e32 v1, v13, v1
	v_alignbit_b32 v3, v3, v3, 22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v0
	v_or_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v0
	v_add3_u32 v5, v6, v5, 0xa3014314
	v_not_b32_e32 v6, v0
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v5, v5, 17
	v_add_nc_u32_e32 v5, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v6, v5, v6
	v_add_nc_u32_e32 v2, v2, v5
	v_xor_b32_e32 v6, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v1, v1, v6, 0x4e0811a1
	v_not_b32_e32 v6, v3
	v_add_nc_u32_e32 v3, v11, v3
	v_alignbit_b32 v1, v1, v1, 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v5
	v_or_b32_e32 v6, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v6, v5
	v_add3_u32 v0, v0, v4, 0xf7537e82
	v_not_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v0, v0, v0, 26
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v4, v0, v4
	v_xor_b32_e32 v4, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v3, v4, 0xbd3af235
	v_not_b32_e32 v4, v1
	v_add_nc_u32_e32 v1, v9, v1
	v_alignbit_b32 v3, v3, v3, 22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v0
	v_or_b32_e32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v0
	v_add3_u32 v2, v2, v4, 0x2ad7d2bb
	v_not_b32_e32 v4, v0
	v_add_nc_u32_e32 v0, 0x67452301, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v2, v2, v2, 17
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v16
	v_add_nc_u32_e32 v0, 0x10325476, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_cmp_eq_u32_e64 s2, v0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v4, v2, v4
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v1, v4, 0xeb86d391
	v_alignbit_b32 v1, v1, v1, 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v2, v1, 0xefcdab89
	v_add_nc_u32_e32 v2, 0x98badcfe, v2
	v_cmp_eq_u32_e64 s0, v1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, v2, v18
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_19
; %bb.16:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_mov_b64 s[0:1], 0
.LBB0_17:                               ; %.preheader
                                        ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s9, s0, 3
	s_add_u32 s10, s4, s0
	v_lshrrev_b64 v[0:1], s9, v[23:24]
	s_addc_u32 s11, s5, s1
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 6
	global_store_b8 v25, v0, s[10:11]
	s_cbranch_scc1 .LBB0_17
; %bb.18:                               ; %Flow
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_xor_b32 s0, exec_lo, -1
.LBB0_19:                               ; %Flow124
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
.LBB0_20:                               ; %Flow125
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_xor_b32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s3, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_10
; %bb.21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12square_arrayPcPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 70
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12square_arrayPcPj, .Lfunc_end0-_Z12square_arrayPcPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7500
; NumSgprs: 72
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 72
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12square_arrayPcPj
    .private_segment_fixed_size: 0
    .sgpr_count:     72
    .sgpr_spill_count: 0
    .symbol:         _Z12square_arrayPcPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
