#include <cuda.h>  
// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernConvolve(float *data, 
                             float *kernels, 
                             float *dataOut, 
                             int signalLength, 
                             int kernelWidth, 
                             int numPtsPerBlock)
{
   // first fetch the data for this block. 

   extern __shared__ float sData[] ; 
   float *arrData = (float *) &sData[0] ; 
   float *arrKernel = (float *) &sData[numPtsPerBlock+kernelWidth-1] ; 

   // copy first the data vector.
   int dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x - kernelWidth/2; 
   int numPtsToCopy = numPtsPerBlock + kernelWidth-1 ; 
  
   for (int index = threadIdx.x ; index < numPtsToCopy ;
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      if (dataIndexInSignal < 0 || dataIndexInSignal >= signalLength)
         arrData[index] = 0 ; 
      else
         arrData[index] = data[dataIndexInSignal] ; 
   }

   __syncthreads() ; 

   // copy the kernel next. 
   int dataIndexInKernel = blockIdx.x * kernelWidth + threadIdx.x ;
  
   for (int index = threadIdx.x ; index < kernelWidth ; 
        index+= blockDim.x, dataIndexInKernel += blockDim.x)
   {
      arrKernel[index] = kernels[dataIndexInKernel] ; 
   }

   __syncthreads() ; 


   // perform the convolution and write out the result.

   //output position.
   dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x ; 

   for (int index = threadIdx.x ; index < numPtsPerBlock && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      float val = 0.0 ; 
      for (int wtIndex = 0 ; wtIndex < kernelWidth ; wtIndex++)
      {
         val += arrKernel[wtIndex] * arrData[index+wtIndex] ;
      }
      // index of output data point in signal
      int outIndex = blockIdx.x * signalLength + dataIndexInSignal ; 
      dataOut[outIndex] = val ; 
   }
}


// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernPartialConvolve(float *dPtrSignal1, float *dPtrSignal2, float *dPtrBlockProducts, 
                                int signalLength, int kernelWidth, int numPtsPerBlock)
{
   extern __shared__ float sData[] ; 
   float *arrData1 = (float *) &sData[0] ; 
   float *arrData2 = (float *) &sData[numPtsPerBlock] ; 

   // copy first data vector.
   int dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x ; 
  
   for (int index = threadIdx.x ; index < numPtsPerBlock && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      arrData1[index] = dPtrSignal1[dataIndexInSignal] ; 
   }

   __syncthreads() ; 

   // copy second data vector.
   int numPtsPerBlock2 = numPtsPerBlock + kernelWidth - 1 ;
   int signalIndex = blockIdx.x * signalLength ; 
   dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x - (kernelWidth-1)/2; 

   for (int index = threadIdx.x ; index < numPtsPerBlock2 && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      if (dataIndexInSignal < 0)
         arrData2[index] = 0  ; 
      else
         arrData2[index] = dPtrSignal2[signalIndex+dataIndexInSignal] ;
   }

   __syncthreads() ; 

   dataIndexInSignal = blockIdx.y * numPtsPerBlock ;
   int maxIndex = numPtsPerBlock+kernelWidth-1 ; 

   if (signalLength + (kernelWidth-1)/2-dataIndexInSignal < maxIndex)
      maxIndex = signalLength + (kernelWidth-1)/2 - dataIndexInSignal ; 

   int dataIndexInBlock = blockIdx.x*gridDim.y*kernelWidth + blockIdx.y ; 
   for (int shift = threadIdx.x ; shift < kernelWidth ; shift+=blockDim.x)
   {
      float val = 0.0 ; 
      for (int index = 0 ; index < numPtsPerBlock ; index++)
      {
         if (index+shift >= maxIndex)
            break ; 
         val += arrData1[index]*arrData2[index+shift] ; 
      }
      dPtrBlockProducts[dataIndexInBlock + (kernelWidth-1-shift)*gridDim.y] = val ; 
   }

}

// Kernel that sums the results from PartialConvolve. 
// Each kernel will have dimension of kernelWidth, so kernelWidth sums have to be computed per block.
// Each block will handle one dimension of a kernel sum. So the number of blocks is (kernel dimension) x (# of kernels)
__global__ void KernPartialConvolveSum(float *dPtrBlockProducts, float *dPtrResults,
                                int kernelWidth, int numPiecesPerKernel, 
                                int numKernels)
{
   // Results from partial convolve resulted in numPiecesPerKernel partial sums for 
   // every dimension of a kernel. Here a block has to sum these together.
   int  numPiecesPerThread = numPiecesPerKernel/blockDim.x ; 
   if (blockDim.x*numPiecesPerThread < numPiecesPerKernel)
      numPiecesPerThread++ ; 

   int startKernelIndex = blockIdx.x *  numPiecesPerKernel * kernelWidth ; 
   int startDataIndexForBlock = startKernelIndex + blockIdx.y * numPiecesPerKernel ; 
   int startDataIndexForThread = numPiecesPerThread*threadIdx.x ; 

   extern __shared__ float sData[] ; 

   int numToCopy1 = numPiecesPerThread ; 
   if (startDataIndexForThread + numToCopy1 > numPiecesPerKernel)
      numToCopy1 = numPiecesPerKernel - startDataIndexForThread ;

   float val = 0 ; 
   for (int index = 0 ; index < numToCopy1 ; index++)
   {
      val += dPtrBlockProducts[startDataIndexForBlock+startDataIndexForThread+index] ;
   }
   sData[threadIdx.x] = val ;

   __syncthreads() ; 


   for (unsigned int s=blockDim.x/2; s>0; s>>=1) 
   {
      if (threadIdx.x < s)
          sData[threadIdx.x] += sData[threadIdx.x + s];
      __syncthreads();
   }
   if (threadIdx.x == 0)
   {
      dPtrResults[blockIdx.y+kernelWidth*blockIdx.x] = sData[0] ; 
   }
  
}
__global__ void KernAddSignals(float *signals, float *sumSignals, int signalLength, 
                           int numSignals, int numPtsPerBlock, int numPtsPerThread)
{
   int startIndex = blockIdx.x * numPtsPerBlock + threadIdx.x * numPtsPerThread ;
   for (int ptNum = 0 ; ptNum < numPtsPerThread; ptNum++)
   {
      // index of data point in signal 
      int index = startIndex + ptNum ; 
      if (index >= signalLength)
         break ; 
     
     float val = 0 ;
     for (int signalNum = 0 ; signalNum < numSignals ; signalNum++)
     {
         val += signals[index+signalNum*signalLength] ;
     }
     sumSignals[index] = val ; 
   }
}

// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernReverseConvolve(float *signals, float *kernels, float *dataOut, int signalLength, int kernelWidth, 
                         int numKernels, int numPtsPerBlock, int numPtsPerThread)
{
   // can probably speed this up well by fetching kernels to local memory or put it in constant memory. 
   int kernelIndex = blockIdx.x ; 
   int signalStartIndex = kernelIndex * signalLength ; 
   int startIndex = blockIdx.y * numPtsPerBlock + threadIdx.x * numPtsPerThread ;
   for (int ptNum = 0 ; ptNum < numPtsPerThread; ptNum++)
   {
      // index of data point in signal 
      int index = startIndex + ptNum ; 
      if (index >= signalLength)
         break ; 
     
     float val = 0 ;
     int startIndexInKernel = kernelIndex*kernelWidth ;
     for (int wtIndex = 0 ; wtIndex < kernelWidth ; wtIndex++)
     {
        if (wtIndex + index >= signalLength + (kernelWidth-1)/2)
            break ;
         if (index+wtIndex < (kernelWidth-1)/2)
            continue ; 
         val += kernels[kernelWidth-1-wtIndex+startIndexInKernel] * 
                       signals[signalStartIndex + index + wtIndex - (kernelWidth-1)/2] ;
      }
      dataOut[signalStartIndex+index] = val ; 
   }
}



	.file	"tmpxft_003b81b3_00000000-6_Convolutions_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii
	.type	_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12KernConvolvePfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii
	.globl	_Z12KernConvolvePfS_S_iii
	.type	_Z12KernConvolvePfS_S_iii, @function
_Z12KernConvolvePfS_S_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12KernConvolvePfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE2033:
	.size	_Z12KernConvolvePfS_S_iii, .-_Z12KernConvolvePfS_S_iii
	.globl	_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii
	.type	_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii, @function
_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19KernPartialConvolvePfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii, .-_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii
	.globl	_Z19KernPartialConvolvePfS_S_iii
	.type	_Z19KernPartialConvolvePfS_S_iii, @function
_Z19KernPartialConvolvePfS_S_iii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19KernPartialConvolvePfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE2035:
	.size	_Z19KernPartialConvolvePfS_S_iii, .-_Z19KernPartialConvolvePfS_S_iii
	.globl	_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii
	.type	_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii, @function
_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22KernPartialConvolveSumPfS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii, .-_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii
	.globl	_Z22KernPartialConvolveSumPfS_iii
	.type	_Z22KernPartialConvolveSumPfS_iii, @function
_Z22KernPartialConvolveSumPfS_iii:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z22KernPartialConvolveSumPfS_iiiPfS_iii
	.cfi_endproc
.LFE2037:
	.size	_Z22KernPartialConvolveSumPfS_iii, .-_Z22KernPartialConvolveSumPfS_iii
	.globl	_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii
	.type	_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii, @function
_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z14KernAddSignalsPfS_iiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L18:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii, .-_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii
	.globl	_Z14KernAddSignalsPfS_iiii
	.type	_Z14KernAddSignalsPfS_iiii, @function
_Z14KernAddSignalsPfS_iiii:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z14KernAddSignalsPfS_iiiiPfS_iiii
	.cfi_endproc
.LFE2039:
	.size	_Z14KernAddSignalsPfS_iiii, .-_Z14KernAddSignalsPfS_iiii
	.globl	_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii
	.type	_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii, @function
_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z19KernReverseConvolvePfS_S_iiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L23:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii, .-_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii
	.globl	_Z19KernReverseConvolvePfS_S_iiiii
	.type	_Z19KernReverseConvolvePfS_S_iiiii, @function
_Z19KernReverseConvolvePfS_S_iiiii:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z19KernReverseConvolvePfS_S_iiiiiPfS_S_iiiii
	.cfi_endproc
.LFE2041:
	.size	_Z19KernReverseConvolvePfS_S_iiiii, .-_Z19KernReverseConvolvePfS_S_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19KernReverseConvolvePfS_S_iiiii"
.LC1:
	.string	"_Z14KernAddSignalsPfS_iiii"
.LC2:
	.string	"_Z22KernPartialConvolveSumPfS_iii"
.LC3:
	.string	"_Z19KernPartialConvolvePfS_S_iii"
.LC4:
	.string	"_Z12KernConvolvePfS_S_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19KernReverseConvolvePfS_S_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14KernAddSignalsPfS_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22KernPartialConvolveSumPfS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19KernPartialConvolvePfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12KernConvolvePfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>  
// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernConvolve(float *data, 
                             float *kernels, 
                             float *dataOut, 
                             int signalLength, 
                             int kernelWidth, 
                             int numPtsPerBlock)
{
   // first fetch the data for this block. 

   extern __shared__ float sData[] ; 
   float *arrData = (float *) &sData[0] ; 
   float *arrKernel = (float *) &sData[numPtsPerBlock+kernelWidth-1] ; 

   // copy first the data vector.
   int dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x - kernelWidth/2; 
   int numPtsToCopy = numPtsPerBlock + kernelWidth-1 ; 
  
   for (int index = threadIdx.x ; index < numPtsToCopy ;
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      if (dataIndexInSignal < 0 || dataIndexInSignal >= signalLength)
         arrData[index] = 0 ; 
      else
         arrData[index] = data[dataIndexInSignal] ; 
   }

   __syncthreads() ; 

   // copy the kernel next. 
   int dataIndexInKernel = blockIdx.x * kernelWidth + threadIdx.x ;
  
   for (int index = threadIdx.x ; index < kernelWidth ; 
        index+= blockDim.x, dataIndexInKernel += blockDim.x)
   {
      arrKernel[index] = kernels[dataIndexInKernel] ; 
   }

   __syncthreads() ; 


   // perform the convolution and write out the result.

   //output position.
   dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x ; 

   for (int index = threadIdx.x ; index < numPtsPerBlock && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      float val = 0.0 ; 
      for (int wtIndex = 0 ; wtIndex < kernelWidth ; wtIndex++)
      {
         val += arrKernel[wtIndex] * arrData[index+wtIndex] ;
      }
      // index of output data point in signal
      int outIndex = blockIdx.x * signalLength + dataIndexInSignal ; 
      dataOut[outIndex] = val ; 
   }
}


// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernPartialConvolve(float *dPtrSignal1, float *dPtrSignal2, float *dPtrBlockProducts, 
                                int signalLength, int kernelWidth, int numPtsPerBlock)
{
   extern __shared__ float sData[] ; 
   float *arrData1 = (float *) &sData[0] ; 
   float *arrData2 = (float *) &sData[numPtsPerBlock] ; 

   // copy first data vector.
   int dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x ; 
  
   for (int index = threadIdx.x ; index < numPtsPerBlock && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      arrData1[index] = dPtrSignal1[dataIndexInSignal] ; 
   }

   __syncthreads() ; 

   // copy second data vector.
   int numPtsPerBlock2 = numPtsPerBlock + kernelWidth - 1 ;
   int signalIndex = blockIdx.x * signalLength ; 
   dataIndexInSignal = blockIdx.y * numPtsPerBlock + threadIdx.x - (kernelWidth-1)/2; 

   for (int index = threadIdx.x ; index < numPtsPerBlock2 && dataIndexInSignal < signalLength ; 
        index+= blockDim.x, dataIndexInSignal += blockDim.x)
   {
      if (dataIndexInSignal < 0)
         arrData2[index] = 0  ; 
      else
         arrData2[index] = dPtrSignal2[signalIndex+dataIndexInSignal] ;
   }

   __syncthreads() ; 

   dataIndexInSignal = blockIdx.y * numPtsPerBlock ;
   int maxIndex = numPtsPerBlock+kernelWidth-1 ; 

   if (signalLength + (kernelWidth-1)/2-dataIndexInSignal < maxIndex)
      maxIndex = signalLength + (kernelWidth-1)/2 - dataIndexInSignal ; 

   int dataIndexInBlock = blockIdx.x*gridDim.y*kernelWidth + blockIdx.y ; 
   for (int shift = threadIdx.x ; shift < kernelWidth ; shift+=blockDim.x)
   {
      float val = 0.0 ; 
      for (int index = 0 ; index < numPtsPerBlock ; index++)
      {
         if (index+shift >= maxIndex)
            break ; 
         val += arrData1[index]*arrData2[index+shift] ; 
      }
      dPtrBlockProducts[dataIndexInBlock + (kernelWidth-1-shift)*gridDim.y] = val ; 
   }

}

// Kernel that sums the results from PartialConvolve. 
// Each kernel will have dimension of kernelWidth, so kernelWidth sums have to be computed per block.
// Each block will handle one dimension of a kernel sum. So the number of blocks is (kernel dimension) x (# of kernels)
__global__ void KernPartialConvolveSum(float *dPtrBlockProducts, float *dPtrResults,
                                int kernelWidth, int numPiecesPerKernel, 
                                int numKernels)
{
   // Results from partial convolve resulted in numPiecesPerKernel partial sums for 
   // every dimension of a kernel. Here a block has to sum these together.
   int  numPiecesPerThread = numPiecesPerKernel/blockDim.x ; 
   if (blockDim.x*numPiecesPerThread < numPiecesPerKernel)
      numPiecesPerThread++ ; 

   int startKernelIndex = blockIdx.x *  numPiecesPerKernel * kernelWidth ; 
   int startDataIndexForBlock = startKernelIndex + blockIdx.y * numPiecesPerKernel ; 
   int startDataIndexForThread = numPiecesPerThread*threadIdx.x ; 

   extern __shared__ float sData[] ; 

   int numToCopy1 = numPiecesPerThread ; 
   if (startDataIndexForThread + numToCopy1 > numPiecesPerKernel)
      numToCopy1 = numPiecesPerKernel - startDataIndexForThread ;

   float val = 0 ; 
   for (int index = 0 ; index < numToCopy1 ; index++)
   {
      val += dPtrBlockProducts[startDataIndexForBlock+startDataIndexForThread+index] ;
   }
   sData[threadIdx.x] = val ;

   __syncthreads() ; 


   for (unsigned int s=blockDim.x/2; s>0; s>>=1) 
   {
      if (threadIdx.x < s)
          sData[threadIdx.x] += sData[threadIdx.x + s];
      __syncthreads();
   }
   if (threadIdx.x == 0)
   {
      dPtrResults[blockIdx.y+kernelWidth*blockIdx.x] = sData[0] ; 
   }
  
}
__global__ void KernAddSignals(float *signals, float *sumSignals, int signalLength, 
                           int numSignals, int numPtsPerBlock, int numPtsPerThread)
{
   int startIndex = blockIdx.x * numPtsPerBlock + threadIdx.x * numPtsPerThread ;
   for (int ptNum = 0 ; ptNum < numPtsPerThread; ptNum++)
   {
      // index of data point in signal 
      int index = startIndex + ptNum ; 
      if (index >= signalLength)
         break ; 
     
     float val = 0 ;
     for (int signalNum = 0 ; signalNum < numSignals ; signalNum++)
     {
         val += signals[index+signalNum*signalLength] ;
     }
     sumSignals[index] = val ; 
   }
}

// Kernel that executes convolution. Nothing fancy is done. We don't even try to avoid
// block effects here.
__global__ void KernReverseConvolve(float *signals, float *kernels, float *dataOut, int signalLength, int kernelWidth, 
                         int numKernels, int numPtsPerBlock, int numPtsPerThread)
{
   // can probably speed this up well by fetching kernels to local memory or put it in constant memory. 
   int kernelIndex = blockIdx.x ; 
   int signalStartIndex = kernelIndex * signalLength ; 
   int startIndex = blockIdx.y * numPtsPerBlock + threadIdx.x * numPtsPerThread ;
   for (int ptNum = 0 ; ptNum < numPtsPerThread; ptNum++)
   {
      // index of data point in signal 
      int index = startIndex + ptNum ; 
      if (index >= signalLength)
         break ; 
     
     float val = 0 ;
     int startIndexInKernel = kernelIndex*kernelWidth ;
     for (int wtIndex = 0 ; wtIndex < kernelWidth ; wtIndex++)
     {
        if (wtIndex + index >= signalLength + (kernelWidth-1)/2)
            break ;
         if (index+wtIndex < (kernelWidth-1)/2)
            continue ; 
         val += kernels[kernelWidth-1-wtIndex+startIndexInKernel] * 
                       signals[signalStartIndex + index + wtIndex - (kernelWidth-1)/2] ;
      }
      dataOut[signalStartIndex+index] = val ; 
   }
}



	.text
	.file	"Convolutions_kernels.hip"
	.globl	_Z27__device_stub__KernConvolvePfS_S_iii # -- Begin function _Z27__device_stub__KernConvolvePfS_S_iii
	.type	_Z27__device_stub__KernConvolvePfS_S_iii,@function
_Z27__device_stub__KernConvolvePfS_S_iii: # @_Z27__device_stub__KernConvolvePfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12KernConvolvePfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__KernConvolvePfS_S_iii, .Lfunc_end0-_Z27__device_stub__KernConvolvePfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__KernPartialConvolvePfS_S_iii # -- Begin function _Z34__device_stub__KernPartialConvolvePfS_S_iii
	.type	_Z34__device_stub__KernPartialConvolvePfS_S_iii,@function
_Z34__device_stub__KernPartialConvolvePfS_S_iii: # @_Z34__device_stub__KernPartialConvolvePfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19KernPartialConvolvePfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__KernPartialConvolvePfS_S_iii, .Lfunc_end1-_Z34__device_stub__KernPartialConvolvePfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__KernPartialConvolveSumPfS_iii # -- Begin function _Z37__device_stub__KernPartialConvolveSumPfS_iii
	.type	_Z37__device_stub__KernPartialConvolveSumPfS_iii,@function
_Z37__device_stub__KernPartialConvolveSumPfS_iii: # @_Z37__device_stub__KernPartialConvolveSumPfS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22KernPartialConvolveSumPfS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z37__device_stub__KernPartialConvolveSumPfS_iii, .Lfunc_end2-_Z37__device_stub__KernPartialConvolveSumPfS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__KernAddSignalsPfS_iiii # -- Begin function _Z29__device_stub__KernAddSignalsPfS_iiii
	.type	_Z29__device_stub__KernAddSignalsPfS_iiii,@function
_Z29__device_stub__KernAddSignalsPfS_iiii: # @_Z29__device_stub__KernAddSignalsPfS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14KernAddSignalsPfS_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29__device_stub__KernAddSignalsPfS_iiii, .Lfunc_end3-_Z29__device_stub__KernAddSignalsPfS_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__KernReverseConvolvePfS_S_iiiii # -- Begin function _Z34__device_stub__KernReverseConvolvePfS_S_iiiii
	.type	_Z34__device_stub__KernReverseConvolvePfS_S_iiiii,@function
_Z34__device_stub__KernReverseConvolvePfS_S_iiiii: # @_Z34__device_stub__KernReverseConvolvePfS_S_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19KernReverseConvolvePfS_S_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z34__device_stub__KernReverseConvolvePfS_S_iiiii, .Lfunc_end4-_Z34__device_stub__KernReverseConvolvePfS_S_iiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12KernConvolvePfS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19KernPartialConvolvePfS_S_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22KernPartialConvolveSumPfS_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14KernAddSignalsPfS_iiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19KernReverseConvolvePfS_S_iiiii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12KernConvolvePfS_S_iii,@object # @_Z12KernConvolvePfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z12KernConvolvePfS_S_iii
	.p2align	3, 0x0
_Z12KernConvolvePfS_S_iii:
	.quad	_Z27__device_stub__KernConvolvePfS_S_iii
	.size	_Z12KernConvolvePfS_S_iii, 8

	.type	_Z19KernPartialConvolvePfS_S_iii,@object # @_Z19KernPartialConvolvePfS_S_iii
	.globl	_Z19KernPartialConvolvePfS_S_iii
	.p2align	3, 0x0
_Z19KernPartialConvolvePfS_S_iii:
	.quad	_Z34__device_stub__KernPartialConvolvePfS_S_iii
	.size	_Z19KernPartialConvolvePfS_S_iii, 8

	.type	_Z22KernPartialConvolveSumPfS_iii,@object # @_Z22KernPartialConvolveSumPfS_iii
	.globl	_Z22KernPartialConvolveSumPfS_iii
	.p2align	3, 0x0
_Z22KernPartialConvolveSumPfS_iii:
	.quad	_Z37__device_stub__KernPartialConvolveSumPfS_iii
	.size	_Z22KernPartialConvolveSumPfS_iii, 8

	.type	_Z14KernAddSignalsPfS_iiii,@object # @_Z14KernAddSignalsPfS_iiii
	.globl	_Z14KernAddSignalsPfS_iiii
	.p2align	3, 0x0
_Z14KernAddSignalsPfS_iiii:
	.quad	_Z29__device_stub__KernAddSignalsPfS_iiii
	.size	_Z14KernAddSignalsPfS_iiii, 8

	.type	_Z19KernReverseConvolvePfS_S_iiiii,@object # @_Z19KernReverseConvolvePfS_S_iiiii
	.globl	_Z19KernReverseConvolvePfS_S_iiiii
	.p2align	3, 0x0
_Z19KernReverseConvolvePfS_S_iiiii:
	.quad	_Z34__device_stub__KernReverseConvolvePfS_S_iiiii
	.size	_Z19KernReverseConvolvePfS_S_iiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12KernConvolvePfS_S_iii"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19KernPartialConvolvePfS_S_iii"
	.size	.L__unnamed_2, 33

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z22KernPartialConvolveSumPfS_iii"
	.size	.L__unnamed_3, 34

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z14KernAddSignalsPfS_iiii"
	.size	.L__unnamed_4, 27

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z19KernReverseConvolvePfS_S_iiiii"
	.size	.L__unnamed_5, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__KernConvolvePfS_S_iii
	.addrsig_sym _Z34__device_stub__KernPartialConvolvePfS_S_iii
	.addrsig_sym _Z37__device_stub__KernPartialConvolveSumPfS_iii
	.addrsig_sym _Z29__device_stub__KernAddSignalsPfS_iiii
	.addrsig_sym _Z34__device_stub__KernReverseConvolvePfS_S_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12KernConvolvePfS_S_iii
	.addrsig_sym _Z19KernPartialConvolvePfS_S_iii
	.addrsig_sym _Z22KernPartialConvolveSumPfS_iii
	.addrsig_sym _Z14KernAddSignalsPfS_iiii
	.addrsig_sym _Z19KernReverseConvolvePfS_S_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12KernConvolvePfS_S_iii ; -- Begin function _Z12KernConvolvePfS_S_iii
	.globl	_Z12KernConvolvePfS_S_iii
	.p2align	8
	.type	_Z12KernConvolvePfS_S_iii,@function
_Z12KernConvolvePfS_S_iii:              ; @_Z12KernConvolvePfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mov_b32 s16, exec_lo
	s_waitcnt lgkmcnt(0)
	s_add_i32 s7, s5, s6
	s_mul_i32 s15, s15, s6
	s_add_i32 s3, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s2, s[0:1], 0x34
	s_lshr_b32 s17, s5, 31
	v_lshl_add_u32 v3, v0, 2, 0
	s_add_i32 s17, s5, s17
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v4, v0
	s_ashr_i32 s18, s17, 1
	s_mov_b32 s19, 0
	s_sub_i32 s18, s15, s18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s17, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s20, s17, 2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s18, v4
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	v_cmp_gt_i32_e64 s2, s4, v1
	s_and_b32 s21, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s21
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v4, s17, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
	v_add_nc_u32_e32 v3, s20, v3
	v_cmp_le_i32_e32 vcc_lo, s3, v4
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow110
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s5, v0
	s_cbranch_execz .LBB0_8
; %bb.6:                                ; %.lr.ph64
	s_load_b32 s8, s[0:1], 0x34
	v_dual_mov_b32 v2, v0 :: v_dual_lshlrev_b32 v1, 2, v0
	s_lshl_b32 s7, s7, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_i32 s9, s7, 0
	s_mul_i32 s7, s14, s5
	v_add3_u32 v1, s9, v1, -4
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s16, s8, 2
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s7, v2
	v_add_nc_u32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s5, v2
	global_load_b32 v3, v[3:4], off
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v3
	v_add_nc_u32_e32 v1, s16, v1
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_7
.LBB0_8:                                ; %Flow107
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v1, s15, v0
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_14
; %bb.9:                                ; %.preheader.lr.ph
	s_load_b32 s0, s[0:1], 0x34
	s_lshl_b32 s2, s3, 2
	v_lshl_add_u32 v2, v0, 2, 0
	s_add_i32 s2, s2, 0
	s_cmp_gt_i32 s5, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s3, -1, 0
	s_mul_i32 s14, s14, s4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s8, s7, 2
.LBB0_10:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_12 Depth 2
	v_mov_b32_e32 v3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_13
; %bb.11:                               ; %.lr.ph68
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_mov_b32_e32 v4, v2
	s_mov_b32 s0, s2
	s_mov_b32 s9, s5
.LBB0_12:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, s0
	s_add_i32 s9, s9, -1
	s_add_i32 s0, s0, 4
	s_cmp_eq_u32 s9, 0
	ds_load_b32 v6, v4
	ds_load_b32 v5, v5
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v3, v5, v6 :: v_dual_add_nc_u32 v4, 4, v4
	s_cbranch_scc0 .LBB0_12
.LBB0_13:                               ; %._crit_edge69
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_add_nc_u32_e32 v4, s14, v1
	v_add_nc_u32_e32 v0, s7, v0
	v_add_nc_u32_e32 v1, s7, v1
	v_add_nc_u32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_le_i32_e32 vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e64 s0, s4, v1
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s1, s0, s1
	v_add_co_u32 v4, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_store_b32 v[4:5], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_10
.LBB0_14:                               ; %._crit_edge72
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12KernConvolvePfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12KernConvolvePfS_S_iii, .Lfunc_end0-_Z12KernConvolvePfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 724
; NumSgprs: 24
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19KernPartialConvolvePfS_S_iii ; -- Begin function _Z19KernPartialConvolvePfS_S_iii
	.globl	_Z19KernPartialConvolvePfS_S_iii
	.p2align	8
	.type	_Z19KernPartialConvolvePfS_S_iii,@function
_Z19KernPartialConvolvePfS_S_iii:       ; @_Z19KernPartialConvolvePfS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[16:17], s[0:1], 0x10
	s_mov_b32 s12, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s13, s15, s6
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_add_nc_u32_e32 v1, s13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s2, s[0:1], 0x34
	v_lshl_add_u32 v2, v0, 2, 0
	v_mov_b32_e32 v3, v0
	s_mov_b32 s15, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s18, s7, s13
	s_lshl_b32 s19, s7, 2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, s13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_add_nc_u32_e32 v5, s7, v3
	v_add_nc_u32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e32 vcc_lo, s6, v5
	v_cmp_le_i32_e64 s2, s4, v3
	v_mov_b32_e32 v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_b32 s2, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s15, s2, s15
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	v_add_nc_u32_e32 v2, s19, v2
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow121
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s7, s5, -1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s7, 31
	s_add_i32 s8, s7, s6
	s_add_i32 s2, s7, s2
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_ashr_i32 s9, s2, 1
	s_barrier
	v_subrev_nc_u32_e32 v1, s9, v1
	buffer_gl0_inv
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s15, vcc_lo, s2
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_and_saveexec_b32 s1, s15
	s_cbranch_execz .LBB1_8
; %bb.4:                                ; %.lr.ph78
	s_load_b32 s0, s[2:3], 0xc
	v_dual_mov_b32 v3, v0 :: v_dual_lshlrev_b32 v2, 2, v0
	s_lshl_b32 s18, s6, 2
	s_mul_i32 s15, s14, s4
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, 0, s18, v2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s0, 0xffff
	s_lshl_b32 s20, s18, 2
.LBB1_5:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v4, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=1
	v_add_nc_u32_e32 v4, s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
.LBB1_7:                                ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, s18, v3
	v_add_nc_u32_e32 v1, s18, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	v_add_nc_u32_e32 v2, s20, v2
	v_cmp_le_i32_e32 vcc_lo, s8, v3
	v_cmp_le_i32_e64 s0, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s19, s0, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB1_5
.LBB1_8:                                ; %Flow118
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s5, v0
	s_cbranch_execz .LBB1_17
; %bb.9:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b32 s0, s[2:3], 0xc
	s_load_b32 s1, s[2:3], 0x4
	s_add_i32 s9, s9, s4
	v_mov_b32_e32 v2, 0
	s_sub_i32 s2, s9, s13
	s_mul_i32 s14, s14, s5
	s_min_i32 s2, s2, s8
	s_cmp_gt_i32 s6, 0
	s_mov_b32 s8, 0
	s_cselect_b32 s3, -1, 0
	s_lshl_b32 s4, s6, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v1, v0, 2, s4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s0, 0xffff
	s_lshl_b32 s9, s4, 2
.LBB1_10:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_12 Depth 2
	v_mov_b32_e32 v3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_16
; %bb.11:                               ; %.lr.ph82.preheader
                                        ;   in Loop: Header=BB1_10 Depth=1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, 0
	s_mov_b32 s0, 0
	s_mov_b32 s11, 0
                                        ; implicit-def: $sgpr13
.LBB1_12:                               ; %.lr.ph82
                                        ;   Parent Loop BB1_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s11, v0
	s_or_b32 s13, s13, exec_lo
	s_mov_b32 s15, exec_lo
	v_cmpx_gt_i32_e64 s2, v4
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_12 Depth=2
	v_dual_mov_b32 v4, s10 :: v_dual_add_nc_u32 v5, s10, v1
	s_add_i32 s11, s11, 1
	s_add_i32 s10, s10, 4
	s_cmp_eq_u32 s6, s11
	ds_load_b32 v4, v4
	ds_load_b32 v5, v5
	s_cselect_b32 s18, -1, 0
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s18, s18, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s13, s18
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v4, v5
.LBB1_14:                               ; %Flow
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s15, exec_lo, s13
	s_or_b32 s0, s15, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_12
; %bb.15:                               ; %Flow113
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB1_16:                               ; %._crit_edge83
                                        ;   in Loop: Header=BB1_10 Depth=1
	v_sub_nc_u32_e32 v4, s7, v0
	v_add_nc_u32_e32 v0, s4, v0
	v_add_nc_u32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, s14, v4
	v_cmp_le_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v6, s1, s[12:13]
	v_mov_b32_e32 v5, v2
	s_or_b32 s8, vcc_lo, s8
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s16, v4
	v_add_co_ci_u32_e64 v5, s0, s17, v5, s0
	global_store_b32 v[4:5], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_10
.LBB1_17:                               ; %._crit_edge87
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19KernPartialConvolvePfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19KernPartialConvolvePfS_S_iii, .Lfunc_end1-_Z19KernPartialConvolvePfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 876
; NumSgprs: 23
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z22KernPartialConvolveSumPfS_iii ; -- Begin function _Z22KernPartialConvolveSumPfS_iii
	.globl	_Z22KernPartialConvolveSumPfS_iii
	.p2align	8
	.type	_Z22KernPartialConvolveSumPfS_iii,@function
_Z22KernPartialConvolveSumPfS_iii:      ; @_Z22KernPartialConvolveSumPfS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s2, 0xffff
	s_mul_i32 s4, s14, s4
	v_cvt_f32_u32_e32 v1, s6
	s_sub_i32 s3, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v1
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s3
	s_add_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s2, s5, s2
	s_mul_i32 s3, s2, s6
	s_add_i32 s7, s2, 1
	s_sub_i32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, s3, s6
	s_cmp_ge_u32 s3, s6
	s_cselect_b32 s2, s7, s2
	s_cselect_b32 s3, s8, s3
	s_add_i32 s7, s2, 1
	s_cmp_ge_u32 s3, s6
	s_cselect_b32 s7, s7, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s7, s6
	s_cmp_lt_u32 s2, s5
	s_load_b128 s[0:3], s[0:1], 0x0
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 vcc_lo, 0
	s_addc_u32 s8, s7, 0
	v_mul_lo_u32 v3, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
	v_sub_nc_u32_e32 v2, s5, v3
	s_mov_b32 s7, exec_lo
	v_cmp_lt_i32_e32 vcc_lo, s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, s8, v2, vcc_lo
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, 0
	v_cmpx_lt_i32_e32 0, v4
	s_cbranch_execz .LBB2_4
; %bb.1:                                ; %.lr.ph
	s_add_i32 s9, s4, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s9, s5, v[3:4]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v5, s5, v1
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, s5, v4
	global_load_b32 v3, v[5:6], off
	s_or_b32 s8, vcc_lo, s8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_2
; %bb.3:                                ; %Flow56
	s_or_b32 exec_lo, exec_lo, s8
.LBB2_4:                                ; %Flow57
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s6, 2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB2_5:                                ; %._crit_edge
                                        ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_9
; %bb.6:                                ; %.lr.ph42
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_lshr_b32 s0, s6, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_5 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB2_8:                                ;   in Loop: Header=BB2_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s6, 4
	s_mov_b32 s6, s0
	s_branch .LBB2_5
.LBB2_9:                                ; %._crit_edge43
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_11
; %bb.10:
	v_mov_b32_e32 v0, 0
	s_add_i32 s0, s4, s15
	s_mov_b32 s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	ds_load_b32 v1, v0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22KernPartialConvolveSumPfS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z22KernPartialConvolveSumPfS_iii, .Lfunc_end2-_Z22KernPartialConvolveSumPfS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14KernAddSignalsPfS_iiii ; -- Begin function _Z14KernAddSignalsPfS_iiii
	.globl	_Z14KernAddSignalsPfS_iiii
	.p2align	8
	.type	_Z14KernAddSignalsPfS_iiii,@function
_Z14KernAddSignalsPfS_iiii:             ; @_Z14KernAddSignalsPfS_iiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB3_8
; %bb.1:                                ; %.lr.ph31
	s_mul_i32 s6, s15, s6
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, v0, s7, s[6:7]
	s_cmp_gt_i32 s5, 0
	s_mov_b32 s10, s4
	s_cselect_b32 s6, -1, 0
	s_ashr_i32 s11, s4, 31
	s_mov_b32 s8, 0
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_lshl_b64 s[0:1], s[10:11], 2
                                        ; implicit-def: $sgpr10
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_5 Depth 2
	v_add_nc_u32_e32 v4, s9, v1
	s_or_b32 s10, s10, exec_lo
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v4
	s_cbranch_execz .LBB3_7
; %bb.3:                                ; %.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mov_b32_e32 v0, 0
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_6
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v5, v2
	s_mov_b32 s12, s5
.LBB3_5:                                ; %.lr.ph
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v7, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v7
	s_cbranch_scc0 .LBB3_5
.LBB3_6:                                ; %._crit_edge
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s9, s9, 1
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_cmp_eq_u32 s9, s7
	s_cselect_b32 s12, -1, 0
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s12, s12, exec_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_or_b32 s10, s10, s12
	global_store_b32 v[4:5], v0, off
.LBB3_7:                                ; %Flow56
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s10
	s_or_b32 s8, s11, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB3_2
.LBB3_8:                                ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14KernAddSignalsPfS_iiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z14KernAddSignalsPfS_iiii, .Lfunc_end3-_Z14KernAddSignalsPfS_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19KernReverseConvolvePfS_S_iiiii ; -- Begin function _Z19KernReverseConvolvePfS_S_iiiii
	.globl	_Z19KernReverseConvolvePfS_S_iiiii
	.p2align	8
	.type	_Z19KernReverseConvolvePfS_S_iiiii,@function
_Z19KernReverseConvolvePfS_S_iiiii:     ; @_Z19KernReverseConvolvePfS_S_iiiii
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB4_13
; %bb.1:                                ; %.lr.ph55
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mul_i32 s8, s15, s8
	s_mov_b32 s18, 0
	v_mad_u64_u32 v[1:2], null, v0, s9, s[8:9]
	v_mov_b32_e32 v0, 0
	s_mov_b32 s8, 0
                                        ; implicit-def: $sgpr19
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s7, 0
	s_mul_i32 s13, s14, s6
	s_cselect_b32 s12, -1, 0
	s_add_i32 s10, s7, -1
	s_mul_i32 s15, s14, s7
	s_lshr_b32 s11, s10, 31
	s_add_i32 s15, s15, s10
	s_add_i32 s11, s10, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s14, s11, 1
	s_add_i32 s16, s14, s6
	s_sub_i32 s17, s13, s14
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_5 Depth 2
	v_add_nc_u32_e32 v4, s18, v1
	s_or_b32 s19, s19, exec_lo
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v4
	s_cbranch_execz .LBB4_12
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_11
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v5, v2
	s_mov_b32 s21, 0
	s_mov_b32 s22, s7
	s_mov_b32 s10, s15
                                        ; implicit-def: $sgpr23
.LBB4_5:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_or_b32 s23, s23, exec_lo
	s_mov_b32 s24, exec_lo
	v_cmpx_gt_i32_e64 s16, v5
	s_cbranch_execz .LBB4_9
; %bb.6:                                ;   in Loop: Header=BB4_5 Depth=2
	s_mov_b32 s25, exec_lo
	v_cmpx_le_i32_e64 s14, v5
	s_cbranch_execz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_5 Depth=2
	v_add_nc_u32_e32 v6, s17, v5
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[26:27], s[10:11], 2
	s_add_u32 s26, s2, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	s_addc_u32 s27, s3, s27
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v8, v0, s[26:27]
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v8, v6
.LBB4_8:                                ;   in Loop: Header=BB4_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	s_add_i32 s22, s22, -1
	s_add_i32 s10, s10, -1
	s_cmp_eq_u32 s22, 0
	v_add_nc_u32_e32 v5, 1, v5
	s_cselect_b32 s11, -1, 0
	s_and_not1_b32 s23, s23, exec_lo
	s_and_b32 s11, s11, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, s11
.LBB4_9:                                ; %Flow
                                        ;   in Loop: Header=BB4_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s23
	s_or_b32 s21, s11, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB4_5
; %bb.10:                               ; %Flow84
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
.LBB4_11:                               ; %._crit_edge
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_add_nc_u32_e32 v4, s13, v4
	s_add_i32 s18, s18, 1
	v_add_nc_u32_e32 v2, 1, v2
	s_cmp_eq_u32 s18, s9
	s_cselect_b32 s10, -1, 0
	v_ashrrev_i32_e32 v5, 31, v4
	s_and_not1_b32 s11, s19, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s19, s11, s10
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_store_b32 v[4:5], v3, off
.LBB4_12:                               ; %Flow86
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, exec_lo, s19
	s_or_b32 s8, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB4_2
.LBB4_13:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19KernReverseConvolvePfS_S_iiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z19KernReverseConvolvePfS_S_iiiii, .Lfunc_end4-_Z19KernReverseConvolvePfS_S_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 468
; NumSgprs: 30
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12KernConvolvePfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z12KernConvolvePfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19KernPartialConvolvePfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z19KernPartialConvolvePfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22KernPartialConvolveSumPfS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22KernPartialConvolveSumPfS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14KernAddSignalsPfS_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14KernAddSignalsPfS_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19KernReverseConvolvePfS_S_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z19KernReverseConvolvePfS_S_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
