#include <cuda.h>
#include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define max(x, y) x > y ? x : y
#define TIME(f, msg) \
  _begin = clock(); \
  (f); \
  _end = clock(); \
  printf("%s done in %f\n", (msg), (float)(_end - _begin) / CLOCKS_PER_SEC);

void testRand(int *a, int n, int max) {
  for (int i = 0; i < n; i++) {
    a[i] = rand() % max;
  }
}

void print(char *pref, int *a, int n) {
  printf("%s", pref);
  for (int i = 0; i < n; i++)
    printf("%d ", a[i]);
  printf("\n");
}

int getMaxError(int *x, int *y, int n) {
  int max_error = -INT_MAX;
  for (int i = 0; i < n; i++) {
    max_error = max(max_error, abs(x[i] - y[i]));
  }
  return max_error;
}

void vectorAddSeq(int* h_a, int *h_b, int *h_c, int n) {
  for (int i = 0; i < n; i++) {
    h_c[i] = h_a[i] + h_b[i];
  }
}

__global__
void vectorAddKernel(int* d_a, int *d_b, int *d_c, int n) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < n) {
    d_c[i] = d_a[i] + d_b[i];
  }
}

void checkError(cudaError_t &err) {
  if (err != cudaSuccess) {
    printf("ERROR: %s in %s, line %d\n",cudaGetErrorString(err), __FILE__, __LINE__);
    exit(EXIT_FAILURE);
  }
}

void vectorAdd(int* h_a, int *h_b, int *h_c, int n, int num_thread) {
  int size = n * sizeof(int);
  int *d_a, *d_b, *d_c;
  cudaError_t err;
  
  err = cudaMalloc((void **) &d_a, size); checkError(err);
  err = cudaMalloc((void **) &d_b, size); checkError(err);
  err = cudaMalloc((void **) &d_c, size); checkError(err);
  
  err = cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice); checkError(err);
  err = cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice); checkError(err);
  
  int num_blocks = ceil((double)n / num_thread);
  vectorAddKernel<<<num_blocks, num_thread>>>(d_a, d_b, d_c, n);
  err = cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost); checkError(err);
  
  cudaDeviceSynchronize();
  
  err = cudaFree(d_a); checkError(err);
  err = cudaFree(d_b); checkError(err);
  err = cudaFree(d_c); checkError(err);
}

int main(int argc, char const *argv[]) {
  int n = 10000000;
  int num_threads = 256;
  int *a, *b, *c_seq, *c_par;
  clock_t _begin, _end;
  
  a = (int *) malloc(n * sizeof(int));
  b = (int *) malloc(n * sizeof(int));
  c_seq = (int *) malloc(n * sizeof(int));
  c_par = (int *) malloc(n * sizeof(int));

  testRand(a, n, 10);
  testRand(b, n, 10);

  TIME(vectorAddSeq(a, b, c_seq, n), "Sequential");
  TIME(vectorAdd(a, b, c_par, n, num_threads), "Parallel");
  
  if (n < 20) {
    print("Seq ", c_seq, n);
    print("Par ", c_par, n);
  }
  printf("Max error: %d\n", getMaxError(c_seq, c_par, n));

  free(a);
  free(b);
  free(c_seq);
  free(c_par);

  return 0;
}

	.file	"tmpxft_00356cd4_00000000-6_vectorAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8testRandPiii
	.type	_Z8testRandPiii, @function
_Z8testRandPiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
.L3:
	cmpl	%ebx, %r12d
	jle	.L7
	call	rand@PLT
	cltd
	idivl	%ebp
	movl	%edx, 0(%r13,%rbx,4)
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8testRandPiii, .-_Z8testRandPiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%s"
.LC1:
	.string	"%d "
.LC2:
	.string	"\n"
	.text
	.globl	_Z5printPcPii
	.type	_Z5printPcPii, @function
_Z5printPcPii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%eax, %eax
	leaq	.LC1(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edx, %ebp
	movq	%rdi, %rdx
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L9:
	cmpl	%ebx, %ebp
	jle	.L12
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L9
.L12:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC2(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5printPcPii, .-_Z5printPcPii
	.globl	_Z11getMaxErrorPiS_i
	.type	_Z11getMaxErrorPiS_i, @function
_Z11getMaxErrorPiS_i:
.LFB2029:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	movl	$-2147483647, %r8d
.L14:
	cmpl	%eax, %edx
	jle	.L16
	movl	(%rdi,%rax,4), %ecx
	subl	(%rsi,%rax,4), %ecx
	movl	%ecx, %r9d
	negl	%r9d
	cmovns	%r9d, %ecx
	cmpl	%ecx, %r8d
	cmovl	%ecx, %r8d
	incq	%rax
	jmp	.L14
.L16:
	movl	%r8d, %eax
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z11getMaxErrorPiS_i, .-_Z11getMaxErrorPiS_i
	.globl	_Z12vectorAddSeqPiS_S_i
	.type	_Z12vectorAddSeqPiS_S_i, @function
_Z12vectorAddSeqPiS_S_i:
.LFB2030:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L18:
	cmpl	%eax, %ecx
	jle	.L20
	movl	(%rsi,%rax,4), %r8d
	addl	(%rdi,%rax,4), %r8d
	movl	%r8d, (%rdx,%rax,4)
	incq	%rax
	jmp	.L18
.L20:
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z12vectorAddSeqPiS_S_i, .-_Z12vectorAddSeqPiS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/sebasvega95/HPC-assignments/master/CUDA/vectorAdd/vectorAdd.cu"
.LC4:
	.string	"ERROR: %s in %s, line %d\n"
	.text
	.globl	_Z10checkErrorR9cudaError
	.type	_Z10checkErrorR9cudaError, @function
_Z10checkErrorR9cudaError:
.LFB2031:
	.cfi_startproc
	endbr64
	movl	(%rdi), %edi
	testl	%edi, %edi
	je	.L21
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movl	$51, %r8d
	leaq	.LC3(%rip), %rcx
	movq	%rax, %rdx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L21:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z10checkErrorR9cudaError, .-_Z10checkErrorR9cudaError
	.globl	_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i
	.type	_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15vectorAddKernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i
	.globl	_Z15vectorAddKernelPiS_S_i
	.type	_Z15vectorAddKernelPiS_S_i, @function
_Z15vectorAddKernelPiS_S_i:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2059:
	.size	_Z15vectorAddKernelPiS_S_i, .-_Z15vectorAddKernelPiS_S_i
	.globl	_Z9vectorAddPiS_S_ii
	.type	_Z9vectorAddPiS_S_ii, @function
_Z9vectorAddPiS_S_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leal	0(,%rcx,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, 20(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	%rbx, %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	cvtsi2sdl	%r12d, %xmm1
	cvtsi2sdl	%ebp, %xmm0
	divsd	%xmm1, %xmm0
	call	ceil@PLT
	movl	%r12d, 60(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	cvttsd2sil	%xmm0, %edx
	movq	%rax, 64(%rsp)
	movl	68(%rsp), %ecx
	movq	%rax, 52(%rsp)
	movl	56(%rsp), %esi
	movl	%edx, 48(%rsp)
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%ebp, %ecx
	movq	24(%rsp), %rdi
	call	_Z40__device_stub__Z15vectorAddKernelPiS_S_iPiS_S_i
.L32:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	_Z10checkErrorR9cudaError
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z9vectorAddPiS_S_ii, .-_Z9vectorAddPiS_S_ii
	.section	.rodata.str1.1
.LC6:
	.string	"Sequential"
.LC7:
	.string	"%s done in %f\n"
.LC8:
	.string	"Parallel"
.LC9:
	.string	"Max error: %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$40000000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%rax
	.cfi_def_cfa_offset 64
	call	malloc@PLT
	movl	$40000000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$40000000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$40000000, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbp, %rdi
	movl	$10, %edx
	movl	$10000000, %esi
	movq	%rax, %r12
	call	_Z8testRandPiii
	movq	%rbx, %rdi
	movl	$10, %edx
	movl	$10000000, %esi
	call	_Z8testRandPiii
	call	clock@PLT
	movl	$10000000, %ecx
	movq	%r13, %rdx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	movq	%rax, %r14
	call	_Z12vectorAddSeqPiS_S_i
	call	clock@PLT
	leaq	.LC6(%rip), %rdx
	movl	$2, %edi
	subq	%r14, %rax
	leaq	.LC7(%rip), %r14
	movq	%r14, %rsi
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC5(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	call	clock@PLT
	movl	$10000000, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$256, %r8d
	movq	%rbp, %rdi
	movq	%rax, %r15
	call	_Z9vectorAddPiS_S_ii
	call	clock@PLT
	movq	%r14, %rsi
	movl	$2, %edi
	leaq	.LC8(%rip), %rdx
	subq	%r15, %rax
	cvtsi2ssq	%rax, %xmm0
	movb	$1, %al
	divss	.LC5(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%r12, %rsi
	movq	%r13, %rdi
	movl	$10000000, %edx
	call	_Z11getMaxErrorPiS_i
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movl	%eax, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	popq	%rdx
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z15vectorAddKernelPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15vectorAddKernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC5:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define max(x, y) x > y ? x : y
#define TIME(f, msg) \
  _begin = clock(); \
  (f); \
  _end = clock(); \
  printf("%s done in %f\n", (msg), (float)(_end - _begin) / CLOCKS_PER_SEC);

void testRand(int *a, int n, int max) {
  for (int i = 0; i < n; i++) {
    a[i] = rand() % max;
  }
}

void print(char *pref, int *a, int n) {
  printf("%s", pref);
  for (int i = 0; i < n; i++)
    printf("%d ", a[i]);
  printf("\n");
}

int getMaxError(int *x, int *y, int n) {
  int max_error = -INT_MAX;
  for (int i = 0; i < n; i++) {
    max_error = max(max_error, abs(x[i] - y[i]));
  }
  return max_error;
}

void vectorAddSeq(int* h_a, int *h_b, int *h_c, int n) {
  for (int i = 0; i < n; i++) {
    h_c[i] = h_a[i] + h_b[i];
  }
}

__global__
void vectorAddKernel(int* d_a, int *d_b, int *d_c, int n) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < n) {
    d_c[i] = d_a[i] + d_b[i];
  }
}

void checkError(hipError_t &err) {
  if (err != hipSuccess) {
    printf("ERROR: %s in %s, line %d\n",hipGetErrorString(err), __FILE__, __LINE__);
    exit(EXIT_FAILURE);
  }
}

void vectorAdd(int* h_a, int *h_b, int *h_c, int n, int num_thread) {
  int size = n * sizeof(int);
  int *d_a, *d_b, *d_c;
  hipError_t err;
  
  err = hipMalloc((void **) &d_a, size); checkError(err);
  err = hipMalloc((void **) &d_b, size); checkError(err);
  err = hipMalloc((void **) &d_c, size); checkError(err);
  
  err = hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice); checkError(err);
  err = hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice); checkError(err);
  
  int num_blocks = ceil((double)n / num_thread);
  vectorAddKernel<<<num_blocks, num_thread>>>(d_a, d_b, d_c, n);
  err = hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost); checkError(err);
  
  hipDeviceSynchronize();
  
  err = hipFree(d_a); checkError(err);
  err = hipFree(d_b); checkError(err);
  err = hipFree(d_c); checkError(err);
}

int main(int argc, char const *argv[]) {
  int n = 10000000;
  int num_threads = 256;
  int *a, *b, *c_seq, *c_par;
  clock_t _begin, _end;
  
  a = (int *) malloc(n * sizeof(int));
  b = (int *) malloc(n * sizeof(int));
  c_seq = (int *) malloc(n * sizeof(int));
  c_par = (int *) malloc(n * sizeof(int));

  testRand(a, n, 10);
  testRand(b, n, 10);

  TIME(vectorAddSeq(a, b, c_seq, n), "Sequential");
  TIME(vectorAdd(a, b, c_par, n, num_threads), "Parallel");
  
  if (n < 20) {
    print("Seq ", c_seq, n);
    print("Par ", c_par, n);
  }
  printf("Max error: %d\n", getMaxError(c_seq, c_par, n));

  free(a);
  free(b);
  free(c_seq);
  free(c_par);

  return 0;
}

	.text
	.file	"vectorAdd.hip"
	.globl	_Z8testRandPiii                 # -- Begin function _Z8testRandPiii
	.type	_Z8testRandPiii,@function
_Z8testRandPiii:                        # @_Z8testRandPiii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB0_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rdi, %r14
	movl	%esi, %r15d
	xorl	%r12d, %r12d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB0_2
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_4:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z8testRandPiii, .Lfunc_end0-_Z8testRandPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5printPcPii                   # -- Begin function _Z5printPcPii
	.type	_Z5printPcPii,@function
_Z5printPcPii:                          # @_Z5printPcPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %rsi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	testl	%ebp, %ebp
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movl	$10, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end1:
	.size	_Z5printPcPii, .Lfunc_end1-_Z5printPcPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11getMaxErrorPiS_i            # -- Begin function _Z11getMaxErrorPiS_i
	.type	_Z11getMaxErrorPiS_i,@function
_Z11getMaxErrorPiS_i:                   # @_Z11getMaxErrorPiS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB2_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%edx, %ecx
	movl	$-2147483647, %r8d              # imm = 0x80000001
	xorl	%edx, %edx
.LBB2_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rdi,%rdx,4), %r9d
	subl	(%rsi,%rdx,4), %r9d
	movl	%r9d, %eax
	negl	%eax
	cmovsl	%r9d, %eax
	cmpl	%eax, %r8d
	cmovgl	%r8d, %eax
	incq	%rdx
	movl	%eax, %r8d
	cmpq	%rdx, %rcx
	jne	.LBB2_4
# %bb.2:                                # %._crit_edge
	retq
.LBB2_1:
	movl	$-2147483647, %eax              # imm = 0x80000001
	retq
.Lfunc_end2:
	.size	_Z11getMaxErrorPiS_i, .Lfunc_end2-_Z11getMaxErrorPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12vectorAddSeqPiS_S_i         # -- Begin function _Z12vectorAddSeqPiS_S_i
	.type	_Z12vectorAddSeqPiS_S_i,@function
_Z12vectorAddSeqPiS_S_i:                # @_Z12vectorAddSeqPiS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ecx, %eax
	xorl	%ecx, %ecx
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rsi,%rcx,4), %r8d
	addl	(%rdi,%rcx,4), %r8d
	movl	%r8d, (%rdx,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB3_2
.LBB3_3:                                # %._crit_edge
	retq
.Lfunc_end3:
	.size	_Z12vectorAddSeqPiS_S_i, .Lfunc_end3-_Z12vectorAddSeqPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__vectorAddKernelPiS_S_i # -- Begin function _Z30__device_stub__vectorAddKernelPiS_S_i
	.type	_Z30__device_stub__vectorAddKernelPiS_S_i,@function
_Z30__device_stub__vectorAddKernelPiS_S_i: # @_Z30__device_stub__vectorAddKernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15vectorAddKernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z30__device_stub__vectorAddKernelPiS_S_i, .Lfunc_end4-_Z30__device_stub__vectorAddKernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z10checkErrorR10hipError_t     # -- Begin function _Z10checkErrorR10hipError_t
	.type	_Z10checkErrorR10hipError_t,@function
_Z10checkErrorR10hipError_t:            # @_Z10checkErrorR10hipError_t
	.cfi_startproc
# %bb.0:
	movl	(%rdi), %edi
	testl	%edi, %edi
	jne	.LBB5_2
# %bb.1:
	retq
.LBB5_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movl	$.L.str.4, %edx
	movq	%rax, %rsi
	movl	$51, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	_Z10checkErrorR10hipError_t, .Lfunc_end5-_Z10checkErrorR10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z9vectorAddPiS_S_ii            # -- Begin function _Z9vectorAddPiS_S_ii
	.type	_Z9vectorAddPiS_S_ii,@function
_Z9vectorAddPiS_S_ii:                   # @_Z9vectorAddPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbx
	leal	(,%r15,4), %eax
	movslq	%eax, %r14
	leaq	32(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	28(%rsp), %r13
	movl	%eax, (%r13)
	movq	%r13, %rdi
	callq	_Z10checkErrorR10hipError_t
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%eax, (%r13)
	movq	%r13, %rdi
	callq	_Z10checkErrorR10hipError_t
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%eax, (%r13)
	movq	%r13, %rdi
	callq	_Z10checkErrorR10hipError_t
	movq	(%r12), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, (%r13)
	movq	%r13, %rdi
	callq	_Z10checkErrorR10hipError_t
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, (%r13)
	movq	%r13, %rdi
	callq	_Z10checkErrorR10hipError_t
	cvtsi2sd	%r15d, %xmm0
	cvtsi2sd	%ebp, %xmm1
	divsd	%xmm1, %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %edi
	btsq	$32, %rdi
	movl	%ebp, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%r15d, %ecx
	callq	_Z30__device_stub__vectorAddKernelPiS_S_i
.LBB6_2:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	28(%rsp), %rbx
	movl	%eax, (%rbx)
	movq	%rbx, %rdi
	callq	_Z10checkErrorR10hipError_t
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rdi
	callq	hipFree
	movl	%eax, (%rbx)
	movq	%rbx, %rdi
	callq	_Z10checkErrorR10hipError_t
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	%eax, (%rbx)
	movq	%rbx, %rdi
	callq	_Z10checkErrorR10hipError_t
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	%eax, (%rbx)
	movq	%rbx, %rdi
	callq	_Z10checkErrorR10hipError_t
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z9vectorAddPiS_S_ii, .Lfunc_end6-_Z9vectorAddPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI7_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	malloc
	movq	%rax, %rbx
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	malloc
	movq	%rax, %r14
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	malloc
	movq	%rax, %r15
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	malloc
	movq	%rax, %r12
	xorl	%r13d, %r13d
.LBB7_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r13,4)
	incq	%r13
	cmpq	$10000000, %r13                 # imm = 0x989680
	jne	.LBB7_1
# %bb.2:                                # %.lr.ph.i32.preheader
	xorl	%r13d, %r13d
.LBB7_3:                                # %.lr.ph.i32
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%r13,4)
	incq	%r13
	cmpq	$10000000, %r13                 # imm = 0x989680
	jne	.LBB7_3
# %bb.4:                                # %_Z8testRandPiii.exit36
	xorl	%ebp, %ebp
	callq	clock
	movq	%rax, %r13
.LBB7_5:                                # %.lr.ph.i37
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rbp,4), %eax
	addl	(%rbx,%rbp,4), %eax
	movl	%eax, (%r15,%rbp,4)
	incq	%rbp
	cmpq	$10000000, %rbp                 # imm = 0x989680
	jne	.LBB7_5
# %bb.6:                                # %_Z12vectorAddSeqPiS_S_i.exit
	callq	clock
	subq	%r13, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI7_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %esi
	movb	$1, %al
	callq	printf
	callq	clock
	movq	%rax, %r13
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$10000000, %ecx                 # imm = 0x989680
	movl	$256, %r8d                      # imm = 0x100
	callq	_Z9vectorAddPiS_S_ii
	callq	clock
	subq	%r13, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI7_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.5, %edi
	movl	$.L.str.7, %esi
	movb	$1, %al
	callq	printf
	movl	$-2147483647, %esi              # imm = 0x80000001
	xorl	%eax, %eax
.LBB7_7:                                # %.lr.ph.i41
                                        # =>This Inner Loop Header: Depth=1
	movl	%esi, %ecx
	movl	(%r15,%rax,4), %edx
	subl	(%r12,%rax,4), %edx
	movl	%edx, %esi
	negl	%esi
	cmovsl	%edx, %esi
	cmpl	%esi, %ecx
	cmovgl	%ecx, %esi
	incq	%rax
	cmpq	$10000000, %rax                 # imm = 0x989680
	jne	.LBB7_7
# %bb.8:                                # %_Z11getMaxErrorPiS_i.exit
	movl	$.L.str.10, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15vectorAddKernelPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	_Z15vectorAddKernelPiS_S_i,@object # @_Z15vectorAddKernelPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15vectorAddKernelPiS_S_i
	.p2align	3, 0x0
_Z15vectorAddKernelPiS_S_i:
	.quad	_Z30__device_stub__vectorAddKernelPiS_S_i
	.size	_Z15vectorAddKernelPiS_S_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"ERROR: %s in %s, line %d\n"
	.size	.L.str.3, 26

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/sebasvega95/HPC-assignments/master/CUDA/vectorAdd/vectorAdd.hip"
	.size	.L.str.4, 126

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%s done in %f\n"
	.size	.L.str.5, 15

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Sequential"
	.size	.L.str.6, 11

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Parallel"
	.size	.L.str.7, 9

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Max error: %d\n"
	.size	.L.str.10, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15vectorAddKernelPiS_S_i"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__vectorAddKernelPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15vectorAddKernelPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15vectorAddKernelPiS_S_i ; -- Begin function _Z15vectorAddKernelPiS_S_i
	.globl	_Z15vectorAddKernelPiS_S_i
	.p2align	8
	.type	_Z15vectorAddKernelPiS_S_i,@function
_Z15vectorAddKernelPiS_S_i:             ; @_Z15vectorAddKernelPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15vectorAddKernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15vectorAddKernelPiS_S_i, .Lfunc_end0-_Z15vectorAddKernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15vectorAddKernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15vectorAddKernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
