#include "cuda_runtime.h"
#include <stdio.h>
#include <time.h>

const int Row = 2 * 2;
const int Col = 2 * 2;

//2维网格2维线程块  最常用
__global__ void VectorAdd(float** a, float** b, float** c) {
    int thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;   //x是线程块的x做行 线程的x做列
    int thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;   //y是线程块的y做行 线程的y做列
    //printf("blockIdx.y/x: %d/%d\tblockDim.y/x: %d/%d\tthreadIdx.y/x: %d/%d\tthread_y/x: %d/%d\n", blockIdx.y, blockIdx.x, blockDim.y, blockDim.x, threadIdx.y, threadIdx.x, thread_y_id, thread_x_id);
    if (thread_x_id < Col && thread_y_id < Row) {
        c[thread_y_id][thread_x_id] = a[thread_y_id][thread_x_id] + b[thread_y_id][thread_x_id];
    }
}

int main() {
    int start = clock();
    //二维指针 指向一维指针（数据指针）
    float* a[Row] = { NULL };
    float* b[Row] = { NULL };
    float* c[Row] = { NULL };
    float data_a[Row * Col] = { 0.0 };
    float data_b[Row * Col] = { 0.0 };
    float data_c[Row * Col] = { 0.0 };

    //二维指针 指向一维指针（数据指针）
    float** device_a = NULL;
    float** device_b = NULL;
    float** device_c = NULL;
    float* device_data_a = NULL;
    float* device_data_b = NULL;
    float* device_data_c = NULL;

    //分配显存
    cudaMalloc((void**)&device_a, sizeof(float*) * Row);
    cudaMalloc((void**)&device_b, sizeof(float*) * Row);
    cudaMalloc((void**)&device_c, sizeof(float*) * Row);
    cudaMalloc((void**)&device_data_a, sizeof(float) * Row * Col);
    cudaMalloc((void**)&device_data_b, sizeof(float) * Row * Col);
    cudaMalloc((void**)&device_data_c, sizeof(float) * Row * Col);

    for (int i = 0; i < Row * Col; i++) {
        data_a[i] = i;
        data_b[i] = i;
    }
    
    //主机二级指针存放着设备一级指针（数据指针）的地址
    //再通过cudacopy 传给设备二级指针 让设备二级指针和设备一级指针关联（数据指针）
    //而设备一级指针已经通过主机一级指针cudacopy了
    for (int i = 0; i < Row; i++) {
        a[i] = device_data_a + i * Col;
        b[i] = device_data_b + i * Col;
        c[i] = device_data_c + i * Col;
    }

    //将内存中a和b数组的值复制到GPU中显存中
    cudaMemcpy(device_a, a, sizeof(float*) * Row, cudaMemcpyHostToDevice);
    cudaMemcpy(device_b, b, sizeof(float*) * Row, cudaMemcpyHostToDevice);
    cudaMemcpy(device_c, c, sizeof(float*) * Row, cudaMemcpyHostToDevice);
    cudaMemcpy(device_data_a, data_a, sizeof(float) * Row * Col, cudaMemcpyHostToDevice);
    cudaMemcpy(device_data_b, data_b, sizeof(float) * Row * Col, cudaMemcpyHostToDevice);

    //一个kernel函数由一个gpu的一个grid执行  
    //调用核函数 cpu调用 gpu运行 
    dim3 dim_block(16, 32);      //一个线程块block包含 512个线程threads(最多不超过512个)
    dim3 dim_grid((Col + dim_block.x - 1) / dim_block.x, (Row + dim_block.y - 1) / dim_block.y); //一个grid网格包含n / 512个线程块blocks(为了充分利用sm blocks尽可能多)
    VectorAdd<<<dim_grid, dim_block>>>(device_a, device_b, device_c);

    //1级指针设备 给1级指针主机 赋值
    cudaMemcpy(data_c, device_data_c, sizeof(float) * Row * Col, cudaMemcpyDeviceToHost);
    
    for (int i = 0; i < Row * Col; i++) 
        printf("%.0f + %.0f = %.0f\t", data_a[i], data_b[i], data_c[i]);
    int end = clock();
    printf("\n程序耗时：%ds\n", (end - start) / 1000);
   

    //释放gpu显存
    cudaFree(device_a);
    cudaFree(device_b);
    cudaFree(device_c);
    cudaFree(device_data_a);
    cudaFree(device_data_b);
    cudaFree(device_data_c);

    return 0;
}

	.file	"tmpxft_002ad19c_00000000-6_dim2_vector_add.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_
	.type	_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_, @function
_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9VectorAddPPfS0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_, .-_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_
	.globl	_Z9VectorAddPPfS0_S0_
	.type	_Z9VectorAddPPfS0_S0_, @function
_Z9VectorAddPPfS0_S0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_
	.cfi_endproc
.LFE2053:
	.size	_Z9VectorAddPPfS0_S0_, .-_Z9VectorAddPPfS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%.0f + %.0f = %.0f\t"
.LC1:
	.string	"\n\347\250\213\345\272\217\350\200\227\346\227\266\357\274\232%ds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$376, %rsp
	.cfi_def_cfa_offset 432
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %r15
	leaq	136(%rsp), %rbx
	call	clock@PLT
	leaq	72(%rsp), %rdi
	movl	$8, %ecx
	movl	$32, %esi
	movq	%rax, %rbp
	xorl	%eax, %eax
	leaq	168(%rsp), %r13
	rep stosl
	leaq	104(%rsp), %rdi
	movl	$8, %ecx
	leaq	232(%rsp), %r12
	rep stosl
	leaq	136(%rsp), %rdi
	movl	$8, %ecx
	leaq	296(%rsp), %r14
	rep stosl
	leaq	168(%rsp), %rdi
	movl	$16, %ecx
	rep stosl
	leaq	232(%rsp), %rdi
	movl	$16, %ecx
	rep stosl
	leaq	296(%rsp), %rdi
	movl	$16, %ecx
	rep stosl
	xorl	%eax, %eax
	movq	%rsp, %rdi
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$32, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$32, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$64, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$64, %esi
	call	cudaMalloc@PLT
	movl	$64, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	xorl	%eax, %eax
	leaq	72(%rsp), %rsi
.L9:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, 0(%r13,%rax,4)
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$16, %rax
	jne	.L9
	movq	24(%rsp), %r9
	movq	32(%rsp), %r8
	xorl	%edx, %edx
	xorl	%eax, %eax
	movq	40(%rsp), %rdi
.L10:
	leaq	(%r9,%rax), %rcx
	movq	%rcx, (%rsi,%rdx)
	leaq	(%r8,%rax), %rcx
	movq	%rcx, (%r15,%rdx)
	leaq	(%rdi,%rax), %rcx
	addq	$16, %rax
	movq	%rcx, (%rbx,%rdx)
	addq	$8, %rdx
	cmpq	$64, %rax
	jne	.L10
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$32, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$32, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$32, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movabsq	$137438953488, %rdx
	movl	$1, 68(%rsp)
	movq	%rdi, 60(%rsp)
	movq	%rdx, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z35__device_stub__Z9VectorAddPPfS0_S0_PPfS0_S0_
.L11:
	movq	40(%rsp), %rsi
	leaq	296(%rsp), %rdi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	movl	$64, %edx
	leaq	.LC0(%rip), %r15
	call	cudaMemcpy@PLT
.L12:
	cvtss2sd	(%r14,%rbx), %xmm2
	cvtss2sd	0(%r13,%rbx), %xmm0
	cvtss2sd	(%r12,%rbx), %xmm1
	movq	%r15, %rsi
	movl	$2, %edi
	movb	$3, %al
	addq	$4, %rbx
	call	__printf_chk@PLT
	cmpq	$64, %rbx
	jne	.L12
	call	clock@PLT
	movl	$1000, %ecx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	subl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%eax, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$376, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z9VectorAddPPfS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9VectorAddPPfS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"
#include <stdio.h>
#include <time.h>

const int Row = 2 * 2;
const int Col = 2 * 2;

//2维网格2维线程块  最常用
__global__ void VectorAdd(float** a, float** b, float** c) {
    int thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;   //x是线程块的x做行 线程的x做列
    int thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;   //y是线程块的y做行 线程的y做列
    //printf("blockIdx.y/x: %d/%d\tblockDim.y/x: %d/%d\tthreadIdx.y/x: %d/%d\tthread_y/x: %d/%d\n", blockIdx.y, blockIdx.x, blockDim.y, blockDim.x, threadIdx.y, threadIdx.x, thread_y_id, thread_x_id);
    if (thread_x_id < Col && thread_y_id < Row) {
        c[thread_y_id][thread_x_id] = a[thread_y_id][thread_x_id] + b[thread_y_id][thread_x_id];
    }
}

int main() {
    int start = clock();
    //二维指针 指向一维指针（数据指针）
    float* a[Row] = { NULL };
    float* b[Row] = { NULL };
    float* c[Row] = { NULL };
    float data_a[Row * Col] = { 0.0 };
    float data_b[Row * Col] = { 0.0 };
    float data_c[Row * Col] = { 0.0 };

    //二维指针 指向一维指针（数据指针）
    float** device_a = NULL;
    float** device_b = NULL;
    float** device_c = NULL;
    float* device_data_a = NULL;
    float* device_data_b = NULL;
    float* device_data_c = NULL;

    //分配显存
    hipMalloc((void**)&device_a, sizeof(float*) * Row);
    hipMalloc((void**)&device_b, sizeof(float*) * Row);
    hipMalloc((void**)&device_c, sizeof(float*) * Row);
    hipMalloc((void**)&device_data_a, sizeof(float) * Row * Col);
    hipMalloc((void**)&device_data_b, sizeof(float) * Row * Col);
    hipMalloc((void**)&device_data_c, sizeof(float) * Row * Col);

    for (int i = 0; i < Row * Col; i++) {
        data_a[i] = i;
        data_b[i] = i;
    }
    
    //主机二级指针存放着设备一级指针（数据指针）的地址
    //再通过cudacopy 传给设备二级指针 让设备二级指针和设备一级指针关联（数据指针）
    //而设备一级指针已经通过主机一级指针cudacopy了
    for (int i = 0; i < Row; i++) {
        a[i] = device_data_a + i * Col;
        b[i] = device_data_b + i * Col;
        c[i] = device_data_c + i * Col;
    }

    //将内存中a和b数组的值复制到GPU中显存中
    hipMemcpy(device_a, a, sizeof(float*) * Row, hipMemcpyHostToDevice);
    hipMemcpy(device_b, b, sizeof(float*) * Row, hipMemcpyHostToDevice);
    hipMemcpy(device_c, c, sizeof(float*) * Row, hipMemcpyHostToDevice);
    hipMemcpy(device_data_a, data_a, sizeof(float) * Row * Col, hipMemcpyHostToDevice);
    hipMemcpy(device_data_b, data_b, sizeof(float) * Row * Col, hipMemcpyHostToDevice);

    //一个kernel函数由一个gpu的一个grid执行  
    //调用核函数 cpu调用 gpu运行 
    dim3 dim_block(16, 32);      //一个线程块block包含 512个线程threads(最多不超过512个)
    dim3 dim_grid((Col + dim_block.x - 1) / dim_block.x, (Row + dim_block.y - 1) / dim_block.y); //一个grid网格包含n / 512个线程块blocks(为了充分利用sm blocks尽可能多)
    VectorAdd<<<dim_grid, dim_block>>>(device_a, device_b, device_c);

    //1级指针设备 给1级指针主机 赋值
    hipMemcpy(data_c, device_data_c, sizeof(float) * Row * Col, hipMemcpyDeviceToHost);
    
    for (int i = 0; i < Row * Col; i++) 
        printf("%.0f + %.0f = %.0f\t", data_a[i], data_b[i], data_c[i]);
    int end = clock();
    printf("\n程序耗时：%ds\n", (end - start) / 1000);
   

    //释放gpu显存
    hipFree(device_a);
    hipFree(device_b);
    hipFree(device_c);
    hipFree(device_data_a);
    hipFree(device_data_b);
    hipFree(device_data_c);

    return 0;
}

	.text
	.file	"dim2_vector_add.hip"
	.globl	_Z24__device_stub__VectorAddPPfS0_S0_ # -- Begin function _Z24__device_stub__VectorAddPPfS0_S0_
	.type	_Z24__device_stub__VectorAddPPfS0_S0_,@function
_Z24__device_stub__VectorAddPPfS0_S0_:  # @_Z24__device_stub__VectorAddPPfS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9VectorAddPPfS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__VectorAddPPfS0_S0_, .Lfunc_end0-_Z24__device_stub__VectorAddPPfS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$360, %rsp                      # imm = 0x168
	.cfi_def_cfa_offset 416
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	callq	clock
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 144(%rsp)
	movaps	%xmm0, 128(%rsp)
	movaps	%xmm0, 112(%rsp)
	movaps	%xmm0, 96(%rsp)
	movaps	%xmm0, 80(%rsp)
	movaps	%xmm0, 64(%rsp)
	movaps	%xmm0, 272(%rsp)
	movaps	%xmm0, 256(%rsp)
	movaps	%xmm0, 240(%rsp)
	movaps	%xmm0, 224(%rsp)
	movaps	%xmm0, 208(%rsp)
	movaps	%xmm0, 192(%rsp)
	movaps	%xmm0, 176(%rsp)
	movaps	%xmm0, 160(%rsp)
	movaps	%xmm0, 336(%rsp)
	movaps	%xmm0, 320(%rsp)
	movaps	%xmm0, 304(%rsp)
	movaps	%xmm0, 288(%rsp)
	xorl	%ebx, %ebx
	leaq	48(%rsp), %rdi
	movq	%rbx, (%rdi)
	leaq	40(%rsp), %r12
	movq	%rbx, (%r12)
	leaq	32(%rsp), %r13
	movq	%rbx, (%r13)
	leaq	24(%rsp), %rbp
	movq	%rbx, (%rbp)
	leaq	16(%rsp), %r15
	movq	%rbx, (%r15)
	leaq	8(%rsp), %r14
	movq	%rbx, (%r14)
	movl	$32, %esi
	callq	hipMalloc
	movl	$32, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movl	$32, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	movl	$64, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movl	$64, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$64, %esi
	movq	%r14, %rdi
	callq	hipMalloc
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebx, %xmm0
	movss	%xmm0, 224(%rsp,%rbx,4)
	movss	%xmm0, 160(%rsp,%rbx,4)
	incq	%rbx
	cmpq	$16, %rbx
	jne	.LBB1_1
# %bb.2:                                # %.preheader
	movq	24(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	xorl	%esi, %esi
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movq	%rax, 128(%rsp,%rsi,8)
	movq	%rcx, 96(%rsp,%rsi,8)
	movq	%rdx, 64(%rsp,%rsi,8)
	incq	%rsi
	addq	$16, %rdx
	addq	$16, %rcx
	addq	$16, %rax
	cmpq	$4, %rsi
	jne	.LBB1_3
# %bb.4:
	movq	48(%rsp), %rdi
	leaq	128(%rsp), %rsi
	movl	$32, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	leaq	96(%rsp), %rsi
	movl	$32, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	leaq	64(%rsp), %rsi
	movl	$32, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	leaq	224(%rsp), %rsi
	movl	$64, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	leaq	160(%rsp), %rsi
	movl	$64, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$137438953488, %rdx             # imm = 0x2000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	callq	_Z24__device_stub__VectorAddPPfS0_S0_
.LBB1_6:
	movq	8(%rsp), %rsi
	leaq	288(%rsp), %rdi
	movl	$64, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	224(%rsp,%rbx,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	160(%rsp,%rbx,4), %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	288(%rsp,%rbx,4), %xmm2
	movl	$.L.str, %edi
	movb	$3, %al
	callq	printf
	incq	%rbx
	cmpq	$16, %rbx
	jne	.LBB1_7
# %bb.8:
	callq	clock
	subl	56(%rsp), %eax                  # 4-byte Folded Reload
	cltq
	imulq	$274877907, %rax, %rsi          # imm = 0x10624DD3
	movq	%rsi, %rax
	shrq	$63, %rax
	sarq	$38, %rsi
	addl	%eax, %esi
	movl	$.L.str.1, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$360, %rsp                      # imm = 0x168
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9VectorAddPPfS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9VectorAddPPfS0_S0_,@object   # @_Z9VectorAddPPfS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z9VectorAddPPfS0_S0_
	.p2align	3, 0x0
_Z9VectorAddPPfS0_S0_:
	.quad	_Z24__device_stub__VectorAddPPfS0_S0_
	.size	_Z9VectorAddPPfS0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%.0f + %.0f = %.0f\t"
	.size	.L.str, 20

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n\347\250\213\345\272\217\350\200\227\346\227\266\357\274\232%ds\n"
	.size	.L.str.1, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9VectorAddPPfS0_S0_"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__VectorAddPPfS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9VectorAddPPfS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9VectorAddPPfS0_S0_   ; -- Begin function _Z9VectorAddPPfS0_S0_
	.globl	_Z9VectorAddPPfS0_S0_
	.p2align	8
	.type	_Z9VectorAddPPfS0_S0_,@function
_Z9VectorAddPPfS0_S0_:                  ; @_Z9VectorAddPPfS0_S0_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 4, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(1)
	v_add_co_u32 v4, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9VectorAddPPfS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9VectorAddPPfS0_S0_, .Lfunc_end0-_Z9VectorAddPPfS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9VectorAddPPfS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9VectorAddPPfS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
