

#include <iostream>
#include <numeric>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <ctime>

using namespace std;

#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define random(x) (rand()%x)

/**
 * Check the return value of the CUDA runtime API call and exit
 * the application if the call has failed.
 */
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
	if (err == cudaSuccess)
		return;
	std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
	exit (1);
}


void printMatrix(double* inputMatrix, const int rows, const int cols)
{
    for (int i = 0; i < rows; i++) {
        for (int j = 0; j < cols; j++) {
            std::cout << inputMatrix[i * cols + j] << "\t";
        }
        std::cout << std::endl;
    }
}

/**
 * CUDA kernel that computes reciprocal values for a given vector
 */

__global__ void harnessZeroKernel(double *d_augmentedMatrix, const int rowId1, const int rowId2, const int size) {
	__shared__ double blockR1[512];
	__shared__ double blockR2[512];
	const int tIdx = threadIdx.x;
	const int bIdx = blockIdx.x;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2) {
		blockR1[tIdx] = d_augmentedMatrix[rowId1 * 2 * size + blockDim.x * bIdx + tIdx];
		blockR2[tIdx] = d_augmentedMatrix[rowId2 * 2 * size + blockDim.x * bIdx + tIdx];
		__syncthreads();
		d_augmentedMatrix[rowId1 * 2 * size + blockDim.x * bIdx + tIdx] = blockR1[tIdx] + blockR2[tIdx];
	}
}

__global__ void computeRowsKernel(double *d_augmentedMatrix, const int rowId, const int size) {
	__shared__ double blockR[512];
	__shared__ double Aii;
	const int tIdx = threadIdx.x;
	const int bIdx = blockIdx.x;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2) {
		blockR[tIdx] = d_augmentedMatrix[rowId * 2 * size + blockDim.x * bIdx + tIdx];
		Aii = d_augmentedMatrix[rowId * 2 * size + rowId];
		__syncthreads();
		blockR[tIdx] = blockR[tIdx] / Aii;
		d_augmentedMatrix[rowId * 2 * size + blockDim.x * bIdx + tIdx] = blockR[tIdx];
	}
}

__global__ void computeColsKernel(double *d_augmentedMatrix, const int colId, const int size) {
	__shared__ double blockC[16][16];    // which col need to be zero
	__shared__ double blockCCurent[16][16];   // which col is the current col
	__shared__ double ARow[16];        // the pivot row
	const int tIdx = threadIdx.x;
	const int tIdy = threadIdx.y;
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2 && rowI < size) {
		blockC[tIdy][tIdx] = d_augmentedMatrix[rowI * size * 2 + colId];
		if (blockC[tIdy][tIdx] != 0) {
			blockCCurent[tIdy][tIdx] = d_augmentedMatrix[rowI * size * 2 + colI];
			ARow[tIdx] = d_augmentedMatrix[colId * size * 2 + colI];
			__syncthreads();
			if (rowI != colId) {   // current row can't sub by current row
				blockCCurent[tIdy][tIdx] = blockCCurent[tIdy][tIdx] - blockC[tIdy][tIdx] * ARow[tIdx];
			}
			d_augmentedMatrix[rowI * size * 2 + colI] = blockCCurent[tIdy][tIdx];
			//d_augmentedMatrix[rowI * size * 2 + colI] = ARow[tIdx];
		}
	}
}

__global__ void augmentMatrixKernel(double *d_augmentedMatrix, double *d_inputMatrix, const int rows, const int cols) {
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;

	if (colI < cols && rowI < rows) {
			// initialize augmentedMatrix
			if (colI < cols / 2) {
				d_augmentedMatrix[rowI * cols + colI] = d_inputMatrix[rowI * cols / 2 + colI];
			}
			else if (colI - cols / 2 == rowI) {
				d_augmentedMatrix[rowI * cols + colI] = 1;
			} else {
				d_augmentedMatrix[rowI * cols + colI] = 0;
			}

	}
}

__global__ void getInverseMatrixKernel(double *d_augmentedMatrix, double *d_inverseMatrix, const int rows, const int cols) {
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;

	if (colI < cols / 2 && rowI < rows) {
			// initialize augmentedMatrix
			d_inverseMatrix[rowI * cols / 2 + colI] = d_augmentedMatrix[rowI * cols + colI + cols / 2];
	}
}

/**
 * Host function that copies the data and launches the work on GPU
 */
double *gpuMatrixInverse(double *inputMatrix, const int rows, const int cols)
{
	double *h_inverseMatrix;
	//double *h_augmentedMatrix;
	double *d_inputMatrix;
	double *d_inverseMatrix;
	double *d_augmentedMatrix;
	const int length = rows * cols;
	const int size = rows;
	//printMatrix(inputMatrix, rows, cols);
	cout << endl;
	// initialization
	h_inverseMatrix = (double *)malloc(length * sizeof(double));
	//h_augmentedMatrix = (double *)malloc(length * 2 * sizeof(double));
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_augmentedMatrix, sizeof(double) * length * 2));
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_inputMatrix, sizeof(double) * length));
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_inverseMatrix, sizeof(double) * length));
	CUDA_CHECK_RETURN(cudaMemcpy(d_inputMatrix, inputMatrix, sizeof(double) * length, cudaMemcpyHostToDevice));


	dim3 blockSize1(16, 16);
	dim3 gridSize1(cols * 2.0 / blockSize1.x + 1, rows * 1.0 / blockSize1.y + 1);
	augmentMatrixKernel<<<gridSize1, blockSize1>>>(d_augmentedMatrix, d_inputMatrix, rows, cols * 2);
	cudaDeviceSynchronize();

	int i = 0;
	while (i < size) {
		if (inputMatrix[i * size + i] != 0) {
			dim3 blockSize2(256);
			dim3 gridSize2(cols * 2.0 / blockSize2.x + 1, 1);
			computeRowsKernel<<<gridSize2, blockSize2>>>(d_augmentedMatrix, i, size);
			cudaDeviceSynchronize();
		} else {
			int nonZeroRowIndex = 0;
			for (int j = 0; j < size; j++) {
				if (inputMatrix[j * size + i] != 0) {
					nonZeroRowIndex = j;
					break;
				}
			}
			dim3 blockSize3(256);
			dim3 gridSize3(cols * 2.0 / blockSize3.x + 1, 1);
			harnessZeroKernel<<<gridSize3, blockSize3>>>(d_augmentedMatrix, i, nonZeroRowIndex, size);
			cudaDeviceSynchronize();
			dim3 blockSize4(256);
			dim3 gridSize4(cols * 2.0 / blockSize4.x + 1, 1);
			computeRowsKernel<<<gridSize4, blockSize4>>>(d_augmentedMatrix, i, size);
			cudaDeviceSynchronize();
		}

		dim3 blockSize5(16, 16);
		dim3 gridSize5(cols * 2.0 / blockSize5.x + 1, rows * 1.0 / blockSize5.y + 1);
		computeColsKernel<<<gridSize5, blockSize5>>>(d_augmentedMatrix, i, size);
		cudaDeviceSynchronize();
		i++;
	}

	dim3 blockSize6(16, 16);
	dim3 gridSize6(cols * 2.0 / blockSize6.x + 1, rows * 1.0 / blockSize6.y + 1);
	getInverseMatrixKernel<<<gridSize1, blockSize1>>>(d_augmentedMatrix, d_inverseMatrix, rows, cols * 2);

	CUDA_CHECK_RETURN(cudaMemcpy(h_inverseMatrix, d_inverseMatrix, sizeof(double) * length, cudaMemcpyDeviceToHost));
	//CUDA_CHECK_RETURN(cudaMemcpy(h_augmentedMatrix, d_augmentedMatrix, sizeof(double) * length * 2, cudaMemcpyDeviceToHost));
	CUDA_CHECK_RETURN(cudaFree(d_augmentedMatrix));
	CUDA_CHECK_RETURN(cudaFree(d_inverseMatrix));
	CUDA_CHECK_RETURN(cudaFree(d_inputMatrix));

	return h_inverseMatrix;
}

double *createTest(const int rows, const int cols)
{
	double *data = (double *)malloc(rows * cols * sizeof(double));

	for (int i = 0; i < rows; i++) {
		for (int j = 0; j < cols; ++j) {
			data[i * rows + j]  = 0.0;
			if (i == j) {
				data[i * rows + j]  = 1.0;
			}
		}
	}

	return data;
}


int main(void)
{
	const int rows = 10;
	const int cols = 10;
	double *testMatrix = createTest(rows, cols);
	double *inverseMatrixGPU;


	// GPU code

	clock_t start1,end1;
	start1 = clock();
	inverseMatrixGPU = gpuMatrixInverse(testMatrix, rows, cols);
	end1 = clock();
	double dur1 = (double)(end1 - start1);
	cout << "\n running time on GPU is " << dur1 / CLOCKS_PER_SEC << " secs！\n" << endl;

	if (rows < 20) {
		printMatrix(inverseMatrixGPU, rows, cols);
		double *resultMatrix = (double *)malloc(cols * rows * sizeof(double));
		for (int i = 0; i < rows; i++) {
			for (int j = 0; j < cols; j++) {
				resultMatrix[i * cols + j] = 0;
			}
		}
		for (int i = 0; i < rows; i++) {
			for (int j = 0; j < cols; j++) {
				for (int k = 0; k < cols; k++) {
					resultMatrix[i * cols + j] +=  testMatrix[i * cols + k] * inverseMatrixGPU[k * cols + j];
				}
			}
		}

		cout << "\nTest the result from GPU\n" << endl;
		printMatrix(resultMatrix, rows, cols);

	}
	/* Free memory */
	delete[] inverseMatrixGPU;

	return 0;
}

	.file	"tmpxft_002d34e4_00000000-6_MatrixInverse.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3681:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4346:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4346:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" returned "
.LC1:
	.string	"("
.LC2:
	.string	") at "
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/Otiliaa/matrixInversionCUDA/master/MatrixInverse.cu"
.LC4:
	.string	":"
	.text
	.type	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0:
.LFB4347:
	.cfi_startproc
	testl	%edx, %edx
	je	.L5
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %r12
	call	cudaGetErrorString@PLT
	movq	%r12, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L5:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	ret
	.cfi_endproc
.LFE4347:
	.size	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	.section	.rodata.str1.1
.LC5:
	.string	"\t"
	.text
	.globl	_Z11printMatrixPdii
	.type	_Z11printMatrixPdii, @function
_Z11printMatrixPdii:
.LFB3675:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
.L11:
	cmpl	%r14d, %r13d
	jge	.L10
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,8), %rcx
.L14:
	cmpl	%r15d, %ebx
	jle	.L16
	movsd	(%rcx,%r15,8), %xmm0
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rcx, 8(%rsp)
	incq	%r15
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rcx
	jmp	.L14
.L16:
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	incl	%r13d
	addl	%ebx, %r12d
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L11
.L10:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_Z11printMatrixPdii, .-_Z11printMatrixPdii
	.globl	_Z10createTestii
	.type	_Z10createTestii, @function
_Z10createTestii:
.LFB3677:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	imull	%esi, %edi
	pushq	%rcx
	.cfi_def_cfa_offset 32
	movslq	%edi, %rdi
	salq	$3, %rdi
	call	malloc@PLT
	xorl	%esi, %esi
	xorl	%ecx, %ecx
.L18:
	cmpl	%ebx, %ecx
	jge	.L17
	movslq	%esi, %rdx
	leaq	(%rax,%rdx,8), %rdi
	xorl	%edx, %edx
.L22:
	cmpl	%edx, %ebp
	jle	.L25
	xorps	%xmm0, %xmm0
	cmpl	%edx, %ecx
	jne	.L19
	movsd	.LC7(%rip), %xmm0
.L19:
	movsd	%xmm0, (%rdi,%rdx,8)
	incq	%rdx
	jmp	.L22
.L25:
	incl	%ecx
	addl	%ebx, %esi
	jmp	.L18
.L17:
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_Z10createTestii, .-_Z10createTestii
	.globl	_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii
	.type	_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii, @function
_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii:
.LFB3703:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17harnessZeroKernelPdiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3703:
	.size	_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii, .-_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii
	.globl	_Z17harnessZeroKernelPdiii
	.type	_Z17harnessZeroKernelPdiii, @function
_Z17harnessZeroKernelPdiii:
.LFB3704:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii
	.cfi_endproc
.LFE3704:
	.size	_Z17harnessZeroKernelPdiii, .-_Z17harnessZeroKernelPdiii
	.globl	_Z39__device_stub__Z17computeRowsKernelPdiiPdii
	.type	_Z39__device_stub__Z17computeRowsKernelPdiiPdii, @function
_Z39__device_stub__Z17computeRowsKernelPdiiPdii:
.LFB3705:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17computeRowsKernelPdii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L31:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3705:
	.size	_Z39__device_stub__Z17computeRowsKernelPdiiPdii, .-_Z39__device_stub__Z17computeRowsKernelPdiiPdii
	.globl	_Z17computeRowsKernelPdii
	.type	_Z17computeRowsKernelPdii, @function
_Z17computeRowsKernelPdii:
.LFB3706:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17computeRowsKernelPdiiPdii
	.cfi_endproc
.LFE3706:
	.size	_Z17computeRowsKernelPdii, .-_Z17computeRowsKernelPdii
	.globl	_Z39__device_stub__Z17computeColsKernelPdiiPdii
	.type	_Z39__device_stub__Z17computeColsKernelPdiiPdii, @function
_Z39__device_stub__Z17computeColsKernelPdiiPdii:
.LFB3707:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17computeColsKernelPdii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L36:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3707:
	.size	_Z39__device_stub__Z17computeColsKernelPdiiPdii, .-_Z39__device_stub__Z17computeColsKernelPdiiPdii
	.globl	_Z17computeColsKernelPdii
	.type	_Z17computeColsKernelPdii, @function
_Z17computeColsKernelPdii:
.LFB3708:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17computeColsKernelPdiiPdii
	.cfi_endproc
.LFE3708:
	.size	_Z17computeColsKernelPdii, .-_Z17computeColsKernelPdii
	.globl	_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii
	.type	_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii, @function
_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii:
.LFB3709:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19augmentMatrixKernelPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L41:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3709:
	.size	_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii, .-_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii
	.globl	_Z19augmentMatrixKernelPdS_ii
	.type	_Z19augmentMatrixKernelPdS_ii, @function
_Z19augmentMatrixKernelPdS_ii:
.LFB3710:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii
	.cfi_endproc
.LFE3710:
	.size	_Z19augmentMatrixKernelPdS_ii, .-_Z19augmentMatrixKernelPdS_ii
	.globl	_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii
	.type	_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii, @function
_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii:
.LFB3711:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22getInverseMatrixKernelPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L46:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3711:
	.size	_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii, .-_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii
	.globl	_Z22getInverseMatrixKernelPdS_ii
	.type	_Z22getInverseMatrixKernelPdS_ii, @function
_Z22getInverseMatrixKernelPdS_ii:
.LFB3712:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii
	.cfi_endproc
.LFE3712:
	.size	_Z22getInverseMatrixKernelPdS_ii, .-_Z22getInverseMatrixKernelPdS_ii
	.section	.rodata.str1.1
.LC8:
	.string	"cudaMalloc((void **)&d_augmentedMatrix, sizeof(double) * length * 2)"
.LC9:
	.string	"cudaMalloc((void **)&d_inputMatrix, sizeof(double) * length)"
.LC10:
	.string	"cudaMalloc((void **)&d_inverseMatrix, sizeof(double) * length)"
.LC11:
	.string	"cudaMemcpy(d_inputMatrix, inputMatrix, sizeof(double) * length, cudaMemcpyHostToDevice)"
.LC14:
	.string	"cudaMemcpy(h_inverseMatrix, d_inverseMatrix, sizeof(double) * length, cudaMemcpyDeviceToHost)"
.LC15:
	.string	"cudaFree(d_augmentedMatrix)"
.LC16:
	.string	"cudaFree(d_inverseMatrix)"
.LC17:
	.string	"cudaFree(d_inputMatrix)"
	.text
	.globl	_Z16gpuMatrixInversePdii
	.type	_Z16gpuMatrixInversePdii, @function
_Z16gpuMatrixInversePdii:
.LFB3676:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	imull	%edx, %r12d
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	movslq	%r12d, %r12
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rdi, 16(%rsp)
	leaq	_ZSt4cout(%rip), %rdi
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	0(,%r12,8), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%r12, %rsi
	leaq	88(%rsp), %rdi
	salq	$4, %rsi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	leaq	.LC8(%rip), %rsi
	movl	$138, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC9(%rip), %rsi
	movl	$139, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	8(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC10(%rip), %rsi
	movl	$140, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC11(%rip), %rsi
	movl	$141, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	cvtsi2sdl	%ebx, %xmm1
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movsd	.LC12(%rip), %xmm0
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 116(%rsp)
	movl	$1, 104(%rsp)
	mulsd	%xmm0, %xmm1
	addsd	.LC7(%rip), %xmm1
	cvttsd2siq	%xmm1, %rax
	cvtsi2sdl	%ebp, %xmm1
	movl	%eax, 112(%rsp)
	addsd	%xmm1, %xmm1
	movl	%eax, 44(%rsp)
	mulsd	%xmm1, %xmm0
	movsd	%xmm1, 24(%rsp)
	addsd	.LC7(%rip), %xmm0
	cvttsd2siq	%xmm0, %rdx
	movl	%edx, 108(%rsp)
	movq	108(%rsp), %rdi
	movl	%edx, 56(%rsp)
	movabsq	$68719476752, %rdx
	movq	%rdx, 96(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	movq	72(%rsp), %rsi
	movq	88(%rsp), %rdi
	leal	(%rbp,%rbp), %ecx
	movl	%ebx, %edx
	call	_Z43__device_stub__Z19augmentMatrixKernelPdS_iiPdS_ii
.L52:
	call	cudaDeviceSynchronize@PLT
	movslq	%ebx, %rax
	movq	16(%rsp), %r13
	xorl	%r12d, %r12d
	leaq	8(,%rax,8), %r15
	leaq	-8(%r15), %rax
	movq	%rax, 48(%rsp)
.L53:
	movl	%r12d, 40(%rsp)
	cmpl	%r12d, %ebx
	jle	.L73
	movsd	.LC13(%rip), %xmm0
	mulsd	24(%rsp), %xmm0
	addsd	.LC7(%rip), %xmm0
	cvttsd2siq	%xmm0, %r14
	xorps	%xmm0, %xmm0
	ucomisd	0(%r13), %xmm0
	jp	.L72
	jne	.L72
	movq	16(%rsp), %rax
	xorl	%r10d, %r10d
	xorps	%xmm0, %xmm0
	leaq	(%rax,%r12,8), %rax
.L60:
	ucomisd	(%rax), %xmm0
	jp	.L58
	jne	.L58
	movq	48(%rsp), %rcx
	incl	%r10d
	addq	%rcx, %rax
	cmpl	%r10d, %ebx
	jne	.L60
	xorl	%r10d, %r10d
.L58:
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$8, %rdx
	movl	%r10d, 60(%rsp)
	movq	%rax, 136(%rsp)
	movl	140(%rsp), %esi
	movl	%r14d, 132(%rsp)
	movq	132(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	60(%rsp), %r10d
	testl	%eax, %eax
	jne	.L61
	movl	40(%rsp), %esi
	movq	88(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%r10d, %edx
	call	_Z40__device_stub__Z17harnessZeroKernelPdiiiPdiii
.L61:
	call	cudaDeviceSynchronize@PLT
.L72:
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$8, %rdx
	movl	%r14d, 156(%rsp)
	movq	%rax, 160(%rsp)
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	movq	%rdx, 144(%rsp)
	movl	$1, 152(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movl	40(%rsp), %esi
	movq	88(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z39__device_stub__Z17computeRowsKernelPdiiPdii
.L62:
	call	cudaDeviceSynchronize@PLT
	movl	56(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 164(%rsp)
	movl	%eax, 156(%rsp)
	movl	44(%rsp), %eax
	movq	%rdx, 144(%rsp)
	movl	%eax, 160(%rsp)
	movq	156(%rsp), %rdi
	movl	$1, 152(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	movl	40(%rsp), %esi
	movq	88(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z39__device_stub__Z17computeColsKernelPdiiPdii
.L63:
	call	cudaDeviceSynchronize@PLT
	incq	%r12
	addq	%r15, %r13
	jmp	.L53
.L73:
	movl	104(%rsp), %ecx
	movq	96(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	108(%rsp), %rdi
	movl	116(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	movq	80(%rsp), %rsi
	movq	88(%rsp), %rdi
	leal	(%rbp,%rbp), %ecx
	movl	%ebx, %edx
	call	_Z46__device_stub__Z22getInverseMatrixKernelPdS_iiPdS_ii
.L65:
	movq	8(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC14(%rip), %rsi
	movl	$185, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC15(%rip), %rsi
	movl	$187, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC16(%rip), %rsi
	movl	$188, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC17(%rip), %rsi
	movl	$189, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	movq	32(%rsp), %rax
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3676:
	.size	_Z16gpuMatrixInversePdii, .-_Z16gpuMatrixInversePdii
	.section	.rodata.str1.1
.LC18:
	.string	"\n running time on GPU is "
.LC20:
	.string	" secs\357\274\201\n"
.LC21:
	.string	"\nTest the result from GPU\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3678:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$10, %esi
	movl	$10, %edi
	leaq	_ZSt4cout(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	call	_Z10createTestii
	movq	%rax, %r12
	call	clock@PLT
	movl	$10, %edx
	movl	$10, %esi
	movq	%r12, %rdi
	movq	%rax, %rbp
	call	_Z16gpuMatrixInversePdii
	movq	%rax, %rbx
	call	clock@PLT
	leaq	.LC18(%rip), %rsi
	movq	%r13, %rdi
	subq	%rbp, %rax
	cvtsi2sdq	%rax, %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	divsd	.LC19(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC20(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$10, %edx
	movl	$10, %esi
	movq	%rbx, %rdi
	call	_Z11printMatrixPdii
	movl	$800, %edi
	call	malloc@PLT
	movl	$200, %ecx
	movq	%rax, %rbp
	xorl	%eax, %eax
	movq	%rbp, %rdi
	rep stosl
	xorl	%eax, %eax
.L75:
	leaq	0(%rbp,%rax), %rcx
	xorl	%edx, %edx
	leaq	(%r12,%rax), %r8
.L79:
	movsd	(%rcx), %xmm0
	leaq	(%rbx,%rdx,8), %rdi
	xorl	%esi, %esi
.L76:
	movsd	(%r8,%rsi,8), %xmm1
	mulsd	(%rdi), %xmm1
	incq	%rsi
	addq	$80, %rdi
	addsd	%xmm1, %xmm0
	cmpq	$10, %rsi
	jne	.L76
	incq	%rdx
	movsd	%xmm0, (%rcx)
	addq	$8, %rcx
	cmpq	$10, %rdx
	jne	.L79
	addq	$80, %rax
	cmpq	$800, %rax
	jne	.L75
	leaq	.LC21(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$10, %edx
	movl	$10, %esi
	movq	%rbp, %rdi
	call	_Z11printMatrixPdii
	testq	%rbx, %rbx
	je	.L80
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
.L80:
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3678:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z22getInverseMatrixKernelPdS_ii"
.LC23:
	.string	"_Z19augmentMatrixKernelPdS_ii"
.LC24:
	.string	"_Z17computeColsKernelPdii"
.LC25:
	.string	"_Z17computeRowsKernelPdii"
.LC26:
	.string	"_Z17harnessZeroKernelPdiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3714:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22getInverseMatrixKernelPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19augmentMatrixKernelPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17computeColsKernelPdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17computeRowsKernelPdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17harnessZeroKernelPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3714:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC7:
	.long	0
	.long	1072693248
	.align 8
.LC12:
	.long	0
	.long	1068498944
	.align 8
.LC13:
	.long	0
	.long	1064304640
	.align 8
.LC19:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:



#include <iostream>
#include <numeric>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <ctime>

using namespace std;

#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define random(x) (rand()%x)

/**
 * Check the return value of the CUDA runtime API call and exit
 * the application if the call has failed.
 */
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
	if (err == hipSuccess)
		return;
	std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
	exit (1);
}


void printMatrix(double* inputMatrix, const int rows, const int cols)
{
    for (int i = 0; i < rows; i++) {
        for (int j = 0; j < cols; j++) {
            std::cout << inputMatrix[i * cols + j] << "\t";
        }
        std::cout << std::endl;
    }
}

/**
 * CUDA kernel that computes reciprocal values for a given vector
 */

__global__ void harnessZeroKernel(double *d_augmentedMatrix, const int rowId1, const int rowId2, const int size) {
	__shared__ double blockR1[512];
	__shared__ double blockR2[512];
	const int tIdx = threadIdx.x;
	const int bIdx = blockIdx.x;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2) {
		blockR1[tIdx] = d_augmentedMatrix[rowId1 * 2 * size + blockDim.x * bIdx + tIdx];
		blockR2[tIdx] = d_augmentedMatrix[rowId2 * 2 * size + blockDim.x * bIdx + tIdx];
		__syncthreads();
		d_augmentedMatrix[rowId1 * 2 * size + blockDim.x * bIdx + tIdx] = blockR1[tIdx] + blockR2[tIdx];
	}
}

__global__ void computeRowsKernel(double *d_augmentedMatrix, const int rowId, const int size) {
	__shared__ double blockR[512];
	__shared__ double Aii;
	const int tIdx = threadIdx.x;
	const int bIdx = blockIdx.x;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2) {
		blockR[tIdx] = d_augmentedMatrix[rowId * 2 * size + blockDim.x * bIdx + tIdx];
		Aii = d_augmentedMatrix[rowId * 2 * size + rowId];
		__syncthreads();
		blockR[tIdx] = blockR[tIdx] / Aii;
		d_augmentedMatrix[rowId * 2 * size + blockDim.x * bIdx + tIdx] = blockR[tIdx];
	}
}

__global__ void computeColsKernel(double *d_augmentedMatrix, const int colId, const int size) {
	__shared__ double blockC[16][16];    // which col need to be zero
	__shared__ double blockCCurent[16][16];   // which col is the current col
	__shared__ double ARow[16];        // the pivot row
	const int tIdx = threadIdx.x;
	const int tIdy = threadIdx.y;
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;
	if (colI < size * 2 && rowI < size) {
		blockC[tIdy][tIdx] = d_augmentedMatrix[rowI * size * 2 + colId];
		if (blockC[tIdy][tIdx] != 0) {
			blockCCurent[tIdy][tIdx] = d_augmentedMatrix[rowI * size * 2 + colI];
			ARow[tIdx] = d_augmentedMatrix[colId * size * 2 + colI];
			__syncthreads();
			if (rowI != colId) {   // current row can't sub by current row
				blockCCurent[tIdy][tIdx] = blockCCurent[tIdy][tIdx] - blockC[tIdy][tIdx] * ARow[tIdx];
			}
			d_augmentedMatrix[rowI * size * 2 + colI] = blockCCurent[tIdy][tIdx];
			//d_augmentedMatrix[rowI * size * 2 + colI] = ARow[tIdx];
		}
	}
}

__global__ void augmentMatrixKernel(double *d_augmentedMatrix, double *d_inputMatrix, const int rows, const int cols) {
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;

	if (colI < cols && rowI < rows) {
			// initialize augmentedMatrix
			if (colI < cols / 2) {
				d_augmentedMatrix[rowI * cols + colI] = d_inputMatrix[rowI * cols / 2 + colI];
			}
			else if (colI - cols / 2 == rowI) {
				d_augmentedMatrix[rowI * cols + colI] = 1;
			} else {
				d_augmentedMatrix[rowI * cols + colI] = 0;
			}

	}
}

__global__ void getInverseMatrixKernel(double *d_augmentedMatrix, double *d_inverseMatrix, const int rows, const int cols) {
	const int rowI = blockIdx.y * blockDim.y + threadIdx.y;
	const int colI = blockIdx.x * blockDim.x + threadIdx.x;

	if (colI < cols / 2 && rowI < rows) {
			// initialize augmentedMatrix
			d_inverseMatrix[rowI * cols / 2 + colI] = d_augmentedMatrix[rowI * cols + colI + cols / 2];
	}
}

/**
 * Host function that copies the data and launches the work on GPU
 */
double *gpuMatrixInverse(double *inputMatrix, const int rows, const int cols)
{
	double *h_inverseMatrix;
	//double *h_augmentedMatrix;
	double *d_inputMatrix;
	double *d_inverseMatrix;
	double *d_augmentedMatrix;
	const int length = rows * cols;
	const int size = rows;
	//printMatrix(inputMatrix, rows, cols);
	cout << endl;
	// initialization
	h_inverseMatrix = (double *)malloc(length * sizeof(double));
	//h_augmentedMatrix = (double *)malloc(length * 2 * sizeof(double));
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_augmentedMatrix, sizeof(double) * length * 2));
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_inputMatrix, sizeof(double) * length));
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_inverseMatrix, sizeof(double) * length));
	CUDA_CHECK_RETURN(hipMemcpy(d_inputMatrix, inputMatrix, sizeof(double) * length, hipMemcpyHostToDevice));


	dim3 blockSize1(16, 16);
	dim3 gridSize1(cols * 2.0 / blockSize1.x + 1, rows * 1.0 / blockSize1.y + 1);
	augmentMatrixKernel<<<gridSize1, blockSize1>>>(d_augmentedMatrix, d_inputMatrix, rows, cols * 2);
	hipDeviceSynchronize();

	int i = 0;
	while (i < size) {
		if (inputMatrix[i * size + i] != 0) {
			dim3 blockSize2(256);
			dim3 gridSize2(cols * 2.0 / blockSize2.x + 1, 1);
			computeRowsKernel<<<gridSize2, blockSize2>>>(d_augmentedMatrix, i, size);
			hipDeviceSynchronize();
		} else {
			int nonZeroRowIndex = 0;
			for (int j = 0; j < size; j++) {
				if (inputMatrix[j * size + i] != 0) {
					nonZeroRowIndex = j;
					break;
				}
			}
			dim3 blockSize3(256);
			dim3 gridSize3(cols * 2.0 / blockSize3.x + 1, 1);
			harnessZeroKernel<<<gridSize3, blockSize3>>>(d_augmentedMatrix, i, nonZeroRowIndex, size);
			hipDeviceSynchronize();
			dim3 blockSize4(256);
			dim3 gridSize4(cols * 2.0 / blockSize4.x + 1, 1);
			computeRowsKernel<<<gridSize4, blockSize4>>>(d_augmentedMatrix, i, size);
			hipDeviceSynchronize();
		}

		dim3 blockSize5(16, 16);
		dim3 gridSize5(cols * 2.0 / blockSize5.x + 1, rows * 1.0 / blockSize5.y + 1);
		computeColsKernel<<<gridSize5, blockSize5>>>(d_augmentedMatrix, i, size);
		hipDeviceSynchronize();
		i++;
	}

	dim3 blockSize6(16, 16);
	dim3 gridSize6(cols * 2.0 / blockSize6.x + 1, rows * 1.0 / blockSize6.y + 1);
	getInverseMatrixKernel<<<gridSize1, blockSize1>>>(d_augmentedMatrix, d_inverseMatrix, rows, cols * 2);

	CUDA_CHECK_RETURN(hipMemcpy(h_inverseMatrix, d_inverseMatrix, sizeof(double) * length, hipMemcpyDeviceToHost));
	//CUDA_CHECK_RETURN(cudaMemcpy(h_augmentedMatrix, d_augmentedMatrix, sizeof(double) * length * 2, cudaMemcpyDeviceToHost));
	CUDA_CHECK_RETURN(hipFree(d_augmentedMatrix));
	CUDA_CHECK_RETURN(hipFree(d_inverseMatrix));
	CUDA_CHECK_RETURN(hipFree(d_inputMatrix));

	return h_inverseMatrix;
}

double *createTest(const int rows, const int cols)
{
	double *data = (double *)malloc(rows * cols * sizeof(double));

	for (int i = 0; i < rows; i++) {
		for (int j = 0; j < cols; ++j) {
			data[i * rows + j]  = 0.0;
			if (i == j) {
				data[i * rows + j]  = 1.0;
			}
		}
	}

	return data;
}


int main(void)
{
	const int rows = 10;
	const int cols = 10;
	double *testMatrix = createTest(rows, cols);
	double *inverseMatrixGPU;


	// GPU code

	clock_t start1,end1;
	start1 = clock();
	inverseMatrixGPU = gpuMatrixInverse(testMatrix, rows, cols);
	end1 = clock();
	double dur1 = (double)(end1 - start1);
	cout << "\n running time on GPU is " << dur1 / CLOCKS_PER_SEC << " secs！\n" << endl;

	if (rows < 20) {
		printMatrix(inverseMatrixGPU, rows, cols);
		double *resultMatrix = (double *)malloc(cols * rows * sizeof(double));
		for (int i = 0; i < rows; i++) {
			for (int j = 0; j < cols; j++) {
				resultMatrix[i * cols + j] = 0;
			}
		}
		for (int i = 0; i < rows; i++) {
			for (int j = 0; j < cols; j++) {
				for (int k = 0; k < cols; k++) {
					resultMatrix[i * cols + j] +=  testMatrix[i * cols + k] * inverseMatrixGPU[k * cols + j];
				}
			}
		}

		cout << "\nTest the result from GPU\n" << endl;
		printMatrix(resultMatrix, rows, cols);

	}
	/* Free memory */
	delete[] inverseMatrixGPU;

	return 0;
}

	.text
	.file	"MatrixInverse.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z11printMatrixPdii             # -- Begin function _Z11printMatrixPdii
	.type	_Z11printMatrixPdii,@function
_Z11printMatrixPdii:                    # @_Z11printMatrixPdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB0_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %ebx
	movl	%esi, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %r12d
	xorl	%r13d, %r13d
	xorl	%ebp, %ebp
.LBB0_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB0_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,8), %r14
	xorl	%r15d, %r15d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%r14,%r15,8), %xmm0            # xmm0 = mem[0],zero
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB0_4
.LBB0_5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cout, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%rbp
	addl	%ebx, %r13d
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB0_2
.LBB0_6:                                # %._crit_edge13
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z11printMatrixPdii, .Lfunc_end0-_Z11printMatrixPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__harnessZeroKernelPdiii # -- Begin function _Z32__device_stub__harnessZeroKernelPdiii
	.type	_Z32__device_stub__harnessZeroKernelPdiii,@function
_Z32__device_stub__harnessZeroKernelPdiii: # @_Z32__device_stub__harnessZeroKernelPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17harnessZeroKernelPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__harnessZeroKernelPdiii, .Lfunc_end1-_Z32__device_stub__harnessZeroKernelPdiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__computeRowsKernelPdii # -- Begin function _Z32__device_stub__computeRowsKernelPdii
	.type	_Z32__device_stub__computeRowsKernelPdii,@function
_Z32__device_stub__computeRowsKernelPdii: # @_Z32__device_stub__computeRowsKernelPdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17computeRowsKernelPdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__computeRowsKernelPdii, .Lfunc_end2-_Z32__device_stub__computeRowsKernelPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__computeColsKernelPdii # -- Begin function _Z32__device_stub__computeColsKernelPdii
	.type	_Z32__device_stub__computeColsKernelPdii,@function
_Z32__device_stub__computeColsKernelPdii: # @_Z32__device_stub__computeColsKernelPdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17computeColsKernelPdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z32__device_stub__computeColsKernelPdii, .Lfunc_end3-_Z32__device_stub__computeColsKernelPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__augmentMatrixKernelPdS_ii # -- Begin function _Z34__device_stub__augmentMatrixKernelPdS_ii
	.type	_Z34__device_stub__augmentMatrixKernelPdS_ii,@function
_Z34__device_stub__augmentMatrixKernelPdS_ii: # @_Z34__device_stub__augmentMatrixKernelPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19augmentMatrixKernelPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z34__device_stub__augmentMatrixKernelPdS_ii, .Lfunc_end4-_Z34__device_stub__augmentMatrixKernelPdS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__getInverseMatrixKernelPdS_ii # -- Begin function _Z37__device_stub__getInverseMatrixKernelPdS_ii
	.type	_Z37__device_stub__getInverseMatrixKernelPdS_ii,@function
_Z37__device_stub__getInverseMatrixKernelPdS_ii: # @_Z37__device_stub__getInverseMatrixKernelPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22getInverseMatrixKernelPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z37__device_stub__getInverseMatrixKernelPdS_ii, .Lfunc_end5-_Z37__device_stub__getInverseMatrixKernelPdS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z16gpuMatrixInversePdii
.LCPI6_0:
	.quad	0x3fb0000000000000              # double 0.0625
.LCPI6_1:
	.quad	0x3ff0000000000000              # double 1
.LCPI6_2:
	.quad	0x3f70000000000000              # double 0.00390625
	.text
	.globl	_Z16gpuMatrixInversePdii
	.type	_Z16gpuMatrixInversePdii,@function
_Z16gpuMatrixInversePdii:               # @_Z16gpuMatrixInversePdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r14d
	movl	%esi, %ebp
	movq	%rdi, %r12
	movabsq	$68719476752, %r13              # imm = 0x1000000010
	movl	%edx, %ebx
	imull	%esi, %ebx
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movslq	%ebx, %rbx
	leaq	(,%rbx,8), %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	shlq	$4, %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %esi
	movl	$138, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %esi
	movl	$139, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %esi
	movl	$140, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	(%rbx), %rdi
	movq	%r12, 32(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	movq	%r15, 64(%rsp)                  # 8-byte Spill
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	$141, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	cvtsi2sd	%r14d, %xmm1
	addsd	%xmm1, %xmm1
	movsd	.LCPI6_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm1, 8(%rsp)                  # 8-byte Spill
	mulsd	%xmm0, %xmm1
	movsd	.LCPI6_1(%rip), %xmm2           # xmm2 = mem[0],zero
	addsd	%xmm2, %xmm1
	cvttsd2si	%xmm1, %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%ebp, %xmm1
	mulsd	%xmm0, %xmm1
	addsd	%xmm2, %xmm1
	cvttsd2si	%xmm1, %rdi
	movl	%eax, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	(%rsp), %rdi
	movq	48(%rsp), %rsi
	leal	(%r14,%r14), %ecx
	movl	%ebp, %edx
	callq	_Z34__device_stub__augmentMatrixKernelPdS_ii
.LBB6_2:
	movq	%r14, 56(%rsp)                  # 8-byte Spill
	callq	hipDeviceSynchronize
	testl	%ebp, %ebp
	jle	.LBB6_16
# %bb.3:                                # %.lr.ph137
	movl	%ebp, %r14d
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	leal	1(%rbp), %eax
	movl	%eax, 28(%rsp)                  # 4-byte Spill
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	mulsd	.LCPI6_2(%rip), %xmm0
	addsd	.LCPI6_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	movl	%eax, %eax
	leaq	(%rax,%rdx), %rdi
	addq	$-256, %rdi
	leaq	(,%r14,8), %r12
	xorl	%r15d, %r15d
	xorpd	%xmm1, %xmm1
	movq	32(%rsp), %rbx                  # 8-byte Reload
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movq	%rbp, 80(%rsp)                  # 8-byte Spill
.LBB6_4:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_6 Depth 2
	movl	28(%rsp), %eax                  # 4-byte Reload
	imull	%r15d, %eax
	cltq
	movq	32(%rsp), %rcx                  # 8-byte Reload
	movsd	(%rcx,%rax,8), %xmm0            # xmm0 = mem[0],zero
	ucomisd	%xmm1, %xmm0
	jne	.LBB6_19
	jnp	.LBB6_5
.LBB6_19:                               #   in Loop: Header=BB6_4 Depth=1
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_13
.LBB6_12:                               # %.sink.split
                                        #   in Loop: Header=BB6_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	callq	_Z32__device_stub__computeRowsKernelPdii
.LBB6_13:                               #   in Loop: Header=BB6_4 Depth=1
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_15
# %bb.14:                               #   in Loop: Header=BB6_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	callq	_Z32__device_stub__computeColsKernelPdii
.LBB6_15:                               #   in Loop: Header=BB6_4 Depth=1
	callq	hipDeviceSynchronize
	incq	%r15
	addq	$8, %rbx
	cmpq	%r14, %r15
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movq	8(%rsp), %rdi                   # 8-byte Reload
	xorpd	%xmm1, %xmm1
	jne	.LBB6_4
	jmp	.LBB6_16
.LBB6_5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB6_4 Depth=1
	movq	%rbx, %rax
	xorl	%ebp, %ebp
.LBB6_6:                                # %.lr.ph
                                        #   Parent Loop BB6_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rax), %xmm0                   # xmm0 = mem[0],zero
	ucomisd	%xmm1, %xmm0
	jne	.LBB6_9
	jp	.LBB6_9
# %bb.7:                                #   in Loop: Header=BB6_6 Depth=2
	incq	%rbp
	addq	%r12, %rax
	cmpq	%rbp, %r14
	jne	.LBB6_6
# %bb.8:                                #   in Loop: Header=BB6_4 Depth=1
	xorl	%ebp, %ebp
.LBB6_9:                                # %._crit_edge
                                        #   in Loop: Header=BB6_4 Depth=1
	movl	$1, %esi
	movq	%rdx, %r13
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_11
# %bb.10:                               #   in Loop: Header=BB6_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	movl	%r14d, %ecx
	callq	_Z32__device_stub__harnessZeroKernelPdiii
.LBB6_11:                               #   in Loop: Header=BB6_4 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	80(%rsp), %rbp                  # 8-byte Reload
	movabsq	$68719476752, %r13              # imm = 0x1000000010
	jne	.LBB6_13
	jmp	.LBB6_12
.LBB6_16:                               # %._crit_edge138
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_18
# %bb.17:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rcx                  # 8-byte Reload
	addl	%ecx, %ecx
	movl	%ebp, %edx
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z37__device_stub__getInverseMatrixKernelPdS_ii
.LBB6_18:
	movq	16(%rsp), %rsi
	movq	72(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.6, %esi
	movl	$185, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.7, %esi
	movl	$187, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.8, %esi
	movl	$188, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	48(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.9, %esi
	movl	$189, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	%rbx, %rax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z16gpuMatrixInversePdii, .Lfunc_end6-_Z16gpuMatrixInversePdii
	.cfi_endproc
                                        # -- End function
	.type	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jne	.LBB7_2
# %bb.1:
	retq
.LBB7_2:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.13, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebp, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.14, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.15, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.16, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEj
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end7:
	.size	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end7-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z10createTestii
.LCPI8_0:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z10createTestii
	.type	_Z10createTestii,@function
_Z10createTestii:                       # @_Z10createTestii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebx
	movl	%edi, %ebp
	movl	%esi, %eax
	imull	%edi, %eax
	movslq	%eax, %rdi
	shlq	$3, %rdi
	callq	malloc
	testl	%ebp, %ebp
	jle	.LBB8_8
# %bb.1:                                # %.preheader.lr.ph
	movl	%ebp, %ecx
	movl	%ebx, %edx
	xorl	%esi, %esi
	movsd	.LCPI8_0(%rip), %xmm0           # xmm0 = mem[0],zero
	xorl	%edi, %edi
.LBB8_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB8_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB8_7
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB8_2 Depth=1
	movl	%esi, %r8d
	leaq	(%rax,%r8,8), %r8
	xorl	%r9d, %r9d
.LBB8_4:                                #   Parent Loop BB8_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm0, %xmm1
	cmpq	%r9, %rdi
	je	.LBB8_6
# %bb.5:                                #   in Loop: Header=BB8_4 Depth=2
	xorps	%xmm1, %xmm1
.LBB8_6:                                #   in Loop: Header=BB8_4 Depth=2
	movsd	%xmm1, (%r8,%r9,8)
	incq	%r9
	cmpq	%r9, %rdx
	jne	.LBB8_4
.LBB8_7:                                # %._crit_edge
                                        #   in Loop: Header=BB8_2 Depth=1
	incq	%rdi
	addl	%ebp, %esi
	cmpq	%rcx, %rdi
	jne	.LBB8_2
.LBB8_8:                                # %._crit_edge22
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z10createTestii, .Lfunc_end8-_Z10createTestii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI9_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI9_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$800, %edi                      # imm = 0x320
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
	movsd	.LCPI9_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%rbx, %rcx
.LBB9_1:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB9_2 Depth 2
	xorl	%edx, %edx
.LBB9_2:                                #   Parent Loop BB9_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movapd	%xmm0, %xmm1
	cmpq	%rdx, %rax
	je	.LBB9_4
# %bb.3:                                #   in Loop: Header=BB9_2 Depth=2
	xorpd	%xmm1, %xmm1
.LBB9_4:                                #   in Loop: Header=BB9_2 Depth=2
	movsd	%xmm1, (%rcx,%rdx,8)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.LBB9_2
# %bb.5:                                # %._crit_edge.i
                                        #   in Loop: Header=BB9_1 Depth=1
	incq	%rax
	addq	$80, %rcx
	cmpq	$10, %rax
	jne	.LBB9_1
# %bb.6:                                # %_Z10createTestii.exit
	callq	clock
	movq	%rax, %r15
	movq	%rbx, %rdi
	movl	$10, %esi
	movl	$10, %edx
	callq	_Z16gpuMatrixInversePdii
	movq	%rax, %r14
	callq	clock
	subq	%r15, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.10, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	.LCPI9_1(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.11, %esi
	movl	$9, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%r14, %rdi
	movl	$10, %esi
	movl	$10, %edx
	callq	_Z11printMatrixPdii
	movl	$1, %edi
	movl	$800, %esi                      # imm = 0x320
	callq	calloc@PLT
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB9_7:                                # %.preheader34
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB9_8 Depth 2
                                        #       Child Loop BB9_9 Depth 3
	leaq	(%rax,%rax,4), %rcx
	shlq	$4, %rcx
	addq	%r15, %rcx
	movq	%r14, %rdx
	xorl	%esi, %esi
.LBB9_8:                                # %.preheader
                                        #   Parent Loop BB9_7 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB9_9 Depth 3
	movsd	(%rcx,%rsi,8), %xmm0            # xmm0 = mem[0],zero
	movq	%rdx, %rdi
	xorl	%r8d, %r8d
.LBB9_9:                                #   Parent Loop BB9_7 Depth=1
                                        #     Parent Loop BB9_8 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movsd	(%rbx,%r8,8), %xmm1             # xmm1 = mem[0],zero
	mulsd	(%rdi), %xmm1
	addsd	%xmm1, %xmm0
	incq	%r8
	addq	$80, %rdi
	cmpq	$10, %r8
	jne	.LBB9_9
# %bb.10:                               #   in Loop: Header=BB9_8 Depth=2
	movsd	%xmm0, (%rcx,%rsi,8)
	incq	%rsi
	addq	$8, %rdx
	cmpq	$10, %rsi
	jne	.LBB9_8
# %bb.11:                               #   in Loop: Header=BB9_7 Depth=1
	incq	%rax
	addq	$80, %rbx
	cmpq	$10, %rax
	jne	.LBB9_7
# %bb.12:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%r15, %rdi
	movl	$10, %esi
	movl	$10, %edx
	callq	_Z11printMatrixPdii
	movq	%r14, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	main, .Lfunc_end9-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17harnessZeroKernelPdiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17computeRowsKernelPdii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17computeColsKernelPdii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19augmentMatrixKernelPdS_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22getInverseMatrixKernelPdS_ii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\t"
	.size	.L.str, 2

	.type	_Z17harnessZeroKernelPdiii,@object # @_Z17harnessZeroKernelPdiii
	.section	.rodata,"a",@progbits
	.globl	_Z17harnessZeroKernelPdiii
	.p2align	3, 0x0
_Z17harnessZeroKernelPdiii:
	.quad	_Z32__device_stub__harnessZeroKernelPdiii
	.size	_Z17harnessZeroKernelPdiii, 8

	.type	_Z17computeRowsKernelPdii,@object # @_Z17computeRowsKernelPdii
	.globl	_Z17computeRowsKernelPdii
	.p2align	3, 0x0
_Z17computeRowsKernelPdii:
	.quad	_Z32__device_stub__computeRowsKernelPdii
	.size	_Z17computeRowsKernelPdii, 8

	.type	_Z17computeColsKernelPdii,@object # @_Z17computeColsKernelPdii
	.globl	_Z17computeColsKernelPdii
	.p2align	3, 0x0
_Z17computeColsKernelPdii:
	.quad	_Z32__device_stub__computeColsKernelPdii
	.size	_Z17computeColsKernelPdii, 8

	.type	_Z19augmentMatrixKernelPdS_ii,@object # @_Z19augmentMatrixKernelPdS_ii
	.globl	_Z19augmentMatrixKernelPdS_ii
	.p2align	3, 0x0
_Z19augmentMatrixKernelPdS_ii:
	.quad	_Z34__device_stub__augmentMatrixKernelPdS_ii
	.size	_Z19augmentMatrixKernelPdS_ii, 8

	.type	_Z22getInverseMatrixKernelPdS_ii,@object # @_Z22getInverseMatrixKernelPdS_ii
	.globl	_Z22getInverseMatrixKernelPdS_ii
	.p2align	3, 0x0
_Z22getInverseMatrixKernelPdS_ii:
	.quad	_Z37__device_stub__getInverseMatrixKernelPdS_ii
	.size	_Z22getInverseMatrixKernelPdS_ii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/Otiliaa/matrixInversionCUDA/master/MatrixInverse.hip"
	.size	.L.str.1, 115

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMalloc((void **)&d_augmentedMatrix, sizeof(double) * length * 2)"
	.size	.L.str.2, 68

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipMalloc((void **)&d_inputMatrix, sizeof(double) * length)"
	.size	.L.str.3, 60

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipMalloc((void **)&d_inverseMatrix, sizeof(double) * length)"
	.size	.L.str.4, 62

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipMemcpy(d_inputMatrix, inputMatrix, sizeof(double) * length, hipMemcpyHostToDevice)"
	.size	.L.str.5, 86

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMemcpy(h_inverseMatrix, d_inverseMatrix, sizeof(double) * length, hipMemcpyDeviceToHost)"
	.size	.L.str.6, 92

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"hipFree(d_augmentedMatrix)"
	.size	.L.str.7, 27

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipFree(d_inverseMatrix)"
	.size	.L.str.8, 25

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipFree(d_inputMatrix)"
	.size	.L.str.9, 23

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"\n running time on GPU is "
	.size	.L.str.10, 26

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	" secs\357\274\201\n"
	.size	.L.str.11, 10

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"\nTest the result from GPU\n"
	.size	.L.str.12, 27

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	" returned "
	.size	.L.str.13, 11

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"("
	.size	.L.str.14, 2

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	") at "
	.size	.L.str.15, 6

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	":"
	.size	.L.str.16, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17harnessZeroKernelPdiii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17computeRowsKernelPdii"
	.size	.L__unnamed_2, 26

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z17computeColsKernelPdii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z19augmentMatrixKernelPdS_ii"
	.size	.L__unnamed_4, 30

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z22getInverseMatrixKernelPdS_ii"
	.size	.L__unnamed_5, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__harnessZeroKernelPdiii
	.addrsig_sym _Z32__device_stub__computeRowsKernelPdii
	.addrsig_sym _Z32__device_stub__computeColsKernelPdii
	.addrsig_sym _Z34__device_stub__augmentMatrixKernelPdS_ii
	.addrsig_sym _Z37__device_stub__getInverseMatrixKernelPdS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z17harnessZeroKernelPdiii
	.addrsig_sym _Z17computeRowsKernelPdii
	.addrsig_sym _Z17computeColsKernelPdii
	.addrsig_sym _Z19augmentMatrixKernelPdS_ii
	.addrsig_sym _Z22getInverseMatrixKernelPdS_ii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17harnessZeroKernelPdiii ; -- Begin function _Z17harnessZeroKernelPdiii
	.globl	_Z17harnessZeroKernelPdiii
	.p2align	8
	.type	_Z17harnessZeroKernelPdiii,@function
_Z17harnessZeroKernelPdiii:             ; @_Z17harnessZeroKernelPdiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_lshl_b32 s2, s6, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mul_i32 s2, s4, s6
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 3, v0
	v_lshl_add_u32 v2, s2, 1, v1
	s_mul_i32 s2, s5, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_lshl_add_u32 v2, s2, 1, v1
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[4:5], off
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b64 v0, v[6:7], v[1:2] offset1:8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b64 v[0:3], v0 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	global_store_b64 v[4:5], v[0:1], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17harnessZeroKernelPdiii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17harnessZeroKernelPdiii, .Lfunc_end0-_Z17harnessZeroKernelPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17computeRowsKernelPdii ; -- Begin function _Z17computeRowsKernelPdii
	.globl	_Z17computeRowsKernelPdii
	.p2align	8
	.type	_Z17computeRowsKernelPdii,@function
_Z17computeRowsKernelPdii:              ; @_Z17computeRowsKernelPdii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_lshl_b32 s4, s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mul_i32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 1
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s3, v1
	s_add_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_lshl_b64 s[2:3], s[2:3], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_load_b64 v[5:6], v[3:4], off
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, s0 :: v_dual_lshlrev_b32 v15, 3, v0
	v_mov_b32_e32 v1, s1
	s_waitcnt vmcnt(0)
	ds_store_b64 v15, v[5:6]
	ds_store_b64 v2, v[0:1] offset:4096
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[0:1], v15
	ds_load_b64 v[5:6], v2 offset:4096
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[0:1]
	v_div_scale_f64 v[13:14], vcc_lo, v[0:1], v[5:6], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
	v_div_fixup_f64 v[0:1], v[7:8], v[5:6], v[0:1]
	ds_store_b64 v15, v[0:1]
	global_store_b64 v[3:4], v[0:1], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17computeRowsKernelPdii
		.amdhsa_group_segment_fixed_size 4104
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17computeRowsKernelPdii, .Lfunc_end1-_Z17computeRowsKernelPdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4104 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17computeColsKernelPdii ; -- Begin function _Z17computeColsKernelPdii
	.globl	_Z17computeColsKernelPdii
	.p2align	8
	.type	_Z17computeColsKernelPdii,@function
_Z17computeColsKernelPdii:              ; @_Z17computeColsKernelPdii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[4:5], s[0:1], 0x8
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[5:6]
	v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
	s_lshl_b32 s3, s5, 1
	v_cmp_gt_i32_e64 s2, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v2
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s2
	s_cbranch_execz .LBB2_5
; %bb.1:
	v_mul_lo_u32 v1, s3, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s4, v1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b64 v[7:8], v[6:7], off
	v_lshlrev_b32_e32 v6, 3, v4
	v_lshl_add_u32 v5, v5, 7, v6
	s_waitcnt vmcnt(0)
	v_cmp_neq_f64_e32 vcc_lo, 0, v[7:8]
	ds_store_b64 v5, v[7:8] offset:2048
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.2:
	v_add_nc_u32_e32 v1, v1, v2
	s_mul_i32 s2, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, s2, 1, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v5, v[7:8]
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[3:4] offset:4096
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[3:4], v5
	v_cmpx_ne_u32_e64 s4, v0
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_add_nc_u32_e32 v0, 0x800, v5
	v_add_nc_u32_e32 v8, 0x1000, v6
	ds_load_b64 v[6:7], v0
	ds_load_b64 v[8:9], v8
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[3:4], -v[6:7], v[8:9], v[3:4]
	ds_store_b64 v5, v[3:4]
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[1:2], v[3:4], off
.LBB2_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17computeColsKernelPdii
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z17computeColsKernelPdii, .Lfunc_end2-_Z17computeColsKernelPdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19augmentMatrixKernelPdS_ii ; -- Begin function _Z19augmentMatrixKernelPdS_ii
	.globl	_Z19augmentMatrixKernelPdS_ii
	.p2align	8
	.type	_Z19augmentMatrixKernelPdS_ii,@function
_Z19augmentMatrixKernelPdS_ii:          ; @_Z19augmentMatrixKernelPdS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s5, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v2
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB3_9
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_lshr_b32 s0, s3, 31
	s_mov_b32 s1, exec_lo
	s_add_i32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s0, s0, 1
	v_cmpx_le_i32_e64 s0, v0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_7
; %bb.2:
	v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
	v_subrev_nc_u32_e32 v5, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s4, v0
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 v5, v2
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v3, v2
	global_store_b64 v[0:1], v[2:3], off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB3_4:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB3_6
; %bb.5:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x3ff00000
	global_store_b64 v[0:1], v[2:3], off
.LBB3_6:                                ; %Flow43
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr0_vgpr1
.LBB3_7:                                ; %Flow44
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_9
; %bb.8:
	v_mul_lo_u32 v3, v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v3
	v_add_nc_u32_e32 v1, v3, v1
	v_add_nc_u32_e32 v3, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 1, v1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v1, v0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[1:2], off
.LBB3_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19augmentMatrixKernelPdS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z19augmentMatrixKernelPdS_ii, .Lfunc_end3-_Z19augmentMatrixKernelPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22getInverseMatrixKernelPdS_ii ; -- Begin function _Z22getInverseMatrixKernelPdS_ii
	.globl	_Z22getInverseMatrixKernelPdS_ii
	.p2align	8
	.type	_Z22getInverseMatrixKernelPdS_ii,@function
_Z22getInverseMatrixKernelPdS_ii:       ; @_Z22getInverseMatrixKernelPdS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_lshr_b32 s4, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s3, s4
	s_ashr_i32 s4, s4, 1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mul_lo_u32 v3, v1, s3
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v0, s4, v3
	v_lshrrev_b32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 1, v3
	v_add_nc_u32_e32 v3, v3, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	global_load_b64 v[1:2], v[1:2], off
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[1:2], off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22getInverseMatrixKernelPdS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z22getInverseMatrixKernelPdS_ii, .Lfunc_end4-_Z22getInverseMatrixKernelPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17harnessZeroKernelPdiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17harnessZeroKernelPdiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
