#include <cstdio>
#include <cmath>

#define OCCUPIED(board, field) ((board) & (1L<<(field)))
#define ON_BOARD(field) (0 <= (field) && (field) < 64)
#define EVALUATE(p1, p2) ((builtin_popcount(p1))-(builtin_popcount(p2)))

extern "C" {

const int INF = 128;
const int BOARD_SIZE = 8;
const int WARP_SIZE = 32;
const int MAX_DEPTH = 1;
const int STACK_SIZE = MAX_DEPTH * BOARD_SIZE * BOARD_SIZE;

__device__ void print(long long int X) {
    printf(">>%lld\n", X);
    for (int i = 0; i < BOARD_SIZE; ++i) {
        for (int j = 0; j < BOARD_SIZE; ++j) {
            if (X & (1L << (i * BOARD_SIZE + j))) printf("1");
            else printf("0");
        }
        printf("\n");
    }
}

__device__ int builtin_popcount(long long int x) {
	int ret = 0;
	for(int i = 0; i < 64; ++i) {
		if(x&(1L<<i)) ++ret;
	}
	return ret;
}

/* args: Boards[N][2], N-count of boards, PossibleMoves[N][64], Results[N], player_token-'O' or 'X' */
__global__ void generate_moves(long long *Boards, int N, long long *PossibleMoves, int *Results) {
   
	int X[8] = {-1, -1, 0, 1, 1, 1, 0, -1};
 	int Y[8] = {0, -BOARD_SIZE, -BOARD_SIZE, -BOARD_SIZE, 0, BOARD_SIZE, BOARD_SIZE, BOARD_SIZE};

    // 28KB
    __shared__ long long int S[4][STACK_SIZE][2];
    __shared__ int Result[4][STACK_SIZE];
    __shared__ int Parent[4][STACK_SIZE];
    __shared__ int Depth[4][STACK_SIZE];
    __shared__ int Size[4];

    /* INDICES */
    int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
    int board_id = thread_id / WARP_SIZE;
    if ( board_id >= N ) return;
    int field_id = (int) threadIdx.x % WARP_SIZE;
    int idx_board = board_id % 4;

    /* COPY INPUT BOARD */
    if (field_id == 0) {
        S[idx_board][0][0] = Boards[board_id];
        S[idx_board][0][1] = Boards[N + board_id];
        Depth[idx_board][0] = MAX_DEPTH;
        Parent[idx_board][0] = -1;
        Result[idx_board][0] = -INF;
        Size[idx_board] = 1;
    }
    __syncthreads();

    /* DFS */
    while (Size[idx_board] != 0) {
        int end = Size[idx_board] - 1;
        long long player_pawns = S[idx_board][end][0];
        long long opponent_pawns = S[idx_board][end][1];
        int parent = Parent[idx_board][end];
        int depth = Depth[idx_board][end];
        bool pop_vertex = false;
		
        if (depth == 0 && field_id == 0) Result[idx_board][end] = EVALUATE(player_pawns, opponent_pawns);	
        __syncthreads();

        // terminal
        if (field_id == 0 && Result[idx_board][end] != -INF) {												
            if(parent != -1) Result[idx_board][parent] = max(Result[idx_board][parent], -Result[idx_board][end]);			
            Size[idx_board] -= 1;
            pop_vertex = true;																			
        }
        __syncthreads();

        // visit current node
        if (field_id == 0 && !pop_vertex) Result[idx_board][end] = EVALUATE(player_pawns, opponent_pawns);

        // thread #idInBoard processes fields idInBoard and idInBoard + 32
        if(!pop_vertex)
        for (int k = 0; k < 2; ++k) {
            int field = WARP_SIZE * k + field_id;

            // Move cannot be applied if the field is occupied
            if (!OCCUPIED(player_pawns, field) && !OCCUPIED(opponent_pawns, field)) {    //check whether field is free
                bool flag = false;
                long long tmp = 0;

                // Try all 8 directions
                for (int i = 0; i < 8; ++i) {
                    // Direction of the move
                    int shift = X[i] + Y[i];
                    int opponents_field = field + shift;
                    int j = 0;

                    // Continue as long as fields in the row are occupied by the opponent
                    while (ON_BOARD(opponents_field) && OCCUPIED(opponent_pawns, opponents_field)) {
                        j++;
                        opponents_field += shift;
                    }

                    // If move is possible, Reversi!
                    if (ON_BOARD(opponents_field) && OCCUPIED(player_pawns, opponents_field) && j > 1) {
                        // Reversi!
                        while (opponents_field != field) {
                            tmp |= 1L << opponents_field;    //all gained fields
                            opponents_field -= shift;
                        }
                        flag = true;
                    }
                }

                // Place the new pawn
                tmp |= 1L << field;
                // Avoid if
                tmp *= flag;
                PossibleMoves[board_id * 64 + field] = tmp;            //save gained fields
            }
        }
        __syncthreads();

        //zero-thread in board pushes possible moves onto stack
        if (field_id == 0 && !pop_vertex) {
            for (int i = 0; i < BOARD_SIZE; ++i) {
                for (int j = 0; j < BOARD_SIZE; ++j) {
                    long long move = PossibleMoves[board_id * 64 + i * BOARD_SIZE + j];
                    if (move) {
                        int top = Size[idx_board];
                        Size[idx_board] = top + 1;				
                        S[idx_board][top][1] = player_pawns | move;        //old fields + gained
                        S[idx_board][top][0] = opponent_pawns ^ move;      //old fields xor gained by opponent player
                        Parent[idx_board][top] = end;
                        Result[idx_board][top] = -INF;
                        Depth[idx_board][top] = depth - 1;
                    }
                }
            }
        }
        __syncthreads();
    }
    Results[board_id] = Result[idx_board][0];
}

}

	.file	"tmpxft_00368f83_00000000-6_othello.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	print
	.type	print, @function
print:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	print, .-print
	.globl	builtin_popcount
	.type	builtin_popcount, @function
builtin_popcount:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	builtin_popcount, .-builtin_popcount
	.globl	_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi
	.type	_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi, @function
_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	generate_moves(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L6:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi, .-_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi
	.globl	generate_moves
	.type	generate_moves, @function
generate_moves:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z14generate_movesPxiS_PiPxiS_Pi
	.cfi_endproc
.LFE2054:
	.size	generate_moves, .-generate_moves
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"generate_moves"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	generate_moves(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>

#define OCCUPIED(board, field) ((board) & (1L<<(field)))
#define ON_BOARD(field) (0 <= (field) && (field) < 64)
#define EVALUATE(p1, p2) ((builtin_popcount(p1))-(builtin_popcount(p2)))

extern "C" {

const int INF = 128;
const int BOARD_SIZE = 8;
const int WARP_SIZE = 32;
const int MAX_DEPTH = 1;
const int STACK_SIZE = MAX_DEPTH * BOARD_SIZE * BOARD_SIZE;

__device__ void print(long long int X) {
    printf(">>%lld\n", X);
    for (int i = 0; i < BOARD_SIZE; ++i) {
        for (int j = 0; j < BOARD_SIZE; ++j) {
            if (X & (1L << (i * BOARD_SIZE + j))) printf("1");
            else printf("0");
        }
        printf("\n");
    }
}

__device__ int builtin_popcount(long long int x) {
	int ret = 0;
	for(int i = 0; i < 64; ++i) {
		if(x&(1L<<i)) ++ret;
	}
	return ret;
}

/* args: Boards[N][2], N-count of boards, PossibleMoves[N][64], Results[N], player_token-'O' or 'X' */
__global__ void generate_moves(long long *Boards, int N, long long *PossibleMoves, int *Results) {
   
	int X[8] = {-1, -1, 0, 1, 1, 1, 0, -1};
 	int Y[8] = {0, -BOARD_SIZE, -BOARD_SIZE, -BOARD_SIZE, 0, BOARD_SIZE, BOARD_SIZE, BOARD_SIZE};

    // 28KB
    __shared__ long long int S[4][STACK_SIZE][2];
    __shared__ int Result[4][STACK_SIZE];
    __shared__ int Parent[4][STACK_SIZE];
    __shared__ int Depth[4][STACK_SIZE];
    __shared__ int Size[4];

    /* INDICES */
    int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
    int board_id = thread_id / WARP_SIZE;
    if ( board_id >= N ) return;
    int field_id = (int) threadIdx.x % WARP_SIZE;
    int idx_board = board_id % 4;

    /* COPY INPUT BOARD */
    if (field_id == 0) {
        S[idx_board][0][0] = Boards[board_id];
        S[idx_board][0][1] = Boards[N + board_id];
        Depth[idx_board][0] = MAX_DEPTH;
        Parent[idx_board][0] = -1;
        Result[idx_board][0] = -INF;
        Size[idx_board] = 1;
    }
    __syncthreads();

    /* DFS */
    while (Size[idx_board] != 0) {
        int end = Size[idx_board] - 1;
        long long player_pawns = S[idx_board][end][0];
        long long opponent_pawns = S[idx_board][end][1];
        int parent = Parent[idx_board][end];
        int depth = Depth[idx_board][end];
        bool pop_vertex = false;
		
        if (depth == 0 && field_id == 0) Result[idx_board][end] = EVALUATE(player_pawns, opponent_pawns);	
        __syncthreads();

        // terminal
        if (field_id == 0 && Result[idx_board][end] != -INF) {												
            if(parent != -1) Result[idx_board][parent] = max(Result[idx_board][parent], -Result[idx_board][end]);			
            Size[idx_board] -= 1;
            pop_vertex = true;																			
        }
        __syncthreads();

        // visit current node
        if (field_id == 0 && !pop_vertex) Result[idx_board][end] = EVALUATE(player_pawns, opponent_pawns);

        // thread #idInBoard processes fields idInBoard and idInBoard + 32
        if(!pop_vertex)
        for (int k = 0; k < 2; ++k) {
            int field = WARP_SIZE * k + field_id;

            // Move cannot be applied if the field is occupied
            if (!OCCUPIED(player_pawns, field) && !OCCUPIED(opponent_pawns, field)) {    //check whether field is free
                bool flag = false;
                long long tmp = 0;

                // Try all 8 directions
                for (int i = 0; i < 8; ++i) {
                    // Direction of the move
                    int shift = X[i] + Y[i];
                    int opponents_field = field + shift;
                    int j = 0;

                    // Continue as long as fields in the row are occupied by the opponent
                    while (ON_BOARD(opponents_field) && OCCUPIED(opponent_pawns, opponents_field)) {
                        j++;
                        opponents_field += shift;
                    }

                    // If move is possible, Reversi!
                    if (ON_BOARD(opponents_field) && OCCUPIED(player_pawns, opponents_field) && j > 1) {
                        // Reversi!
                        while (opponents_field != field) {
                            tmp |= 1L << opponents_field;    //all gained fields
                            opponents_field -= shift;
                        }
                        flag = true;
                    }
                }

                // Place the new pawn
                tmp |= 1L << field;
                // Avoid if
                tmp *= flag;
                PossibleMoves[board_id * 64 + field] = tmp;            //save gained fields
            }
        }
        __syncthreads();

        //zero-thread in board pushes possible moves onto stack
        if (field_id == 0 && !pop_vertex) {
            for (int i = 0; i < BOARD_SIZE; ++i) {
                for (int j = 0; j < BOARD_SIZE; ++j) {
                    long long move = PossibleMoves[board_id * 64 + i * BOARD_SIZE + j];
                    if (move) {
                        int top = Size[idx_board];
                        Size[idx_board] = top + 1;				
                        S[idx_board][top][1] = player_pawns | move;        //old fields + gained
                        S[idx_board][top][0] = opponent_pawns ^ move;      //old fields xor gained by opponent player
                        Parent[idx_board][top] = end;
                        Result[idx_board][top] = -INF;
                        Depth[idx_board][top] = depth - 1;
                    }
                }
            }
        }
        __syncthreads();
    }
    Results[board_id] = Result[idx_board][0];
}

}

	.text
	.file	"othello.hip"
	.globl	__device_stub__generate_moves   # -- Begin function __device_stub__generate_moves
	.type	__device_stub__generate_moves,@function
__device_stub__generate_moves:          # @__device_stub__generate_moves
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$generate_moves, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__generate_moves, .Lfunc_end0-__device_stub__generate_moves
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$generate_moves, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	generate_moves,@object          # @generate_moves
	.section	.rodata,"a",@progbits
	.globl	generate_moves
	.p2align	3, 0x0
generate_moves:
	.quad	__device_stub__generate_moves
	.size	generate_moves, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"generate_moves"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__generate_moves
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym generate_moves
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	generate_moves          ; -- Begin function generate_moves
	.globl	generate_moves
	.p2align	8
	.type	generate_moves,@function
generate_moves:                         ; @generate_moves
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 27, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 5, v1
	v_cmpx_gt_i32_e64 s4, v20
	s_cbranch_execz .LBB0_54
; %bb.1:
	v_lshrrev_b32_e32 v1, 30, v20
	v_and_b32_e32 v30, 31, v0
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v20, v1
	v_cmp_ne_u32_e64 s2, 0, v30
	v_cmp_eq_u32_e64 s3, 0, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, -4, v1
	v_sub_nc_u32_e32 v31, v20, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v32, 8, v31
	v_lshlrev_b32_e32 v0, 2, v31
	s_and_saveexec_b32 s6, s3
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_load_b64 s[8:9], s[0:1], 0x0
	v_lshlrev_b64 v[1:2], 3, v[20:21]
	s_ashr_i32 s5, s4, 31
	v_dual_mov_b32 v5, 1 :: v_dual_mov_b32 v6, -1
	s_lshl_b64 s[4:5], s[4:5], 3
	v_dual_mov_b32 v8, 0xffffff80 :: v_dual_lshlrev_b32 v7, 10, v31
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	ds_store_2addr_stride64_b32 v32, v5, v6 offset0:16 offset1:20
	s_waitcnt vmcnt(0)
	ds_store_b128 v7, v[1:4]
	ds_store_b32 v32, v8 offset:6144
	ds_store_b32 v0, v5 offset:7168
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v1, v0 offset:7168
	s_load_b128 s[4:7], s[0:1], 0x10
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e32 0, v1
	s_cbranch_execz .LBB0_53
; %bb.4:                                ; %.lr.ph206
	v_dual_mov_b32 v3, 1 :: v_dual_lshlrev_b32 v22, 6, v20
	v_dual_mov_b32 v0, -1 :: v_dual_add_nc_u32 v33, 0x1c00, v0
	v_dual_mov_b32 v34, 0xffffff80 :: v_dual_mov_b32 v9, -8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v23, 31, v22
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, 8
	s_mov_b32 s9, 0
	v_lshlrev_b64 v[4:5], 3, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v5, vcc_lo
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_25 Depth 2
                                        ;       Child Loop BB0_27 Depth 3
                                        ;         Child Loop BB0_29 Depth 4
                                        ;         Child Loop BB0_36 Depth 4
                                        ;     Child Loop BB0_47 Depth 2
                                        ;       Child Loop BB0_48 Depth 3
	v_add_nc_u32_e32 v35, -1, v1
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v1, 2, v35
	v_lshlrev_b32_e32 v4, 4, v35
	v_lshl_add_u32 v1, v31, 8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v4, v31, 10, v4
	ds_load_2addr_stride64_b32 v[25:26], v1 offset0:16 offset1:20
	ds_load_b128 v[16:19], v4
	s_waitcnt lgkmcnt(1)
	v_or_b32_e32 v4, v25, v30
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_11
; %bb.6:                                ; %.preheader188.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v4, 0
	s_mov_b64 s[0:1], 0
.LBB0_7:                                ; %.preheader188
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	v_lshrrev_b64 v[5:6], s0, v[16:17]
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 64
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v5
	v_add_nc_u32_e32 v4, v4, v5
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ; %builtin_popcount.exit.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
.LBB0_9:                                ; %builtin_popcount.exit
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[6:7], s0, v[18:19]
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 64
	v_and_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %builtin_popcount.exit168
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v5
	ds_store_b32 v1, v4 offset:6144
.LBB0_11:                               ; %Flow278
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_17
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=1
	ds_load_b32 v4, v1 offset:6144
	s_mov_b32 s10, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e32 0xffffff80, v4
	s_cbranch_execz .LBB0_16
; %bb.13:                               ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s10, exec_lo
	v_cmpx_ne_u32_e32 -1, v26
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_5 Depth=1
	v_lshlrev_b32_e32 v5, 2, v26
	v_sub_nc_u32_e32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v5, v31, 8, v5
	ds_load_b32 v6, v5 offset:6144
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v4, v6, v4
	ds_store_b32 v5, v4 offset:6144
.LBB0_15:                               ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	ds_load_b32 v4, v33
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, -1, v4
	ds_store_b32 v33, v4
.LBB0_16:                               ; %Flow276
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, exec_lo
.LBB0_17:                               ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_or_b32 s0, s2, s11
	s_waitcnt lgkmcnt(0)
	s_xor_b32 s10, s0, -1
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s12, s10
	s_cbranch_execz .LBB0_23
; %bb.18:                               ; %.preheader187.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v4, 0
	s_mov_b64 s[0:1], 0
.LBB0_19:                               ; %.preheader187
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[5:6], s0, v[16:17]
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 64
	v_and_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v5
	s_cbranch_scc1 .LBB0_19
; %bb.20:                               ; %builtin_popcount.exit174.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
.LBB0_21:                               ; %builtin_popcount.exit174
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[6:7], s0, v[18:19]
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 64
	v_and_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	s_cbranch_scc1 .LBB0_21
; %bb.22:                               ; %builtin_popcount.exit180
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v5
	ds_store_b32 v1, v4 offset:6144
.LBB0_23:                               ; %Flow275
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_xor_b32 s0, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_45
; %bb.24:                               ; %.preheader185.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_or_b32_e32 v36, v17, v19
	v_or_b32_e32 v37, v16, v18
	s_mov_b32 s0, 0
	s_mov_b32 s11, -1
.LBB0_25:                               ; %.preheader185
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_27 Depth 3
                                        ;         Child Loop BB0_29 Depth 4
                                        ;         Child Loop BB0_36 Depth 4
	v_or_b32_e32 v38, s0, v30
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], v38, 1
	v_and_b32_e32 v5, v27, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v26, v37
	v_cmpx_eq_u64_e32 0, v[4:5]
	s_cbranch_execz .LBB0_44
; %bb.26:                               ; %.preheader183.preheader
                                        ;   in Loop: Header=BB0_25 Depth=2
	v_mov_b32_e32 v28, 0
	v_mov_b32_e32 v29, 0
	s_mov_b32 s15, 0
	s_mov_b32 s14, 0
                                        ; implicit-def: $sgpr13
.LBB0_27:                               ; %.preheader183
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_25 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_29 Depth 4
                                        ;         Child Loop BB0_36 Depth 4
	v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, v2
	s_mov_b32 m0, s14
	v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v4, v3
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v6, v2
	v_mov_b32_e32 v10, v9
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v2
	v_mov_b32_e32 v14, v13
	v_mov_b32_e32 v15, v13
	v_movrels_b32_e32 v1, v0
	v_movrels_b32_e32 v4, v8
	s_and_not1_b32 s0, s13, exec_lo
	s_and_b32 s13, s15, exec_lo
	s_mov_b32 s16, exec_lo
	s_or_b32 s13, s0, s13
	v_add_nc_u32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v38, v1
	v_cmpx_gt_u32_e32 64, v8
	s_cbranch_execz .LBB0_41
; %bb.28:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_27 Depth=3
	v_mov_b32_e32 v10, v1
	s_mov_b32 s0, 0
	s_mov_b32 s22, 0
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr19
.LBB0_29:                               ; %.lr.ph
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_25 Depth=2
                                        ;       Parent Loop BB0_27 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v7, v8
	s_or_b32 s19, s19, exec_lo
	s_and_not1_b32 s21, s21, exec_lo
	s_or_b32 s20, s20, exec_lo
	s_mov_b32 s24, exec_lo
	v_lshlrev_b64 v[4:5], v7, 1
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $vgpr8
	v_mov_b32_e32 v6, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v12, v5, v19
	v_and_b32_e32 v11, v4, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e32 0, v[11:12]
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=4
	v_add_nc_u32_e32 v8, v7, v1
	v_add_nc_u32_e32 v10, v6, v1
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s25, s15, exec_lo
	s_and_not1_b32 s20, s20, exec_lo
	v_cmp_lt_u32_e32 vcc_lo, 63, v8
	s_add_i32 s23, s22, 1
	s_and_not1_b32 s19, s19, exec_lo
	s_or_b32 s21, s21, s25
	s_and_b32 s26, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s20, s20, s26
; %bb.31:                               ; %Flow270
                                        ;   in Loop: Header=BB0_29 Depth=4
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s24, exec_lo, s20
	v_mov_b32_e32 v11, s22
	s_or_b32 s0, s24, s0
	s_and_not1_b32 s18, s18, exec_lo
	s_and_b32 s22, s19, exec_lo
	s_and_not1_b32 s17, s17, exec_lo
	s_and_b32 s24, s21, exec_lo
	s_or_b32 s18, s18, s22
	s_or_b32 s17, s17, s24
	s_mov_b32 s22, s23
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_29
; %bb.32:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.33:                               ; %.critedge
                                        ;   in Loop: Header=BB0_27 Depth=3
	v_and_b32_e32 v5, v5, v17
	v_and_b32_e32 v4, v4, v16
	v_cmp_lt_u32_e64 s0, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
	s_and_b32 s19, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s19
	s_cbranch_execz .LBB0_39
; %bb.34:                               ; %.preheader
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_mov_b32 s19, exec_lo
	v_cmpx_ne_u32_e64 v7, v38
	s_cbranch_execz .LBB0_38
; %bb.35:                               ; %.lr.ph198.preheader
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_mov_b32 s20, 0
.LBB0_36:                               ; %.lr.ph198
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_25 Depth=2
                                        ;       Parent Loop BB0_27 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_add_nc_u32_e32 v4, v38, v6
	v_sub_nc_u32_e32 v6, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], v4, 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v29, v5, v29
	v_or_b32_e32 v28, v4, v28
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_36
; %bb.37:                               ; %Flow266
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_38:                               ; %Flow267
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s19
	s_or_b32 s15, s15, exec_lo
.LBB0_39:                               ; %Flow268
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s17, exec_lo
	s_and_b32 s15, s15, exec_lo
	s_or_b32 s17, s0, s15
.LBB0_40:                               ; %Flow269
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s13, exec_lo
	s_and_b32 s13, s17, exec_lo
	s_or_b32 s13, s0, s13
.LBB0_41:                               ; %Flow271
                                        ;   in Loop: Header=BB0_27 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, 8
	s_cbranch_scc1 .LBB0_43
; %bb.42:                               ;   in Loop: Header=BB0_27 Depth=3
	s_mov_b32 s15, s13
	s_branch .LBB0_27
.LBB0_43:                               ;   in Loop: Header=BB0_25 Depth=2
	v_or_b32_e32 v4, v38, v22
	v_or_b32_e32 v1, v29, v27
	v_or_b32_e32 v6, v28, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cndmask_b32_e64 v7, 0, v1, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, 0, v6, s13
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_store_b64 v[4:5], v[6:7], off
.LBB0_44:                               ; %Flow272
                                        ;   in Loop: Header=BB0_25 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	s_xor_b32 s11, s11, -1
	s_mov_b32 s0, 32
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_mov_b32 s11, 0
	s_cbranch_vccnz .LBB0_25
.LBB0_45:                               ; %Flow274
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s11, s10
	s_cbranch_execz .LBB0_52
; %bb.46:                               ; %.preheader184
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v4, v23 :: v_dual_add_nc_u32 v1, -1, v25
	v_mov_b32_e32 v5, v24
	s_mov_b32 s10, 0
.LBB0_47:                               ; %.preheader182
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_48 Depth 3
	s_mov_b64 s[0:1], 0
.LBB0_48:                               ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_47 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v6, vcc_lo, v4, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	s_mov_b32 s12, exec_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e32 0, v[6:7]
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_48 Depth=3
	ds_load_b32 v8, v33
	v_or_b32_e32 v27, v6, v16
	v_xor_b32_e32 v25, v6, v18
	v_or_b32_e32 v28, v7, v17
	v_xor_b32_e32 v26, v7, v19
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v10, 4, v8
	v_lshlrev_b32_e32 v11, 2, v8
	v_add_nc_u32_e32 v6, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v7, v31, 10, v10
	v_lshl_add_u32 v8, v31, 8, v11
	ds_store_b32 v33, v6
	ds_store_b128 v7, v[25:28]
	ds_store_b32 v8, v34 offset:6144
	ds_store_2addr_stride64_b32 v8, v1, v35 offset0:16 offset1:20
.LBB0_50:                               ;   in Loop: Header=BB0_48 Depth=3
	s_or_b32 exec_lo, exec_lo, s12
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 64
	s_cbranch_scc0 .LBB0_48
; %bb.51:                               ;   in Loop: Header=BB0_47 Depth=2
	v_add_co_u32 v4, vcc_lo, v4, 64
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 8
	s_cbranch_scc0 .LBB0_47
.LBB0_52:                               ; %Flow265
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v1, v33
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_5
.LBB0_53:                               ; %Flow280
	s_or_b32 exec_lo, exec_lo, s8
	ds_load_b32 v2, v32 offset:6144
	v_lshlrev_b64 v[0:1], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_54:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel generate_moves
		.amdhsa_group_segment_fixed_size 7184
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	generate_moves, .Lfunc_end0-generate_moves
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1916
; NumSgprs: 29
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 7184 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 7184
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           generate_moves
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         generate_moves.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
