extern "C"
__global__ void dispatchDots(
						   //Tree specs
						   // per Block In
						   int* dotIndexes, 
                           int* stBl0, int* nPtBl0,
						   int* stBl1, int* nPtBl1,
						   int* blLevel,
						   // per GPU Block In
						   int* idBl, 
						   int* offsBl,
						   // input values, per dot
						   int* rkBlPos,
						   int* rkBlNeg,
						   int* rkBlMid0,
						   int* rkBlMid1,
						   // input value, per Blocks Out
						   int* nPtBlPos,
						   int* nPtBlNeg,
						   int* nPtBlMid0,
						   int* nPtBlMid1,
						   int nBlocks,
						   int nDots, 
						   int* whatToDo, 
						   int* addrPt,
						   int* addrBloc,
						   int* newBlockLvl,
						   
						   // bloc split				   	
						   int* blKeep_dotIndexes, 
                           int* blKeep_stBl0, int* blKeep_nPtBl0,
						   int* blKeep_stBl1, int* blKeep_nPtBl1,
						   int* blKeep_blLevel,
						   
						   //bloc keep						   
						   int* blFinal_dotIndexes, 
                           int* blFinal_stBl0, int* blFinal_nPtBl0,
						   int* blFinal_stBl1, int* blFinal_nPtBl1,
						   int* blFinal_blLevel,
						   
						   // bloc discard
						   int* blDiscard_dotIndexes, 
                           int* blDiscard_stBl0, int* blDiscard_nPtBl0,
						   int* blDiscard_stBl1, int* blDiscard_nPtBl1,
						   int* blDiscard_blLevel
						   
						)
{
	extern __shared__ int array[]; 
	int* whatTD = (int*)&array[7];
	int* addrPtSh = (int*)&whatTD[4];
	int* addrBlSh = (int*)&addrPtSh[4];
	// Fetch block data
    int iGPUBlock=blockIdx.x;
	int iThread=threadIdx.x;
	int idBloc;
	if (iThread==0) {
		 idBloc=idBl[iGPUBlock];		 
		 array[0]=offsBl[iGPUBlock];
		 array[1]=stBl0[idBloc];
		 array[2]=nPtBl0[idBloc];
		 array[3]=stBl1[idBloc];		 
		 array[4]=nPtBl1[idBloc];
		 array[5]=blLevel[idBloc];
		 array[6]=idBloc;
		 
		 for (int i=0;i<4;i++) {
			 whatTD[i]=whatToDo[4*idBloc+i];
			 addrPtSh[i]=addrPt[4*idBloc+i];
			 addrBlSh[i]=addrBloc[4*idBloc+i];
			 /*if (array[0]==0) {
				printf("BlocIni= %i; NBloc= %i; AddrPt= %i; AddrBl= %i; WTd= %i \n",idBloc, i, addrPtSh[i], addrBlSh[i], whatTD[i] );
			 }*/
		 }	 
	}	
	__syncthreads();		
	int offsPt = array[0];
	int startIndexBl0 = array[1];	 
	int nPtBlock0 = array[2];
	int startIndexBl1 = array[3]; // useless in fact
	int nPtBlock1 = array[4];
	int blockLevel = array[5];
	int nPts = nPtBlock0 + nPtBlock1;	
	int ptToBeComputed = iThread+offsPt;
	idBloc = array[6];

	if (ptToBeComputed<nPts) {
		// Oki, copy dots at the proper location
		int addr_pt = startIndexBl0+ptToBeComputed;
		int id_pt=dotIndexes[addr_pt];
		//if (id_pt<0) {printf("Ca joue pas \n");}
		int inBloc1 = (ptToBeComputed>=nPtBlock0);
		int rK, wTD;
		//int* tabDest;
		//int isSet=0;
		//int shouldBeSomeWhere = 0;
		// Let's handle bloc Neg = 0
		wTD=whatTD[0];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlNeg[addr_pt];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut \n", (addrPtSh[0]+rK+inBloc1*nPtBlNeg[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
			}
			rK=rkBlNeg[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut \n", (addrPtSh[0]+rK+inBloc1*nPtBlNeg[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[1];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlPos[addr_pt];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[1]+rK+inBloc1*nPtBlPos[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[1]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[1]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[1]+rK]=id_pt;
			}
			rK=rkBlPos[addr_pt+nDots];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[1]+rK+inBloc1*nPtBlPos[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[2];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlMid0[addr_pt];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n",(addrPtSh[2]+rK), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[2]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[2]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[2]+rK]=id_pt;
			}
			rK=rkBlMid0[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[2]+rK+nPtBlMid0[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[3];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlMid1[addr_pt];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[3]+rK), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[3]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[3]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[3]+rK]=id_pt;
			}
			rK=rkBlMid1[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[3]+rK+nPtBlMid1[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
			}
		}
		//if ((isSet==0)&&(shouldBeSomeWhere==1)) {printf("De bleu! Le point %i n'a été mis nulle part! [%i, %i, %i, %i]\n", id_pt, whatTD[0], whatTD[1], whatTD[2], whatTD[3]);}
	}
	if ((iThread==0)&&(offsPt==0)) {
		// needs to fill bloc properties
		for (int i=0;i<4;i++) {
			int wTD = wTD=whatTD[i];
			int idNewBloc = addrBlSh[i];
			
			int nPtInBloc0, nPtInBloc1;
			if (i==0) {
				nPtInBloc0 = nPtBlNeg[idBloc];
				nPtInBloc1 = nPtBlNeg[idBloc+nBlocks];
			}
			if (i==1) {
				nPtInBloc0 = nPtBlPos[idBloc];
				nPtInBloc1 = nPtBlPos[idBloc+nBlocks];
			}
			if (i==2) {
				nPtInBloc0 = nPtBlMid0[idBloc];
				nPtInBloc1 = nPtBlMid0[idBloc+nBlocks];
			}
			if (i==3) {
				nPtInBloc0 = nPtBlMid1[idBloc];
				nPtInBloc1 = nPtBlMid1[idBloc+nBlocks];
			}
			//printf("\n idNewBloc = %i, on en fait %i \n nPtInBloc0 = %i, nPtInBloc1 = %i , addrPtSh = %i \n",idNewBloc, wTD,nPtInBloc0,nPtInBloc1, addrPtSh[i]);
			if (wTD==0) {
				//SPLIT
				//printf("SPLIT!!\n");
				blKeep_stBl0[idNewBloc]=addrPtSh[i];
				blKeep_nPtBl0[idNewBloc]=nPtInBloc0;
				blKeep_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blKeep_nPtBl1[idNewBloc]=nPtInBloc1;
				blKeep_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			if (wTD==1) {
				//KEEP
				blFinal_stBl0[idNewBloc]=addrPtSh[i];
				blFinal_nPtBl0[idNewBloc]=nPtInBloc0;
				blFinal_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blFinal_nPtBl1[idNewBloc]=nPtInBloc1;
				blFinal_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			if (wTD==2) {
				//DISCARD
				blDiscard_stBl0[idNewBloc]=addrPtSh[i];
				blDiscard_nPtBl0[idNewBloc]=nPtInBloc0;
				blDiscard_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blDiscard_nPtBl1[idNewBloc]=nPtInBloc1;
				blDiscard_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			
		}
	}
}
	.file	"tmpxft_002236a7_00000000-6_gpuDispatchDots.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$712, %rsp
	.cfi_def_cfa_offset 720
	movq	720(%rsp), %rax
	movq	%rdi, 296(%rsp)
	leaq	328(%rsp), %rdi
	movq	%rsi, 288(%rsp)
	leaq	340(%rsp), %rsi
	movq	%rax, 248(%rsp)
	movq	728(%rsp), %rax
	movq	%rdx, 280(%rsp)
	leaq	312(%rsp), %rdx
	movq	%rax, 240(%rsp)
	movq	736(%rsp), %rax
	movq	%rcx, 272(%rsp)
	leaq	320(%rsp), %rcx
	movq	%rax, 232(%rsp)
	movq	744(%rsp), %rax
	movq	%r8, 264(%rsp)
	movq	%rax, 224(%rsp)
	movq	752(%rsp), %rax
	movq	%r9, 256(%rsp)
	movq	%rax, 216(%rsp)
	movq	760(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	768(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	776(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	784(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	792(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	816(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	824(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	832(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	840(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	848(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	856(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	864(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	872(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	880(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	888(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	896(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	904(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	912(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	920(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	928(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	936(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	944(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	952(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	960(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	968(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	976(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	984(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 696(%rsp)
	xorl	%eax, %eax
	leaq	296(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 480(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 488(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 496(%rsp)
	leaq	800(%rsp), %rax
	movq	%rax, 504(%rsp)
	leaq	808(%rsp), %rax
	movq	%rax, 512(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 520(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 528(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 536(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 544(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 552(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 560(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 568(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 576(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 584(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 592(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 600(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 608(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 616(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 624(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 632(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 640(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 648(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 656(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 664(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 672(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 680(%rsp)
	movq	%rsp, %rax
	movq	%rax, 688(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 328(%rsp)
	movl	$1, 336(%rsp)
	movq	%rax, 340(%rsp)
	movl	$1, 348(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	320(%rsp)
	.cfi_def_cfa_offset 728
	leaq	dispatchDots(%rip), %rdi
	pushq	320(%rsp)
	.cfi_def_cfa_offset 736
	movq	356(%rsp), %rcx
	movl	364(%rsp), %r8d
	movq	344(%rsp), %rsi
	movl	352(%rsp), %edx
	leaq	392(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 728
	popq	%rdx
	.cfi_def_cfa_offset 720
.L2:
	movq	696(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$712, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	dispatchDots
	.type	dispatchDots, @function
dispatchDots:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z108__device_stub__Z12dispatchDotsPiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	dispatchDots, .-dispatchDots
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"dispatchDots"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	dispatchDots(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"
__global__ void dispatchDots(
						   //Tree specs
						   // per Block In
						   int* dotIndexes, 
                           int* stBl0, int* nPtBl0,
						   int* stBl1, int* nPtBl1,
						   int* blLevel,
						   // per GPU Block In
						   int* idBl, 
						   int* offsBl,
						   // input values, per dot
						   int* rkBlPos,
						   int* rkBlNeg,
						   int* rkBlMid0,
						   int* rkBlMid1,
						   // input value, per Blocks Out
						   int* nPtBlPos,
						   int* nPtBlNeg,
						   int* nPtBlMid0,
						   int* nPtBlMid1,
						   int nBlocks,
						   int nDots, 
						   int* whatToDo, 
						   int* addrPt,
						   int* addrBloc,
						   int* newBlockLvl,
						   
						   // bloc split				   	
						   int* blKeep_dotIndexes, 
                           int* blKeep_stBl0, int* blKeep_nPtBl0,
						   int* blKeep_stBl1, int* blKeep_nPtBl1,
						   int* blKeep_blLevel,
						   
						   //bloc keep						   
						   int* blFinal_dotIndexes, 
                           int* blFinal_stBl0, int* blFinal_nPtBl0,
						   int* blFinal_stBl1, int* blFinal_nPtBl1,
						   int* blFinal_blLevel,
						   
						   // bloc discard
						   int* blDiscard_dotIndexes, 
                           int* blDiscard_stBl0, int* blDiscard_nPtBl0,
						   int* blDiscard_stBl1, int* blDiscard_nPtBl1,
						   int* blDiscard_blLevel
						   
						)
{
	extern __shared__ int array[]; 
	int* whatTD = (int*)&array[7];
	int* addrPtSh = (int*)&whatTD[4];
	int* addrBlSh = (int*)&addrPtSh[4];
	// Fetch block data
    int iGPUBlock=blockIdx.x;
	int iThread=threadIdx.x;
	int idBloc;
	if (iThread==0) {
		 idBloc=idBl[iGPUBlock];		 
		 array[0]=offsBl[iGPUBlock];
		 array[1]=stBl0[idBloc];
		 array[2]=nPtBl0[idBloc];
		 array[3]=stBl1[idBloc];		 
		 array[4]=nPtBl1[idBloc];
		 array[5]=blLevel[idBloc];
		 array[6]=idBloc;
		 
		 for (int i=0;i<4;i++) {
			 whatTD[i]=whatToDo[4*idBloc+i];
			 addrPtSh[i]=addrPt[4*idBloc+i];
			 addrBlSh[i]=addrBloc[4*idBloc+i];
			 /*if (array[0]==0) {
				printf("BlocIni= %i; NBloc= %i; AddrPt= %i; AddrBl= %i; WTd= %i \n",idBloc, i, addrPtSh[i], addrBlSh[i], whatTD[i] );
			 }*/
		 }	 
	}	
	__syncthreads();		
	int offsPt = array[0];
	int startIndexBl0 = array[1];	 
	int nPtBlock0 = array[2];
	int startIndexBl1 = array[3]; // useless in fact
	int nPtBlock1 = array[4];
	int blockLevel = array[5];
	int nPts = nPtBlock0 + nPtBlock1;	
	int ptToBeComputed = iThread+offsPt;
	idBloc = array[6];

	if (ptToBeComputed<nPts) {
		// Oki, copy dots at the proper location
		int addr_pt = startIndexBl0+ptToBeComputed;
		int id_pt=dotIndexes[addr_pt];
		//if (id_pt<0) {printf("Ca joue pas \n");}
		int inBloc1 = (ptToBeComputed>=nPtBlock0);
		int rK, wTD;
		//int* tabDest;
		//int isSet=0;
		//int shouldBeSomeWhere = 0;
		// Let's handle bloc Neg = 0
		wTD=whatTD[0];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlNeg[addr_pt];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut \n", (addrPtSh[0]+rK+inBloc1*nPtBlNeg[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[0]+rK]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
			}
			rK=rkBlNeg[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut \n", (addrPtSh[0]+rK+inBloc1*nPtBlNeg[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[0]+rK+nPtBlNeg[idBloc]]=id_pt;//+inBloc1*nPtBlNeg[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[1];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlPos[addr_pt];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[1]+rK+inBloc1*nPtBlPos[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[1]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[1]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[1]+rK]=id_pt;
			}
			rK=rkBlPos[addr_pt+nDots];//+inBloc1*nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[1]+rK+inBloc1*nPtBlPos[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[1]+rK+nPtBlPos[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[2];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlMid0[addr_pt];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n",(addrPtSh[2]+rK), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[2]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[2]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[2]+rK]=id_pt;
			}
			rK=rkBlMid0[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[2]+rK+nPtBlMid0[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[2]+rK+nPtBlMid0[idBloc]]=id_pt;
			}
		}
		wTD=whatTD[3];
		if (wTD!=3) {
			//shouldBeSomeWhere=1;
			rK=rkBlMid1[addr_pt];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[3]+rK), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[3]+rK]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[3]+rK]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[3]+rK]=id_pt;
			}
			rK=rkBlMid1[addr_pt+nDots];
			if (rK!=-1) {
				//printf("on a mis %i qui vaut %i\n", (addrPtSh[3]+rK+nPtBlMid1[idBloc]), id_pt);
				//isSet=1;
				if (wTD==0) blKeep_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
				if (wTD==1) blFinal_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
				if (wTD==2) blDiscard_dotIndexes[addrPtSh[3]+rK+nPtBlMid1[idBloc]]=id_pt;
			}
		}
		//if ((isSet==0)&&(shouldBeSomeWhere==1)) {printf("De bleu! Le point %i n'a été mis nulle part! [%i, %i, %i, %i]\n", id_pt, whatTD[0], whatTD[1], whatTD[2], whatTD[3]);}
	}
	if ((iThread==0)&&(offsPt==0)) {
		// needs to fill bloc properties
		for (int i=0;i<4;i++) {
			int wTD = wTD=whatTD[i];
			int idNewBloc = addrBlSh[i];
			
			int nPtInBloc0, nPtInBloc1;
			if (i==0) {
				nPtInBloc0 = nPtBlNeg[idBloc];
				nPtInBloc1 = nPtBlNeg[idBloc+nBlocks];
			}
			if (i==1) {
				nPtInBloc0 = nPtBlPos[idBloc];
				nPtInBloc1 = nPtBlPos[idBloc+nBlocks];
			}
			if (i==2) {
				nPtInBloc0 = nPtBlMid0[idBloc];
				nPtInBloc1 = nPtBlMid0[idBloc+nBlocks];
			}
			if (i==3) {
				nPtInBloc0 = nPtBlMid1[idBloc];
				nPtInBloc1 = nPtBlMid1[idBloc+nBlocks];
			}
			//printf("\n idNewBloc = %i, on en fait %i \n nPtInBloc0 = %i, nPtInBloc1 = %i , addrPtSh = %i \n",idNewBloc, wTD,nPtInBloc0,nPtInBloc1, addrPtSh[i]);
			if (wTD==0) {
				//SPLIT
				//printf("SPLIT!!\n");
				blKeep_stBl0[idNewBloc]=addrPtSh[i];
				blKeep_nPtBl0[idNewBloc]=nPtInBloc0;
				blKeep_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blKeep_nPtBl1[idNewBloc]=nPtInBloc1;
				blKeep_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			if (wTD==1) {
				//KEEP
				blFinal_stBl0[idNewBloc]=addrPtSh[i];
				blFinal_nPtBl0[idNewBloc]=nPtInBloc0;
				blFinal_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blFinal_nPtBl1[idNewBloc]=nPtInBloc1;
				blFinal_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			if (wTD==2) {
				//DISCARD
				blDiscard_stBl0[idNewBloc]=addrPtSh[i];
				blDiscard_nPtBl0[idNewBloc]=nPtInBloc0;
				blDiscard_stBl1[idNewBloc]=addrPtSh[i]+nPtInBloc0;
				blDiscard_nPtBl1[idNewBloc]=nPtInBloc1;
				blDiscard_blLevel[idNewBloc]=newBlockLvl[4*idBloc+i];
			}
			
		}
	}
}
	.text
	.file	"gpuDispatchDots.hip"
	.globl	__device_stub__dispatchDots     # -- Begin function __device_stub__dispatchDots
	.type	__device_stub__dispatchDots,@function
__device_stub__dispatchDots:            # @__device_stub__dispatchDots
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$416, %rsp                      # imm = 0x1A0
	.cfi_def_cfa_offset 464
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	512(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	520(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	528(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	536(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	544(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	552(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	560(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	568(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	576(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	584(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	592(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	600(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	608(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	616(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	624(%rsp), %rax
	movq	%rax, 208(%rbx)
	leaq	632(%rsp), %rax
	movq	%rax, 216(%rbx)
	leaq	640(%rsp), %rax
	movq	%rax, 224(%rbx)
	leaq	648(%rsp), %rax
	movq	%rax, 232(%rbx)
	leaq	656(%rsp), %rax
	movq	%rax, 240(%rbx)
	leaq	664(%rsp), %rax
	movq	%rax, 248(%rbx)
	leaq	672(%rsp), %rax
	movq	%rax, 256(%rbx)
	leaq	680(%rsp), %rax
	movq	%rax, 264(%rbx)
	leaq	688(%rsp), %rax
	movq	%rax, 272(%rbx)
	leaq	696(%rsp), %rax
	movq	%rax, 280(%rbx)
	leaq	704(%rsp), %rax
	movq	%rax, 288(%rbx)
	leaq	712(%rsp), %rax
	movq	%rax, 296(%rbx)
	leaq	720(%rsp), %rax
	movq	%rax, 304(%rbx)
	leaq	728(%rsp), %rax
	movq	%rax, 312(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$dispatchDots, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$432, %rsp                      # imm = 0x1B0
	.cfi_adjust_cfa_offset -432
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__dispatchDots, .Lfunc_end0-__device_stub__dispatchDots
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$dispatchDots, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	dispatchDots,@object            # @dispatchDots
	.section	.rodata,"a",@progbits
	.globl	dispatchDots
	.p2align	3, 0x0
dispatchDots:
	.quad	__device_stub__dispatchDots
	.size	dispatchDots, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"dispatchDots"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__dispatchDots
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym dispatchDots
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	dispatchDots            ; -- Begin function dispatchDots
	.globl	dispatchDots
	.p2align	8
	.type	dispatchDots,@function
dispatchDots:                           ; @dispatchDots
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b512 s[68:83], s[0:1], 0x0
	s_load_b512 s[4:19], s[0:1], 0x88
	s_mov_b32 s20, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s22, s80, s2
	s_addc_u32 s23, s81, s3
	s_load_b32 s22, s[22:23], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s22
	s_ashr_i32 s23, s22, 31
	s_add_u32 s2, s82, s2
	s_addc_u32 s3, s83, s3
	s_lshl_b64 s[24:25], s[22:23], 2
	s_load_b32 s21, s[2:3], 0x0
	s_add_u32 s2, s70, s24
	s_addc_u32 s3, s71, s25
	s_add_u32 s26, s72, s24
	s_addc_u32 s27, s73, s25
	s_load_b32 s23, s[2:3], 0x0
	s_add_u32 s2, s74, s24
	s_addc_u32 s3, s75, s25
	s_load_b32 s28, s[26:27], 0x0
	s_add_u32 s26, s76, s24
	s_addc_u32 s27, s77, s25
	s_load_b32 s29, s[2:3], 0x0
	s_add_u32 s2, s78, s24
	s_addc_u32 s3, s79, s25
	s_load_b32 s26, s[26:27], 0x0
	s_load_b32 s27, s[2:3], 0x0
	s_lshl_b32 s24, s22, 2
	s_mov_b64 s[2:3], 0
	s_ashr_i32 s25, s24, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[24:25], s[24:25], 2
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s21
	s_add_u32 s4, s4, s24
	s_addc_u32 s5, s5, s25
	s_add_u32 s6, s6, s24
	s_addc_u32 s7, s7, s25
	v_mov_b32_e32 v4, s23
	s_add_u32 s8, s8, s24
	s_addc_u32 s9, s9, s25
	v_mov_b32_e32 v5, s28
	s_add_i32 s21, 0, 28
	v_dual_mov_b32 v6, s29 :: v_dual_mov_b32 v7, s26
	v_mov_b32_e32 v8, s27
	ds_store_2addr_b32 v1, v3, v4 offset1:1
	ds_store_2addr_b32 v1, v5, v6 offset0:2 offset1:3
	ds_store_2addr_b32 v1, v7, v8 offset0:4 offset1:5
	ds_store_b32 v1, v2 offset:24
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s22, s4, s2
	s_addc_u32 s23, s5, s3
	s_add_u32 s24, s6, s2
	s_addc_u32 s25, s7, s3
	s_load_b32 s26, s[22:23], 0x0
	s_add_u32 s22, s8, s2
	s_addc_u32 s23, s9, s3
	s_load_b32 s24, s[24:25], 0x0
	s_load_b32 s22, s[22:23], 0x0
	v_mov_b32_e32 v1, s21
	s_add_i32 s21, s21, 4
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 16
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s24
	v_mov_b32_e32 v4, s22
	ds_store_2addr_b32 v1, v2, v3 offset1:4
	ds_store_b32 v1, v4 offset:32
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %Flow720
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s28, exec_lo
	ds_load_2addr_b32 v[1:2], v3 offset1:2
	ds_load_2addr_b32 v[4:5], v3 offset0:4 offset1:6
	s_clause 0x4
	s_load_b512 s[52:67], s[0:1], 0x40
	s_load_b64 s[24:25], s[0:1], 0x80
	s_load_b512 s[36:51], s[0:1], 0xc8
	s_load_b128 s[20:23], s[0:1], 0x128
	s_load_b256 s[0:7], s[0:1], 0x108
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v4, v2
	v_add_nc_u32_e32 v2, v1, v0
	v_readfirstlane_b32 s8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e64 v2, v4
	s_cbranch_execz .LBB0_130
; %bb.4:
	ds_load_2addr_b32 v[3:4], v3 offset0:1 offset1:7
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s68, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s69, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	global_load_b32 v6, v[5:6], off
	s_cbranch_vccnz .LBB0_36
; %bb.5:
	v_add_co_u32 v4, vcc_lo, s54, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s55, v3, vcc_lo
	s_mov_b32 s29, exec_lo
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v7
	s_cbranch_execz .LBB0_20
; %bb.6:                                ; %NodeBlock586
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_11
; %bb.7:                                ; %NodeBlock
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_12
; %bb.8:                                ; %LeafBlock584
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_10
; %bb.9:
	s_mov_b32 s30, -1
.LBB0_10:                               ; %Flow712
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_13
.LBB0_11:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_16
.LBB0_12:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_13:                               ; %Flow711
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_15
; %bb.14:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_15:                               ; %Flow713
	s_mov_b32 s31, 0
.LBB0_16:                               ; %Flow710
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_18
; %bb.17:                               ; %LeafBlock
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_18:                               ; %Flow714
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_20
; %bb.19:                               ; %.sink.split
	v_mov_b32_e32 v8, 0
	ds_load_b32 v8, v8 offset:44
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v8, vcc_lo
	global_store_b32 v[7:8], v6, off
.LBB0_20:                               ; %Flow716
	s_or_b32 exec_lo, exec_lo, s29
	s_ashr_i32 s27, s25, 31
	s_mov_b32 s26, s25
	s_mov_b32 s29, exec_lo
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v4, s26
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB0_35
; %bb.21:                               ; %NodeBlock594
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_26
; %bb.22:                               ; %NodeBlock592
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_27
; %bb.23:                               ; %LeafBlock590
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_25
; %bb.24:
	s_mov_b32 s30, -1
.LBB0_25:                               ; %Flow705
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_28
.LBB0_26:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_31
.LBB0_27:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_28:                               ; %Flow704
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_30
; %bb.29:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_30:                               ; %Flow706
	s_mov_b32 s31, 0
.LBB0_31:                               ; %Flow703
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_33
; %bb.32:                               ; %LeafBlock588
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_33:                               ; %Flow707
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_35
; %bb.34:                               ; %.sink.split400
	s_ashr_i32 s9, s8, 31
	v_mov_b32_e32 v5, 0
	s_lshl_b64 s[30:31], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s62, s30
	s_addc_u32 s31, s63, s31
	global_load_b32 v7, v5, s[30:31]
	ds_load_b32 v5, v5 offset:44
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add3_u32 v4, v7, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB0_35:                               ; %Flow709
	s_or_b32 exec_lo, exec_lo, s29
.LBB0_36:
	v_mov_b32_e32 v7, 0
	ds_load_b32 v4, v7 offset:32
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_readfirstlane_b32 s9, v4
	s_cbranch_vccnz .LBB0_68
; %bb.37:
	v_add_co_u32 v4, vcc_lo, s52, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s53, v3, vcc_lo
	s_mov_b32 s29, exec_lo
	global_load_b32 v8, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v8
	s_cbranch_execz .LBB0_52
; %bb.38:                               ; %NodeBlock602
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_43
; %bb.39:                               ; %NodeBlock600
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_44
; %bb.40:                               ; %LeafBlock598
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_42
; %bb.41:
	s_mov_b32 s30, -1
.LBB0_42:                               ; %Flow697
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_45
.LBB0_43:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_48
.LBB0_44:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_45:                               ; %Flow696
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_47
; %bb.46:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_47:                               ; %Flow698
	s_mov_b32 s31, 0
.LBB0_48:                               ; %Flow695
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_50
; %bb.49:                               ; %LeafBlock596
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_50:                               ; %Flow699
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ; %.sink.split406
	v_mov_b32_e32 v9, 0
	ds_load_b32 v9, v9 offset:48
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s26, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s27, v9, vcc_lo
	global_store_b32 v[8:9], v6, off
.LBB0_52:                               ; %Flow701
	s_or_b32 exec_lo, exec_lo, s29
	s_ashr_i32 s27, s25, 31
	s_mov_b32 s26, s25
	s_mov_b32 s29, exec_lo
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v4, s26
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB0_67
; %bb.53:                               ; %NodeBlock610
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_58
; %bb.54:                               ; %NodeBlock608
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_59
; %bb.55:                               ; %LeafBlock606
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_57
; %bb.56:
	s_mov_b32 s30, -1
.LBB0_57:                               ; %Flow690
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_60
.LBB0_58:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_63
.LBB0_59:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_60:                               ; %Flow689
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_62
; %bb.61:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_62:                               ; %Flow691
	s_mov_b32 s31, 0
.LBB0_63:                               ; %Flow688
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_65
; %bb.64:                               ; %LeafBlock604
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_65:                               ; %Flow692
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_67
; %bb.66:                               ; %.sink.split410
	s_ashr_i32 s9, s8, 31
	v_mov_b32_e32 v5, 0
	s_lshl_b64 s[30:31], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s60, s30
	s_addc_u32 s31, s61, s31
	global_load_b32 v8, v5, s[30:31]
	ds_load_b32 v5, v5 offset:48
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add3_u32 v4, v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB0_67:                               ; %Flow694
	s_or_b32 exec_lo, exec_lo, s29
.LBB0_68:
	ds_load_b32 v4, v7 offset:36
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_readfirstlane_b32 s9, v4
	s_cbranch_vccnz .LBB0_100
; %bb.69:
	v_add_co_u32 v4, vcc_lo, s56, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v3, vcc_lo
	s_mov_b32 s29, exec_lo
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v7
	s_cbranch_execz .LBB0_84
; %bb.70:                               ; %NodeBlock618
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_75
; %bb.71:                               ; %NodeBlock616
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_76
; %bb.72:                               ; %LeafBlock614
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_74
; %bb.73:
	s_mov_b32 s30, -1
.LBB0_74:                               ; %Flow682
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_77
.LBB0_75:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_80
.LBB0_76:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_77:                               ; %Flow681
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_79
; %bb.78:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_79:                               ; %Flow683
	s_mov_b32 s31, 0
.LBB0_80:                               ; %Flow680
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_82
; %bb.81:                               ; %LeafBlock612
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_82:                               ; %Flow684
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ; %.sink.split416
	v_mov_b32_e32 v8, 0
	ds_load_b32 v8, v8 offset:52
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s26, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s27, v8, vcc_lo
	global_store_b32 v[7:8], v6, off
.LBB0_84:                               ; %Flow686
	s_or_b32 exec_lo, exec_lo, s29
	s_ashr_i32 s27, s25, 31
	s_mov_b32 s26, s25
	s_mov_b32 s29, exec_lo
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v4, s26
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB0_99
; %bb.85:                               ; %NodeBlock626
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_90
; %bb.86:                               ; %NodeBlock624
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_91
; %bb.87:                               ; %LeafBlock622
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_89
; %bb.88:
	s_mov_b32 s30, -1
.LBB0_89:                               ; %Flow675
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_92
.LBB0_90:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_95
.LBB0_91:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_92:                               ; %Flow674
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_94
; %bb.93:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_94:                               ; %Flow676
	s_mov_b32 s31, 0
.LBB0_95:                               ; %Flow673
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_97
; %bb.96:                               ; %LeafBlock620
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_97:                               ; %Flow677
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_99
; %bb.98:                               ; %.sink.split420
	s_ashr_i32 s9, s8, 31
	v_mov_b32_e32 v5, 0
	s_lshl_b64 s[30:31], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s64, s30
	s_addc_u32 s31, s65, s31
	global_load_b32 v7, v5, s[30:31]
	ds_load_b32 v5, v5 offset:52
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add3_u32 v4, v7, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB0_99:                               ; %Flow679
	s_or_b32 exec_lo, exec_lo, s29
.LBB0_100:
	v_mov_b32_e32 v4, 0
	ds_load_b32 v4, v4 offset:40
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_readfirstlane_b32 s9, v4
	s_cbranch_vccnz .LBB0_130
; %bb.101:
	v_add_co_u32 v2, vcc_lo, s58, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s59, v3, vcc_lo
	s_mov_b32 s29, exec_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB0_116
; %bb.102:                              ; %NodeBlock634
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_107
; %bb.103:                              ; %NodeBlock632
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_108
; %bb.104:                              ; %LeafBlock630
	s_mov_b32 s31, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s30, 0
	s_cbranch_scc0 .LBB0_106
; %bb.105:
	s_mov_b32 s30, -1
.LBB0_106:                              ; %Flow667
	s_mov_b64 s[26:27], s[0:1]
	s_branch .LBB0_109
.LBB0_107:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
	s_branch .LBB0_112
.LBB0_108:
	s_mov_b32 s31, -1
	s_mov_b32 s30, 0
                                        ; implicit-def: $sgpr26_sgpr27
.LBB0_109:                              ; %Flow666
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_111
; %bb.110:
	s_mov_b32 s30, -1
	s_mov_b64 s[26:27], s[40:41]
.LBB0_111:                              ; %Flow668
	s_mov_b32 s31, 0
.LBB0_112:                              ; %Flow665
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccz .LBB0_114
; %bb.113:                              ; %LeafBlock628
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[26:27], s[12:13]
	s_cselect_b32 s30, -1, 0
.LBB0_114:                              ; %Flow669
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_116
; %bb.115:                              ; %.sink.split426
	v_mov_b32_e32 v5, 0
	ds_load_b32 v5, v5 offset:56
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s26, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v5, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB0_116:                              ; %Flow671
	s_or_b32 exec_lo, exec_lo, s29
	s_ashr_i32 s27, s25, 31
	s_mov_b32 s26, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[26:27], s[26:27], 2
	v_add_co_u32 v2, vcc_lo, v2, s26
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_130
; %bb.117:                              ; %NodeBlock642
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_121
; %bb.118:                              ; %NodeBlock640
	s_cmp_gt_i32 s9, 1
	s_cbranch_scc0 .LBB0_122
; %bb.119:                              ; %LeafBlock638
	s_mov_b32 s26, 0
	s_cmp_eq_u32 s9, 2
	s_mov_b32 s25, 0
	s_cbranch_scc0 .LBB0_123
; %bb.120:
	s_mov_b32 s25, -1
	s_branch .LBB0_123
.LBB0_121:
	s_mov_b32 s26, -1
	s_mov_b32 s25, 0
	s_branch .LBB0_126
.LBB0_122:
	s_mov_b32 s26, -1
	s_mov_b32 s25, 0
.LBB0_123:                              ; %Flow659
	s_and_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccz .LBB0_125
; %bb.124:
	s_mov_b32 s25, -1
	s_mov_b64 s[0:1], s[40:41]
.LBB0_125:                              ; %Flow661
	s_mov_b32 s26, 0
.LBB0_126:                              ; %Flow658
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccz .LBB0_128
; %bb.127:                              ; %LeafBlock636
	s_cmp_eq_u32 s9, 0
	s_mov_b64 s[0:1], s[12:13]
	s_cselect_b32 s25, -1, 0
.LBB0_128:                              ; %Flow662
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB0_130
; %bb.129:                              ; %.sink.split430
	s_ashr_i32 s9, s8, 31
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[12:13], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s66, s12
	s_addc_u32 s13, s67, s13
	global_load_b32 v4, v3, s[12:13]
	ds_load_b32 v3, v3 offset:56
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add3_u32 v2, v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v6, off
.LBB0_130:                              ; %Flow718
	s_or_b32 exec_lo, exec_lo, s28
	v_or_b32_e32 v0, v1, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_152
; %bb.131:                              ; %.preheader
	s_add_i32 s0, s8, s24
	v_mov_b32_e32 v0, 0
	s_ashr_i32 s1, s0, 31
	s_mov_b32 s33, -16
	s_lshl_b64 s[34:35], s[0:1], 2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s0, s62, s34
	s_addc_u32 s1, s63, s35
	s_ashr_i32 s9, s8, 31
	s_lshl_b64 s[40:41], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s62, s40
	s_addc_u32 s13, s63, s41
	s_add_u32 s24, s60, s34
	s_addc_u32 s25, s61, s35
	s_add_u32 s26, s60, s40
	s_addc_u32 s27, s61, s41
	s_add_u32 s28, s64, s34
	s_addc_u32 s29, s65, s35
	s_add_u32 s30, s64, s40
	s_addc_u32 s31, s65, s41
	s_add_u32 s34, s66, s34
	s_addc_u32 s35, s67, s35
	s_add_u32 s40, s66, s40
	s_addc_u32 s41, s67, s41
	s_lshl_b32 s8, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s9, s8, 31
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s10, s8
	s_addc_u32 s9, s11, s9
.LBB0_132:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s52, s33, 0
	s_cmp_lg_u32 s33, -16
	v_mov_b32_e32 v3, s52
	ds_load_2addr_b32 v[3:4], v3 offset0:11 offset1:19
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s53, v3
	v_readfirstlane_b32 s10, v4
	s_cbranch_scc1 .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_132 Depth=1
	s_clause 0x1
	global_load_b32 v1, v0, s[12:13]
	global_load_b32 v2, v0, s[0:1]
.LBB0_134:                              ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lg_u32 s33, -12
	s_cbranch_scc1 .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_132 Depth=1
	s_clause 0x1
	global_load_b32 v1, v0, s[26:27]
	global_load_b32 v2, v0, s[24:25]
.LBB0_136:                              ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lg_u32 s33, -8
	s_cbranch_scc1 .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_132 Depth=1
	s_clause 0x1
	global_load_b32 v1, v0, s[30:31]
	global_load_b32 v2, v0, s[28:29]
.LBB0_138:                              ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lg_u32 s33, -4
	s_cbranch_scc1 .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_132 Depth=1
	s_clause 0x1
	global_load_b32 v1, v0, s[40:41]
	global_load_b32 v2, v0, s[34:35]
.LBB0_140:                              ; %NodeBlock650
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lt_i32 s53, 1
	s_mov_b32 s11, -1
	s_cbranch_scc1 .LBB0_148
; %bb.141:                              ; %NodeBlock648
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lt_i32 s53, 2
	s_cbranch_scc1 .LBB0_145
; %bb.142:                              ; %LeafBlock646
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_eq_u32 s53, 2
	s_cbranch_scc0 .LBB0_144
; %bb.143:                              ;   in Loop: Header=BB0_132 Depth=1
	v_mov_b32_e32 v3, s52
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[54:55], s[10:11], 2
	s_add_u32 s56, s2, s54
	ds_load_b32 v3, v3 offset:60
	s_addc_u32 s57, s3, s55
	s_add_u32 s58, s4, s54
	s_addc_u32 s59, s5, s55
	s_add_u32 s60, s6, s54
	s_addc_u32 s61, s7, s55
	s_add_u32 s62, s20, s54
	s_addc_u32 s63, s21, s55
	s_add_u32 s54, s22, s54
	s_addc_u32 s55, s23, s55
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v1
	s_clause 0x2
	global_store_b32 v0, v3, s[56:57]
	global_store_b32 v0, v1, s[58:59]
	global_store_b32 v0, v4, s[60:61]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v2, s[62:63]
	global_load_b32 v3, v0, s[8:9]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v3, s[54:55]
.LBB0_144:                              ; %Flow
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s11, 0
.LBB0_145:                              ; %Flow652
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_132 Depth=1
	v_mov_b32_e32 v3, s52
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[54:55], s[10:11], 2
	s_add_u32 s56, s42, s54
	ds_load_b32 v3, v3 offset:60
	s_addc_u32 s57, s43, s55
	s_add_u32 s58, s44, s54
	s_addc_u32 s59, s45, s55
	s_add_u32 s60, s46, s54
	s_addc_u32 s61, s47, s55
	s_add_u32 s62, s48, s54
	s_addc_u32 s63, s49, s55
	s_add_u32 s54, s50, s54
	s_addc_u32 s55, s51, s55
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v1
	s_clause 0x2
	global_store_b32 v0, v3, s[56:57]
	global_store_b32 v0, v1, s[58:59]
	global_store_b32 v0, v4, s[60:61]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v2, s[62:63]
	global_load_b32 v3, v0, s[8:9]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v3, s[54:55]
.LBB0_147:                              ; %Flow653
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s11, 0
.LBB0_148:                              ; %Flow655
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_151
; %bb.149:                              ; %LeafBlock644
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_cmp_lg_u32 s53, 0
	s_cbranch_scc1 .LBB0_151
; %bb.150:                              ;   in Loop: Header=BB0_132 Depth=1
	v_mov_b32_e32 v3, s52
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[10:11], 2
	s_add_u32 s52, s14, s10
	ds_load_b32 v3, v3 offset:60
	s_addc_u32 s53, s15, s11
	s_add_u32 s54, s16, s10
	s_addc_u32 s55, s17, s11
	s_add_u32 s56, s18, s10
	s_addc_u32 s57, s19, s11
	s_add_u32 s58, s36, s10
	s_addc_u32 s59, s37, s11
	s_add_u32 s10, s38, s10
	s_addc_u32 s11, s39, s11
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v1
	s_clause 0x2
	global_store_b32 v0, v3, s[52:53]
	global_store_b32 v0, v1, s[54:55]
	global_store_b32 v0, v4, s[56:57]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v2, s[58:59]
	global_load_b32 v3, v0, s[8:9]
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v3, s[10:11]
.LBB0_151:                              ;   in Loop: Header=BB0_132 Depth=1
	s_add_i32 s33, s33, 4
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_lg_u32 s33, 0
	s_cbranch_scc1 .LBB0_132
.LBB0_152:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel dispatchDots
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 84
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	dispatchDots, .Lfunc_end0-dispatchDots
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3396
; NumSgprs: 86
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 86
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .offset:         128
        .size:           4
        .value_kind:     by_value
      - .offset:         132
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         144
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         152
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         160
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         168
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         176
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         184
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         192
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         200
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         208
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         216
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         224
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         232
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         240
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         248
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         256
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         264
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         272
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         280
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         288
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         296
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         304
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           dispatchDots
    .private_segment_fixed_size: 0
    .sgpr_count:     86
    .sgpr_spill_count: 0
    .symbol:         dispatchDots.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
