#include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;

line_length = gridDim.y * blockDim.y;

global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;

i_start	= global_thread_x * thread_work;
j_start	= global_thread_y * thread_work;
i_final	= global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);

if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1:  need a thread barrier here -> not done, I chose option 2
// Option 2:  simply write 2 kernels and syncCPU -> done, I chose this option
//	 	CPU is setting source_active = 0 after this kernel is done executing.
}
	.file	"tmpxft_002051ca_00000000-6_wireless_src_pulse_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13is_source_gpuiiiiii
	.type	_Z13is_source_gpuiiiiii, @function
_Z13is_source_gpuiiiiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z13is_source_gpuiiiiii, .-_Z13is_source_gpuiiiiii
	.globl	_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
	.type	_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, @function
_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	264(%rsp), %rax
	movl	%edx, 44(%rsp)
	leaq	80(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	88(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movsd	%xmm0, 64(%rsp)
	movsd	%xmm1, 56(%rsp)
	movsd	%xmm2, 48(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L4:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, .-_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
	.globl	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.type	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, @function
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
	.cfi_endproc
.LFE2034:
	.size	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, .-_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;

line_length = gridDim.y * blockDim.y;

global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;

i_start	= global_thread_x * thread_work;
j_start	= global_thread_y * thread_work;
i_final	= global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);

if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1:  need a thread barrier here -> not done, I chose option 2
// Option 2:  simply write 2 kernels and syncCPU -> done, I chose this option
//	 	CPU is setting source_active = 0 after this kernel is done executing.
}
	.text
	.file	"wireless_src_pulse_kernel.hip"
	.globl	_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_ # -- Begin function _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
	.type	_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_,@function
_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_: # @_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	72(%rsp), %rdi
	movsd	%xmm0, (%rdi)
	leaq	64(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	24(%rsp), %r14
	movl	%esi, (%r14)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%r11, 24(%rbx)
	movq	%r14, 32(%rbx)
	movq	%rsi, 40(%rbx)
	movq	%rdx, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_, .Lfunc_end0-_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_,@object # @_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.p2align	3, 0x0
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
	.quad	_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
	.size	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z13is_source_gpuiiiiii
	.type	_Z13is_source_gpuiiiiii,@function
_Z13is_source_gpuiiiiii:                ; @_Z13is_source_gpuiiiiii
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_sub_nc_u32_e32 v5, v3, v0
	v_sub_nc_u32_e32 v6, v4, v1
	s_mov_b32 s1, 0x3e76c4e1
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v5, v5
	v_cvt_f32_i32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v7, |v5|
	v_frexp_mant_f32_e64 v8, |v6|
	v_frexp_exp_i32_f32_e32 v5, v5
	v_frexp_exp_i32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v7
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v8
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, 0, 1, s0
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v6, vcc_lo, 0, v6, s0
	v_ldexp_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v8, v8, v10
	v_cvt_f32_i32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v6, v6
	v_dual_add_f32 v9, 1.0, v7 :: v_dual_add_f32 v10, 1.0, v8
	v_dual_add_f32 v13, -1.0, v7 :: v_dual_add_f32 v14, -1.0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v11, v9
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v15, v13, v11 :: v_dual_mul_f32 v16, v14, v12
	v_add_f32_e32 v17, -1.0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v19, -1.0, v10 :: v_dual_mul_f32 v18, v9, v15
	v_dual_mul_f32 v20, v10, v16 :: v_dual_sub_f32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v8, v19
	v_fma_f32 v9, v15, v9, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v16, v10, -v20
	v_dual_fmac_f32 v9, v15, v7 :: v_dual_fmac_f32 v10, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v18, v9 :: v_dual_add_f32 v8, v20, v10
	v_dual_sub_f32 v17, v13, v7 :: v_dual_sub_f32 v18, v7, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v8, v20
	v_sub_f32_e32 v19, v14, v8
	v_dual_sub_f32 v13, v13, v17 :: v_dual_sub_f32 v10, v20, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v18, v9
	v_sub_f32_e32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v9, v7
	v_add_f32_e32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v11, v7
	v_add_f32_e32 v9, v15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v14, v19 :: v_dual_mul_f32 v13, v9, v9
	v_sub_f32_e32 v8, v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v8
	v_add_f32_e32 v8, v19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v12, v8
	v_add_f32_e32 v10, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v10, v16 :: v_dual_sub_f32 v11, v9, v15
	v_dual_sub_f32 v8, v8, v12 :: v_dual_sub_f32 v7, v7, v11
	v_fma_f32 v12, v9, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, v8, v8 :: v_dual_mul_f32 v11, v10, v10
	v_add_f32_e32 v14, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v10, v10, -v11
	v_dual_fmac_f32 v12, v9, v14 :: v_dual_fmac_f32 v15, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v11, v15
	v_dual_add_f32 v14, v13, v12 :: v_dual_sub_f32 v11, v16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v17, s1, v14, 0x3e91f4c4 :: v_dual_fmaak_f32 v18, s1, v16, 0x3e91f4c4
	v_sub_f32_e32 v13, v14, v13
	v_sub_f32_e32 v11, v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v17, v14, v17, 0x3ecccdef :: v_dual_fmaak_f32 v18, v16, v18, 0x3ecccdef
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, v14, v17 :: v_dual_mul_f32 v20, v16, v18
	v_fma_f32 v13, v14, v17, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v16, v18, -v20
	v_fmac_f32_e32 v13, v12, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, v11, v18
	v_mul_f32_e32 v17, v9, v14
	v_dual_mul_f32 v21, v10, v16 :: v_dual_add_f32 v18, v19, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v20, v15
	v_fma_f32 v23, v14, v9, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, v16, v10, -v21
	v_dual_sub_f32 v19, v18, v19 :: v_dual_add_f32 v26, 0x3f2aaaaa, v22
	v_sub_f32_e32 v20, v22, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v24, 0x3f2aaaaa, v18 :: v_dual_fmac_f32 v23, v14, v7
	v_sub_f32_e32 v13, v13, v19
	v_fmac_f32_e32 v25, v16, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v14, v15, v20 :: v_dual_add_f32 v15, 0xbf2aaaaa, v26
	v_add_f32_e32 v19, 0xbf2aaaaa, v24
	v_fmac_f32_e32 v23, v12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v13, 0x31739010, v13 :: v_dual_add_f32 v12, 0x31739010, v14
	v_sub_f32_e32 v14, v22, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v18, v18, v19 :: v_dual_fmac_f32 v25, v11, v10
	v_ldexp_f32 v9, v9, 1
	v_ldexp_f32 v10, v10, 1
	v_dual_add_f32 v11, v12, v14 :: v_dual_add_f32 v12, v17, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v16, v21, v25
	v_ldexp_f32 v7, v7, 1
	v_ldexp_f32 v8, v8, 1
	v_add_f32_e32 v15, v26, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v13, v18 :: v_dual_mul_f32 v22, v16, v15
	v_add_f32_e32 v14, v24, v13
	v_sub_f32_e32 v21, v16, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v24, v14
	v_dual_mul_f32 v19, v12, v14 :: v_dual_sub_f32 v20, v26, v15
	v_sub_f32_e32 v17, v12, v17
	v_add_f32_e32 v11, v11, v20
	v_fma_f32 v20, v16, v15, -v22
	v_add_f32_e32 v13, v13, v18
	v_fma_f32 v18, v12, v14, -v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v16, v11
	v_fmac_f32_e32 v18, v12, v13
	v_sub_f32_e32 v12, v25, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v23, v17 :: v_dual_fmac_f32 v20, v12, v15
	v_fmac_f32_e32 v18, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v22, v20
	v_dual_add_f32 v12, v19, v18 :: v_dual_mul_f32 v11, 0x3f317218, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, v9, v12 :: v_dual_sub_f32 v17, v12, v19
	v_add_f32_e32 v19, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3f317218, v5, -v11
	v_dual_sub_f32 v10, v19, v10 :: v_dual_sub_f32 v9, v16, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v18, v17
	v_dual_fmac_f32 v15, 0xb102e308, v5 :: v_dual_sub_f32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v12, v9
	v_add_f32_e32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v5, v7, v9
	v_add_f32_e32 v7, v11, v15
	v_sub_f32_e32 v21, v14, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, 0x3f317218, v6 :: v_dual_sub_f32 v18, v20, v21
	v_fma_f32 v12, 0x3f317218, v6, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v8, v18
	v_fmac_f32_e32 v12, 0xb102e308, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v6, v8, v10 :: v_dual_add_f32 v9, v13, v12
	v_dual_add_f32 v8, v16, v5 :: v_dual_sub_f32 v11, v7, v11
	v_dual_add_f32 v10, v19, v6 :: v_dual_sub_f32 v13, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v19, v10, v19 :: v_dual_sub_f32 v12, v12, v13
	v_dual_add_f32 v17, v9, v10 :: v_dual_sub_f32 v6, v6, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v15, v11
	v_dual_sub_f32 v15, v8, v16 :: v_dual_sub_f32 v16, v17, v9
	v_add_f32_e32 v14, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v10, v16
	v_sub_f32_e32 v18, v14, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v5, v15
	v_sub_f32_e32 v15, v17, v16
	v_sub_f32_e32 v13, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v8, v18 :: v_dual_sub_f32 v9, v9, v15
	v_sub_f32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v10, v9
	v_add_f32_e32 v7, v8, v7
	v_add_f32_e32 v8, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v8, v12
	v_add_f32_e32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v15
	v_sub_f32_e32 v6, v6, v15
	v_dual_sub_f32 v8, v12, v8 :: v_dual_add_f32 v13, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v6, v8
	v_sub_f32_e32 v10, v13, v11
	v_add_f32_e32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v10
	v_sub_f32_e32 v5, v5, v10
	v_add_f32_e32 v10, v17, v9
	v_sub_f32_e32 v12, v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v9, v12
	v_add_f32_e32 v6, v6, v8
	v_add_f32_e32 v16, v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v6
	v_dual_sub_f32 v10, v8, v10 :: v_dual_sub_f32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v16, v14
	v_dual_sub_f32 v6, v6, v10 :: v_dual_add_f32 v5, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v13
	v_mul_f32_e32 v13, 0, v8
	v_add_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, 2.0, v6
	v_add_f32_e32 v7, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v7, v16 :: v_dual_mul_f32 v12, 0, v7
	v_sub_f32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v8, v8 :: v_dual_fmac_f32 v12, 2.0, v5
	v_fma_f32 v5, v8, 2.0, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v13
	v_dual_add_f32 v8, v9, v5 :: v_dual_add_f32 v11, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v7, 2.0, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_add_f32_e32 v6, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v6
	v_cndmask_b32_e32 v10, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_cndmask_b32_e32 v12, v8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v7, v7, v11
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_dual_sub_f32 v6, v6, v7 :: v_dual_sub_f32 v5, v5, v8
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v12, v14
	v_dual_cndmask_b32 v6, 0, v6 :: v_dual_sub_f32 v15, v10, v13
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, 0x3fb8aa3b, v16
	v_dual_add_f32 v6, v13, v6 :: v_dual_mul_f32 v17, 0x3fb8aa3b, v15
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f32 v21, 0x3fb8aa3b, v16, -v18
	v_rndne_f32_e32 v22, v18
	v_fma_f32 v19, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v20, v17
	v_add_f32_e32 v5, v14, v5
	v_dual_fmac_f32 v21, 0x32a5705f, v16 :: v_dual_sub_f32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, 0x32a5705f, v15
	v_sub_f32_e32 v17, v17, v20
	v_cvt_i32_f32_e32 v7, v20
	v_cvt_i32_f32_e32 v8, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v18, v18, v21 :: v_dual_add_f32 v17, v17, v19
	v_exp_f32_e32 v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v11, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v9, v8
	v_ldexp_f32 v7, v11, v7
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v7, v6, v7
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	v_fma_f32 v5, v8, v5, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, 0, |v6|, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, v4, v1
	v_cndmask_b32_e64 v1, 0, |v5|, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v1
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v1
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v1, v0
	v_fma_f32 v6, -v4, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v5
	v_cndmask_b32_e64 v1, v1, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v6
	v_cndmask_b32_e64 v1, v1, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x37800000, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_cmp_le_f32_e32 vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z13is_source_gpuiiiiii, .Lfunc_end0-_Z13is_source_gpuiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1908
; NumSgprs: 34
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_ ; -- Begin function _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.globl	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
	.p2align	8
	.type	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_,@function
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_: ; @_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
; %bb.0:
	s_clause 0x2
	s_load_b128 s[8:11], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x20
	s_mov_b32 s21, -1
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[1:2], null, s[2:3], s[2:3], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[3:4], v[1:2]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
	v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
	v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
	v_div_scale_f64 v[5:6], vcc_lo, s[10:11], s[2:3], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[5:6], v[3:4]
	v_fma_f64 v[1:2], -v[1:2], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[1:2], v[1:2], v[3:4], v[7:8]
	v_div_fixup_f64 v[1:2], v[1:2], s[2:3], s[10:11]
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x54
	s_load_b32 s3, s[0:1], 0x0
	s_load_b64 s[10:11], s[0:1], 0x40
	s_load_b32 s19, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s2, 0xffff
	s_lshr_b32 s20, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s18, s19, s20
	v_cvt_i32_f64_e32 v2, v[1:2]
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 31, v2
	v_mad_u64_u32 v[32:33], null, s14, s12, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v3
	v_lshlrev_b32_e32 v27, 5, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, s15, s20, v[0:1]
	v_ashrrev_i32_e32 v0, 1, v1
	v_lshl_add_u32 v31, v32, 5, v32
	v_cmp_ge_i32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v35, 5, v30
	v_lshl_add_u32 v36, v30, 5, v30
	v_cmp_lt_i32_e64 s2, v27, v31
	s_cbranch_vccz .LBB1_10
; %bb.1:
	s_cmp_lg_u32 s5, 0
	s_mov_b32 s21, 0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s5, s2
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB1_9
; %bb.2:                                ; %.preheader68.lr.ph
	v_mul_lo_u32 v0, s19, v32
	s_load_b128 s[12:15], s[0:1], 0x30
	v_cmp_lt_i32_e64 s2, v35, v36
	s_mov_b32 s16, 0
	s_mov_b32 s22, 0
	v_mov_b32_e32 v28, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s20
	v_lshlrev_b32_e32 v33, 5, v0
.LBB1_3:                                ; %.preheader68
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB1_8
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v34, v30 :: v_dual_mov_b32 v29, v35
	s_mov_b32 s24, 0
.LBB1_5:                                ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v28 :: v_dual_mov_b32 v1, v29
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s6
	v_mov_b32_e32 v4, s7
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z13is_source_gpuiiiiii@rel32@lo+4
	s_addc_u32 s1, s1, _Z13is_source_gpuiiiiii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=2
	s_mov_b32 s17, s16
	v_add_nc_u32_e32 v0, v33, v29
	v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	global_store_b64 v[6:7], v[2:3], off
	global_store_b64 v[0:1], v[2:3], off
.LBB1_7:                                ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v34, -1, v34
	v_add_nc_u32_e32 v29, 1, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v34
	s_or_b32 s24, vcc_lo, s24
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB1_5
.LBB1_8:                                ; %Flow125
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_add_nc_u32_e32 v28, 1, v28
	v_add_nc_u32_e32 v33, s18, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, v28, v31
	s_or_b32 s22, vcc_lo, s22
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB1_3
.LBB1_9:                                ; %Flow127
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_10:                               ; %Flow132
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccnz .LBB1_19
; %bb.11:                               ; %.preheader67
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e64 v27, v31
	s_cbranch_execz .LBB1_19
; %bb.12:                               ; %.preheader.lr.ph
	v_cvt_f64_i32_e32 v[0:1], s3
	s_mov_b32 s3, 0x400921fb
	s_mov_b32 s2, 0x54442d18
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s12, 0
	s_mov_b32 s15, 0xbc91a626
	s_mov_b32 s14, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[2:3]
	s_mov_b32 s3, 0x3ff921fb
	v_ldexp_f64 v[0:1], v[0:1], -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[2:3], |v[0:1]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
	v_trig_preop_f64 v[4:5], |v[0:1]|, 0
	v_and_b32_e32 v6, 0x7fffffff, v1
	v_trig_preop_f64 v[16:17], |v[0:1]|, 2
	v_dual_cndmask_b32 v3, v6, v3 :: v_dual_cndmask_b32 v2, v0, v2
	v_trig_preop_f64 v[6:7], |v[0:1]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[8:9], v[4:5], v[2:3]
	v_mul_f64 v[22:23], v[16:17], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], v[6:7], v[2:3]
	v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
	v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[10:11], v[4:5]
	v_add_f64 v[14:15], v[12:13], -v[10:11]
	v_add_f64 v[20:21], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[12:13], -v[14:15]
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	v_ldexp_f64 v[14:15], v[20:21], -2
	v_add_f64 v[8:9], v[20:21], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	v_add_f64 v[18:19], v[22:23], v[6:7]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[12:13], -v[8:9]
	v_add_f64 v[4:5], v[4:5], v[10:11]
	v_fract_f64_e32 v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[18:19], v[4:5]
	v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[10:11], v[10:11], 2
	v_add_f64 v[14:15], v[8:9], v[12:13]
	v_add_f64 v[24:25], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[14:15], v[10:11]
	v_add_f64 v[37:38], v[12:13], -v[24:25]
	v_add_f64 v[4:5], v[4:5], -v[24:25]
	v_add_f64 v[8:9], v[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
	v_add_f64 v[20:21], v[18:19], -v[22:23]
	v_add_f64 v[8:9], v[12:13], -v[8:9]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s13, 0x40100000, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[18:19], -v[20:21]
	v_add_f64 v[10:11], v[10:11], s[12:13]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[37:38]
	v_add_f64 v[20:21], v[22:23], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[14:15], v[10:11]
	v_add_f64 v[4:5], v[4:5], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], v[20:21]
	v_cvt_i32_f64_e32 v26, v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_cvt_f64_i32_e32 v[24:25], v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_f64 v[10:11], v[10:11], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[8:9], v[2:3]
	v_add_f64 v[6:7], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[6:7], -v[10:11]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[6:7]
	v_add_f64 v[4:5], v[14:15], -v[4:5]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s13, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v24, s0, 0, v26, vcc_lo
	v_add_f64 v[6:7], v[6:7], -s[12:13]
	s_mov_b32 s0, 0x6dc9c883
	s_mov_b32 s1, 0x3fe45f30
	v_cmp_gt_f64_e64 vcc_lo, 0x41d00000, |v[0:1]|
	v_mul_f64 v[12:13], |v[0:1]|, s[0:1]
	s_mov_b32 s0, 0x33145c07
	s_mov_b32 s1, 0x3c91a626
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[6:7], v[2:3]
	v_mul_f64 v[8:9], v[4:5], s[2:3]
	v_add_f64 v[6:7], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[4:5], s[2:3], -v[8:9]
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_rndne_f64_e32 v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], s[0:1], v[10:11]
	v_fma_f64 v[2:3], v[2:3], s[2:3], v[4:5]
	s_mov_b32 s3, 0xbff921fb
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[6:7], s[14:15]
	v_fma_f64 v[10:11], v[6:7], s[2:3], |v[0:1]|
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s3, 0x3de5e0b2
	v_add_f64 v[12:13], v[10:11], v[4:5]
	v_fma_f64 v[14:15], v[6:7], s[14:15], v[10:11]
	s_mov_b32 s15, s1
	s_mov_b32 s0, 0x252049c0
	s_mov_b32 s1, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[4:5]
	v_fma_f64 v[4:5], v[6:7], s[14:15], v[4:5]
	s_mov_b32 s14, 0x796cde01
	s_mov_b32 s15, 0x3ec71de3
	v_add_f64 v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[10:11], -v[4:5]
	v_add_f64 v[10:11], v[8:9], v[2:3]
	v_fma_f64 v[4:5], v[6:7], s[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s1, 0xbe5ae600
	v_cvt_i32_f64_e32 v6, v[6:7]
	v_add_f64 v[12:13], v[14:15], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	v_cndmask_b32_e32 v6, v24, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v7, 1, v6
	v_dual_cndmask_b32 v9, v11, v13 :: v_dual_cndmask_b32 v8, v10, v12
	v_add_f64 v[14:15], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[8:9], v[8:9]
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[12:13], v[10:11], s[2:3], s[0:1]
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s2, 0x46cc5e42
	s_mov_b32 s1, 0x3e21eeb6
	s_mov_b32 s3, 0xbda907db
	v_mul_f64 v[16:17], v[10:11], 0.5
	v_fma_f64 v[14:15], v[10:11], s[2:3], s[0:1]
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s3, 0xbf2a01a0
	v_mul_f64 v[20:21], v[8:9], -v[10:11]
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[4:5], v[2:3], 0.5
	v_add_f64 v[18:19], -v[16:17], 1.0
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	s_mov_b32 s0, 0x19f4ec90
	s_mov_b32 s1, 0x3efa01a0
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[2:3]
	s_mov_b32 s2, 0x11110bb3
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], -v[18:19], 1.0
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[2:3]
	v_cmp_lt_i32_e64 s2, v35, v36
	v_add_f64 v[16:17], v[22:23], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	s_mov_b32 s1, 0x3fa55555
	s_mov_b32 s0, 0x55555555
	v_fma_f64 v[4:5], v[20:21], v[12:13], v[4:5]
	v_mul_f64 v[12:13], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[8:9], -v[2:3], v[16:17]
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[10:11], v[4:5], -v[2:3]
	v_fma_f64 v[4:5], v[12:13], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[2:3], v[20:21], s[0:1], v[2:3]
	v_cmp_class_f64_e64 s0, v[0:1], 0x1f8
	v_lshlrev_b32_e32 v0, 30, v6
	v_add_f64 v[4:5], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v1
	v_and_b32_e32 v0, 0x80000000, v0
	v_add_f64 v[2:3], v[8:9], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
	v_xor_b32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, 0, v2, s0
	v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[33:34], |v[0:1]|, s[8:9]
	v_mul_lo_u32 v0, s19, v32
	v_mul_lo_u32 v0, v0, s20
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v29, 5, v0
.LBB1_13:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_15 Depth 2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_18
; %bb.14:                               ; %.lr.ph74
                                        ;   in Loop: Header=BB1_13 Depth=1
	v_mov_b32_e32 v32, v30
	v_mov_b32_e32 v28, v35
	s_mov_b32 s5, 0
.LBB1_15:                               ;   Parent Loop BB1_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v27 :: v_dual_mov_b32 v1, v28
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s6
	v_mov_b32_e32 v4, s7
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z13is_source_gpuiiiiii@rel32@lo+4
	s_addc_u32 s1, s1, _Z13is_source_gpuiiiiii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB1_17
; %bb.16:                               ; %_ZL3sind.exit
                                        ;   in Loop: Header=BB1_15 Depth=2
	v_add_nc_u32_e32 v0, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[0:1], v[33:34], off
.LBB1_17:                               ;   in Loop: Header=BB1_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v32, -1, v32
	v_add_nc_u32_e32 v28, 1, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v32
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_15
.LBB1_18:                               ; %Flow129
                                        ;   in Loop: Header=BB1_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v27, 1, v27
	v_add_nc_u32_e32 v29, s18, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, v27, v31
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_13
.LBB1_19:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, .Lfunc_end1-_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2372
; NumSgprs: 35
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z25wireless_src_pulse_kernelidddiiiiPdS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
