/*
nvcc flagg.cu -o flagg

file = open("noise.bin", "wb");
file.write(np.random.normal(0.,10.,2000000,dtype=np.float32));
file.close()
*/

#include <iostream>
#include <math.h>

#define NCHANS 1000	// # of channels -- assume no more than 2048 channels for now, see blinest call in main{}
#define NANTS 2000	// # of antennas
#define NFILT 101	// filter size -- need to be odd

__device__
void swap(float *p,float *q) {
   float t;
   
   t=*p; 
   *p=*q; 
   *q=t;
}

/*median value for NCHANS-long array*/
__device__
float medchans(float *a) {
	int i,j;
	float tmp[NCHANS] = {0};
	for (i = 0; i < NCHANS; i++)
		tmp[i] = a[i];
	
	for(i = 0; i < NCHANS-1; i++) {
		for(j = 0; j < NCHANS-i-1; j++) {
			if(tmp[j] > tmp[j+1])
				swap(&tmp[j],&tmp[j+1]);
		}
	}
	return tmp[(int)((NCHANS+1)/2-1)];
}

/*computes MAD for one spectrum*/
__device__
float mad(float *a) {
	int i;
	float med;
	float dev[NCHANS];
	med = medchans(a);
	for (i = 0; i < NCHANS; i++)
		dev[i] = abs(a[i]-med);
	return 1.4826*medchans(dev);
}

/*median value for NFILT-long array + manages edge effects*/
__device__
float medval(float *a, int idx, int n) {
	int i,j;
	float tmp[NFILT] = {0};
	if (idx < (NFILT-1)/2+1) {
		for (i=idx+(NFILT-1)/2+1; i<NFILT; i++)
			tmp[i] = a[0];
		for (i = 0; i<idx+(NFILT-1)/2+1; i++)
			tmp[i] = a[i];
	}
	else if(idx > n - ((NFILT-1)/2+1)) {
		for (i=n-(idx-(NFILT-1)/2); i<NFILT; i++)
			tmp[i] = a[n-1];
		for (i = idx-(NFILT-1)/2; i<n; i++)
			tmp[i-(idx-(NFILT-1)/2)] = a[i];
	}
	else{
		for (i = idx-(NFILT-1)/2; i<idx+(NFILT-1)/2+1; i++)
			tmp[i-(idx-(NFILT-1)/2)] = a[i];
	}
	
	for(i = 0; i<NFILT-1;i++) {
		for(j = 0;j < NFILT-i-1;j++) {
			if(tmp[j] > tmp[j+1])
				swap(&tmp[j],&tmp[j+1]);
		}
	}
	return tmp[(NFILT+1)/2-1];
}

__global__
void blinest(float *d_data, float *d_bline) {
	if (threadIdx.x < NCHANS/4){
		int idx = blockIdx.x * NCHANS/4 + threadIdx.x;
		int nAnt = (int)(blockIdx.x/4);
		int nSam = (blockIdx.x % 4) * NCHANS/4 + threadIdx.x;
		d_bline[idx] = medval(&d_data[nAnt*NCHANS], nSam, NCHANS);
	}
	__syncthreads();
}

__global__
void blincorr(float *d_data, float *d_bline) {
	if (threadIdx.x < NCHANS/4){
		int idx = blockIdx.x * NCHANS/4 + threadIdx.x;
		d_data[idx] = d_data[idx] - d_bline[idx];
	}
	__syncthreads();
}

__global__
void flagg(float *d_data, float *d_flags, float dThres)
{
	int i;
	int nAnt = blockIdx.x;
	float mv;
	mv = mad(&d_data[nAnt*NCHANS]);
	//printf("antenns %d : sigma = %f\n", nAnt, mv);
	for(i = nAnt*NCHANS; i < (nAnt+1)*NCHANS; i++)	// possible to write kernel to compute flags over blocks and threads
		if (d_data[i] > dThres*mv || d_data[i] < -dThres*mv)
			d_flags[i] = 1;
}

int main(void)
{

	int N = NANTS*NCHANS;	// size of 1 time sample, autocorrelations only
	float dThres = 6.;
	
	float *x = (float *)malloc(N*sizeof(float));	// data in (autocorrelations)
	float *fl_data = (float *)malloc(N*sizeof(float));	// data out (corrected data)
	float *d_data;	// input data on device
	cudaMalloc((void **)&d_data, N*sizeof(float));
	
	float *h_bline = (float *)malloc(N*sizeof(float));	// baseline
	float *d_bline;	// baseline
	cudaMalloc((void **)&d_bline, N*sizeof(float));
	
	float *h_flags = (float *)malloc(N*sizeof(float));	// data out (corrected data)
	float *d_flags;	// flags on device
	cudaMalloc((void **)&d_flags, N*sizeof(float));
	cudaMemset(d_flags, 0., N*sizeof(float));

	/*disk files management*/
	FILE *ptr;
	FILE *write_ptr;
	FILE *write_flg;
	FILE *write_bl;
	ptr = fopen("noise.bin","rb");
	write_ptr = fopen("output.bin","wb");
	write_flg = fopen("flags.bin","wb");
	write_bl = fopen("bline.bin","wb");
	int rd;
	rd = fread(x,N,sizeof(float),ptr);

	/*copy data onto GPU*/
	cudaMemcpy(d_data, x, N*sizeof(float), cudaMemcpyHostToDevice);
	
	/*FLAG DATA*/
	blinest<<<NANTS*4, NCHANS/4>>>(d_data, d_bline);
	cudaDeviceSynchronize();
	blincorr<<<NANTS*4, NCHANS/4>>>(d_data, d_bline);
	cudaDeviceSynchronize();
	flagg<<<NANTS, 1>>>(d_data, d_flags, dThres);
	cudaDeviceSynchronize();
	
	/*copy back to CPU and write to disk*/
	cudaMemcpy(fl_data, d_data, N*sizeof(float), cudaMemcpyDeviceToHost);
	fwrite(fl_data,N,sizeof(float),write_ptr);
	cudaMemcpy(h_flags, d_flags, N*sizeof(float), cudaMemcpyDeviceToHost);
	fwrite(h_flags,N,sizeof(float),write_flg);
	cudaMemcpy(h_bline, d_bline, N*sizeof(float), cudaMemcpyDeviceToHost);
	fwrite(h_bline,N,sizeof(float),write_bl);

	/*Free memory*/
	free(x);
	free(fl_data);
	free(h_bline);
	free(h_flags);
	cudaFree(d_data);
	cudaFree(d_bline);
	cudaFree(d_flags);
	fclose(ptr);
	fclose(write_ptr);
	fclose(write_flg);
	fclose(write_bl);
	return 0;
}

	.file	"tmpxft_0023bd36_00000000-6_flagg.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4swapPfS_
	.type	_Z4swapPfS_, @function
_Z4swapPfS_:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z4swapPfS_, .-_Z4swapPfS_
	.globl	_Z8medchansPf
	.type	_Z8medchansPf, @function
_Z8medchansPf:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z8medchansPf, .-_Z8medchansPf
	.globl	_Z3madPf
	.type	_Z3madPf, @function
_Z3madPf:
.LFB4291:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z8medchansPf
	.cfi_endproc
.LFE4291:
	.size	_Z3madPf, .-_Z3madPf
	.globl	_Z6medvalPfii
	.type	_Z6medvalPfii, @function
_Z6medvalPfii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3638:
	.size	_Z6medvalPfii, .-_Z6medvalPfii
	.globl	_Z28__device_stub__Z7blinestPfS_PfS_
	.type	_Z28__device_stub__Z7blinestPfS_PfS_, @function
_Z28__device_stub__Z7blinestPfS_PfS_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7blinestPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L10:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z28__device_stub__Z7blinestPfS_PfS_, .-_Z28__device_stub__Z7blinestPfS_PfS_
	.globl	_Z7blinestPfS_
	.type	_Z7blinestPfS_, @function
_Z7blinestPfS_:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7blinestPfS_PfS_
	.cfi_endproc
.LFE3665:
	.size	_Z7blinestPfS_, .-_Z7blinestPfS_
	.globl	_Z29__device_stub__Z8blincorrPfS_PfS_
	.type	_Z29__device_stub__Z8blincorrPfS_PfS_, @function
_Z29__device_stub__Z8blincorrPfS_PfS_:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8blincorrPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z29__device_stub__Z8blincorrPfS_PfS_, .-_Z29__device_stub__Z8blincorrPfS_PfS_
	.globl	_Z8blincorrPfS_
	.type	_Z8blincorrPfS_, @function
_Z8blincorrPfS_:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8blincorrPfS_PfS_
	.cfi_endproc
.LFE3667:
	.size	_Z8blincorrPfS_, .-_Z8blincorrPfS_
	.globl	_Z27__device_stub__Z5flaggPfS_fPfS_f
	.type	_Z27__device_stub__Z5flaggPfS_fPfS_f, @function
_Z27__device_stub__Z5flaggPfS_fPfS_f:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5flaggPfS_f(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L21:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z27__device_stub__Z5flaggPfS_fPfS_f, .-_Z27__device_stub__Z5flaggPfS_fPfS_f
	.globl	_Z5flaggPfS_f
	.type	_Z5flaggPfS_f, @function
_Z5flaggPfS_f:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z5flaggPfS_fPfS_f
	.cfi_endproc
.LFE3669:
	.size	_Z5flaggPfS_f, .-_Z5flaggPfS_f
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
.LC1:
	.string	"noise.bin"
.LC2:
	.string	"wb"
.LC3:
	.string	"output.bin"
.LC4:
	.string	"flags.bin"
.LC5:
	.string	"bline.bin"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$8000000, %edi
	leaq	.LC2(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$8000000, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$8000000, %esi
	leaq	24(%rsp), %rdi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	movl	$8000000, %edi
	call	malloc@PLT
	movl	$8000000, %esi
	leaq	32(%rsp), %rdi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	movl	$8000000, %edi
	call	malloc@PLT
	leaq	40(%rsp), %rdi
	movl	$8000000, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$8000000, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	call	fopen@PLT
	movq	%r15, %rsi
	leaq	.LC3(%rip), %rdi
	movq	%rax, %r14
	call	fopen@PLT
	movq	%r15, %rsi
	leaq	.LC4(%rip), %rdi
	movq	%rax, (%rsp)
	call	fopen@PLT
	movq	%r15, %rsi
	leaq	.LC5(%rip), %rdi
	movq	%rax, 8(%rsp)
	call	fopen@PLT
	movq	%r14, %r8
	movl	$4, %ecx
	movq	%r13, %rdi
	movl	$2000000, %edx
	movl	$8000000, %esi
	movq	%rax, %r15
	call	__fread_chk@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$8000000, %edx
	call	cudaMemcpy@PLT
	movl	$2147483773, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108989, %edi
	addq	%rdx, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z28__device_stub__Z7blinestPfS_PfS_
.L27:
	call	cudaDeviceSynchronize@PLT
	movl	$2147483773, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$67108989, %edi
	addq	%rdx, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$6, %rdi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z29__device_stub__Z8blincorrPfS_PfS_
.L28:
	call	cudaDeviceSynchronize@PLT
	movl	$268435581, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdi
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movss	.LC6(%rip), %xmm0
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z27__device_stub__Z5flaggPfS_fPfS_f
.L29:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$8000000, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rcx
	movl	$4, %edx
	movq	%r12, %rdi
	movl	$2000000, %esi
	call	fwrite@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$8000000, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rcx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2000000, %esi
	call	fwrite@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$8000000, %edx
	call	cudaMemcpy@PLT
	movq	%r15, %rcx
	movl	$4, %edx
	movq	%rbp, %rdi
	movl	$2000000, %esi
	call	fwrite@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r14, %rdi
	call	fclose@PLT
	movq	(%rsp), %rdi
	call	fclose@PLT
	movq	8(%rsp), %rdi
	call	fclose@PLT
	movq	%r15, %rdi
	call	fclose@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z5flaggPfS_f"
.LC8:
	.string	"_Z8blincorrPfS_"
.LC9:
	.string	"_Z7blinestPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3671:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5flaggPfS_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8blincorrPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7blinestPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3671:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC6:
	.long	1086324736
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
nvcc flagg.cu -o flagg

file = open("noise.bin", "wb");
file.write(np.random.normal(0.,10.,2000000,dtype=np.float32));
file.close()
*/


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>

#define NCHANS 1000	// # of channels -- assume no more than 2048 channels for now, see blinest call in main{}
#define NANTS 2000	// # of antennas
#define NFILT 101	// filter size -- need to be odd

__device__
void swap(float *p,float *q) {
   float t;
   
   t=*p; 
   *p=*q; 
   *q=t;
}

/*median value for NCHANS-long array*/
__device__
float medchans(float *a) {
	int i,j;
	float tmp[NCHANS] = {0};
	for (i = 0; i < NCHANS; i++)
		tmp[i] = a[i];
	
	for(i = 0; i < NCHANS-1; i++) {
		for(j = 0; j < NCHANS-i-1; j++) {
			if(tmp[j] > tmp[j+1])
				swap(&tmp[j],&tmp[j+1]);
		}
	}
	return tmp[(int)((NCHANS+1)/2-1)];
}

/*computes MAD for one spectrum*/
__device__
float mad(float *a) {
	int i;
	float med;
	float dev[NCHANS];
	med = medchans(a);
	for (i = 0; i < NCHANS; i++)
		dev[i] = abs(a[i]-med);
	return 1.4826*medchans(dev);
}

/*median value for NFILT-long array + manages edge effects*/
__device__
float medval(float *a, int idx, int n) {
	int i,j;
	float tmp[NFILT] = {0};
	if (idx < (NFILT-1)/2+1) {
		for (i=idx+(NFILT-1)/2+1; i<NFILT; i++)
			tmp[i] = a[0];
		for (i = 0; i<idx+(NFILT-1)/2+1; i++)
			tmp[i] = a[i];
	}
	else if(idx > n - ((NFILT-1)/2+1)) {
		for (i=n-(idx-(NFILT-1)/2); i<NFILT; i++)
			tmp[i] = a[n-1];
		for (i = idx-(NFILT-1)/2; i<n; i++)
			tmp[i-(idx-(NFILT-1)/2)] = a[i];
	}
	else{
		for (i = idx-(NFILT-1)/2; i<idx+(NFILT-1)/2+1; i++)
			tmp[i-(idx-(NFILT-1)/2)] = a[i];
	}
	
	for(i = 0; i<NFILT-1;i++) {
		for(j = 0;j < NFILT-i-1;j++) {
			if(tmp[j] > tmp[j+1])
				swap(&tmp[j],&tmp[j+1]);
		}
	}
	return tmp[(NFILT+1)/2-1];
}

__global__
void blinest(float *d_data, float *d_bline) {
	if (threadIdx.x < NCHANS/4){
		int idx = blockIdx.x * NCHANS/4 + threadIdx.x;
		int nAnt = (int)(blockIdx.x/4);
		int nSam = (blockIdx.x % 4) * NCHANS/4 + threadIdx.x;
		d_bline[idx] = medval(&d_data[nAnt*NCHANS], nSam, NCHANS);
	}
	__syncthreads();
}

__global__
void blincorr(float *d_data, float *d_bline) {
	if (threadIdx.x < NCHANS/4){
		int idx = blockIdx.x * NCHANS/4 + threadIdx.x;
		d_data[idx] = d_data[idx] - d_bline[idx];
	}
	__syncthreads();
}

__global__
void flagg(float *d_data, float *d_flags, float dThres)
{
	int i;
	int nAnt = blockIdx.x;
	float mv;
	mv = mad(&d_data[nAnt*NCHANS]);
	//printf("antenns %d : sigma = %f\n", nAnt, mv);
	for(i = nAnt*NCHANS; i < (nAnt+1)*NCHANS; i++)	// possible to write kernel to compute flags over blocks and threads
		if (d_data[i] > dThres*mv || d_data[i] < -dThres*mv)
			d_flags[i] = 1;
}

int main(void)
{

	int N = NANTS*NCHANS;	// size of 1 time sample, autocorrelations only
	float dThres = 6.;
	
	float *x = (float *)malloc(N*sizeof(float));	// data in (autocorrelations)
	float *fl_data = (float *)malloc(N*sizeof(float));	// data out (corrected data)
	float *d_data;	// input data on device
	hipMalloc((void **)&d_data, N*sizeof(float));
	
	float *h_bline = (float *)malloc(N*sizeof(float));	// baseline
	float *d_bline;	// baseline
	hipMalloc((void **)&d_bline, N*sizeof(float));
	
	float *h_flags = (float *)malloc(N*sizeof(float));	// data out (corrected data)
	float *d_flags;	// flags on device
	hipMalloc((void **)&d_flags, N*sizeof(float));
	hipMemset(d_flags, 0., N*sizeof(float));

	/*disk files management*/
	FILE *ptr;
	FILE *write_ptr;
	FILE *write_flg;
	FILE *write_bl;
	ptr = fopen("noise.bin","rb");
	write_ptr = fopen("output.bin","wb");
	write_flg = fopen("flags.bin","wb");
	write_bl = fopen("bline.bin","wb");
	int rd;
	rd = fread(x,N,sizeof(float),ptr);

	/*copy data onto GPU*/
	hipMemcpy(d_data, x, N*sizeof(float), hipMemcpyHostToDevice);
	
	/*FLAG DATA*/
	blinest<<<NANTS*4, NCHANS/4>>>(d_data, d_bline);
	hipDeviceSynchronize();
	blincorr<<<NANTS*4, NCHANS/4>>>(d_data, d_bline);
	hipDeviceSynchronize();
	flagg<<<NANTS, 1>>>(d_data, d_flags, dThres);
	hipDeviceSynchronize();
	
	/*copy back to CPU and write to disk*/
	hipMemcpy(fl_data, d_data, N*sizeof(float), hipMemcpyDeviceToHost);
	fwrite(fl_data,N,sizeof(float),write_ptr);
	hipMemcpy(h_flags, d_flags, N*sizeof(float), hipMemcpyDeviceToHost);
	fwrite(h_flags,N,sizeof(float),write_flg);
	hipMemcpy(h_bline, d_bline, N*sizeof(float), hipMemcpyDeviceToHost);
	fwrite(h_bline,N,sizeof(float),write_bl);

	/*Free memory*/
	free(x);
	free(fl_data);
	free(h_bline);
	free(h_flags);
	hipFree(d_data);
	hipFree(d_bline);
	hipFree(d_flags);
	fclose(ptr);
	fclose(write_ptr);
	fclose(write_flg);
	fclose(write_bl);
	return 0;
}

	.text
	.file	"flagg.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__blinestPfS_  # -- Begin function _Z22__device_stub__blinestPfS_
	.type	_Z22__device_stub__blinestPfS_,@function
_Z22__device_stub__blinestPfS_:         # @_Z22__device_stub__blinestPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7blinestPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__blinestPfS_, .Lfunc_end0-_Z22__device_stub__blinestPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__blincorrPfS_ # -- Begin function _Z23__device_stub__blincorrPfS_
	.type	_Z23__device_stub__blincorrPfS_,@function
_Z23__device_stub__blincorrPfS_:        # @_Z23__device_stub__blincorrPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8blincorrPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__blincorrPfS_, .Lfunc_end1-_Z23__device_stub__blincorrPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__flaggPfS_f   # -- Begin function _Z20__device_stub__flaggPfS_f
	.type	_Z20__device_stub__flaggPfS_f,@function
_Z20__device_stub__flaggPfS_f:          # @_Z20__device_stub__flaggPfS_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5flaggPfS_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__flaggPfS_f, .Lfunc_end2-_Z20__device_stub__flaggPfS_f
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x40c00000                      # float 6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967546, %r13               # imm = 0x1000000FA
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, %r14
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	%rsp, %rbp
	movl	$8000000, %esi                  # imm = 0x7A1200
	movq	%rbp, %rdi
	callq	hipMalloc
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, %r15
	leaq	8(%rsp), %rdi
	movl	$8000000, %esi                  # imm = 0x7A1200
	callq	hipMalloc
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, %r12
	leaq	16(%rsp), %rbx
	movl	$8000000, %esi                  # imm = 0x7A1200
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r14, %rbx
	movl	$8000000, %edx                  # imm = 0x7A1200
	xorl	%esi, %esi
	callq	hipMemset
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$.L.str.4, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	$.L.str.5, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	$2000000, %esi                  # imm = 0x1E8480
	movl	$4, %edx
	movq	%rbx, %rdi
	movq	%r14, 56(%rsp)                  # 8-byte Spill
	movq	%r14, %rcx
	callq	fread
	movq	(%rbp), %rdi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	%rbx, 24(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	7750(%r13), %rbp
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z22__device_stub__blinestPfS_
.LBB3_2:
	callq	hipDeviceSynchronize
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z23__device_stub__blincorrPfS_
.LBB3_4:
	callq	hipDeviceSynchronize
	leaq	-249(%r13), %rdx
	addq	$1750, %r13                     # imm = 0x6D6
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movss	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	callq	_Z20__device_stub__flaggPfS_f
.LBB3_6:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	64(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$2000000, %esi                  # imm = 0x1E8480
	movl	$4, %edx
	movq	%r14, %rdi
	movq	48(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rcx
	callq	fwrite
	movq	16(%rsp), %rsi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$2000000, %esi                  # imm = 0x1E8480
	movl	$4, %edx
	movq	%r12, %rdi
	movq	40(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rcx
	callq	fwrite
	movq	8(%rsp), %rsi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$2000000, %esi                  # imm = 0x1E8480
	movl	$4, %edx
	movq	%r15, %rdi
	movq	32(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rcx
	callq	fwrite
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi                  # 8-byte Reload
	callq	fclose
	movq	%r13, %rdi
	callq	fclose
	movq	%rbp, %rdi
	callq	fclose
	movq	%rbx, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7blinestPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8blincorrPfS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5flaggPfS_f, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7blinestPfS_,@object          # @_Z7blinestPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z7blinestPfS_
	.p2align	3, 0x0
_Z7blinestPfS_:
	.quad	_Z22__device_stub__blinestPfS_
	.size	_Z7blinestPfS_, 8

	.type	_Z8blincorrPfS_,@object         # @_Z8blincorrPfS_
	.globl	_Z8blincorrPfS_
	.p2align	3, 0x0
_Z8blincorrPfS_:
	.quad	_Z23__device_stub__blincorrPfS_
	.size	_Z8blincorrPfS_, 8

	.type	_Z5flaggPfS_f,@object           # @_Z5flaggPfS_f
	.globl	_Z5flaggPfS_f
	.p2align	3, 0x0
_Z5flaggPfS_f:
	.quad	_Z20__device_stub__flaggPfS_f
	.size	_Z5flaggPfS_f, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"noise.bin"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"rb"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"output.bin"
	.size	.L.str.2, 11

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"wb"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"flags.bin"
	.size	.L.str.4, 10

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"bline.bin"
	.size	.L.str.5, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7blinestPfS_"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8blincorrPfS_"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z5flaggPfS_f"
	.size	.L__unnamed_3, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__blinestPfS_
	.addrsig_sym _Z23__device_stub__blincorrPfS_
	.addrsig_sym _Z20__device_stub__flaggPfS_f
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7blinestPfS_
	.addrsig_sym _Z8blincorrPfS_
	.addrsig_sym _Z5flaggPfS_f
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7blinestPfS_          ; -- Begin function _Z7blinestPfS_
	.globl	_Z7blinestPfS_
	.p2align	8
	.type	_Z7blinestPfS_,@function
_Z7blinestPfS_:                         ; @_Z7blinestPfS_
; %bb.0:
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e32 0xfa, v0
	s_cbranch_execz .LBB0_27
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshr_b32 s4, s15, 2
	s_mov_b32 s17, 0
	s_mul_i32 s16, s4, 0x3e8
	s_and_b32 s9, s15, 3
	s_lshl_b64 s[6:7], s[16:17], 2
	s_mov_b32 s16, s17
	v_mad_u64_u32 v[1:2], null, 0xfa, s9, v[0:1]
	s_mov_b32 s18, s17
	s_mov_b32 s19, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v6, s19
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, s17
	v_mov_b32_e32 v5, s18
	s_mov_b32 s10, exec_lo
	s_clause 0x5
	scratch_store_b32 off, v7, off offset:416
	scratch_store_b128 off, v[3:6], off offset:400
	scratch_store_b128 off, v[3:6], off offset:384
	scratch_store_b128 off, v[3:6], off offset:368
	scratch_store_b128 off, v[3:6], off offset:352
	scratch_store_b128 off, v[3:6], off offset:336
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s0, s6
	s_addc_u32 s5, s1, s7
	s_clause 0x13
	scratch_store_b128 off, v[3:6], off offset:320
	scratch_store_b128 off, v[3:6], off offset:304
	scratch_store_b128 off, v[3:6], off offset:288
	scratch_store_b128 off, v[3:6], off offset:272
	scratch_store_b128 off, v[3:6], off offset:256
	scratch_store_b128 off, v[3:6], off offset:240
	scratch_store_b128 off, v[3:6], off offset:224
	scratch_store_b128 off, v[3:6], off offset:208
	scratch_store_b128 off, v[3:6], off offset:192
	scratch_store_b128 off, v[3:6], off offset:176
	scratch_store_b128 off, v[3:6], off offset:160
	scratch_store_b128 off, v[3:6], off offset:144
	scratch_store_b128 off, v[3:6], off offset:128
	scratch_store_b128 off, v[3:6], off offset:112
	scratch_store_b128 off, v[3:6], off offset:96
	scratch_store_b128 off, v[3:6], off offset:80
	scratch_store_b128 off, v[3:6], off offset:64
	scratch_store_b128 off, v[3:6], off offset:48
	scratch_store_b128 off, v[3:6], off offset:32
	scratch_store_b128 off, v[3:6], off offset:16
	v_cmpx_lt_u32_e32 50, v1
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_13
; %bb.2:
	v_subrev_nc_u32_e32 v2, 50, v1
	s_mov_b32 s11, exec_lo
	v_cmpx_gt_u32_e32 0x3b6, v1
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB0_5
; %bb.3:
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_u32 s12, s0, s6
	s_addc_u32 s13, s1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v2, vcc_lo
	s_mov_b32 s12, 0
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_i32 s13, s12, 16
	s_add_i32 s12, s12, 4
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s12, 0x194
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v5, s13
	s_cbranch_scc1 .LBB0_4
.LBB0_5:                                ; %Flow55
	s_and_not1_saveexec_b32 s11, s11
	s_cbranch_execz .LBB0_12
; %bb.6:                                ; %.lr.ph.i
	s_load_b32 s12, s[4:5], 0xf9c
	s_mul_i32 s13, s9, 0x3e8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, v0, 2, s13
	v_sub_nc_u32_e32 v4, 16, v3
	v_add_nc_u32_e32 v3, 0xfffffc4b, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v5, s12 :: v_dual_add_nc_u32 v4, 0x1068, v4
	s_mov_b32 s12, 0
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, -1, v3
	scratch_store_b32 v4, v5, off
	v_add_nc_u32_e32 v4, 4, v4
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %.preheader49.i
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e32 0x41a, v1
	s_cbranch_execz .LBB0_11
; %bb.9:                                ; %.lr.ph55.i.preheader
	v_mov_b32_e32 v3, 0
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_subrev_nc_u32_e32 v3, 51, v1
	v_add_co_u32 v1, vcc_lo, s0, v4
	v_mov_b32_e32 v4, 16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v5, vcc_lo
	s_mov_b32 s1, 0
.LBB0_10:                               ; %.lr.ph55.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[1:2], off
	v_add_nc_u32_e32 v3, 1, v3
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, 0x3e6, v3
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	scratch_store_b32 v4, v5, off
	v_add_nc_u32_e32 v4, 4, v4
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_10
.LBB0_11:                               ; %Flow54
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_12:                               ; %Flow56
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_13:                               ; %Flow60
	s_and_not1_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_20
; %bb.14:
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 50, v1
	s_cbranch_execz .LBB0_17
; %bb.15:                               ; %.lr.ph57.i
	s_load_b32 s6, s[4:5], 0x0
	s_mulk_i32 s9, 0x3e8
	v_lshlrev_b32_e32 v3, 2, v0
	v_add_nc_u32_e64 v4, s9, 16
	v_add_nc_u32_e32 v2, 50, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v3, v4, v3, 0xcc
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, s6
	s_mov_b32 s6, 0
.LBB0_16:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, 1, v2
	scratch_store_b32 v3, v4, off
	v_add_nc_u32_e32 v3, 4, v3
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v2
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_16
.LBB0_17:                               ; %Flow59
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, 16 :: v_dual_add_nc_u32 v1, 51, v1
	s_mov_b32 s1, 0
.LBB0_18:                               ; %.lr.ph59.i
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s6, s[4:5], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, -1, v1
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s6
	scratch_store_b32 v2, v3, off
	v_add_nc_u32_e32 v2, 4, v2
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %Flow57
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_20:                               ; %Flow61
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e64 v3, 16, 4
	s_mov_b32 s0, 0
.LBB0_21:                               ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_22 Depth 2
	scratch_load_b32 v2, off, off offset:16
	v_mov_b32_e32 v4, v3
	s_sub_i32 s1, 0x64, s0
	s_mov_b32 s4, 0
.LBB0_22:                               ; %.lr.ph61.i
                                        ;   Parent Loop BB0_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v1, v4, off
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_f32_e32 v2, v1
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=2
	scratch_store_b64 v4, v[1:2], off offset:-4
	v_mov_b32_e32 v1, v2
.LBB0_24:                               ;   in Loop: Header=BB0_22 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v4, 4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v2, v1
	s_add_i32 s4, s4, 1
	s_cmp_lt_u32 s4, s1
	s_cbranch_scc1 .LBB0_22
; %bb.25:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_21 Depth=1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s0, 0x64
	s_cbranch_scc1 .LBB0_21
; %bb.26:                               ; %_Z6medvalPfii.exit
	scratch_load_b32 v2, off, off offset:216
	s_mulk_i32 s15, 0x3e8
	v_mov_b32_e32 v1, 0
	s_lshr_b32 s0, s15, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s0, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_27:                               ; %Flow62
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7blinestPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 432
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7blinestPfS_, .Lfunc_end0-_Z7blinestPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1132
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 432
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8blincorrPfS_         ; -- Begin function _Z8blincorrPfS_
	.globl	_Z8blincorrPfS_
	.p2align	8
	.type	_Z8blincorrPfS_,@function
_Z8blincorrPfS_:                        ; @_Z8blincorrPfS_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 0xfa, v0
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mulk_i32 s15, 0x3e8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s0, s15, 2
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v4, v0
	global_store_b32 v[2:3], v0, off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8blincorrPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8blincorrPfS_, .Lfunc_end1-_Z8blincorrPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5flaggPfS_f           ; -- Begin function _Z5flaggPfS_f
	.globl	_Z5flaggPfS_f
	.p2align	8
	.type	_Z5flaggPfS_f,@function
_Z5flaggPfS_f:                          ; @_Z5flaggPfS_f
; %bb.0:                                ; %loadstoreloop22.preheader
	v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
	s_mov_b64 s[2:3], 0
.LBB2_1:                                ; %loadstoreloop22
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	scratch_store_b8 v0, v1, off
	v_cmp_gt_u64_e64 s4, 0xfa0, s[2:3]
	v_add_nc_u32_e32 v0, 1, v0
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB2_1
; %bb.2:                                ; %split21
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mul_i32 s2, s15, 0x3e8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s10, s4, s8
	s_addc_u32 s11, s5, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[12:13], s[10:11]
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	s_load_b32 s14, s[12:13], 0x0
	s_add_i32 s16, s3, 16
	s_add_i32 s3, s3, 4
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_cmpk_lg_i32 s3, 0xfa0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v0, s14
	scratch_store_b32 off, v0, s16
	s_cbranch_scc1 .LBB2_3
; %bb.4:                                ; %.preheader.i.i.preheader
	v_or_b32_e64 v2, 16, 4
	s_mov_b32 s3, 0
.LBB2_5:                                ; %.preheader.i.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_6 Depth 2
	scratch_load_b32 v1, off, off offset:16
	v_mov_b32_e32 v3, v2
	s_sub_i32 s12, 0x3e7, s3
	s_mov_b32 s13, 0
.LBB2_6:                                ; %.lr.ph.i.i
                                        ;   Parent Loop BB2_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v0, v3, off
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_f32_e32 v1, v0
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_6 Depth=2
	scratch_store_b64 v3, v[0:1], off offset:-4
	v_mov_b32_e32 v0, v1
.LBB2_8:                                ;   in Loop: Header=BB2_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v3, 4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v1, v0
	s_add_i32 s13, s13, 1
	s_cmp_lt_u32 s13, s12
	s_cbranch_scc1 .LBB2_6
; %bb.9:                                ; %._crit_edge.i.i
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s3, 0x3e7
	s_cbranch_scc1 .LBB2_5
; %bb.10:                               ; %_Z8medchansPf.exit.i
	scratch_load_b32 v0, off, off offset:2012
	s_mov_b32 s3, 0
.LBB2_11:                               ; =>This Inner Loop Header: Depth=1
	s_load_b32 s12, s[10:11], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v1, s12, v0
	s_add_i32 s12, s3, 0xfb0
	s_add_i32 s3, s3, 4
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	v_and_b32_e32 v1, 0x7fffffff, v1
	s_cmpk_lg_i32 s3, 0xfa0
	scratch_store_b32 off, v1, s12
	s_cbranch_scc1 .LBB2_11
; %bb.12:                               ; %loadstoreloop.preheader
	v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
	s_mov_b64 s[10:11], 0
.LBB2_13:                               ; %loadstoreloop
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	scratch_store_b8 v0, v1, off
	v_cmp_gt_u64_e64 s3, 0xfa0, s[10:11]
	v_add_nc_u32_e32 v0, 1, v0
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB2_13
; %bb.14:                               ; %split
	s_mov_b32 s3, 0
.LBB2_15:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s3, 0xfb0
	scratch_load_b32 v0, off, s10
	s_add_i32 s10, s3, 16
	s_add_i32 s3, s3, 4
	s_cmpk_lg_i32 s3, 0xfa0
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB2_15
; %bb.16:                               ; %.preheader.i8.i.preheader
	v_or_b32_e64 v2, 16, 4
	s_mov_b32 s3, 0
.LBB2_17:                               ; %.preheader.i8.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_18 Depth 2
	scratch_load_b32 v1, off, off offset:16
	v_mov_b32_e32 v3, v2
	s_sub_i32 s10, 0x3e7, s3
	s_mov_b32 s11, 0
.LBB2_18:                               ; %.lr.ph.i11.i
                                        ;   Parent Loop BB2_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v0, v3, off
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_f32_e32 v1, v0
	s_cbranch_execz .LBB2_20
; %bb.19:                               ;   in Loop: Header=BB2_18 Depth=2
	scratch_store_b64 v3, v[0:1], off offset:-4
	v_mov_b32_e32 v0, v1
.LBB2_20:                               ;   in Loop: Header=BB2_18 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v3, 4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v1, v0
	s_add_i32 s11, s11, 1
	s_cmp_lt_u32 s11, s10
	s_cbranch_scc1 .LBB2_18
; %bb.21:                               ; %._crit_edge.i13.i
                                        ;   in Loop: Header=BB2_17 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s3, 0x3e7
	s_cbranch_scc1 .LBB2_17
; %bb.22:                               ; %_Z3madPf.exit
	scratch_load_b32 v0, off, off offset:2012
	s_cmp_gt_i32 s15, 0x20c49a
	s_cbranch_scc1 .LBB2_27
; %bb.23:                               ; %.lr.ph
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], v0
	s_mov_b32 s10, 0xc710cb29
	s_mov_b32 s11, 0x3ff7b8ba
	s_load_b32 s0, s[0:1], 0x10
	s_add_i32 s1, s2, 0x3e8
	s_add_u32 s4, s4, s8
	v_mov_b32_e32 v3, 1.0
	s_addc_u32 s5, s5, s9
	s_add_u32 s6, s6, s8
	s_addc_u32 s7, s7, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[10:11]
	v_cvt_f32_f64_e32 v2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mul_f32 v1, s0, v2
	v_mul_f32_e64 v2, -s0, v2
.LBB2_24:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v0, s[4:5]
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v4, v1
	v_cmp_lt_f32_e64 s0, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, vcc_lo, s0
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB2_26
; %bb.25:                               ;   in Loop: Header=BB2_24 Depth=1
	global_store_b32 v0, v3, s[6:7]
.LBB2_26:                               ;   in Loop: Header=BB2_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s2, s2, 1
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lt_i32 s2, s1
	s_cbranch_scc1 .LBB2_24
.LBB2_27:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5flaggPfS_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8016
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z5flaggPfS_f, .Lfunc_end2-_Z5flaggPfS_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 772
; NumSgprs: 19
; NumVgprs: 5
; ScratchSize: 8016
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7blinestPfS_
    .private_segment_fixed_size: 432
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z7blinestPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8blincorrPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8blincorrPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5flaggPfS_f
    .private_segment_fixed_size: 8016
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z5flaggPfS_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
