#include <stdio.h>
#include <cuda.h>

__device__ int getnum(char *queryArray, int &i)
{
    int ans=0;
    while(queryArray[i]==' ' || queryArray[i]=='\t')
        i++;
    while(queryArray[i]<=57 && queryArray[i]>=48)
    {
        ans = ans*10 + (queryArray[i]-'0');
        i++;
    }
    while(queryArray[i]==' ' || queryArray[i]=='\t')
        i++;
    return ans;
}
__global__ void updateDB(int* dB, char* queryArray_GPU, int *queryIndices_GPU, int m, int n, int q)
{
    int id = threadIdx.x + blockIdx.x * blockDim.x;
    if(id < q)
    {
        int base = queryIndices_GPU[id];
        int i=base+3, j, rowno;
        int updval;
        int updcol;
        int colno = getnum(queryArray_GPU, i)-1;      
        int ncomp = getnum(queryArray_GPU, i); 
        int p = getnum(queryArray_GPU, i);
        queryIndices_GPU[id] = i;
        for(rowno = 0; rowno<m; rowno++)
        {
            if(dB[rowno*n + colno] == ncomp)
            {
                i = queryIndices_GPU[id];
                for(j = 0; j<p; j++)
                {
                    i+=1;
                    updcol = getnum(queryArray_GPU, i)-1;
                    updval = getnum(queryArray_GPU, i);
                    if(queryArray_GPU[i]=='-')
                        updval*=(-1);
                    i+=2;
                    atomicAdd(&dB[rowno*n + updcol], updval);
                }
            }
        }
    }
}

int main(int argc, char* argv[])
{
    FILE *inp, *otp;
    inp = fopen(argv[1], "r");
    int m, n, i, j;
    fscanf(inp, "%d", &m);
    fscanf(inp, "%d", &n);
    int *dataBase = (int *) malloc (m*n*sizeof(int));
    for(i=0;i<m*n;++i)
        fscanf(inp, "%d", &dataBase[i]);
    int *dB;
    cudaMalloc(&dB,n*m*sizeof(int));
    cudaMemcpy(dB,dataBase,n*m*sizeof(int),cudaMemcpyHostToDevice);
    int q;
    fscanf(inp, "%d", &q);
    int *queryIndices_CPU = (int *) malloc (q*sizeof(int));
    int *queryIndices_GPU;
    cudaMalloc(&queryIndices_GPU, q*sizeof(int));
    char *queryArray_CPU = (char *)malloc(q*300*sizeof(char));
    j=0;
    i=0;
    while(fscanf(inp, "%c", &queryArray_CPU[i]) != EOF)
    {
        if(queryArray_CPU[i] == 'U')
        {
            queryIndices_CPU[j] = i;
            j+=1;
        }
        i+=1;
    }
    char *queryArray_GPU;
    cudaMalloc(&queryArray_GPU, (i)*sizeof(char));
    fclose(inp);
    cudaMemcpy(queryIndices_GPU,queryIndices_CPU,q*sizeof(int),cudaMemcpyHostToDevice);
    cudaMemcpy(queryArray_GPU,queryArray_CPU,(i)*sizeof(char),cudaMemcpyHostToDevice);
    updateDB<<<2, 1024>>>(dB, queryArray_GPU, queryIndices_GPU, m, n, q);
    cudaDeviceSynchronize();
    cudaMemcpy(dataBase,dB,n*m*sizeof(int),cudaMemcpyDeviceToHost);
    otp = fopen(argv[2], "w");
    for(i=0; i<m; ++i)
    {
        for(j=0; j<n; ++j)
            fprintf(otp, "%d ", dataBase[i*n + j]);
        fprintf(otp, "\n");
    } 
    return 0;
}

	.file	"tmpxft_002e8053_00000000-6_A3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6getnumPcRi
	.type	_Z6getnumPcRi, @function
_Z6getnumPcRi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z6getnumPcRi, .-_Z6getnumPcRi
	.globl	_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii
	.type	_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii, @function
_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8updateDBPiPcS_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii, .-_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii
	.globl	_Z8updateDBPiPcS_iii
	.type	_Z8updateDBPiPcS_iii, @function
_Z8updateDBPiPcS_iii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii
	.cfi_endproc
.LFE2054:
	.size	_Z8updateDBPiPcS_iii, .-_Z8updateDBPiPcS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%d"
.LC2:
	.string	"%c"
.LC3:
	.string	"w"
.LC4:
	.string	"%d "
.LC5:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	.LC1(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	8(%rsi), %rdi
	leaq	.LC0(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	28(%rsp), %rdx
	movq	%r13, %rsi
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	8(%rsp), %rdi
	movq	%r13, %rsi
	xorl	%eax, %eax
	leaq	32(%rsp), %rdx
	call	__isoc23_fscanf@PLT
	movl	28(%rsp), %edi
	imull	32(%rsp), %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rbx
	movq	%rax, %r15
.L11:
	movl	28(%rsp), %esi
	imull	32(%rsp), %esi
	cmpl	%r14d, %esi
	jle	.L23
	movq	8(%rsp), %rdi
	movq	%r15, %rdx
	movq	%r13, %rsi
	xorl	%eax, %eax
	incl	%r14d
	addq	$4, %r15
	call	__isoc23_fscanf@PLT
	jmp	.L11
.L23:
	movslq	%esi, %rsi
	leaq	40(%rsp), %rdi
	xorl	%ebp, %ebp
	xorl	%r15d, %r15d
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	32(%rsp), %edx
	imull	28(%rsp), %edx
	movq	%rbx, %rsi
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movq	%r13, %rsi
	xorl	%eax, %eax
	leaq	36(%rsp), %rdx
	call	__isoc23_fscanf@PLT
	movslq	36(%rsp), %r13
	salq	$2, %r13
	movq	%r13, %rdi
	call	malloc@PLT
	movq	%r13, %rsi
	leaq	48(%rsp), %rdi
	movq	%rax, %r14
	call	cudaMalloc@PLT
	imull	$300, 36(%rsp), %edi
	movslq	%edi, %rdi
	call	malloc@PLT
	movq	%rax, %r13
.L13:
	movq	8(%rsp), %rdi
	xorl	%eax, %eax
	leaq	0(%r13,%rbp), %rdx
	leaq	.LC2(%rip), %rsi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L24
	cmpb	$85, 0(%r13,%rbp)
	jne	.L14
	movslq	%r15d, %rax
	incl	%r15d
	movl	%ebp, (%r14,%rax,4)
.L14:
	incq	%rbp
	jmp	.L13
.L24:
	movq	%rbp, %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	call	fclose@PLT
	movslq	36(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2147483649, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	addq	%rdi, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movl	36(%rsp), %r9d
	movl	32(%rsp), %r8d
	movl	28(%rsp), %ecx
	movq	48(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z34__device_stub__Z8updateDBPiPcS_iiiPiPcS_iii
.L16:
	call	cudaDeviceSynchronize@PLT
	movl	32(%rsp), %edx
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	imull	28(%rsp), %edx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	16(%r12), %rdi
	leaq	.LC3(%rip), %rsi
	leaq	.LC4(%rip), %r12
	call	fopen@PLT
	movq	%rax, %rbp
.L17:
	cmpl	%r13d, 28(%rsp)
	jle	.L25
	xorl	%r14d, %r14d
.L19:
	movl	32(%rsp), %eax
	cmpl	%r14d, %eax
	jle	.L26
	imull	%r13d, %eax
	movq	%r12, %rdx
	movl	$2, %esi
	movq	%rbp, %rdi
	addl	%r14d, %eax
	incl	%r14d
	cltq
	movl	(%rbx,%rax,4), %ecx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L19
.L26:
	leaq	.LC5(%rip), %rdx
	movq	%rbp, %rdi
	xorl	%eax, %eax
	incl	%r13d
	movl	$2, %esi
	call	__fprintf_chk@PLT
	jmp	.L17
.L25:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z8updateDBPiPcS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8updateDBPiPcS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

__device__ int getnum(char *queryArray, int &i)
{
    int ans=0;
    while(queryArray[i]==' ' || queryArray[i]=='\t')
        i++;
    while(queryArray[i]<=57 && queryArray[i]>=48)
    {
        ans = ans*10 + (queryArray[i]-'0');
        i++;
    }
    while(queryArray[i]==' ' || queryArray[i]=='\t')
        i++;
    return ans;
}
__global__ void updateDB(int* dB, char* queryArray_GPU, int *queryIndices_GPU, int m, int n, int q)
{
    int id = threadIdx.x + blockIdx.x * blockDim.x;
    if(id < q)
    {
        int base = queryIndices_GPU[id];
        int i=base+3, j, rowno;
        int updval;
        int updcol;
        int colno = getnum(queryArray_GPU, i)-1;      
        int ncomp = getnum(queryArray_GPU, i); 
        int p = getnum(queryArray_GPU, i);
        queryIndices_GPU[id] = i;
        for(rowno = 0; rowno<m; rowno++)
        {
            if(dB[rowno*n + colno] == ncomp)
            {
                i = queryIndices_GPU[id];
                for(j = 0; j<p; j++)
                {
                    i+=1;
                    updcol = getnum(queryArray_GPU, i)-1;
                    updval = getnum(queryArray_GPU, i);
                    if(queryArray_GPU[i]=='-')
                        updval*=(-1);
                    i+=2;
                    atomicAdd(&dB[rowno*n + updcol], updval);
                }
            }
        }
    }
}

int main(int argc, char* argv[])
{
    FILE *inp, *otp;
    inp = fopen(argv[1], "r");
    int m, n, i, j;
    fscanf(inp, "%d", &m);
    fscanf(inp, "%d", &n);
    int *dataBase = (int *) malloc (m*n*sizeof(int));
    for(i=0;i<m*n;++i)
        fscanf(inp, "%d", &dataBase[i]);
    int *dB;
    hipMalloc(&dB,n*m*sizeof(int));
    hipMemcpy(dB,dataBase,n*m*sizeof(int),hipMemcpyHostToDevice);
    int q;
    fscanf(inp, "%d", &q);
    int *queryIndices_CPU = (int *) malloc (q*sizeof(int));
    int *queryIndices_GPU;
    hipMalloc(&queryIndices_GPU, q*sizeof(int));
    char *queryArray_CPU = (char *)malloc(q*300*sizeof(char));
    j=0;
    i=0;
    while(fscanf(inp, "%c", &queryArray_CPU[i]) != EOF)
    {
        if(queryArray_CPU[i] == 'U')
        {
            queryIndices_CPU[j] = i;
            j+=1;
        }
        i+=1;
    }
    char *queryArray_GPU;
    hipMalloc(&queryArray_GPU, (i)*sizeof(char));
    fclose(inp);
    hipMemcpy(queryIndices_GPU,queryIndices_CPU,q*sizeof(int),hipMemcpyHostToDevice);
    hipMemcpy(queryArray_GPU,queryArray_CPU,(i)*sizeof(char),hipMemcpyHostToDevice);
    updateDB<<<2, 1024>>>(dB, queryArray_GPU, queryIndices_GPU, m, n, q);
    hipDeviceSynchronize();
    hipMemcpy(dataBase,dB,n*m*sizeof(int),hipMemcpyDeviceToHost);
    otp = fopen(argv[2], "w");
    for(i=0; i<m; ++i)
    {
        for(j=0; j<n; ++j)
            fprintf(otp, "%d ", dataBase[i*n + j]);
        fprintf(otp, "\n");
    } 
    return 0;
}

	.text
	.file	"A3.hip"
	.globl	_Z23__device_stub__updateDBPiPcS_iii # -- Begin function _Z23__device_stub__updateDBPiPcS_iii
	.type	_Z23__device_stub__updateDBPiPcS_iii,@function
_Z23__device_stub__updateDBPiPcS_iii:   # @_Z23__device_stub__updateDBPiPcS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8updateDBPiPcS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__updateDBPiPcS_iii, .Lfunc_end0-_Z23__device_stub__updateDBPiPcS_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	8(%rsi), %rdi
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %r15
	leaq	16(%rsp), %rbx
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	12(%rsp), %r12
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%rbx), %rax
	movslq	(%r12), %r14
	imulq	%rax, %r14
	movq	%r14, %r12
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	testl	%r14d, %r14d
	jle	.LBB1_4
# %bb.1:                                # %.lr.ph.preheader
	movq	%rbx, %r13
	xorl	%r14d, %r14d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incq	%r14
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %r12
	imulq	%rax, %r12
	addq	$4, %r13
	cmpq	%r12, %r14
	jl	.LBB1_2
# %bb.3:                                # %._crit_edge.loopexit
	shlq	$2, %r12
.LBB1_4:                                # %._crit_edge
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	12(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	20(%rsp), %r13
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%r13), %rbp
	shlq	$2, %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r12
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	(%r13), %rax
	imulq	$300, %rax, %rdi                # imm = 0x12C
	callq	malloc
	movq	%rax, %r13
	movl	$.L.str.2, %esi
	movq	%r15, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	xorl	%ebp, %ebp
	cmpl	$-1, %eax
	je	.LBB1_9
# %bb.5:                                # %.lr.ph51.preheader
	xorl	%r14d, %r14d
.LBB1_6:                                # %.lr.ph51
                                        # =>This Inner Loop Header: Depth=1
	cmpb	$85, (%r13,%rbp)
	jne	.LBB1_8
# %bb.7:                                #   in Loop: Header=BB1_6 Depth=1
	movslq	%r14d, %r14
	movl	%ebp, (%r12,%r14,4)
	incl	%r14d
.LBB1_8:                                #   in Loop: Header=BB1_6 Depth=1
	leaq	1(,%r13), %rdx
	addq	%rbp, %rdx
	incq	%rbp
	movl	$.L.str.2, %esi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$-1, %eax
	jne	.LBB1_6
.LBB1_9:                                # %._crit_edge52
	leaq	48(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	%r15, %rdi
	callq	fclose
	movq	24(%rsp), %rdi
	movslq	20(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	leaq	1022(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_11
# %bb.10:
	movq	32(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	16(%rsp), %ecx
	movl	12(%rsp), %r8d
	movl	20(%rsp), %r9d
	callq	_Z23__device_stub__updateDBPiPcS_iii
.LBB1_11:
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rsi
	movslq	12(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rax                  # 8-byte Reload
	movq	16(%rax), %rdi
	movl	$.L.str.3, %esi
	callq	fopen
	cmpl	$0, 16(%rsp)
	jle	.LBB1_17
# %bb.12:                               # %.preheader.preheader
	movq	%rax, %r14
	xorl	%ebp, %ebp
.LBB1_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_15 Depth 2
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB1_16
# %bb.14:                               # %.lr.ph55.preheader
                                        #   in Loop: Header=BB1_13 Depth=1
	xorl	%r15d, %r15d
.LBB1_15:                               # %.lr.ph55
                                        #   Parent Loop BB1_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebp, %eax
	cltq
	addq	%r15, %rax
	movl	(%rbx,%rax,4), %edx
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	12(%rsp), %eax
	incq	%r15
	cmpl	%eax, %r15d
	jl	.LBB1_15
.LBB1_16:                               # %._crit_edge56
                                        #   in Loop: Header=BB1_13 Depth=1
	movl	$10, %edi
	movq	%r14, %rsi
	callq	fputc@PLT
	incl	%ebp
	cmpl	16(%rsp), %ebp
	jl	.LBB1_13
.LBB1_17:                               # %._crit_edge58
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8updateDBPiPcS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8updateDBPiPcS_iii,@object    # @_Z8updateDBPiPcS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z8updateDBPiPcS_iii
	.p2align	3, 0x0
_Z8updateDBPiPcS_iii:
	.quad	_Z23__device_stub__updateDBPiPcS_iii
	.size	_Z8updateDBPiPcS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%c"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d "
	.size	.L.str.4, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8updateDBPiPcS_iii"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__updateDBPiPcS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8updateDBPiPcS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8updateDBPiPcS_iii    ; -- Begin function _Z8updateDBPiPcS_iii
	.globl	_Z8updateDBPiPcS_iii
	.p2align	8
	.type	_Z8updateDBPiPcS_iii,@function
_Z8updateDBPiPcS_iii:                   ; @_Z8updateDBPiPcS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_107
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, 3, v2
	v_ashrrev_i32_e32 v7, 31, v6
.LBB0_2:                                ; %NodeBlock
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	v_add_co_u32 v4, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
	global_load_u8 v9, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v9
	s_xor_b32 s2, exec_lo, s2
; %bb.3:                                ; %LeafBlock379
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v9
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.4:                                ; %Flow474
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s2
; %bb.5:                                ; %LeafBlock
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v9
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
; %bb.6:                                ; %Flow475
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr6_vgpr7
	s_and_saveexec_b32 s3, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s3
; %bb.7:                                ; %.critedge.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v6, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
	s_xor_b32 s2, exec_lo, -1
; %bb.8:                                ; %Flow476
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s2
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_2
; %bb.9:                                ; %.preheader.i
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u16 v3, v9, 48
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, -1 :: v_dual_and_b32 v3, 0xff, v3
	v_cmpx_gt_u16_e32 10, v3
	s_cbranch_execz .LBB0_13
; %bb.10:                               ; %.lr.ph.i.preheader
	v_add_co_u32 v3, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	v_mov_b32_e32 v7, 0
	s_mov_b32 s2, 0
.LBB0_11:                               ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_sub_nc_u16 v5, v9, 48
	global_load_u8 v9, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, 1
	v_add_nc_u32_e32 v2, 1, v2
	v_and_b32_e32 v8, 0xff, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v10, v9, 48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v7, 10, v[8:9]
	v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v6, 0xff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u16_e64 s0, 9, v6
	s_or_b32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_11
; %bb.12:                               ; %.critedge2.preheader.i.loopexit
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v8, -1, v5
.LBB0_13:                               ; %Flow473
	s_or_b32 exec_lo, exec_lo, s1
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s0, 0
.LBB0_14:                               ; %NodeBlock385
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_mov_b32 s1, 0
	s_mov_b32 s2, exec_lo
	v_add_co_u32 v2, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	global_load_u8 v7, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v7
	s_xor_b32 s2, exec_lo, s2
; %bb.15:                               ; %LeafBlock383
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v7
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.16:                               ; %Flow470
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s2, s2
; %bb.17:                               ; %LeafBlock381
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v7
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
; %bb.18:                               ; %Flow471
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s3, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s3
; %bb.19:                               ; %.critedge4.i
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
	s_xor_b32 s2, exec_lo, -1
; %bb.20:                               ; %Flow472
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s2
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_14
; %bb.21:                               ; %_Z6getnumPcRi.exit.preheader
	s_or_b32 exec_lo, exec_lo, s0
	s_add_u32 s2, s10, 1
	s_addc_u32 s3, s11, 0
	s_mov_b32 s0, 0
.LBB0_22:                               ; %NodeBlock391
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v6, v7
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_mov_b32 s1, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v6
	v_cmpx_lt_i16_e32 31, v4
	s_xor_b32 s6, exec_lo, s6
; %bb.23:                               ; %LeafBlock389
                                        ;   in Loop: Header=BB0_22 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v4
                                        ; implicit-def: $vgpr4
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.24:                               ; %Flow467
                                        ;   in Loop: Header=BB0_22 Depth=1
	s_and_not1_saveexec_b32 s6, s6
; %bb.25:                               ; %LeafBlock387
                                        ;   in Loop: Header=BB0_22 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v4
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s7, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s7
; %bb.26:                               ; %Flow468
                                        ;   in Loop: Header=BB0_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
	s_and_saveexec_b32 s7, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s7
	s_cbranch_execz .LBB0_28
; %bb.27:                               ; %.critedge.i39
                                        ;   in Loop: Header=BB0_22 Depth=1
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_xor_b32 s6, exec_lo, -1
	global_load_u8 v7, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
.LBB0_28:                               ; %Flow469
                                        ;   in Loop: Header=BB0_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s6
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_22
; %bb.29:                               ; %.preheader.i40
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u16 v4, v6, 48
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v4, 0xff, v4
	v_cmpx_gt_u16_e32 10, v4
	s_cbranch_execz .LBB0_33
; %bb.30:                               ; %.lr.ph.i47.preheader
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_mov_b32_e32 v9, 0
	s_mov_b32 s6, 0
.LBB0_31:                               ; %.lr.ph.i47
                                        ; =>This Inner Loop Header: Depth=1
	v_sub_nc_u16 v3, v6, 48
	global_load_u8 v6, v[4:5], off
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[10:11], null, v9, 10, v[3:4]
	v_add_co_u32 v4, vcc_lo, v4, 1
	v_add_nc_u32_e32 v2, 1, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_mov_b32_e32 v9, v10
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v7, v6, 48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xff, v7
	v_cmp_lt_u16_e64 s0, 9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s0, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_31
; %bb.32:                               ; %Flow465
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_33:                               ; %Flow466
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s0, 0
.LBB0_34:                               ; %NodeBlock397
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_mov_b32 s1, 0
	s_mov_b32 s6, exec_lo
	v_add_co_u32 v2, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	global_load_u8 v7, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v7
	s_xor_b32 s6, exec_lo, s6
; %bb.35:                               ; %LeafBlock395
                                        ;   in Loop: Header=BB0_34 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v7
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.36:                               ; %Flow462
                                        ;   in Loop: Header=BB0_34 Depth=1
	s_and_not1_saveexec_b32 s6, s6
; %bb.37:                               ; %LeafBlock393
                                        ;   in Loop: Header=BB0_34 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v7
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s7, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s7
; %bb.38:                               ; %Flow463
                                        ;   in Loop: Header=BB0_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s7, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s7
; %bb.39:                               ; %.critedge4.i46
                                        ;   in Loop: Header=BB0_34 Depth=1
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
	s_xor_b32 s6, exec_lo, -1
; %bb.40:                               ; %Flow464
                                        ;   in Loop: Header=BB0_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s6
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_34
; %bb.41:                               ; %_Z6getnumPcRi.exit51.preheader
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
.LBB0_42:                               ; %NodeBlock403
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v6, v7
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_mov_b32 s1, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v6
	v_cmpx_lt_i16_e32 31, v4
	s_xor_b32 s6, exec_lo, s6
; %bb.43:                               ; %LeafBlock401
                                        ;   in Loop: Header=BB0_42 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v4
                                        ; implicit-def: $vgpr4
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.44:                               ; %Flow459
                                        ;   in Loop: Header=BB0_42 Depth=1
	s_and_not1_saveexec_b32 s6, s6
; %bb.45:                               ; %LeafBlock399
                                        ;   in Loop: Header=BB0_42 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v4
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s7, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s7
; %bb.46:                               ; %Flow460
                                        ;   in Loop: Header=BB0_42 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
	s_and_saveexec_b32 s7, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s7
	s_cbranch_execz .LBB0_48
; %bb.47:                               ; %.critedge.i54
                                        ;   in Loop: Header=BB0_42 Depth=1
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_xor_b32 s6, exec_lo, -1
	global_load_u8 v7, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
.LBB0_48:                               ; %Flow461
                                        ;   in Loop: Header=BB0_42 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s6
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_42
; %bb.49:                               ; %.preheader.i55
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u16 v4, v6, 48
	v_mov_b32_e32 v10, 0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v4
	v_cmpx_gt_u16_e32 10, v4
	s_cbranch_execz .LBB0_53
; %bb.50:                               ; %.lr.ph.i62.preheader
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_mov_b32_e32 v10, 0
	s_mov_b32 s6, 0
.LBB0_51:                               ; %.lr.ph.i62
                                        ; =>This Inner Loop Header: Depth=1
	v_sub_nc_u16 v3, v6, 48
	global_load_u8 v6, v[4:5], off
	v_add_nc_u32_e32 v2, 1, v2
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, v10, 10, v[3:4]
	v_add_co_u32 v4, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_mov_b32_e32 v10, v11
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v7, v6, 48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xff, v7
	v_cmp_lt_u16_e64 s0, 9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s0, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_51
; %bb.52:                               ; %Flow457
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_53:                               ; %Flow458
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s0, 0
.LBB0_54:                               ; %NodeBlock409
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_mov_b32 s1, 0
	s_mov_b32 s6, exec_lo
	v_add_co_u32 v2, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v2
	s_xor_b32 s6, exec_lo, s6
; %bb.55:                               ; %LeafBlock407
                                        ;   in Loop: Header=BB0_54 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 32, v2
                                        ; implicit-def: $vgpr2
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.56:                               ; %Flow454
                                        ;   in Loop: Header=BB0_54 Depth=1
	s_and_not1_saveexec_b32 s6, s6
; %bb.57:                               ; %LeafBlock405
                                        ;   in Loop: Header=BB0_54 Depth=1
	v_cmp_eq_u16_e32 vcc_lo, 9, v2
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s7, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s7
; %bb.58:                               ; %Flow455
                                        ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s7, s1
; %bb.59:                               ; %.critedge4.i61
                                        ;   in Loop: Header=BB0_54 Depth=1
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
	s_xor_b32 s6, exec_lo, -1
; %bb.60:                               ; %Flow456
                                        ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s6
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_54
; %bb.61:                               ; %_Z6getnumPcRi.exit66
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lt_i32 s4, 1
	global_store_b32 v[0:1], v4, off
	s_cbranch_scc1 .LBB0_107
; %bb.62:                               ; %.lr.ph
	v_cmp_gt_i32_e32 vcc_lo, 1, v10
	s_mov_b32 s6, 0
	s_xor_b32 s7, vcc_lo, -1
.LBB0_63:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_65 Depth 2
                                        ;       Child Loop BB0_66 Depth 3
                                        ;       Child Loop BB0_75 Depth 3
                                        ;       Child Loop BB0_78 Depth 3
                                        ;       Child Loop BB0_86 Depth 3
                                        ;       Child Loop BB0_95 Depth 3
                                        ;       Child Loop BB0_98 Depth 3
	s_mul_i32 s13, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s13, v8
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v9
	s_and_b32 s0, vcc_lo, s7
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_106
; %bb.64:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_63 Depth=1
	global_load_b32 v4, v[0:1], off
	s_add_i32 s13, s13, -1
	s_mov_b32 s14, 0
	s_mov_b32 s15, 0
.LBB0_65:                               ; %.preheader
                                        ;   Parent Loop BB0_63 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_66 Depth 3
                                        ;       Child Loop BB0_75 Depth 3
                                        ;       Child Loop BB0_78 Depth 3
                                        ;       Child Loop BB0_86 Depth 3
                                        ;       Child Loop BB0_95 Depth 3
                                        ;       Child Loop BB0_98 Depth 3
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v11, 1, v4
	s_mov_b32 s0, 0
.LBB0_66:                               ; %NodeBlock415
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	v_mov_b32_e32 v7, v11
	s_mov_b32 s1, 0
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	global_load_u8 v6, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v6
	s_xor_b32 s16, exec_lo, s16
; %bb.67:                               ; %LeafBlock413
                                        ;   in Loop: Header=BB0_66 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 32, v6
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.68:                               ; %Flow447
                                        ;   in Loop: Header=BB0_66 Depth=3
	s_and_not1_saveexec_b32 s16, s16
; %bb.69:                               ; %LeafBlock411
                                        ;   in Loop: Header=BB0_66 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 9, v6
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s17
; %bb.70:                               ; %Flow448
                                        ;   in Loop: Header=BB0_66 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s17, s1
; %bb.71:                               ; %.critedge.i69.backedge
                                        ;   in Loop: Header=BB0_66 Depth=3
	v_add_nc_u32_e32 v11, 1, v7
	s_xor_b32 s16, exec_lo, -1
; %bb.72:                               ; %Flow449
                                        ;   in Loop: Header=BB0_66 Depth=3
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s16
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_66
; %bb.73:                               ; %.preheader.i70
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u16 v3, v6, 48
	v_mov_b32_e32 v11, 0
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xff, v3
	v_cmpx_gt_u16_e32 10, v3
	s_cbranch_execz .LBB0_77
; %bb.74:                               ; %.lr.ph.i77.preheader
                                        ;   in Loop: Header=BB0_65 Depth=2
	v_ashrrev_i32_e32 v4, 31, v7
	v_add_co_u32 v3, vcc_lo, s10, v7
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v4, vcc_lo
	s_mov_b32 s17, 0
.LBB0_75:                               ; %.lr.ph.i77
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_co_u32 v12, vcc_lo, v3, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v5, vcc_lo
	v_sub_nc_u16 v4, v6, 48
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	global_load_u8 v6, v[12:13], off
	v_and_b32_e32 v4, 0xff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v11, 10, v[4:5]
	v_mov_b32_e32 v11, v12
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v7, v6, 48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v7
	v_cmp_lt_u16_e32 vcc_lo, 9, v4
	v_add_nc_u32_e32 v4, s0, v2
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_75
; %bb.76:                               ; %Flow445
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
.LBB0_77:                               ; %Flow446
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s0, 0
.LBB0_78:                               ; %NodeBlock421
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_mov_b32 s1, 0
	s_mov_b32 s16, exec_lo
	v_add_co_u32 v2, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
	global_load_u8 v12, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v12
	s_xor_b32 s16, exec_lo, s16
; %bb.79:                               ; %LeafBlock419
                                        ;   in Loop: Header=BB0_78 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 32, v12
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.80:                               ; %Flow442
                                        ;   in Loop: Header=BB0_78 Depth=3
	s_and_not1_saveexec_b32 s16, s16
; %bb.81:                               ; %LeafBlock417
                                        ;   in Loop: Header=BB0_78 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 9, v12
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s17
; %bb.82:                               ; %Flow443
                                        ;   in Loop: Header=BB0_78 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr4_vgpr5
	s_and_saveexec_b32 s17, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s17
; %bb.83:                               ; %.critedge4.i76
                                        ;   in Loop: Header=BB0_78 Depth=3
	v_add_co_u32 v4, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
	s_xor_b32 s16, exec_lo, -1
; %bb.84:                               ; %Flow444
                                        ;   in Loop: Header=BB0_78 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s16
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_78
; %bb.85:                               ; %_Z6getnumPcRi.exit81.preheader
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
.LBB0_86:                               ; %NodeBlock427
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v5, v12 :: v_dual_mov_b32 v2, v6
	v_mov_b32_e32 v3, v7
	s_mov_b32 s1, 0
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v5
	v_cmpx_lt_i16_e32 31, v4
	s_xor_b32 s16, exec_lo, s16
; %bb.87:                               ; %LeafBlock425
                                        ;   in Loop: Header=BB0_86 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 32, v4
                                        ; implicit-def: $vgpr4
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.88:                               ; %Flow439
                                        ;   in Loop: Header=BB0_86 Depth=3
	s_and_not1_saveexec_b32 s16, s16
; %bb.89:                               ; %LeafBlock423
                                        ;   in Loop: Header=BB0_86 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 9, v4
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s17
; %bb.90:                               ; %Flow440
                                        ;   in Loop: Header=BB0_86 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr6_vgpr7
	s_and_saveexec_b32 s17, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s17
	s_cbranch_execz .LBB0_92
; %bb.91:                               ; %.critedge.i84
                                        ;   in Loop: Header=BB0_86 Depth=3
	v_add_co_u32 v6, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
	s_xor_b32 s16, exec_lo, -1
	global_load_u8 v12, v[6:7], off
	v_add_co_u32 v6, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
.LBB0_92:                               ; %Flow441
                                        ;   in Loop: Header=BB0_86 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s16
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_86
; %bb.93:                               ; %.preheader.i85
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u16 v4, v5, 48
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xff, v4
	v_cmp_gt_u16_e32 vcc_lo, 10, v4
	v_mov_b32_e32 v4, v2
	s_and_saveexec_b32 s16, vcc_lo
	s_cbranch_execz .LBB0_97
; %bb.94:                               ; %.lr.ph.i92.preheader
                                        ;   in Loop: Header=BB0_65 Depth=2
	v_add_co_u32 v7, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_mov_b32_e32 v6, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s17, 0
.LBB0_95:                               ; %.lr.ph.i92
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v7, s0
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v3, vcc_lo
	v_sub_nc_u16 v4, v5, 48
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	global_load_u8 v5, v[12:13], off offset:1
	v_and_b32_e32 v4, 0xff, v4
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v14, v5, 48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, v6, 10, v[4:5]
	v_and_b32_e32 v4, 0xff, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v6, v12
	v_cmp_lt_u16_e32 vcc_lo, 9, v4
	v_add_nc_u32_e32 v4, s0, v2
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_95
; %bb.96:                               ; %Flow437
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
.LBB0_97:                               ; %Flow438
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s16
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s0, 0
.LBB0_98:                               ; %NodeBlock433
                                        ;   Parent Loop BB0_63 Depth=1
                                        ;     Parent Loop BB0_65 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_mov_b32 s1, 0
	s_mov_b32 s16, exec_lo
	v_add_co_u32 v4, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
	global_load_u8 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 31, v7
	s_xor_b32 s16, exec_lo, s16
; %bb.99:                               ; %LeafBlock431
                                        ;   in Loop: Header=BB0_98 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 32, v7
	s_and_b32 s1, vcc_lo, exec_lo
; %bb.100:                              ; %Flow
                                        ;   in Loop: Header=BB0_98 Depth=3
	s_and_not1_saveexec_b32 s16, s16
; %bb.101:                              ; %LeafBlock429
                                        ;   in Loop: Header=BB0_98 Depth=3
	v_cmp_eq_u16_e32 vcc_lo, 9, v7
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s17
; %bb.102:                              ; %Flow435
                                        ;   in Loop: Header=BB0_98 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr4_vgpr5
	s_and_saveexec_b32 s17, s1
; %bb.103:                              ; %.critedge4.i91
                                        ;   in Loop: Header=BB0_98 Depth=3
	v_add_co_u32 v4, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_xor_b32 s16, exec_lo, -1
; %bb.104:                              ; %Flow436
                                        ;   in Loop: Header=BB0_98 Depth=3
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s16
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_98
; %bb.105:                              ; %_Z6getnumPcRi.exit96
                                        ;   in Loop: Header=BB0_65 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, s13, v11
	v_sub_nc_u32_e32 v5, 0, v6
	v_cmp_eq_u16_e32 vcc_lo, 45, v7
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_cndmask_b32_e32 v5, v6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s15, v10
	global_atomic_add_u32 v[3:4], v5, off
	v_add_nc_u32_e32 v4, 2, v2
	s_or_b32 s14, vcc_lo, s14
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_65
.LBB0_106:                              ; %Flow451
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s6, s4
	s_cbranch_scc1 .LBB0_63
.LBB0_107:                              ; %.loopexit106
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8updateDBPiPcS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8updateDBPiPcS_iii, .Lfunc_end0-_Z8updateDBPiPcS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2928
; NumSgprs: 20
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8updateDBPiPcS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z8updateDBPiPcS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
