/* 
Implementing Sparse Matrix Vector multiplication (SpMV) in CUDA with one thread per row.
The matrix uses a Compressed Sparse Row (CSR) representation.
*/

#include <stdio.h>
#define MATRIX_SIZE 4
#define NON_ZERO_ELEMENTS 6
#define NUM_BLOCKS 2
#define NUM_THREADS 2

void print_vector(int* array){
    for(unsigned int i = 0; i < MATRIX_SIZE; i++){
            printf("%d ", array[i]);
    }
}

__global__ void spmv(const int* value, const int* index, const int* row_ptr, int* d_in, int* d_out){
    const unsigned int row = threadIdx.x + blockIdx.x * blockDim.x;

    if(row < MATRIX_SIZE){
        int start_row = row_ptr[row];
        int end_row;

        // Fixing special case for the last row
        if(row == MATRIX_SIZE - 1){
            end_row = NON_ZERO_ELEMENTS;
        }else{
            end_row = row_ptr[row + 1];
        }

        int sum = 0;
        for(unsigned int i = start_row; i < end_row; i++){
            sum += value[i] * d_in[index[i]];
        }
        d_out[row] = sum;
    }
}

int main(){
    const unsigned int MATRIX_BYTES = MATRIX_SIZE * sizeof(int);
    const unsigned int ELEMENT_BYTES = NON_ZERO_ELEMENTS * sizeof(int);

    // CSR definition
    int h_value[NON_ZERO_ELEMENTS] = {1, -3, 2, 5, -2, 7};
    int h_index[NON_ZERO_ELEMENTS] = {0, 2, 1, 0, 2, 3};
    int h_row_ptr[MATRIX_SIZE] = {0, 2, 3, 5};

    int* d_value;
    int* d_index;
    int* d_row_ptr;

    cudaMalloc((void **) &d_value, ELEMENT_BYTES);
    cudaMalloc((void **) &d_index, ELEMENT_BYTES);
    cudaMalloc((void **) &d_row_ptr, MATRIX_BYTES);

    cudaMemcpy(d_value, h_value, ELEMENT_BYTES, cudaMemcpyHostToDevice);
    cudaMemcpy(d_index, h_index, ELEMENT_BYTES, cudaMemcpyHostToDevice);
    cudaMemcpy(d_row_ptr, h_row_ptr, MATRIX_BYTES, cudaMemcpyHostToDevice);

    // The vector
    int h_in[MATRIX_SIZE] = {1, 1, 1, 1};
    int h_out[MATRIX_SIZE];

    int* d_in;
    int* d_out;
    
    cudaMalloc((void **) &d_in, MATRIX_BYTES);
    cudaMalloc((void **) &d_out, MATRIX_BYTES);

    cudaMemcpy(d_in, h_in, MATRIX_BYTES, cudaMemcpyHostToDevice);
    spmv<<<NUM_BLOCKS, NUM_THREADS>>>(d_value, d_index, d_row_ptr, d_in, d_out);
    cudaMemcpy(h_out, d_out, MATRIX_BYTES, cudaMemcpyDeviceToHost);

    print_vector(h_out);

    cudaFree(d_value);
    cudaFree(d_index);
    cudaFree(d_row_ptr);
    cudaFree(d_in);
    cudaFree(d_out);
    return 0;
}

	.file	"tmpxft_002eaf73_00000000-6_spmv.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
	.text
	.globl	_Z12print_vectorPi
	.type	_Z12print_vectorPi, @function
_Z12print_vectorPi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L3:
	movl	0(%rbp,%rbx,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$4, %rbx
	jne	.L3
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12print_vectorPi, .-_Z12print_vectorPi
	.globl	_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_
	.type	_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_, @function
_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z4spmvPKiS0_S0_PiS1_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L7:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_, .-_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_
	.globl	_Z4spmvPKiS0_S0_PiS1_
	.type	_Z4spmvPKiS0_S0_PiS1_, @function
_Z4spmvPKiS0_S0_PiS1_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_
	.cfi_endproc
.LFE2054:
	.size	_Z4spmvPKiS0_S0_PiS1_, .-_Z4spmvPKiS0_S0_PiS1_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$24, %esi
	movabsq	$12884901890, %rbx
	subq	$176, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	movabsq	$-12884901887, %rax
	leaq	8(%rsp), %rdi
	movq	%rbx, 160(%rsp)
	movq	$1, 152(%rsp)
	movq	%rax, 120(%rsp)
	movabsq	$21474836482, %rax
	movq	%rax, 128(%rsp)
	movabsq	$34359738366, %rax
	movq	%rax, 136(%rsp)
	movl	$1, %eax
	salq	$33, %rax
	movq	%rax, 144(%rsp)
	movq	%rax, 72(%rsp)
	movabsq	$21474836483, %rax
	movq	%rax, 80(%rsp)
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$24, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	leaq	120(%rsp), %rsi
	movl	$1, %ecx
	movl	$24, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	leaq	144(%rsp), %rsi
	movl	$24, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$16, %edx
	leaq	72(%rsp), %rsi
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movl	$16, %esi
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 96(%rsp)
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	leaq	88(%rsp), %rsi
	movl	$1, %ecx
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movl	$2147483649, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdi, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z35__device_stub__Z4spmvPKiS0_S0_PiS1_PKiS0_S0_PiS1_
.L13:
	movq	40(%rsp), %rsi
	leaq	104(%rsp), %rbx
	movl	$2, %ecx
	movl	$16, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	%rbx, %rdi
	call	_Z12print_vectorPi
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$176, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z4spmvPKiS0_S0_PiS1_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4spmvPKiS0_S0_PiS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
Implementing Sparse Matrix Vector multiplication (SpMV) in CUDA with one thread per row.
The matrix uses a Compressed Sparse Row (CSR) representation.
*/


#include <hip/hip_runtime.h>
#include <stdio.h>
#define MATRIX_SIZE 4
#define NON_ZERO_ELEMENTS 6
#define NUM_BLOCKS 2
#define NUM_THREADS 2

void print_vector(int* array){
    for(unsigned int i = 0; i < MATRIX_SIZE; i++){
            printf("%d ", array[i]);
    }
}

__global__ void spmv(const int* value, const int* index, const int* row_ptr, int* d_in, int* d_out){
    const unsigned int row = threadIdx.x + blockIdx.x * blockDim.x;

    if(row < MATRIX_SIZE){
        int start_row = row_ptr[row];
        int end_row;

        // Fixing special case for the last row
        if(row == MATRIX_SIZE - 1){
            end_row = NON_ZERO_ELEMENTS;
        }else{
            end_row = row_ptr[row + 1];
        }

        int sum = 0;
        for(unsigned int i = start_row; i < end_row; i++){
            sum += value[i] * d_in[index[i]];
        }
        d_out[row] = sum;
    }
}

int main(){
    const unsigned int MATRIX_BYTES = MATRIX_SIZE * sizeof(int);
    const unsigned int ELEMENT_BYTES = NON_ZERO_ELEMENTS * sizeof(int);

    // CSR definition
    int h_value[NON_ZERO_ELEMENTS] = {1, -3, 2, 5, -2, 7};
    int h_index[NON_ZERO_ELEMENTS] = {0, 2, 1, 0, 2, 3};
    int h_row_ptr[MATRIX_SIZE] = {0, 2, 3, 5};

    int* d_value;
    int* d_index;
    int* d_row_ptr;

    hipMalloc((void **) &d_value, ELEMENT_BYTES);
    hipMalloc((void **) &d_index, ELEMENT_BYTES);
    hipMalloc((void **) &d_row_ptr, MATRIX_BYTES);

    hipMemcpy(d_value, h_value, ELEMENT_BYTES, hipMemcpyHostToDevice);
    hipMemcpy(d_index, h_index, ELEMENT_BYTES, hipMemcpyHostToDevice);
    hipMemcpy(d_row_ptr, h_row_ptr, MATRIX_BYTES, hipMemcpyHostToDevice);

    // The vector
    int h_in[MATRIX_SIZE] = {1, 1, 1, 1};
    int h_out[MATRIX_SIZE];

    int* d_in;
    int* d_out;
    
    hipMalloc((void **) &d_in, MATRIX_BYTES);
    hipMalloc((void **) &d_out, MATRIX_BYTES);

    hipMemcpy(d_in, h_in, MATRIX_BYTES, hipMemcpyHostToDevice);
    spmv<<<NUM_BLOCKS, NUM_THREADS>>>(d_value, d_index, d_row_ptr, d_in, d_out);
    hipMemcpy(h_out, d_out, MATRIX_BYTES, hipMemcpyDeviceToHost);

    print_vector(h_out);

    hipFree(d_value);
    hipFree(d_index);
    hipFree(d_row_ptr);
    hipFree(d_in);
    hipFree(d_out);
    return 0;
}

	.text
	.file	"spmv.hip"
	.globl	_Z12print_vectorPi              # -- Begin function _Z12print_vectorPi
	.type	_Z12print_vectorPi,@function
_Z12print_vectorPi:                     # @_Z12print_vectorPi
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	xorl	%r14d, %r14d
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$4, %r14
	jne	.LBB0_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z12print_vectorPi, .Lfunc_end0-_Z12print_vectorPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__spmvPKiS0_S0_PiS1_ # -- Begin function _Z19__device_stub__spmvPKiS0_S0_PiS1_
	.type	_Z19__device_stub__spmvPKiS0_S0_PiS1_,@function
_Z19__device_stub__spmvPKiS0_S0_PiS1_:  # @_Z19__device_stub__spmvPKiS0_S0_PiS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4spmvPKiS0_S0_PiS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__spmvPKiS0_S0_PiS1_, .Lfunc_end1-_Z19__device_stub__spmvPKiS0_S0_PiS1_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	1                               # 0x1
	.long	4294967293                      # 0xfffffffd
	.long	2                               # 0x2
	.long	5                               # 0x5
.LCPI2_1:
	.long	0                               # 0x0
	.long	2                               # 0x2
	.long	1                               # 0x1
	.long	0                               # 0x0
.LCPI2_2:
	.long	0                               # 0x0
	.long	2                               # 0x2
	.long	3                               # 0x3
	.long	5                               # 0x5
.LCPI2_3:
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	1                               # 0x1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [1,4294967293,2,5]
	leaq	128(%rsp), %r15
	movaps	%xmm0, (%r15)
	movabsq	$34359738366, %rax              # imm = 0x7FFFFFFFE
	movq	%rax, 16(%r15)
	movaps	.LCPI2_1(%rip), %xmm0           # xmm0 = [0,2,1,0]
	leaq	96(%rsp), %r14
	movaps	%xmm0, (%r14)
	movabsq	$12884901890, %rax              # imm = 0x300000002
	movq	%rax, 16(%r14)
	movaps	.LCPI2_2(%rip), %xmm0           # xmm0 = [0,2,3,5]
	leaq	80(%rsp), %rbx
	movaps	%xmm0, (%rbx)
	leaq	40(%rsp), %r12
	movl	$24, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r13
	movl	$24, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rbp
	movl	$16, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$24, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$24, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$16, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movaps	.LCPI2_3(%rip), %xmm0           # xmm0 = [1,1,1,1]
	leaq	64(%rsp), %rbx
	movaps	%xmm0, (%rbx)
	leaq	16(%rsp), %r14
	movl	$16, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$16, %esi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$16, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	callq	_Z19__device_stub__spmvPKiS0_S0_PiS1_
.LBB2_2:
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	movl	$16, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movl	48(%rsp,%rbx,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$4, %rbx
	jne	.LBB2_3
# %bb.4:                                # %_Z12print_vectorPi.exit
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4spmvPKiS0_S0_PiS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	_Z4spmvPKiS0_S0_PiS1_,@object   # @_Z4spmvPKiS0_S0_PiS1_
	.section	.rodata,"a",@progbits
	.globl	_Z4spmvPKiS0_S0_PiS1_
	.p2align	3, 0x0
_Z4spmvPKiS0_S0_PiS1_:
	.quad	_Z19__device_stub__spmvPKiS0_S0_PiS1_
	.size	_Z4spmvPKiS0_S0_PiS1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4spmvPKiS0_S0_PiS1_"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__spmvPKiS0_S0_PiS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4spmvPKiS0_S0_PiS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4spmvPKiS0_S0_PiS1_   ; -- Begin function _Z4spmvPKiS0_S0_PiS1_
	.globl	_Z4spmvPKiS0_S0_PiS1_
	.p2align	8
	.type	_Z4spmvPKiS0_S0_PiS1_,@function
_Z4spmvPKiS0_S0_PiS1_:                  ; @_Z4spmvPKiS0_S0_PiS1_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 4, v4
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v8, 6
	s_load_b64 s[2:3], s[0:1], 0x20
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v3
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_cmpx_ne_u32_e32 3, v4
	s_cbranch_execz .LBB0_3
; %bb.2:
	global_load_b32 v8, v[5:6], off offset:4
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e64 v2, v8
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s4, 0
.LBB0_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s10, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	global_load_b32 v11, v[4:5], off
	global_load_b32 v12, v[9:10], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v12, v11, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v9 :: v_dual_add_nc_u32 v2, 1, v2
	v_cmp_ge_u32_e64 s0, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s0, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:                                ; %Flow46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4spmvPKiS0_S0_PiS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4spmvPKiS0_S0_PiS1_, .Lfunc_end0-_Z4spmvPKiS0_S0_PiS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4spmvPKiS0_S0_PiS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4spmvPKiS0_S0_PiS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
