/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <cuda.h>
#include <cuda_runtime.h>

namespace nvinfer1
{
namespace plugin
{
template <typename T>
__global__ void cropAndResizeKernel(const int nthreads, const T* image_ptr, const float* boxes_ptr,
                                    int num_boxes, int batch, int image_height, int image_width,
                                    int crop_height, int crop_width, int depth,
                                    float extrapolation_value, float* crops_ptr)
{
    for (int out_idx = threadIdx.x + blockIdx.x * blockDim.x ; out_idx < nthreads;
            out_idx += blockDim.x * gridDim.x)
    {
        int idx =  out_idx;
        const int x = idx % crop_width;
        idx /= crop_width;
        const int y = idx % crop_height;
        idx /= crop_height;
        const int d = idx % depth;
        const int b = idx / depth;
        const float y1 = boxes_ptr[b * 4];
        const float x1 = boxes_ptr[b * 4 + 1];
        const float y2 = boxes_ptr[b * 4 + 2];
        const float x2 = boxes_ptr[b * 4 + 3];
        //each image has num_boxes of boxes, so we simply divide to get the box index.
        const int b_in = b / num_boxes;

        if (b_in < 0 || b_in >= batch)
        {
            continue;
        }

        const float height_scale =
            (crop_height > 1) ? (y2 - y1) * (image_height - 1) / (crop_height - 1)
            : 0;
        const float width_scale =
            (crop_width > 1) ? (x2 - x1) * (image_width - 1) / (crop_width - 1) : 0;
        const float in_y = (crop_height > 1)
                            ? y1 * (image_height - 1) + y * height_scale
                            : 0.5 * (y1 + y2) * (image_height - 1);

        if (in_y < 0 || in_y > image_height - 1)
        {
            crops_ptr[out_idx] = extrapolation_value;
            continue;
        }

        const float in_x = (crop_width > 1)
                           ? x1 * (image_width - 1) + x * width_scale
                           : 0.5 * (x1 + x2) * (image_width - 1);

        if (in_x < 0 || in_x > image_width - 1)
        {
            crops_ptr[out_idx] = extrapolation_value;
            continue;
        }

        const int top_y_index = floorf(in_y);
        const int bottom_y_index = ceilf(in_y);
        const float y_lerp = in_y - top_y_index;
        const int left_x_index = floorf(in_x);
        const int right_x_index = ceilf(in_x);
        const float x_lerp = in_x - left_x_index;
        const float top_left(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               top_y_index) *
                                               image_width +
                                               left_x_index]));
        const float top_right(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                                top_y_index) *
                                                image_width +
                                                right_x_index]));
        const float bottom_left(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               bottom_y_index) *
                                               image_width +
                                               left_x_index]));
        const float bottom_right(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               bottom_y_index) *
                                               image_width +
                                               right_x_index]));
        const float top = top_left + (top_right - top_left) * x_lerp;
        const float bottom = bottom_left + (bottom_right - bottom_left) * x_lerp;
        crops_ptr[out_idx] = top + (bottom - top) * y_lerp;
    }
}





int cropAndResizeInference(
    cudaStream_t stream,
    int n,
    const void* image,
    const void* rois,
    int batch_size,
    int input_height,
    int input_width,
    int num_boxes,
    int crop_height,
    int crop_width,
    int depth,
    void* output)
{
    int output_volume = batch_size * num_boxes * crop_height * crop_width * depth;
    int block_size = 1024;
    int grid_size = (output_volume + block_size - 1 ) / block_size;
    cropAndResizeKernel<float> <<< grid_size, block_size, 0, stream>>>(output_volume,
            static_cast<const float*>(image),
            static_cast<const float*>(rois),
            num_boxes,
            batch_size,
            input_height,
            input_width,
            crop_height,
            crop_width,
            depth,
            0.0f,
            static_cast<float*>(output));
    return 0;
}
} // namespace plugin
} // namespace nvinfer1

	.file	"tmpxft_0023ed1e_00000000-6_cropAndResizeKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf, @function
_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf:
.LFB2035:
	.cfi_startproc
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	272(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movl	%r9d, 16(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf, .-_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf
	.section	.text._ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,"axG",@progbits,_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,comdat
	.weak	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.type	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, @function
_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf:
.LFB2084:
	.cfi_startproc
	endbr64
	jmp	_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf
	.cfi_endproc
.LFE2084:
	.size	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, .-_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.text
	.globl	_ZN8nvinfer16plugin22cropAndResizeInferenceEP11CUstream_stiPKvS4_iiiiiiiPv
	.type	_ZN8nvinfer16plugin22cropAndResizeInferenceEP11CUstream_stiPKvS4_iiiiiiiPv, @function
_ZN8nvinfer16plugin22cropAndResizeInferenceEP11CUstream_stiPKvS4_iiiiiiiPv:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	movq	%rdi, %r9
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	movl	$1024, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	120(%rsp), %r10d
	movl	128(%rsp), %r13d
	movq	%rdx, (%rsp)
	movl	136(%rsp), %r14d
	movl	144(%rsp), %r15d
	imull	%r8d, %r10d
	xorl	%r8d, %r8d
	imull	%r13d, %r10d
	imull	%r14d, %r10d
	imull	%r15d, %r10d
	leal	1023(%r10), %eax
	movl	%r10d, 12(%rsp)
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movl	12(%rsp), %r10d
	testl	%eax, %eax
	jne	.L9
	pushq	%rax
	.cfi_def_cfa_offset 120
	xorps	%xmm0, %xmm0
	movl	%r12d, %r9d
	movl	%ebx, %r8d
	pushq	160(%rsp)
	.cfi_def_cfa_offset 128
	movq	%rbp, %rdx
	movl	%r10d, %edi
	pushq	%r15
	.cfi_def_cfa_offset 136
	pushq	%r14
	.cfi_def_cfa_offset 144
	pushq	%r13
	.cfi_def_cfa_offset 152
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 160
	movl	168(%rsp), %ecx
	movq	48(%rsp), %rsi
	call	_ZL77__device_stub__ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPfiPKfS0_iiiiiiifPf
	addq	$48, %rsp
	.cfi_def_cfa_offset 112
.L9:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	_ZN8nvinfer16plugin22cropAndResizeInferenceEP11CUstream_stiPKvS4_iiiiiiiPv, .-_ZN8nvinfer16plugin22cropAndResizeInferenceEP11CUstream_stiPKvS4_iiiiiiiPv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <hip/hip_runtime.h>


namespace nvinfer1
{
namespace plugin
{
template <typename T>
__global__ void cropAndResizeKernel(const int nthreads, const T* image_ptr, const float* boxes_ptr,
                                    int num_boxes, int batch, int image_height, int image_width,
                                    int crop_height, int crop_width, int depth,
                                    float extrapolation_value, float* crops_ptr)
{
    for (int out_idx = threadIdx.x + blockIdx.x * blockDim.x ; out_idx < nthreads;
            out_idx += blockDim.x * gridDim.x)
    {
        int idx =  out_idx;
        const int x = idx % crop_width;
        idx /= crop_width;
        const int y = idx % crop_height;
        idx /= crop_height;
        const int d = idx % depth;
        const int b = idx / depth;
        const float y1 = boxes_ptr[b * 4];
        const float x1 = boxes_ptr[b * 4 + 1];
        const float y2 = boxes_ptr[b * 4 + 2];
        const float x2 = boxes_ptr[b * 4 + 3];
        //each image has num_boxes of boxes, so we simply divide to get the box index.
        const int b_in = b / num_boxes;

        if (b_in < 0 || b_in >= batch)
        {
            continue;
        }

        const float height_scale =
            (crop_height > 1) ? (y2 - y1) * (image_height - 1) / (crop_height - 1)
            : 0;
        const float width_scale =
            (crop_width > 1) ? (x2 - x1) * (image_width - 1) / (crop_width - 1) : 0;
        const float in_y = (crop_height > 1)
                            ? y1 * (image_height - 1) + y * height_scale
                            : 0.5 * (y1 + y2) * (image_height - 1);

        if (in_y < 0 || in_y > image_height - 1)
        {
            crops_ptr[out_idx] = extrapolation_value;
            continue;
        }

        const float in_x = (crop_width > 1)
                           ? x1 * (image_width - 1) + x * width_scale
                           : 0.5 * (x1 + x2) * (image_width - 1);

        if (in_x < 0 || in_x > image_width - 1)
        {
            crops_ptr[out_idx] = extrapolation_value;
            continue;
        }

        const int top_y_index = floorf(in_y);
        const int bottom_y_index = ceilf(in_y);
        const float y_lerp = in_y - top_y_index;
        const int left_x_index = floorf(in_x);
        const int right_x_index = ceilf(in_x);
        const float x_lerp = in_x - left_x_index;
        const float top_left(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               top_y_index) *
                                               image_width +
                                               left_x_index]));
        const float top_right(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                                top_y_index) *
                                                image_width +
                                                right_x_index]));
        const float bottom_left(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               bottom_y_index) *
                                               image_width +
                                               left_x_index]));
        const float bottom_right(static_cast<float>(
                                     image_ptr[((b_in * depth + d) * image_height +
                                               bottom_y_index) *
                                               image_width +
                                               right_x_index]));
        const float top = top_left + (top_right - top_left) * x_lerp;
        const float bottom = bottom_left + (bottom_right - bottom_left) * x_lerp;
        crops_ptr[out_idx] = top + (bottom - top) * y_lerp;
    }
}





int cropAndResizeInference(
    hipStream_t stream,
    int n,
    const void* image,
    const void* rois,
    int batch_size,
    int input_height,
    int input_width,
    int num_boxes,
    int crop_height,
    int crop_width,
    int depth,
    void* output)
{
    int output_volume = batch_size * num_boxes * crop_height * crop_width * depth;
    int block_size = 1024;
    int grid_size = (output_volume + block_size - 1 ) / block_size;
    cropAndResizeKernel<float> <<< grid_size, block_size, 0, stream>>>(output_volume,
            static_cast<const float*>(image),
            static_cast<const float*>(rois),
            num_boxes,
            batch_size,
            input_height,
            input_width,
            crop_height,
            crop_width,
            depth,
            0.0f,
            static_cast<float*>(output));
    return 0;
}
} // namespace plugin
} // namespace nvinfer1

	.text
	.file	"cropAndResizeKernel.hip"
	.globl	_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv # -- Begin function _ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv
	.type	_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv,@function
_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv: # @_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rdi, %r9
	movl	96(%rsp), %edx
	movl	88(%rsp), %ecx
	movl	80(%rsp), %r13d
	movl	72(%rsp), %r12d
	movl	%r12d, %eax
	imull	%r8d, %eax
                                        # kill: def $r13d killed $r13d killed $r13 def $r13
	imull	%ecx, %r13d
	imull	%eax, %r13d
	imull	%edx, %r13d
	leal	1023(%r13), %eax
	leal	2046(%r13), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movl	64(%rsp), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	xorps	%xmm0, %xmm0
	movl	%r13d, %edi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%r12d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	movl	112(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	movl	112(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	movl	112(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB0_2:
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv, .Lfunc_end0-_ZN8nvinfer16plugin22cropAndResizeInferenceEP12ihipStream_tiPKvS4_iiiiiiiPv
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,"axG",@progbits,_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,comdat
	.weak	_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf # -- Begin function _ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.type	_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,@function
_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf: # @_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, .Lfunc_end1-_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,@object # @_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.section	.rodata._ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,"aG",@progbits,_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,comdat
	.weak	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.p2align	3, 0x0
_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf:
	.quad	_ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.size	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf"
	.size	.L__unnamed_1, 64

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN8nvinfer16plugin34__device_stub__cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,"axG",@progbits,_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,comdat
	.protected	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf ; -- Begin function _ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.globl	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
	.p2align	8
	.type	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,@function
_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf: ; @_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b32 s16, s[0:1], 0x0
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s28, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[4:5], null, s15, s28, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s16, v4
	s_cbranch_execz .LBB0_23
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b32 s31, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s8, 1
	s_cselect_b32 s17, -1, 0
	s_cmp_lt_i32 s8, 2
	s_cselect_b32 s18, -1, 0
	s_add_i32 s29, s6, -1
	s_add_i32 s30, s8, -1
	s_cmp_gt_i32 s9, 1
	v_cvt_f64_i32_e32 v[6:7], s29
	s_cselect_b32 s19, -1, 0
	s_cmp_lt_i32 s9, 2
	v_cvt_f32_i32_e32 v12, s29
	s_cselect_b32 s20, -1, 0
	s_ashr_i32 s21, s9, 31
	s_ashr_i32 s22, s8, 31
	s_ashr_i32 s23, s10, 31
	s_ashr_i32 s24, s4, 31
	s_add_i32 s12, s9, s21
	s_add_i32 s13, s8, s22
	s_add_i32 s14, s10, s23
	s_add_i32 s15, s4, s24
	s_xor_b32 s4, s12, s21
	s_xor_b32 s25, s13, s22
	s_xor_b32 s26, s14, s23
	s_xor_b32 s27, s15, s24
	v_cvt_f32_u32_e32 v0, s4
	v_cvt_f32_u32_e32 v1, s25
	v_cvt_f32_u32_e32 v2, s26
	v_cvt_f32_u32_e32 v3, s27
	s_add_i32 s33, s7, -1
	v_rcp_iflag_f32_e32 v0, v0
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	v_cvt_f64_i32_e32 v[8:9], s33
	s_sub_i32 s2, 0, s4
	s_sub_i32 s3, 0, s25
	s_sub_i32 s12, 0, s26
	s_sub_i32 s13, 0, s27
	v_cvt_f32_i32_e32 v14, s33
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v5, s2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v10, s3, v1
	v_mul_lo_u32 v11, s12, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v13, s13, v3
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x38
	s_add_i32 s0, s9, -1
	s_mul_i32 s1, s31, s28
	v_cvt_f32_i32_e32 v15, s0
	v_mul_hi_u32 v5, v0, v5
	v_mul_hi_u32 v10, v1, v10
	v_mul_hi_u32 v11, v2, v11
	v_mul_hi_u32 v19, v3, v13
	v_cvt_f32_i32_e32 v13, s30
	s_mov_b32 s28, 0
	s_sub_i32 s9, 0, s9
	v_add_nc_u32_e32 v16, v0, v5
	v_add_nc_u32_e32 v17, v1, v10
	v_add_nc_u32_e32 v18, v2, v11
	v_add_nc_u32_e32 v19, v3, v19
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v4, v5
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v16
	v_mul_lo_u32 v2, v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v2
	v_add_nc_u32_e32 v2, 1, v1
	v_subrev_nc_u32_e32 v3, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v2 :: v_dual_cndmask_b32 v0, v0, v3
	v_xor_b32_e32 v3, s21, v5
	v_add_nc_u32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	v_cndmask_b32_e32 v0, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v21, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v21
	v_add_nc_u32_e32 v1, v21, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v0
	v_xor_b32_e32 v0, s22, v0
	v_mul_hi_u32 v2, v1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v2, s25
	v_sub_nc_u32_e32 v1, v1, v3
	v_add_nc_u32_e32 v3, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v10, s25, v1
	v_cmp_le_u32_e32 vcc_lo, s25, v1
	v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s25, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	v_xor_b32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, v1, v0
	v_ashrrev_i32_e32 v0, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v20, v0
	v_xor_b32_e32 v1, v1, v0
	v_xor_b32_e32 v0, s23, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v18
	v_mul_lo_u32 v3, v2, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v3
	v_add_nc_u32_e32 v3, 1, v2
	v_subrev_nc_u32_e32 v10, s26, v1
	v_cmp_le_u32_e32 vcc_lo, s26, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v10
	v_add_nc_u32_e32 v3, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s26, v1
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v22, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v22
	v_add_nc_u32_e32 v1, v22, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v0
	v_xor_b32_e32 v0, s24, v0
	v_mul_hi_u32 v2, v1, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v2, s27
	v_sub_nc_u32_e32 v1, v1, v3
	v_add_nc_u32_e32 v3, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v10, s27, v1
	v_cmp_le_u32_e32 vcc_lo, s27, v1
	v_dual_cndmask_b32 v2, v2, v3 :: v_dual_cndmask_b32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s27, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	v_xor_b32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, v1, v0
	v_cmp_lt_i32_e32 vcc_lo, -1, v23
	v_cmp_gt_i32_e64 s0, s5, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s29, s0
	s_cbranch_execz .LBB0_22
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v25, 0 :: v_dual_lshlrev_b32 v0, 2, v22
	v_mov_b32_e32 v24, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s17
	global_load_b128 v[0:3], v[0:1], off
	s_cbranch_vccnz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v10, v12
	v_div_scale_f32 v11, null, v13, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v11, v25, 1.0
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v10, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	v_fma_f32 v28, -v11, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v25
	v_fma_f32 v11, -v11, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v25, v27
	v_div_fixup_f32 v25, v11, v13, v10
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v10, v14
	v_div_scale_f32 v11, null, v15, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v11, v24, 1.0
	v_fmac_f32_e32 v24, v26, v24
	v_div_scale_f32 v26, vcc_lo, v10, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v24
	v_fma_f32 v28, -v11, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v24
	v_fma_f32 v11, -v11, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v24, v27
	v_div_fixup_f32 v24, v11, v15, v10
.LBB0_7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v0, v2
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[10:11], v2
	v_mul_f64 v[10:11], v[10:11], 0.5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], v[6:7]
	s_branch .LBB0_10
.LBB0_9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr10_vgpr11
.LBB0_10:                               ; %Flow172
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v20, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v21, v2
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v25, v2
	v_fmac_f32_e32 v2, v0, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[10:11], v2
.LBB0_12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v0, v[10:11]
	v_mov_b32_e32 v2, s11
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	v_cmp_ngt_f32_e64 s0, v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s30, s0
	s_cbranch_execz .LBB0_21
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_f32_e32 v2, v1, v3
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v2
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[8:9]
	s_branch .LBB0_16
.LBB0_15:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_16:                               ; %Flow169
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[2:3], null, s9, v21, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v2
	v_mul_f32_e32 v2, v24, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v1, v14
	v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_18:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v1, v[2:3]
	v_mov_b32_e32 v2, s11
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	v_cmp_ngt_f32_e64 s0, v1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s31, vcc_lo, s0
	s_and_saveexec_b32 s0, s31
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v2, v22, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v20, v2
	v_mad_u64_u32 v[10:11], null, v23, s10, v[2:3]
	v_floor_f32_e32 v2, v0
	v_floor_f32_e32 v11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v24, v2
	v_mul_lo_u32 v3, v10, s6
	v_ceil_f32_e32 v10, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v25, v11
	v_cvt_i32_f32_e32 v2, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v3, v24
	v_add_nc_u32_e32 v2, v3, v2
	v_ceil_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v10, s7
	v_mul_lo_u32 v11, v2, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v3, v3
	v_add_nc_u32_e32 v2, v10, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v10, v3
	v_add_nc_u32_e32 v22, v11, v3
	v_add_nc_u32_e32 v20, v11, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v23, 31, v22
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s12, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	v_add_co_u32 v20, vcc_lo, s12, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s13, v21, vcc_lo
	v_add_co_u32 v22, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s13, v23, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[10:11], off
	global_load_b32 v10, v[20:21], off
	global_load_b32 v11, v[22:23], off
	v_cvt_f32_i32_e32 v20, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v20
	v_cvt_f32_i32_e32 v20, v24
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v0, v0, v20 :: v_dual_sub_f32 v3, v3, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v10 :: v_dual_fmac_f32 v2, v1, v3
	v_fmac_f32_e32 v10, v1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v10, v2
	v_fmac_f32_e32 v2, v0, v1
.LBB0_20:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_21:                               ; %Flow170
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s30
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_22:                               ; %Flow173
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s16, v4
	s_or_b32 s28, vcc_lo, s28
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_2
.LBB0_23:                               ; %Flow176
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,"axG",@progbits,_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf,comdat
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf, .Lfunc_end0-_ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1868
; NumSgprs: 36
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf
    .private_segment_fixed_size: 0
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _ZN8nvinfer16plugin19cropAndResizeKernelIfEEviPKT_PKfiiiiiiifPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
