#include <stdio.h>
#include <assert.h>
#include <curand.h>
#include <curand_kernel.h>
#include <cuda_runtime.h>
#include <unistd.h>
#include <math.h>
#define SIZE 3
#define BLOCKSIZE 512
#define PI 3.1415926535897932384626433


extern "C" void hello_world(){
	printf("oi, fui importada com sucesso. \n");

}

extern "C" void randomize(float *dV, int size){
	curandGenerator_t prng;
	/* create generator*/
	curandCreateGenerator(&prng, CURAND_RNG_PSEUDO_XORWOW);
	/* generate seed */
	curandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) 1337);
	/* randomize */
	curandGenerateUniform(prng, dV, size);
}



extern "C" __global__ void applyfunction(float *dV, float *dV2, int size, float k, float M){	int i = blockIdx.x*blockDim.x + threadIdx.x;
	if (i < size){
		dV[i] = ((float)sin((2*M + 1)*PI*dV[i])*cos(2*PI*k*dV[i]))/sin(PI*dV[i]);
		dV2[i] = dV[i]*dV[i];
	}
}

extern "C" __global__ void sumvec(float *idata, int size){
	__shared__ float sdata[BLOCKSIZE];
	int s;
	int tid = threadIdx.x;
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	int pseudoIf = i < size;
	/*
	if (blockIdx.x == 1 && threadIdx.x == 0){
		printf("i = %d; size = %d; pseudoIf = %d\n", i, size, pseudoIf);
	}*/

	sdata[tid] = pseudoIf*idata[i];
	/*
	__syncthreads();
	if (tid == 0){
		for (s = 0; s < size; s++){
			printf("id = %d sdata[%d] = %f; %f\n", blockIdx.x, s, sdata[s], idata[blockIdx.x*blockDim.x + s]);
		}
	}*/
	
	__syncthreads();
	for (s = blockDim.x/2; s > 0; s >>= 1){
		if (tid < s){
			sdata[tid] = sdata[tid] + sdata[tid+s];
		}
		__syncthreads();
	}
	if (tid == 0){
		printf("id = %d, stored = %f\n", blockIdx.x, sdata[0]);
		idata[blockIdx.x] = sdata[0];
	}

}

extern "C" float* MC_CUDA(int N, float k, float M){

	int i, devID = 0;
	float *dV, *dV2, f, f2;
	cudaError_t error;
	cudaDeviceProp deviceProp;
	static float resultados[2];


	/*CUDA boring stuff */
	error = cudaGetDevice(&devID);
	if (error != cudaSuccess){
		printf("cudaGetDevice returned error %s (code %d), line(%d)\n", cudaGetErrorString(error), error, __LINE__);
	}

	error = cudaGetDeviceProperties(&deviceProp,devID);
	if (deviceProp.computeMode == cudaComputeModeProhibited){
		fprintf(stderr, "Error: device is running in <Compute Mode Prohibited>, no threads can use ::cudaSetDevice().\n");
		exit(EXIT_SUCCESS);
	}
	if (error != cudaSuccess){
		printf("cudaGetDeviceProperties returned error %s (code %d), line(%d)\n", cudaGetErrorString(error), error, __LINE__);
	}
	else{
		printf("GPU Device %d: \"%s\" with compute capability %d.%d\n\n", devID, deviceProp.name, deviceProp.major, deviceProp.minor);
	}

	/* Allocate array on device */
	error = cudaMalloc(&dV, sizeof(float)*N);
	if (error != cudaSuccess){
		printf("cudaMalloc returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
	}
	error = cudaMalloc(&dV2, sizeof(float)*N);
	if (error != cudaSuccess){
		printf("cudaMalloc returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
	}

	/* Generate array */
	randomize(dV, N);
	/* Apply function */
	applyfunction<<<(1 + (N/BLOCKSIZE)), BLOCKSIZE>>>(dV, dV2, N, k, M);
	/* Sum all values */
	for (i = N; i > 1; i = 1+(i/BLOCKSIZE)){
		printf("Number of blocks = %d\n", 1+(i/BLOCKSIZE));
		printf("Size of array = %d\n", i);
		sumvec<<<(1+(i/BLOCKSIZE)), BLOCKSIZE>>>(dV, i);
		error = cudaDeviceSynchronize();
		if (error != cudaSuccess){
			printf("cudaDeviceSynchronize returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
		}
		printf("WAIT!\n");
		sumvec<<<(1+(i/BLOCKSIZE)), BLOCKSIZE>>>(dV2, i);
		error = cudaDeviceSynchronize();
		if (error != cudaSuccess){
			printf("cudaDeviceSynchronize returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
		}
	}
	/* Copy values from device */
	error = cudaMemcpy(&f, &dV[0], sizeof(float), cudaMemcpyDeviceToHost);
	if (error != cudaSuccess){
		printf("cudaMemcpy returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
	}
	error = cudaMemcpy(&f2, &dV2[0], sizeof(float), cudaMemcpyDeviceToHost);
	if (error != cudaSuccess){
		printf("cudaMemcpy returned error %s (code %d), line(%d) \n", cudaGetErrorString(error), error, __LINE__);
	}
	/* Calculate results */
	printf("SOMA = %f\n", f);
	f /= N;
	f2 /= N;

	resultados[0] = f;
	resultados[1] = f2;
	cudaFree(dV);
	cudaFree(dV2);
	return resultados;
}
	.file	"tmpxft_0024ac54_00000000-6_gpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2259:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2259:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"oi, fui importada com sucesso. \n"
	.text
	.globl	hello_world
	.type	hello_world, @function
hello_world:
.LFB2254:
	.cfi_startproc
	endbr64
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2254:
	.size	hello_world, .-hello_world
	.globl	randomize
	.type	randomize, @function
randomize:
.LFB2255:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	movl	$101, %esi
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	curandCreateGenerator@PLT
	movq	(%rsp), %rdi
	movl	$1337, %esi
	call	curandSetPseudoRandomGeneratorSeed@PLT
	movq	(%rsp), %rdi
	movslq	%ebx, %rdx
	movq	%rbp, %rsi
	call	curandGenerateUniform@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2255:
	.size	randomize, .-randomize
	.globl	_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff
	.type	_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff, @function
_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff:
.LFB2281:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	applyfunction(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L7:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2281:
	.size	_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff, .-_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff
	.globl	applyfunction
	.type	applyfunction, @function
applyfunction:
.LFB2282:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff
	.cfi_endproc
.LFE2282:
	.size	applyfunction, .-applyfunction
	.globl	_Z26__device_stub__Z6sumvecPfiPfi
	.type	_Z26__device_stub__Z6sumvecPfiPfi, @function
_Z26__device_stub__Z6sumvecPfiPfi:
.LFB2283:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	sumvec(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2283:
	.size	_Z26__device_stub__Z6sumvecPfiPfi, .-_Z26__device_stub__Z6sumvecPfiPfi
	.globl	sumvec
	.type	sumvec, @function
sumvec:
.LFB2284:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z6sumvecPfiPfi
	.cfi_endproc
.LFE2284:
	.size	sumvec, .-sumvec
	.section	.rodata.str1.1
.LC1:
	.string	"cudaGetDevice returned error %s (code %d), line(%d)\n"
.LC2:
	.string	"Error: device is running in <Compute Mode Prohibited>, no threads can use ::cudaSetDevice().\n"
.LC3:
	.string	"cudaGetDeviceProperties returned error %s (code %d), line(%d)\n"
.LC4:
	.string	"GPU Device %d: \"%s\" with compute capability %d.%d\n\n"
.LC5:
	.string	"cudaMalloc returned error %s (code %d), line(%d) \n"
.LC6:
	.string	"Number of blocks = %d\n"
.LC7:
	.string	"Size of array = %d\n"
.LC8:
	.string	"cudaDeviceSynchronize returned error %s (code %d), line(%d) \n"
.LC9:
	.string	"WAIT!\n"
.LC10:
	.string	"cudaMemcpy returned error %s (code %d), line(%d) \n"
.LC11:
	.string	"SOMA = %f\n"
	.text
	.globl	MC_CUDA
	.type	MC_CUDA, @function
MC_CUDA:
.LFB2256:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movd	%xmm1, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movd	%xmm0, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edi, %ebx
	subq	$1088, %rsp
	.cfi_def_cfa_offset 1136
	movq	%fs:40, %rax
	movq	%rax, 1080(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	xorl	%eax, %eax
	movl	%eax, 4(%rsp)
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	je	.L18
	movl	%eax, %edi
	movl	%eax, %ebp
	call	cudaGetErrorString@PLT
	movl	$83, %r8d
	movl	%ebp, %ecx
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L18:
	movl	4(%rsp), %esi
	leaq	48(%rsp), %r14
	movq	%r14, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	cmpl	$2, 452(%rsp)
	movl	%eax, %ebp
	jne	.L19
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L19:
	testl	%eax, %eax
	je	.L20
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$92, %r8d
	movl	%ebp, %ecx
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L21
.L20:
	movl	4(%rsp), %edx
	movq	%r14, %rcx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	412(%rsp), %r9d
	movl	408(%rsp), %r8d
	movl	$2, %edi
	call	__printf_chk@PLT
.L21:
	movslq	%ebx, %r14
	leaq	8(%rsp), %rdi
	salq	$2, %r14
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L22
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$101, %r8d
	movl	%ebp, %ecx
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L22:
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L23
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$105, %r8d
	movl	%ebp, %ecx
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L23:
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	call	randomize
	movl	%ebx, %eax
	movl	$512, %esi
	xorl	%r9d, %r9d
	cltd
	movl	$8388609, %ecx
	xorl	%r8d, %r8d
	movl	$1, 44(%rsp)
	idivl	%esi
	salq	$9, %rcx
	movq	%rcx, 36(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movd	%r13d, %xmm1
	movl	%ebx, %edx
	movd	%r12d, %xmm0
	call	_Z38__device_stub__Z13applyfunctionPfS_iffPfS_iff
.L24:
	movl	%ebx, %ebp
	leaq	.LC6(%rip), %r13
.L25:
	cmpl	$1, %ebp
	jle	.L56
	movl	%ebp, %r12d
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	sarl	$9, %r12d
	incl	%r12d
	movl	%r12d, %edx
	call	__printf_chk@PLT
	movl	%ebp, %edx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%r12d, 24(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	$1, 44(%rsp)
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	salq	$9, %rdx
	movl	32(%rsp), %esi
	movq	%rdx, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	8(%rsp), %rdi
	movl	%ebp, %esi
	call	_Z26__device_stub__Z6sumvecPfiPfi
.L26:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	je	.L27
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$119, %r8d
	movl	%r14d, %ecx
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L27:
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%r12d, 24(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$8388609, %edx
	movl	$1, %ecx
	movl	$1, 44(%rsp)
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	salq	$9, %rdx
	movl	32(%rsp), %esi
	movq	%rdx, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	16(%rsp), %rdi
	movl	%ebp, %esi
	call	_Z26__device_stub__Z6sumvecPfiPfi
.L28:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L29
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$125, %r8d
	movl	%ebp, %ecx
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L29:
	movl	%r12d, %ebp
	jmp	.L25
.L56:
	movq	8(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L31
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$131, %r8d
	movl	%ebp, %ecx
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L31:
	movq	16(%rsp), %rsi
	leaq	36(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L32
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$135, %r8d
	movl	%ebp, %ecx
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L32:
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	cvtsi2ssl	%ebx, %xmm2
	movss	24(%rsp), %xmm1
	movss	36(%rsp), %xmm0
	movq	8(%rsp), %rdi
	divss	%xmm2, %xmm1
	divss	%xmm2, %xmm0
	movss	%xmm1, 24(%rsp)
	movss	%xmm1, _ZZ7MC_CUDAE10resultados(%rip)
	movss	%xmm0, 36(%rsp)
	movss	%xmm0, 4+_ZZ7MC_CUDAE10resultados(%rip)
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	1080(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$1088, %rsp
	.cfi_def_cfa_offset 48
	leaq	_ZZ7MC_CUDAE10resultados(%rip), %rax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2256:
	.size	MC_CUDA, .-MC_CUDA
	.section	.rodata.str1.1
.LC12:
	.string	"sumvec"
.LC13:
	.string	"applyfunction"
.LC14:
	.string	"precalc_xorwow_matrix"
.LC15:
	.string	"precalc_xorwow_offset_matrix"
.LC16:
	.string	"mrg32k3aM1"
.LC17:
	.string	"mrg32k3aM2"
.LC18:
	.string	"mrg32k3aM1SubSeq"
.LC19:
	.string	"mrg32k3aM2SubSeq"
.LC20:
	.string	"mrg32k3aM1Seq"
.LC21:
	.string	"mrg32k3aM2Seq"
.LC22:
	.string	"__cr_lgamma_table"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2286:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	sumvec(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	applyfunction(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2286:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ7MC_CUDAE10resultados
	.comm	_ZZ7MC_CUDAE10resultados,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <assert.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <math.h>
#define SIZE 3
#define BLOCKSIZE 512
#define PI 3.1415926535897932384626433


extern "C" void hello_world(){
	printf("oi, fui importada com sucesso. \n");

}

extern "C" void randomize(float *dV, int size){
	hiprandGenerator_t prng;
	/* create generator*/
	hiprandCreateGenerator(&prng, HIPRAND_RNG_PSEUDO_XORWOW);
	/* generate seed */
	hiprandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) 1337);
	/* randomize */
	hiprandGenerateUniform(prng, dV, size);
}



extern "C" __global__ void applyfunction(float *dV, float *dV2, int size, float k, float M){	int i = blockIdx.x*blockDim.x + threadIdx.x;
	if (i < size){
		dV[i] = ((float)sin((2*M + 1)*PI*dV[i])*cos(2*PI*k*dV[i]))/sin(PI*dV[i]);
		dV2[i] = dV[i]*dV[i];
	}
}

extern "C" __global__ void sumvec(float *idata, int size){
	__shared__ float sdata[BLOCKSIZE];
	int s;
	int tid = threadIdx.x;
	int i = blockIdx.x*blockDim.x + threadIdx.x;
	int pseudoIf = i < size;
	/*
	if (blockIdx.x == 1 && threadIdx.x == 0){
		printf("i = %d; size = %d; pseudoIf = %d\n", i, size, pseudoIf);
	}*/

	sdata[tid] = pseudoIf*idata[i];
	/*
	__syncthreads();
	if (tid == 0){
		for (s = 0; s < size; s++){
			printf("id = %d sdata[%d] = %f; %f\n", blockIdx.x, s, sdata[s], idata[blockIdx.x*blockDim.x + s]);
		}
	}*/
	
	__syncthreads();
	for (s = blockDim.x/2; s > 0; s >>= 1){
		if (tid < s){
			sdata[tid] = sdata[tid] + sdata[tid+s];
		}
		__syncthreads();
	}
	if (tid == 0){
		printf("id = %d, stored = %f\n", blockIdx.x, sdata[0]);
		idata[blockIdx.x] = sdata[0];
	}

}

extern "C" float* MC_CUDA(int N, float k, float M){

	int i, devID = 0;
	float *dV, *dV2, f, f2;
	hipError_t error;
	hipDeviceProp_t deviceProp;
	static float resultados[2];


	/*CUDA boring stuff */
	error = hipGetDevice(&devID);
	if (error != hipSuccess){
		printf("hipGetDevice returned error %s (code %d), line(%d)\n", hipGetErrorString(error), error, __LINE__);
	}

	error = hipGetDeviceProperties(&deviceProp,devID);
	if (deviceProp.computeMode == hipComputeModeProhibited){
		fprintf(stderr, "Error: device is running in <Compute Mode Prohibited>, no threads can use ::cudaSetDevice().\n");
		exit(EXIT_SUCCESS);
	}
	if (error != hipSuccess){
		printf("hipGetDeviceProperties returned error %s (code %d), line(%d)\n", hipGetErrorString(error), error, __LINE__);
	}
	else{
		printf("GPU Device %d: \"%s\" with compute capability %d.%d\n\n", devID, deviceProp.name, deviceProp.major, deviceProp.minor);
	}

	/* Allocate array on device */
	error = hipMalloc(&dV, sizeof(float)*N);
	if (error != hipSuccess){
		printf("hipMalloc returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
	}
	error = hipMalloc(&dV2, sizeof(float)*N);
	if (error != hipSuccess){
		printf("hipMalloc returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
	}

	/* Generate array */
	randomize(dV, N);
	/* Apply function */
	applyfunction<<<(1 + (N/BLOCKSIZE)), BLOCKSIZE>>>(dV, dV2, N, k, M);
	/* Sum all values */
	for (i = N; i > 1; i = 1+(i/BLOCKSIZE)){
		printf("Number of blocks = %d\n", 1+(i/BLOCKSIZE));
		printf("Size of array = %d\n", i);
		sumvec<<<(1+(i/BLOCKSIZE)), BLOCKSIZE>>>(dV, i);
		error = hipDeviceSynchronize();
		if (error != hipSuccess){
			printf("hipDeviceSynchronize returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
		}
		printf("WAIT!\n");
		sumvec<<<(1+(i/BLOCKSIZE)), BLOCKSIZE>>>(dV2, i);
		error = hipDeviceSynchronize();
		if (error != hipSuccess){
			printf("hipDeviceSynchronize returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
		}
	}
	/* Copy values from device */
	error = hipMemcpy(&f, &dV[0], sizeof(float), hipMemcpyDeviceToHost);
	if (error != hipSuccess){
		printf("hipMemcpy returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
	}
	error = hipMemcpy(&f2, &dV2[0], sizeof(float), hipMemcpyDeviceToHost);
	if (error != hipSuccess){
		printf("hipMemcpy returned error %s (code %d), line(%d) \n", hipGetErrorString(error), error, __LINE__);
	}
	/* Calculate results */
	printf("SOMA = %f\n", f);
	f /= N;
	f2 /= N;

	resultados[0] = f;
	resultados[1] = f2;
	hipFree(dV);
	hipFree(dV2);
	return resultados;
}
	.text
	.file	"gpu.hip"
	.globl	hello_world                     # -- Begin function hello_world
	.type	hello_world,@function
hello_world:                            # @hello_world
	.cfi_startproc
# %bb.0:
	movl	$.Lstr, %edi
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end0:
	.size	hello_world, .Lfunc_end0-hello_world
	.cfi_endproc
                                        # -- End function
	.globl	randomize                       # -- Begin function randomize
	.type	randomize,@function
randomize:                              # @randomize
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	leaq	8(%rsp), %r15
	movq	%r15, %rdi
	movl	$401, %esi                      # imm = 0x191
	callq	hiprandCreateGenerator
	movq	(%r15), %rdi
	movl	$1337, %esi                     # imm = 0x539
	callq	hiprandSetPseudoRandomGeneratorSeed
	movq	(%r15), %rdi
	movslq	%ebx, %rdx
	movq	%r14, %rsi
	callq	hiprandGenerateUniform
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	randomize, .Lfunc_end1-randomize
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__applyfunction    # -- Begin function __device_stub__applyfunction
	.type	__device_stub__applyfunction,@function
__device_stub__applyfunction:           # @__device_stub__applyfunction
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	4(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rdi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$applyfunction, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__applyfunction, .Lfunc_end2-__device_stub__applyfunction
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__sumvec           # -- Begin function __device_stub__sumvec
	.type	__device_stub__sumvec,@function
__device_stub__sumvec:                  # @__device_stub__sumvec
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sumvec, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__sumvec, .Lfunc_end3-__device_stub__sumvec
	.cfi_endproc
                                        # -- End function
	.globl	MC_CUDA                         # -- Begin function MC_CUDA
	.type	MC_CUDA,@function
MC_CUDA:                                # @MC_CUDA
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 1568
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm1, 36(%rsp)                 # 4-byte Spill
	movss	%xmm0, 32(%rsp)                 # 4-byte Spill
	movl	%edi, %ebx
	leaq	20(%rsp), %rdi
	movl	$0, (%rdi)
	callq	hipGetDevice
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$83, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_2:
	movl	20(%rsp), %esi
	leaq	40(%rsp), %r14
	movq	%r14, %rdi
	callq	hipGetDevicePropertiesR0600
	cmpl	$2, 404(%r14)
	je	.LBB4_28
# %bb.3:
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.LBB4_5
# %bb.4:
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$92, %ecx
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB4_6
.LBB4_5:
	movl	20(%rsp), %esi
	leaq	40(%rsp), %rdx
	movl	360(%rdx), %ecx
	movl	364(%rdx), %r8d
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
.LBB4_6:
	movslq	%ebx, %r14
	shlq	$2, %r14
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB4_8
# %bb.7:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$101, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_8:
	leaq	24(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB4_10
# %bb.9:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$105, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_10:
	movabsq	$4294967808, %r14               # imm = 0x100000200
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	callq	randomize
	leal	511(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$9, %eax
	incl	%eax
	leaq	(%rax,%r14), %rdi
	addq	$-512, %rdi                     # imm = 0xFE00
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_12
# %bb.11:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	%ebx, %edx
	movss	32(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	36(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	callq	__device_stub__applyfunction
.LBB4_12:
	cmpl	$2, %ebx
	jl	.LBB4_23
# %bb.13:                               # %.lr.ph.preheader
	movl	%ebx, %ebp
.LBB4_14:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebp, %r12d
	shrl	$9, %r12d
	leal	1(%r12), %r15d
	movl	$.L.str.6, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.7, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	addq	%r14, %r12
	addq	$-511, %r12                     # imm = 0xFE01
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_16
# %bb.15:                               #   in Loop: Header=BB4_14 Depth=1
	movq	8(%rsp), %rdi
	movl	%ebp, %esi
	callq	__device_stub__sumvec
.LBB4_16:                               #   in Loop: Header=BB4_14 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB4_18
# %bb.17:                               #   in Loop: Header=BB4_14 Depth=1
	movl	%eax, %r13d
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %edi
	movq	%rax, %rsi
	movl	%r13d, %edx
	movl	$119, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_18:                               #   in Loop: Header=BB4_14 Depth=1
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.19:                               #   in Loop: Header=BB4_14 Depth=1
	movq	24(%rsp), %rdi
	movl	%ebp, %esi
	callq	__device_stub__sumvec
.LBB4_20:                               #   in Loop: Header=BB4_14 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB4_22
# %bb.21:                               #   in Loop: Header=BB4_14 Depth=1
	movl	%eax, %r12d
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %edi
	movq	%rax, %rsi
	movl	%r12d, %edx
	movl	$125, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_22:                               #   in Loop: Header=BB4_14 Depth=1
	cmpl	$511, %ebp                      # imm = 0x1FF
	movl	%r15d, %ebp
	ja	.LBB4_14
.LBB4_23:                               # %._crit_edge
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB4_25
# %bb.24:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$131, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_25:
	movq	24(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB4_27
# %bb.26:
	movl	%eax, %ebp
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.10, %edi
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	$135, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB4_27:
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0
	movl	$.L.str.11, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebx, %xmm0
	movss	4(%rsp), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)
	movss	16(%rsp), %xmm2                 # xmm2 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm2
	movss	%xmm2, 16(%rsp)
	movss	%xmm1, _ZZ7MC_CUDAE10resultados(%rip)
	movss	%xmm2, _ZZ7MC_CUDAE10resultados+4(%rip)
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movl	$_ZZ7MC_CUDAE10resultados, %eax
	addq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_28:
	.cfi_def_cfa_offset 1568
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$93, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end4:
	.size	MC_CUDA, .Lfunc_end4-MC_CUDA
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$applyfunction, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sumvec, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	applyfunction,@object           # @applyfunction
	.section	.rodata,"a",@progbits
	.globl	applyfunction
	.p2align	3, 0x0
applyfunction:
	.quad	__device_stub__applyfunction
	.size	applyfunction, 8

	.type	sumvec,@object                  # @sumvec
	.globl	sumvec
	.p2align	3, 0x0
sumvec:
	.quad	__device_stub__sumvec
	.size	sumvec, 8

	.type	_ZZ7MC_CUDAE10resultados,@object # @_ZZ7MC_CUDAE10resultados
	.local	_ZZ7MC_CUDAE10resultados
	.comm	_ZZ7MC_CUDAE10resultados,8,4
	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"hipGetDevice returned error %s (code %d), line(%d)\n"
	.size	.L.str.1, 52

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error: device is running in <Compute Mode Prohibited>, no threads can use ::cudaSetDevice().\n"
	.size	.L.str.2, 94

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipGetDeviceProperties returned error %s (code %d), line(%d)\n"
	.size	.L.str.3, 62

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPU Device %d: \"%s\" with compute capability %d.%d\n\n"
	.size	.L.str.4, 52

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipMalloc returned error %s (code %d), line(%d) \n"
	.size	.L.str.5, 50

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Number of blocks = %d\n"
	.size	.L.str.6, 23

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Size of array = %d\n"
	.size	.L.str.7, 20

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipDeviceSynchronize returned error %s (code %d), line(%d) \n"
	.size	.L.str.8, 61

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"hipMemcpy returned error %s (code %d), line(%d) \n"
	.size	.L.str.10, 50

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"SOMA = %f\n"
	.size	.L.str.11, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"applyfunction"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"sumvec"
	.size	.L__unnamed_2, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"oi, fui importada com sucesso. "
	.size	.Lstr, 32

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"WAIT!"
	.size	.Lstr.1, 6

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__applyfunction
	.addrsig_sym __device_stub__sumvec
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym applyfunction
	.addrsig_sym sumvec
	.addrsig_sym _ZZ7MC_CUDAE10resultados
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	applyfunction           ; -- Begin function applyfunction
	.globl	applyfunction
	.p2align	8
	.type	applyfunction,@function
applyfunction:                          ; @applyfunction
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_14
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_fma_f32 v4, s6, 2.0, 1.0
	s_mov_b32 s7, 0x400921fb
	s_mov_b32 s6, 0x54442d18
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr10_vgpr11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_cvt_f64_f32_e32 v[4:5], v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v6, v[0:1], off
	v_mul_f64 v[4:5], v[4:5], s[6:7]
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[14:15], v6
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[4:5], v[14:15]
	v_cmp_ngt_f64_e64 s0, 0x41d00000, |v[4:5]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_ldexp_f64 v[6:7], |v[4:5]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_trig_preop_f64 v[8:9], |v[4:5]|, 0
	v_and_b32_e32 v10, 0x7fffffff, v5
	v_trig_preop_f64 v[22:23], |v[4:5]|, 2
	v_mov_b32_e32 v30, 0
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v7, v10, v7 :: v_dual_cndmask_b32 v6, v4, v6
	v_trig_preop_f64 v[10:11], |v[4:5]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[12:13], v[8:9], v[6:7]
	v_mul_f64 v[28:29], v[22:23], v[6:7]
	v_mul_f64 v[16:17], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], v[6:7], -v[12:13]
	v_fma_f64 v[10:11], v[10:11], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], v[22:23], v[6:7], -v[28:29]
	v_add_f64 v[18:19], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[16:17]
	v_add_f64 v[26:27], v[12:13], v[18:19]
	v_add_f64 v[24:25], v[18:19], -v[20:21]
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[20:21], v[26:27], -2
	v_add_f64 v[12:13], v[26:27], -v[12:13]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[16:17]
	v_fract_f64_e32 v[16:17], v[20:21]
	v_add_f64 v[18:19], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v17, 0, v17 :: v_dual_cndmask_b32 v16, 0, v16
	v_ldexp_f64 v[16:17], v[16:17], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[12:13], v[18:19]
	v_add_f64 v[26:27], v[20:21], v[16:17]
	v_add_f64 v[12:13], v[20:21], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[26:27]
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	v_cndmask_b32_e64 v31, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[24:25], -v[26:27]
	v_add_f64 v[10:11], v[10:11], -v[26:27]
	v_add_f64 v[16:17], v[16:17], v[30:31]
	v_add_f64 v[31:32], v[18:19], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[28:29], -v[35:36]
	v_add_f64 v[33:34], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[18:19], -v[31:32]
	v_add_f64 v[8:9], v[8:9], -v[31:32]
	v_add_f64 v[10:11], v[10:11], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v33, v[33:34]
	v_add_f64 v[24:25], v[24:25], -v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[31:32], v33
	v_add_f64 v[8:9], v[8:9], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[31:32]
	v_add_f64 v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[20:21], v[16:17]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[10:11], -v[16:17]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[10:11]
	v_add_f64 v[6:7], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[20:21], -v[8:9]
	v_cndmask_b32_e64 v31, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v22, s0, 0, v33, vcc_lo
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[10:11], -v[30:31]
	v_add_f64 v[10:11], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[10:11], s[6:7]
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_fma_f64 v[16:17], v[10:11], s[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[8:9]
	v_fma_f64 v[8:9], v[10:11], s[8:9], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], s[6:7], v[8:9]
	v_add_f64 v[6:7], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[6:7], -v[12:13]
	v_add_f64 v[10:11], v[8:9], -v[10:11]
.LBB0_3:                                ; %Flow43
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[6:7], |v[4:5]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[8:9], v[6:7]
	v_fma_f64 v[6:7], v[8:9], s[6:7], |v[4:5]|
	v_mul_f64 v[10:11], v[8:9], s[8:9]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	v_cvt_i32_f64_e32 v22, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[8:9], s[8:9], v[6:7]
	v_add_f64 v[12:13], v[6:7], v[10:11]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[12:13]
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_fma_f64 v[10:11], v[8:9], s[8:9], v[10:11]
	v_add_f64 v[6:7], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_fma_f64 v[10:11], v[8:9], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[10:11]
	v_add_f64 v[12:13], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
.LBB0_5:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f64_f32_e32 v[8:9], s5
	s_mov_b32 s5, 0x401921fb
	s_mov_b32 s4, 0x54442d18
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr16_vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[8:9], v[8:9], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	v_cmp_ngt_f64_e64 s0, 0x41d00000, |v[8:9]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_ldexp_f64 v[12:13], |v[8:9]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
	v_trig_preop_f64 v[16:17], |v[8:9]|, 0
	v_and_b32_e32 v18, 0x7fffffff, v9
	v_trig_preop_f64 v[29:30], |v[8:9]|, 2
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_mov_b32_e32 v37, 0
	v_dual_cndmask_b32 v13, v18, v13 :: v_dual_cndmask_b32 v12, v8, v12
	v_trig_preop_f64 v[18:19], |v[8:9]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[20:21], v[16:17], v[12:13]
	v_mul_f64 v[35:36], v[29:30], v[12:13]
	v_mul_f64 v[23:24], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[16:17], v[12:13], -v[20:21]
	v_fma_f64 v[18:19], v[18:19], v[12:13], -v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[29:30], v[12:13], -v[35:36]
	v_add_f64 v[25:26], v[23:24], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[25:26], -v[23:24]
	v_add_f64 v[33:34], v[20:21], v[25:26]
	v_add_f64 v[31:32], v[25:26], -v[27:28]
	v_add_f64 v[16:17], v[16:17], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[27:28], v[33:34], -2
	v_add_f64 v[20:21], v[33:34], -v[20:21]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	v_add_f64 v[31:32], v[35:36], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[27:28]|
	v_add_f64 v[20:21], v[25:26], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[23:24]
	v_fract_f64_e32 v[23:24], v[27:28]
	v_add_f64 v[25:26], v[31:32], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v24, 0, v24 :: v_dual_cndmask_b32 v23, 0, v23
	v_ldexp_f64 v[23:24], v[23:24], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[20:21], v[25:26]
	v_add_f64 v[33:34], v[27:28], v[23:24]
	v_add_f64 v[20:21], v[27:28], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[33:34]
	v_add_f64 v[33:34], v[31:32], -v[35:36]
	v_add_f64 v[20:21], v[25:26], -v[20:21]
	v_cndmask_b32_e64 v38, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[31:32], -v[33:34]
	v_add_f64 v[18:19], v[18:19], -v[33:34]
	v_add_f64 v[23:24], v[23:24], v[37:38]
	v_add_f64 v[38:39], v[25:26], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[35:36], -v[42:43]
	v_add_f64 v[40:41], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[44:45], v[25:26], -v[38:39]
	v_add_f64 v[16:17], v[16:17], -v[38:39]
	v_add_f64 v[18:19], v[18:19], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v40, v[40:41]
	v_add_f64 v[31:32], v[31:32], -v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[38:39], v40
	v_add_f64 v[16:17], v[16:17], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[23:24], -v[38:39]
	v_add_f64 v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[27:28], v[23:24]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], -v[23:24]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[18:19]
	v_add_f64 v[12:13], v[20:21], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[27:28], -v[16:17]
	v_cndmask_b32_e64 v38, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v23, s0, 0, v40, vcc_lo
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[18:19], -v[37:38]
	v_add_f64 v[18:19], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[20:21], v[18:19], s[4:5]
	v_add_f64 v[16:17], v[18:19], -v[16:17]
	v_fma_f64 v[24:25], v[18:19], s[4:5], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_fma_f64 v[16:17], v[18:19], s[6:7], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[12:13], s[4:5], v[16:17]
	v_add_f64 v[12:13], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[12:13], -v[20:21]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
.LBB0_7:                                ; %Flow42
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[12:13], |v[8:9]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[18:19], v[12:13]
	v_fma_f64 v[12:13], v[18:19], s[4:5], |v[8:9]|
	v_mul_f64 v[16:17], v[18:19], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[18:19], s[6:7], v[12:13]
	v_add_f64 v[20:21], v[12:13], v[16:17]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	v_add_f64 v[20:21], v[20:21], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_fma_f64 v[16:17], v[18:19], s[6:7], v[16:17]
	v_add_f64 v[12:13], v[20:21], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_fma_f64 v[16:17], v[18:19], s[4:5], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[23:24], v[16:17]
	v_add_f64 v[20:21], v[12:13], -v[23:24]
	v_cvt_i32_f64_e32 v23, v[18:19]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[20:21]
.LBB0_9:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0x400921fb
	s_mov_b32 s4, 0x54442d18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr20_vgpr21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[14:15], s[4:5]
	v_cmp_ngt_f64_e64 s0, 0x41d00000, |v[14:15]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_ldexp_f64 v[18:19], |v[14:15]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[14:15]|
	v_trig_preop_f64 v[20:21], |v[14:15]|, 0
	v_and_b32_e32 v24, 0x7fffffff, v15
	v_trig_preop_f64 v[34:35], |v[14:15]|, 2
	v_mov_b32_e32 v42, 0
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v19, v24, v19 :: v_dual_cndmask_b32 v18, v14, v18
	v_trig_preop_f64 v[24:25], |v[14:15]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[26:27], v[20:21], v[18:19]
	v_mul_f64 v[40:41], v[34:35], v[18:19]
	v_mul_f64 v[28:29], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[18:19], -v[26:27]
	v_fma_f64 v[24:25], v[24:25], v[18:19], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[34:35], v[18:19], -v[40:41]
	v_add_f64 v[30:31], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[30:31], -v[28:29]
	v_add_f64 v[38:39], v[26:27], v[30:31]
	v_add_f64 v[36:37], v[30:31], -v[32:33]
	v_add_f64 v[20:21], v[20:21], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[32:33], v[38:39], -2
	v_add_f64 v[26:27], v[38:39], -v[26:27]
	v_add_f64 v[28:29], v[28:29], -v[36:37]
	v_add_f64 v[36:37], v[40:41], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[32:33]|
	v_add_f64 v[26:27], v[30:31], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[28:29]
	v_fract_f64_e32 v[28:29], v[32:33]
	v_add_f64 v[30:31], v[36:37], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v29, 0, v29 :: v_dual_cndmask_b32 v28, 0, v28
	v_ldexp_f64 v[28:29], v[28:29], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[26:27], v[30:31]
	v_add_f64 v[38:39], v[32:33], v[28:29]
	v_add_f64 v[26:27], v[32:33], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[38:39]
	v_add_f64 v[38:39], v[36:37], -v[40:41]
	v_cndmask_b32_e64 v43, 0, 0x40100000, vcc_lo
	v_add_f64 v[47:48], v[36:37], -v[38:39]
	v_add_f64 v[24:25], v[24:25], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], v[42:43]
	v_add_f64 v[43:44], v[30:31], -v[36:37]
	v_add_f64 v[38:39], v[40:41], -v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[45:46], v[32:33], v[28:29]
	v_add_f64 v[49:50], v[30:31], -v[43:44]
	v_add_f64 v[20:21], v[20:21], -v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], v[38:39]
	v_cvt_i32_f64_e32 v45, v[45:46]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[36:37], -v[49:50]
	v_cvt_f64_i32_e32 v[43:44], v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[36:37]
	v_add_f64 v[28:29], v[28:29], -v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[24:25], v[20:21]
	v_add_f64 v[24:25], v[30:31], -v[26:27]
	v_add_f64 v[34:35], v[32:33], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[34:35], -v[28:29]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[24:25], v[18:19]
	v_add_f64 v[20:21], v[32:33], -v[20:21]
	v_cndmask_b32_e64 v43, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v24, s0, 0, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[34:35], -v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[25:26], v[20:21], v[18:19]
	v_mul_f64 v[27:28], v[25:26], s[4:5]
	v_add_f64 v[20:21], v[25:26], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], s[4:5], -v[27:28]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[25:26], s[6:7], v[29:30]
	v_fma_f64 v[20:21], v[18:19], s[4:5], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[27:28], v[20:21]
	v_add_f64 v[25:26], v[18:19], -v[27:28]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[25:26]
.LBB0_11:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_13
; %bb.12:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[18:19], |v[14:15]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[24:25], v[18:19]
	v_fma_f64 v[18:19], v[24:25], s[4:5], |v[14:15]|
	v_mul_f64 v[20:21], v[24:25], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], s[6:7], v[18:19]
	v_add_f64 v[26:27], v[18:19], v[20:21]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_fma_f64 v[20:21], v[24:25], s[6:7], v[20:21]
	v_add_f64 v[18:19], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_fma_f64 v[20:21], v[24:25], s[4:5], v[18:19]
	v_cvt_i32_f64_e32 v24, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[28:29], v[20:21]
	v_add_f64 v[26:27], v[18:19], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[26:27]
.LBB0_13:                               ; %_ZL3sind.exit27
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[25:26], v[6:7], v[6:7]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s4, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s5, 0x3de5e0b2
	v_mul_f64 v[29:30], v[12:13], v[12:13]
	s_mov_b32 s8, 0x9037ab78
	s_mov_b32 s10, 0x46cc5e42
	s_mov_b32 s6, 0x796cde01
	s_mov_b32 s9, 0x3e21eeb6
	s_mov_b32 s11, 0xbda907db
	s_mov_b32 s7, 0x3ec71de3
	v_mul_f64 v[35:36], v[18:19], v[18:19]
	s_mov_b32 s12, 0xa17f65f6
	s_mov_b32 s14, 0x19e83e5c
	s_mov_b32 s13, 0xbe927e4f
	s_mov_b32 s15, 0xbf2a01a0
	s_mov_b32 s16, 0x19f4ec90
	s_mov_b32 s18, 0x11110bb3
	s_mov_b32 s17, 0x3efa01a0
	s_mov_b32 s19, 0x3f811111
	v_mul_f64 v[41:42], v[10:11], 0.5
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[27:28], v[25:26], s[4:5], s[0:1]
	v_fma_f64 v[31:32], v[25:26], s[10:11], s[8:9]
	v_mul_f64 v[33:34], v[25:26], 0.5
	v_mul_f64 v[43:44], v[6:7], -v[25:26]
	v_fma_f64 v[37:38], v[29:30], s[4:5], s[0:1]
	v_mul_f64 v[45:46], v[29:30], 0.5
	v_fma_f64 v[47:48], v[29:30], s[10:11], s[8:9]
	v_mul_f64 v[59:60], v[12:13], -v[29:30]
	v_fma_f64 v[49:50], v[35:36], s[4:5], s[0:1]
	v_mul_f64 v[53:54], v[35:36], 0.5
	v_fma_f64 v[55:56], v[35:36], s[10:11], s[8:9]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_mov_b32 s4, 0x55555555
	s_mov_b32 s5, 0x3fa55555
	v_fma_f64 v[27:28], v[25:26], v[27:28], s[6:7]
	v_fma_f64 v[31:32], v[25:26], v[31:32], s[12:13]
	v_add_f64 v[39:40], -v[33:34], 1.0
	v_fma_f64 v[37:38], v[29:30], v[37:38], s[6:7]
	v_add_f64 v[57:58], -v[45:46], 1.0
	v_fma_f64 v[47:48], v[29:30], v[47:48], s[12:13]
	v_fma_f64 v[49:50], v[35:36], v[49:50], s[6:7]
	v_add_f64 v[61:62], -v[53:54], 1.0
	v_fma_f64 v[55:56], v[35:36], v[55:56], s[12:13]
	s_mov_b32 s7, 0xbfc55555
	s_mov_b32 s6, s4
	v_fma_f64 v[27:28], v[25:26], v[27:28], s[14:15]
	v_fma_f64 v[31:32], v[25:26], v[31:32], s[16:17]
	v_add_f64 v[51:52], -v[39:40], 1.0
	v_fma_f64 v[37:38], v[29:30], v[37:38], s[14:15]
	v_add_f64 v[63:64], -v[57:58], 1.0
	v_fma_f64 v[47:48], v[29:30], v[47:48], s[16:17]
	v_fma_f64 v[49:50], v[35:36], v[49:50], s[14:15]
	v_add_f64 v[65:66], -v[61:62], 1.0
	v_fma_f64 v[55:56], v[35:36], v[55:56], s[16:17]
	v_fma_f64 v[27:28], v[25:26], v[27:28], s[18:19]
	v_fma_f64 v[31:32], v[25:26], v[31:32], s[0:1]
	v_add_f64 v[33:34], v[51:52], -v[33:34]
	v_mul_f64 v[51:52], v[25:26], v[25:26]
	v_fma_f64 v[37:38], v[29:30], v[37:38], s[18:19]
	v_add_f64 v[45:46], v[63:64], -v[45:46]
	v_fma_f64 v[47:48], v[29:30], v[47:48], s[0:1]
	v_fma_f64 v[49:50], v[35:36], v[49:50], s[18:19]
	v_fma_f64 v[27:28], v[43:44], v[27:28], v[41:42]
	v_mul_f64 v[41:42], v[16:17], 0.5
	v_fma_f64 v[31:32], v[25:26], v[31:32], s[4:5]
	v_fma_f64 v[33:34], v[6:7], -v[10:11], v[33:34]
	v_fma_f64 v[45:46], v[12:13], -v[16:17], v[45:46]
	v_fma_f64 v[47:48], v[29:30], v[47:48], s[4:5]
	v_fma_f64 v[10:11], v[25:26], v[27:28], -v[10:11]
	v_fma_f64 v[37:38], v[59:60], v[37:38], v[41:42]
	v_mul_f64 v[25:26], v[20:21], 0.5
	v_mul_f64 v[27:28], v[18:19], -v[35:36]
	v_fma_f64 v[31:32], v[51:52], v[31:32], v[33:34]
	v_add_f64 v[41:42], v[65:66], -v[53:54]
	v_mul_f64 v[33:34], v[29:30], v[29:30]
	v_fma_f64 v[10:11], v[43:44], s[6:7], v[10:11]
	v_fma_f64 v[16:17], v[29:30], v[37:38], -v[16:17]
	v_fma_f64 v[43:44], v[35:36], v[55:56], s[0:1]
	v_fma_f64 v[25:26], v[27:28], v[49:50], v[25:26]
	v_add_f64 v[29:30], v[39:40], v[31:32]
	v_cmp_class_f64_e64 s0, v[4:5], 0x1f8
	v_and_b32_e32 v39, 1, v22
	v_fma_f64 v[37:38], v[18:19], -v[20:21], v[41:42]
	v_fma_f64 v[33:34], v[33:34], v[47:48], v[45:46]
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v39
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_fma_f64 v[16:17], v[59:60], s[6:7], v[16:17]
	v_mul_f64 v[10:11], v[35:36], v[35:36]
	v_fma_f64 v[31:32], v[35:36], v[43:44], s[4:5]
	v_fma_f64 v[20:21], v[35:36], v[25:26], -v[20:21]
	v_dual_cndmask_b32 v7, v30, v7 :: v_dual_lshlrev_b32 v4, 30, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v5
	v_cndmask_b32_e32 v25, v29, v6, vcc_lo
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_and_b32_e32 v6, 0x80000000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, v25, s0
	v_fma_f64 v[4:5], v[10:11], v[31:32], v[37:38]
	v_add_f64 v[10:11], v[57:58], v[33:34]
	v_xor_b32_e32 v22, v7, v6
	v_fma_f64 v[6:7], v[27:28], s[6:7], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, 0x7ff80000, v22, s0
	v_cmp_class_f64_e64 s0, v[8:9], 0x1f8
	v_cvt_f32_f64_e32 v16, v[16:17]
	v_and_b32_e32 v17, 1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_xor_b32_e32 v13, 0x80000000, v13
	v_add_f64 v[4:5], v[61:62], v[4:5]
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	v_lshlrev_b32_e32 v12, 30, v23
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	v_add_f64 v[6:7], v[18:19], -v[6:7]
	v_and_b32_e32 v13, 1, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v12, 0x80000000, v12
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v12
	v_cvt_f64_f32_e32 v[8:9], v16
	v_cndmask_b32_e64 v11, 0x7ff80000, v11, s0
	v_cmp_class_f64_e64 s0, v[14:15], 0x1f8
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_lshlrev_b32 v6, 30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v15
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	v_and_b32_e32 v6, 0x80000000, v6
	v_cndmask_b32_e64 v4, 0, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v6
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[8:9]
	v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[4:5], v[8:9]
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[12:13]
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[6:7], v[4:5], v[8:9]
	v_cvt_f32_f64_e32 v4, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v5, v4, v4
	global_store_b32 v[0:1], v4, off
	global_store_b32 v[2:3], v5, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel applyfunction
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 67
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	applyfunction, .Lfunc_end0-applyfunction
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4308
; NumSgprs: 22
; NumVgprs: 67
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 67
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	sumvec                  ; -- Begin function sumvec
	.globl	sumvec
	.p2align	8
	.type	sumvec,@function
sumvec:                                 ; @sumvec
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x1c
	s_load_b64 s[4:5], s[0:1], 0x0
	s_add_u32 s6, s0, 16
	s_mov_b32 s2, s15
	s_addc_u32 s7, s1, 0
	s_load_b32 s0, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_cmp_lt_u32 s3, 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s0, v1
	global_load_b32 v2, v[2:3], off
	v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v2, v2, v3 :: v_dual_lshlrev_b32 v1, 2, v0
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_4
.LBB1_1:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s3, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB1_3
; %bb.2:                                ;   in Loop: Header=BB1_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v3, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB1_3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_gt_u32 s3, 3
	s_mov_b32 s3, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_1
.LBB1_4:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_203
; %bb.5:
	v_mbcnt_lo_u32_b32 v28, -1, 0
	v_mov_b32_e32 v3, 0
	s_load_b64 s[6:7], s[6:7], 0x50
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v0, v28
	ds_load_b32 v31, v3
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_11
; %bb.6:
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[6:7], v3, s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v3, s[6:7] offset:40
	global_load_b64 v[4:5], v3, s[6:7]
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v7
	v_and_b32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v8, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v8, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v5, v2, vcc_lo
	global_load_b64 v[4:5], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v3, v[4:7], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[6:7]
	s_cbranch_execz .LBB1_10
; %bb.7:                                ; %.preheader3.i.i.i.preheader
	v_mov_b32_e32 v4, 0
	s_mov_b32 s8, 0
.LBB1_8:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[6:7] offset:40
	global_load_b64 v[9:10], v4, s[6:7]
	v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v7, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[2:3]
	v_mov_b32_e32 v2, v5
	global_load_b64 v[5:6], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[5:8], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[7:8]
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_8
; %bb.9:                                ; %Flow386
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_10:                               ; %Flow388
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_11:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[6:7] offset:40
	global_load_b128 v[4:7], v3, s[6:7]
	v_readfirstlane_b32 s8, v1
	v_readfirstlane_b32 s9, v2
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s3, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_13
; %bb.12:
	v_dual_mov_b32 v8, s13 :: v_dual_mov_b32 v9, 0
	s_add_i32 s13, s3, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_13:
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[10:11], s[10:11], 12
	s_mov_b32 s16, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s17, s16
	v_lshlrev_b64 v[2:3], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s18, s16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, v2
	v_mov_b32_e32 v0, 33
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v1
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v8, s16
	v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v10, s18
	v_mov_b32_e32 v11, s19
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_21
; %bb.14:
	s_clause 0x1
	global_load_b64 v[12:13], v1, s[6:7] offset:32 glc
	global_load_b64 v[2:3], v1, s[6:7] offset:40
	v_mov_b32_e32 v10, s8
	s_mov_b32 s11, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v11, s9 :: v_dual_and_b32 v0, s9, v3
	v_and_b32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v3, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v3, v0
	v_add_co_u32 v8, vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v0, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v1, v[10:13], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[12:13]
	s_cbranch_execz .LBB1_17
; %bb.15:                               ; %.preheader1.i.i.i.preheader
	v_mov_b32_e32 v10, 0
	s_mov_b32 s13, 0
.LBB1_16:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_16
.LBB1_17:                               ; %Flow384
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v3, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v2, s13, 0
	global_load_b64 v[0:1], v3, s[6:7] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_19
; %bb.18:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_19:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_21
; %bb.20:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_21:                               ; %Flow385
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s3, s3, s1
	v_add_co_u32 v0, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_22:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_24
; %bb.23:                               ;   in Loop: Header=BB1_22 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_24:                               ;   in Loop: Header=BB1_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_26
; %bb.25:                               ;   in Loop: Header=BB1_22 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_27
.LBB1_26:                               ;   in Loop: Header=BB1_22 Depth=1
	s_mov_b32 s1, -1
.LBB1_27:                               ; %Flow379
                                        ;   in Loop: Header=BB1_22 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_22
; %bb.28:
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_32
; %bb.29:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[6:7] offset:40
	global_load_b64 v[9:10], v8, s[6:7] offset:24 glc
	global_load_b64 v[6:7], v8, s[6:7]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_32
; %bb.30:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_31:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_31
.LBB1_32:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, .str@rel32@lo+4
	s_addc_u32 s9, s9, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc0 .LBB1_118
; %bb.33:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v32, 2, v0
	v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v7, 1
	v_and_b32_e32 v2, -3, v0
	v_mov_b32_e32 v6, 2
	s_mov_b64 s[10:11], 22
.LBB1_34:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_37 Depth 2
                                        ;     Child Loop BB1_44 Depth 2
                                        ;     Child Loop BB1_52 Depth 2
                                        ;     Child Loop BB1_60 Depth 2
                                        ;     Child Loop BB1_68 Depth 2
                                        ;     Child Loop BB1_76 Depth 2
                                        ;     Child Loop BB1_84 Depth 2
                                        ;     Child Loop BB1_92 Depth 2
                                        ;     Child Loop BB1_100 Depth 2
                                        ;     Child Loop BB1_106 Depth 2
                                        ;     Child Loop BB1_115 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[10:11], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr18
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB1_39
; %bb.35:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB1_38
; %bb.36:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_lshl_b64 s[0:1], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[8:9]
.LBB1_37:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s14
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB1_37
.LBB1_38:                               ; %Flow355
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s18, 0
.LBB1_39:                               ; %Flow357
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[8:9]
	s_cbranch_vccnz .LBB1_41
; %bb.40:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[10:11], v30, s[8:9]
	s_add_i32 s18, s12, -8
	s_add_u32 s0, s8, 8
	s_addc_u32 s1, s9, 0
.LBB1_41:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_46
; %bb.42:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_45
; %bb.43:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB1_44:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v30, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB1_44
.LBB1_45:                               ; %Flow350
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s3, 0
	s_branch .LBB1_47
.LBB1_46:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr3
.LBB1_47:                               ; %Flow352
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_49
; %bb.48:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[12:13], v30, s[0:1]
	s_add_i32 s3, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_49:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s3, 7
	s_cbranch_scc1 .LBB1_54
; %bb.50:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_53
; %bb.51:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB1_52:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s16
	s_addc_u32 s19, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v30, s[18:19]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s3, s16
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB1_52
.LBB1_53:                               ; %Flow345
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB1_55
.LBB1_54:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB1_55:                               ; %Flow347
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_57
; %bb.56:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[14:15], v30, s[0:1]
	s_add_i32 s18, s3, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_57:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_62
; %bb.58:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_61
; %bb.59:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB1_60:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v30, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB1_60
.LBB1_61:                               ; %Flow340
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s3, 0
	s_branch .LBB1_63
.LBB1_62:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr3
.LBB1_63:                               ; %Flow342
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_65
; %bb.64:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[16:17], v30, s[0:1]
	s_add_i32 s3, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_65:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s3, 7
	s_cbranch_scc1 .LBB1_70
; %bb.66:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_69
; %bb.67:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB1_68:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s16
	s_addc_u32 s19, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v30, s[18:19]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s3, s16
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB1_68
.LBB1_69:                               ; %Flow335
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB1_71
.LBB1_70:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB1_71:                               ; %Flow337
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_73
; %bb.72:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[18:19], v30, s[0:1]
	s_add_i32 s18, s3, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_73:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB1_78
; %bb.74:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB1_77
; %bb.75:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB1_76:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v30, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB1_76
.LBB1_77:                               ; %Flow330
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s3, 0
	s_branch .LBB1_79
.LBB1_78:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr3
.LBB1_79:                               ; %Flow332
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB1_81
; %bb.80:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[20:21], v30, s[0:1]
	s_add_i32 s3, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_81:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_cmp_gt_u32 s3, 7
	s_cbranch_scc1 .LBB1_86
; %bb.82:                               ;   in Loop: Header=BB1_34 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB1_85
; %bb.83:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB1_84:                               ; %.preheader.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[16:17]
	s_add_i32 s3, s3, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[29:30]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s3, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB1_84
.LBB1_85:                               ; %Flow325
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s3, 0
	s_branch .LBB1_87
.LBB1_86:                               ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s3, -1
.LBB1_87:                               ; %Flow327
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_89
; %bb.88:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[22:23], v30, s[0:1]
.LBB1_89:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v29, v28 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v29
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_95
; %bb.90:                               ;   in Loop: Header=BB1_34 Depth=1
	global_load_b64 v[26:27], v30, s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v30, s[6:7] offset:40
	global_load_b64 v[8:9], v30, s[6:7]
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB1_94
; %bb.91:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s14, 0
.LBB1_92:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[6:7] offset:40
	global_load_b64 v[24:25], v30, s[6:7]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_92
; %bb.93:                               ; %Flow320
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_94:                               ; %Flow322
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_95:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[6:7] offset:40
	global_load_b128 v[24:27], v30, s[6:7]
	v_readfirstlane_b32 s14, v4
	v_readfirstlane_b32 s15, v5
	s_mov_b32 s19, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v8
	v_readfirstlane_b32 s17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s3, s16, 24
	s_mul_i32 s18, s16, 24
	s_and_saveexec_b32 s20, s0
	s_cbranch_execz .LBB1_97
; %bb.96:                               ;   in Loop: Header=BB1_34 Depth=1
	v_dual_mov_b32 v4, s19 :: v_dual_mov_b32 v5, v30
	s_add_i32 s19, s3, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB1_97:                               ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v32
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s19, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s19, s19, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
	s_and_b32 s19, s19, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s19
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_105
; %bb.98:                               ;   in Loop: Header=BB1_34 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v30, s[6:7] offset:32 glc
	global_load_b64 v[2:3], v30, s[6:7] offset:40
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v2
	v_readfirstlane_b32 s21, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[14:15]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s19, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s19, s19, s17
	v_add_co_u32 v8, vcc_lo, v24, s20
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v25, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v30, v[10:13], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_101
; %bb.99:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s19, 0
.LBB1_100:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[2:5], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB1_100
.LBB1_101:                              ; %Flow318
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[2:3], v30, s[6:7] offset:16
	s_mov_b32 s19, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v4, s19, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_34 Depth=1
	s_bcnt1_i32_b32 s19, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s19
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[29:30], off offset:8
.LBB1_103:                              ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_34 Depth=1
	global_load_b32 v29, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[29:30], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_105:                              ; %Flow319
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s3, s3, s1
	v_add_co_u32 v2, vcc_lo, v24, s18
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_106:                              ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_108
; %bb.107:                              ;   in Loop: Header=BB1_106 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_108:                              ;   in Loop: Header=BB1_106 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_110
; %bb.109:                              ;   in Loop: Header=BB1_106 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_111
.LBB1_110:                              ;   in Loop: Header=BB1_106 Depth=2
	s_mov_b32 s1, -1
.LBB1_111:                              ; %Flow313
                                        ;   in Loop: Header=BB1_106 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_106
; %bb.112:                              ;   in Loop: Header=BB1_34 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_116
; %bb.113:                              ;   in Loop: Header=BB1_34 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v30, s[6:7] offset:40
	global_load_b64 v[12:13], v30, s[6:7] offset:24 glc
	global_load_b64 v[10:11], v30, s[6:7]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s14
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v30, v[8:11], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_116
; %bb.114:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_mov_b32 s0, 0
.LBB1_115:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v30, v[8:11], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_115
.LBB1_116:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_34 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s8, s8, s12
	s_addc_u32 s9, s9, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB1_34
; %bb.117:                              ; %Flow358
	s_mov_b32 s0, 0
	s_branch .LBB1_119
.LBB1_118:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB1_119:                              ; %Flow373
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_148
; %bb.120:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v28
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_126
; %bb.121:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s3, exec_lo
	global_load_b64 v[6:7], v3, s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[6:7] offset:40
	global_load_b64 v[8:9], v3, s[6:7]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB1_125
; %bb.122:                              ; %.preheader3.i.i.i22.preheader
	s_mov_b32 s8, 0
.LBB1_123:                              ; %.preheader3.i.i.i22
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[6:7] offset:40
	global_load_b64 v[10:11], v3, s[6:7]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_123
; %bb.124:                              ; %Flow370
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_125:                              ; %Flow372
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_126:                              ; %.loopexit4.i.i.i17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s8, v8
	v_readfirstlane_b32 s9, v9
	s_mov_b32 s13, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[6:7] offset:40
	global_load_b128 v[4:7], v3, s[6:7]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s3, s10, 24
	s_mul_i32 s12, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_128
; %bb.127:
	v_dual_mov_b32 v8, s13 :: v_dual_mov_b32 v9, v3
	s_add_i32 s13, s3, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB1_128:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v11, s19
	v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v10, s18
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_136
; %bb.129:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s8
	v_mov_b32_e32 v12, s9
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[6:7] offset:32 glc
	global_load_b64 v[0:1], v10, s[6:7] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v0
	v_readfirstlane_b32 s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s11
	v_add_co_u32 v8, vcc_lo, v4, s14
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB1_132
; %bb.130:                              ; %.preheader1.i.i.i20.preheader
	s_mov_b32 s13, 0
.LBB1_131:                              ; %.preheader1.i.i.i20
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_131
.LBB1_132:                              ; %Flow368
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v3, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v2, s13, 0
	global_load_b64 v[0:1], v3, s[6:7] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_134
; %bb.133:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_134:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_136
; %bb.135:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_136:                              ; %Flow369
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s3, s3, s1
	v_add_co_u32 v0, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_137:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_139
; %bb.138:                              ;   in Loop: Header=BB1_137 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_139:                              ;   in Loop: Header=BB1_137 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_141
; %bb.140:                              ;   in Loop: Header=BB1_137 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_142
.LBB1_141:                              ;   in Loop: Header=BB1_137 Depth=1
	s_mov_b32 s1, -1
.LBB1_142:                              ; %Flow363
                                        ;   in Loop: Header=BB1_137 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_137
; %bb.143:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_147
; %bb.144:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[6:7] offset:40
	global_load_b64 v[9:10], v8, s[6:7] offset:24 glc
	global_load_b64 v[6:7], v8, s[6:7]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s8
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_147
; %bb.145:                              ; %.preheader.i.i.i19.preheader
	s_mov_b32 s0, 0
.LBB1_146:                              ; %.preheader.i.i.i19
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_146
.LBB1_147:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_148:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, v28
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v4
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_154
; %bb.149:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	global_load_b64 v[8:9], v5, s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[6:7] offset:40
	global_load_b64 v[6:7], v5, s[6:7]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB1_153
; %bb.150:                              ; %.preheader3.i.i.i29.preheader
	s_mov_b32 s8, 0
.LBB1_151:                              ; %.preheader3.i.i.i29
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v5, s[6:7] offset:40
	global_load_b64 v[10:11], v5, s[6:7]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_151
; %bb.152:                              ; %Flow306
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_153:                              ; %Flow308
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_154:                              ; %.loopexit4.i.i.i23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_mov_b32 s3, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v5, s[6:7] offset:40
	global_load_b128 v[6:9], v5, s[6:7]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_156
; %bb.155:
	v_dual_mov_b32 v10, s3 :: v_dual_mov_b32 v11, v5
	s_add_i32 s3, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB1_156:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_mov_b32 s16, s3
	s_mov_b32 s17, s3
	s_mov_b32 s18, s3
	s_mov_b32 s19, s3
	v_and_or_b32 v2, 0xffffff1f, v2, 32
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v4, s2
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_164
; %bb.157:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s8
	v_mov_b32_e32 v12, s9
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[6:7] offset:32 glc
	global_load_b64 v[0:1], v10, s[6:7] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v0
	v_readfirstlane_b32 s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v4, vcc_lo, v6, s14
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v7, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB1_160
; %bb.158:                              ; %.preheader1.i.i.i27.preheader
	s_mov_b32 s14, 0
.LBB1_159:                              ; %.preheader1.i.i.i27
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_159
.LBB1_160:                              ; %Flow304
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v3, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v2, s14, 0
	global_load_b64 v[0:1], v3, s[6:7] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_162
; %bb.161:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_162:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_164
; %bb.163:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_164:                              ; %Flow305
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v0, vcc_lo, v6, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_165:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_167
; %bb.166:                              ;   in Loop: Header=BB1_165 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_167:                              ;   in Loop: Header=BB1_165 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_169
; %bb.168:                              ;   in Loop: Header=BB1_165 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_170
.LBB1_169:                              ;   in Loop: Header=BB1_165 Depth=1
	s_mov_b32 s1, -1
.LBB1_170:                              ; %Flow299
                                        ;   in Loop: Header=BB1_165 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_165
; %bb.171:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_175
; %bb.172:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[6:7] offset:40
	global_load_b64 v[9:10], v8, s[6:7] offset:24 glc
	global_load_b64 v[6:7], v8, s[6:7]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_175
; %bb.173:                              ; %.preheader.i.i.i26.preheader
	s_mov_b32 s0, 0
.LBB1_174:                              ; %.preheader.i.i.i26
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_174
.LBB1_175:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v28
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v28
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_181
; %bb.176:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s8, exec_lo
	global_load_b64 v[7:8], v4, s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v4, s[6:7] offset:40
	global_load_b64 v[5:6], v4, s[6:7]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v8
	v_and_b32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v5, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[7:8]
	s_cbranch_execz .LBB1_180
; %bb.177:                              ; %.preheader3.i.i.i36.preheader
	s_mov_b32 s9, 0
.LBB1_178:                              ; %.preheader3.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[6:7] offset:40
	global_load_b64 v[9:10], v4, s[6:7]
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[3:4]
	v_mov_b32_e32 v3, v5
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_178
; %bb.179:                              ; %Flow292
	s_or_b32 exec_lo, exec_lo, s9
.LBB1_180:                              ; %Flow294
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB1_181:                              ; %.loopexit4.i.i.i30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v29, 0
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_mov_b32 s14, exec_lo
	s_clause 0x1
	global_load_b64 v[8:9], v29, s[6:7] offset:40
	global_load_b128 v[4:7], v29, s[6:7]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB1_183
; %bb.182:
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, v29
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v3, vcc_lo, s14, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[2:3], v[8:11], off offset:8
.LBB1_183:
	s_or_b32 exec_lo, exec_lo, s15
	v_cvt_f64_f32_e32 v[2:3], v31
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[8:9], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v7, s17
	v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v9, s19
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_191
; %bb.184:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s8
	v_mov_b32_e32 v10, s9
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[6:7] offset:32 glc
	global_load_b64 v[0:1], v8, s[6:7] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v0
	v_readfirstlane_b32 s15, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v6, vcc_lo, v4, s14
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v5, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB1_187
; %bb.185:                              ; %.preheader1.i.i.i34.preheader
	s_mov_b32 s14, 0
.LBB1_186:                              ; %.preheader1.i.i.i34
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[6:7] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_186
.LBB1_187:                              ; %Flow290
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v3, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v2, s14, 0
	global_load_b64 v[0:1], v3, s[6:7] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_189
; %bb.188:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_189:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_191
; %bb.190:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_191:                              ; %Flow291
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v0, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_192:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_194
; %bb.193:                              ;   in Loop: Header=BB1_192 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_194:                              ;   in Loop: Header=BB1_192 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_196
; %bb.195:                              ;   in Loop: Header=BB1_192 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_197
.LBB1_196:                              ;   in Loop: Header=BB1_192 Depth=1
	s_mov_b32 s1, -1
.LBB1_197:                              ; %Flow285
                                        ;   in Loop: Header=BB1_192 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_192
; %bb.198:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_202
; %bb.199:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[6:7] offset:40
	global_load_b64 v[7:8], v6, s[6:7] offset:24 glc
	global_load_b64 v[4:5], v6, s[6:7]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_202
; %bb.200:                              ; %.preheader.i.i.i33.preheader
	s_mov_b32 s0, 0
.LBB1_201:                              ; %.preheader.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[6:7] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_201
.LBB1_202:                              ; %__ockl_printf_append_args.exit37
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_203:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sumvec
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	sumvec, .Lfunc_end1-sumvec
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8340
; NumSgprs: 24
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"id = %d, stored = %f\n"
	.size	.str, 22

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           applyfunction
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         applyfunction.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     67
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sumvec
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         sumvec.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
