__global__ void interp3_cuda(
	float * vOutput,
	int     nPoints,
	int     xSize,
	int     ySize,
	int     zSize,
	float * gridX,
	float * gridY,
	float * gridZ,
	float * vInput,
	float * xInterp,
	float * yInterp,
	float * zInterp)
{
	int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
	if (idx >= nPoints)
	{
		return;
	}
	
	float x = xInterp[idx];
	float y = yInterp[idx];
	float z = zInterp[idx];

	if (x < gridX[0] || x > gridX[xSize-1] || 
		y < gridY[0] || y > gridY[ySize-1] || 
		z < gridZ[0] || z > gridZ[zSize-1])
	{
		vOutput[idx] = 0.0f;
		return;
	}
	
	float x0, y0, z0, x1, y1, z1;
	int ibx, itx, iby, ity, ibz, itz, im;

	ibx = 0;
	itx = xSize - 1;
	while (ibx < (itx-1))
	{
		im = ((ibx + itx) >> 1);
		if (x <= gridX[im])
		{
			itx = im;
		}		
		else
		{
			ibx = im;
		}
	}
	x0 = gridX[ibx];
	x1 = gridX[itx];
		
	iby = 0;
	ity = ySize - 1;
	while (iby < (ity-1))
	{
		im = ((iby + ity) >> 1);
		if (y <= gridY[im])
		{
			ity = im;
		}		
		else
		{
			iby = im;
		}
	}
	y0 = gridY[iby];
	y1 = gridY[ity];

	ibz = 0;
	itz = zSize - 1;
	while (ibz < (itz-1))
	{
		im = ((ibz + itz) >> 1);
		if (z <= gridZ[im])
		{
			itz = im;
		}
		else
		{
			ibz = im;
		}
	}
	z0 = gridZ[ibz];
	z1 = gridZ[itz];

	int sliceDim = xSize * ySize;
	int zOff0 = sliceDim * ibz;
	int zOff1 = zOff0 + sliceDim;
	int yOff0 = ySize * ibx;
	int yOff1 = yOff0 + ySize;

	float ax0 = (x - x0) / (x1 - x0);
	float ay0 = (y - y0) / (y1 - y0);
	float az0 = (z - z0) / (z1 - z0);
	float ax1 = 1.0f - ax0;
	float ay1 = 1.0f - ay0;
	
	float v000 = vInput[zOff0 + yOff0 + iby];
	float v001 = vInput[zOff0 + yOff0 + ity];
	float v010 = vInput[zOff0 + yOff1 + iby];
	float v011 = vInput[zOff0 + yOff1 + ity];
	float v100 = vInput[zOff1 + yOff0 + iby];
	float v101 = vInput[zOff1 + yOff0 + ity];
	float v110 = vInput[zOff1 + yOff1 + iby];
	float v111 = vInput[zOff1 + yOff1 + ity];
	
	float v00 = v000 * ay1 + v001 * ay0;
	float v01 = v010 * ay1 + v011 * ay0;
	float v10 = v100 * ay1 + v101 * ay0;
	float v11 = v110 * ay1 + v111 * ay0;
	
	float v0 = v00 * ax1 + v01 * ax0;
	float v1 = v10 * ax1 + v11 * ax0;

	vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
}
	.file	"tmpxft_0025d3e3_00000000-6_interp3_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
	.type	_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 68(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 64(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 60(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movl	%r8d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
	.globl	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.type	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, @function
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, .-_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void interp3_cuda(
	float * vOutput,
	int     nPoints,
	int     xSize,
	int     ySize,
	int     zSize,
	float * gridX,
	float * gridY,
	float * gridZ,
	float * vInput,
	float * xInterp,
	float * yInterp,
	float * zInterp)
{
	int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
	if (idx >= nPoints)
	{
		return;
	}
	
	float x = xInterp[idx];
	float y = yInterp[idx];
	float z = zInterp[idx];

	if (x < gridX[0] || x > gridX[xSize-1] || 
		y < gridY[0] || y > gridY[ySize-1] || 
		z < gridZ[0] || z > gridZ[zSize-1])
	{
		vOutput[idx] = 0.0f;
		return;
	}
	
	float x0, y0, z0, x1, y1, z1;
	int ibx, itx, iby, ity, ibz, itz, im;

	ibx = 0;
	itx = xSize - 1;
	while (ibx < (itx-1))
	{
		im = ((ibx + itx) >> 1);
		if (x <= gridX[im])
		{
			itx = im;
		}		
		else
		{
			ibx = im;
		}
	}
	x0 = gridX[ibx];
	x1 = gridX[itx];
		
	iby = 0;
	ity = ySize - 1;
	while (iby < (ity-1))
	{
		im = ((iby + ity) >> 1);
		if (y <= gridY[im])
		{
			ity = im;
		}		
		else
		{
			iby = im;
		}
	}
	y0 = gridY[iby];
	y1 = gridY[ity];

	ibz = 0;
	itz = zSize - 1;
	while (ibz < (itz-1))
	{
		im = ((ibz + itz) >> 1);
		if (z <= gridZ[im])
		{
			itz = im;
		}
		else
		{
			ibz = im;
		}
	}
	z0 = gridZ[ibz];
	z1 = gridZ[itz];

	int sliceDim = xSize * ySize;
	int zOff0 = sliceDim * ibz;
	int zOff1 = zOff0 + sliceDim;
	int yOff0 = ySize * ibx;
	int yOff1 = yOff0 + ySize;

	float ax0 = (x - x0) / (x1 - x0);
	float ay0 = (y - y0) / (y1 - y0);
	float az0 = (z - z0) / (z1 - z0);
	float ax1 = 1.0f - ax0;
	float ay1 = 1.0f - ay0;
	
	float v000 = vInput[zOff0 + yOff0 + iby];
	float v001 = vInput[zOff0 + yOff0 + ity];
	float v010 = vInput[zOff0 + yOff1 + iby];
	float v011 = vInput[zOff0 + yOff1 + ity];
	float v100 = vInput[zOff1 + yOff0 + iby];
	float v101 = vInput[zOff1 + yOff0 + ity];
	float v110 = vInput[zOff1 + yOff1 + iby];
	float v111 = vInput[zOff1 + yOff1 + ity];
	
	float v00 = v000 * ay1 + v001 * ay0;
	float v01 = v010 * ay1 + v011 * ay0;
	float v10 = v100 * ay1 + v101 * ay0;
	float v11 = v110 * ay1 + v111 * ay0;
	
	float v0 = v00 * ax1 + v01 * ax0;
	float v1 = v10 * ax1 + v11 * ax0;

	vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
}
	.text
	.file	"interp3_cuda.hip"
	.globl	_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_ # -- Begin function _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.type	_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_,@function
_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_: # @_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_, .Lfunc_end0-_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_,@object # @_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
	.quad	_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.size	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_ ; -- Begin function _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.globl	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
	.p2align	8
	.type	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_,@function
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:   ; @_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x50
	s_load_b32 s3, s[0:1], 0x5c
	s_load_b128 s[16:19], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s16, v1
	s_cbranch_execz .LBB0_26
; %bb.1:
	s_load_b128 s[12:15], s[0:1], 0x38
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b256 s[4:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v1, vcc_lo
	s_load_b32 s23, s[4:5], 0x0
	s_mov_b32 s12, exec_lo
	global_load_b32 v11, v[2:3], off
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_ngt_f32_e32 s23, v11
	s_cbranch_execz .LBB0_25
; %bb.2:
	s_ashr_i32 s3, s17, 31
	s_mov_b32 s2, s17
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	s_mov_b32 s13, exec_lo
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_add_u32 s2, s2, -4
	s_addc_u32 s3, s3, -1
	s_load_b32 s24, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmpx_nlt_f32_e32 s24, v11
	s_cbranch_execz .LBB0_24
; %bb.3:
	v_add_co_u32 v2, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v1, vcc_lo
	s_mov_b32 s14, exec_lo
	global_load_b32 v12, v[2:3], off
	s_load_b32 s21, s[6:7], 0x0
	s_load_b64 s[2:3], s[0:1], 0x48
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_ngt_f32_e32 s21, v12
	s_cbranch_execz .LBB0_23
; %bb.4:
	s_ashr_i32 s27, s18, 31
	s_mov_b32 s26, s18
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s15, s6, s26
	s_addc_u32 s16, s7, s27
	s_add_u32 s26, s15, -4
	s_addc_u32 s27, s16, -1
	s_mov_b32 s15, exec_lo
	s_load_b32 s22, s[26:27], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmpx_nlt_f32_e32 s22, v12
	s_cbranch_execz .LBB0_22
; %bb.5:
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	s_load_b32 s2, s[8:9], 0x0
	s_mov_b32 s16, exec_lo
	global_load_b32 v13, v[2:3], off
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_ngt_f32_e32 s2, v13
	s_cbranch_execz .LBB0_21
; %bb.6:
	s_ashr_i32 s27, s19, 31
	s_mov_b32 s26, s19
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[26:27], s[26:27], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s3, s8, s26
	s_addc_u32 s20, s9, s27
	s_add_u32 s26, s3, -4
	s_addc_u32 s27, s20, -1
	s_mov_b32 s20, exec_lo
	s_load_b32 s3, s[26:27], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmpx_nlt_f32_e32 s3, v13
	s_cbranch_execz .LBB0_20
; %bb.7:                                ; %.preheader
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v15, s24
	v_mov_b32_e32 v14, s23
	s_cmp_lt_i32 s17, 3
	s_cbranch_scc1 .LBB0_11
; %bb.8:                                ; %.lr.ph.preheader
	s_add_i32 s23, s17, -1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v2, s23
	s_mov_b32 s23, 0
.LBB0_9:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v6, v2
	v_ashrrev_i32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_nle_f32_e32 vcc_lo, v11, v4
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v6, v6, v3 :: v_dual_add_nc_u32 v3, -1, v2
	v_cmp_ge_i32_e32 vcc_lo, v6, v3
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %._crit_edge.loopexit
	s_or_b32 exec_lo, exec_lo, s23
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[4:5], off
	global_load_b32 v15, v[2:3], off
.LBB0_11:                               ; %._crit_edge
	s_add_i32 s4, s18, -1
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s21
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v5, s22
	s_cmp_lt_i32 s18, 3
	s_cbranch_scc1 .LBB0_15
; %bb.12:                               ; %.lr.ph180.preheader
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v2, s4
	s_mov_b32 s4, 0
.LBB0_13:                               ; %.lr.ph180
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v4, v2
	v_ashrrev_i32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[8:9], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b32 v3, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_nle_f32_e32 vcc_lo, v12, v3
	v_cndmask_b32_e32 v2, v7, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v3, -1, v2
	v_cmp_ge_i32_e32 vcc_lo, v4, v3
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %._crit_edge181.loopexit
	s_or_b32 exec_lo, exec_lo, s4
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[7:8], off
	global_load_b32 v5, v[9:10], off
.LBB0_15:                               ; %._crit_edge181
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, s2
	v_mov_b32_e32 v9, s3
	s_cmp_lt_i32 s19, 3
	s_cbranch_scc1 .LBB0_19
; %bb.16:                               ; %.lr.ph187.preheader
	s_add_i32 s2, s19, -1
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v9, s2
	s_mov_b32 s2, 0
.LBB0_17:                               ; %.lr.ph187
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v7, v9
	v_ashrrev_i32_e32 v16, 1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[17:18], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s8, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
	global_load_b32 v8, v[17:18], off
	s_waitcnt vmcnt(0)
	v_cmp_nle_f32_e32 vcc_lo, v13, v8
	v_cndmask_b32_e32 v9, v16, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v16 :: v_dual_add_nc_u32 v8, -1, v9
	v_cmp_ge_i32_e32 vcc_lo, v7, v8
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %._crit_edge188.loopexit
	s_or_b32 exec_lo, exec_lo, s2
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[16:17], 2, v[7:8]
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v8, v[16:17], off
	global_load_b32 v9, v[18:19], off
.LBB0_19:                               ; %._crit_edge188
	s_mul_i32 s2, s18, s17
	v_mul_lo_u32 v10, v6, s18
	v_mul_lo_u32 v6, v7, s2
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v12, v12, v3
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v3, v5, v3
	v_sub_f32_e32 v13, v13, v8
	v_dual_sub_f32 v8, v9, v8 :: v_dual_add_nc_u32 v7, s18, v10
	v_add_nc_u32_e32 v16, v6, v10
	v_add_nc_u32_e32 v17, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v19, v6, v7
	v_add_nc_u32_e32 v6, v16, v4
	v_add_nc_u32_e32 v16, v16, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v17, v10
	v_add_nc_u32_e32 v29, v17, v7
	v_add_nc_u32_e32 v18, v19, v4
	v_add_nc_u32_e32 v20, v19, v2
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_nc_u32_e32 v23, v10, v2
	v_add_nc_u32_e32 v25, v29, v4
	v_ashrrev_i32_e32 v19, 31, v18
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_ashrrev_i32_e32 v24, 31, v23
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_nc_u32_e32 v22, v10, v4
	v_lshlrev_b64 v[27:28], 2, v[23:24]
	v_add_nc_u32_e32 v24, v29, v2
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, s10, v18
	v_lshlrev_b64 v[29:30], 2, v[25:26]
	v_ashrrev_i32_e32 v25, 31, v24
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s10, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s11, v21, vcc_lo
	v_add_co_u32 v26, vcc_lo, s10, v27
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v28, vcc_lo
	v_ashrrev_i32_e32 v23, 31, v22
	v_add_co_u32 v28, vcc_lo, s10, v29
	v_add_co_ci_u32_e32 v29, vcc_lo, s11, v30, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v24, vcc_lo, s10, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s11, v25, vcc_lo
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	s_clause 0x3
	global_load_b32 v2, v[20:21], off
	global_load_b32 v4, v[26:27], off
	global_load_b32 v10, v[28:29], off
	global_load_b32 v24, v[24:25], off
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_div_scale_f32 v27, s3, v13, v8, v13
	v_add_co_u32 v20, vcc_lo, s10, v22
	v_add_co_ci_u32_e32 v21, vcc_lo, s11, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	s_clause 0x3
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	global_load_b32 v18, v[20:21], off
	global_load_b32 v6, v[6:7], off
	v_sub_f32_e32 v7, v11, v14
	v_sub_f32_e32 v11, v15, v14
	v_div_scale_f32 v14, null, v3, v3, v12
	v_div_scale_f32 v19, null, v8, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v5, null, v11, v11, v7
	v_rcp_f32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v21, v19
	v_div_scale_f32 v23, vcc_lo, v7, v11, v7
	v_rcp_f32_e32 v15, v5
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f32 v22, -v14, v9, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v19, v21, 1.0
	v_fma_f32 v20, -v5, v15, 1.0
	v_fmac_f32_e32 v9, v22, v9
	v_fmac_f32_e32 v21, v25, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v20, v15
	v_div_scale_f32 v20, s2, v12, v3, v12
	v_mul_f32_e32 v22, v23, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, v20, v9
	v_fma_f32 v28, -v5, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v14, v26, v20
	v_fmac_f32_e32 v22, v28, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v25, v9
	v_mul_f32_e32 v28, v27, v21
	v_fma_f32 v5, -v5, v22, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, -v14, v26, v20
	v_fma_f32 v23, -v19, v28, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v5, v15, v22
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v9, v14, v9, v26
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v5, v11, v7
	v_div_fixup_f32 v3, v9, v3, v12
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, 1.0, v3 :: v_dual_mul_f32 v4, v3, v4
	s_waitcnt vmcnt(4)
	v_mul_f32_e32 v11, v3, v24
	v_dual_fmac_f32 v11, v7, v10 :: v_dual_sub_f32 v10, 1.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v28, v23, v21 :: v_dual_mul_f32 v11, v5, v11
	v_fma_f32 v9, -v19, v28, v27
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v4, v7, v18
	v_mul_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v9, v21, v28
	v_dual_fmac_f32 v11, v10, v4 :: v_dual_fmac_f32 v2, v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v5, v5, v2
	v_div_fixup_f32 v2, v9, v8, v13
	v_mul_f32_e32 v3, v3, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v7, v6
	v_fmac_f32_e32 v5, v10, v3
	v_dual_sub_f32 v3, 1.0, v2 :: v_dual_mul_f32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v5
.LBB0_20:                               ; %Flow246
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_21:                               ; %Flow247
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_22:                               ; %Flow248
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_23:                               ; %Flow249
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_24:                               ; %Flow250
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_25:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, .Lfunc_end0-_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1944
; NumSgprs: 30
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
