#include <iostream>
#include <stdlib.h>

#include <cuda.h>
#include <curand_kernel.h>

#define WIDTH 64

using crngState = curandStatePhilox4_32_10_t;

/* Each thread gets same seed, a different sequence
   number, no offset */
__global__ void setup_curand(crngState *state, unsigned long seed, unsigned dim) {
    uint32_t xid = blockIdx.z * blockDim.x + threadIdx.x;
    uint32_t id  = blockIdx.y*dim + xid;
    if(xid >= dim) return;

    //printf("blocks: %d %d %d / %d %d %d\n", blockIdx.x, blockIdx.y, blockIdx.z, gridDim.x, gridDim.y, gridDim.z);
    //printf("threads: %d %d %d / %d %d %d\n", threadIdx.x, threadIdx.y, threadIdx.z, blockDim.x, blockDim.y, blockDim.z);
    curand_init(seed, id, 0, &state[id]);
}

__global__ void gen_image_kernel(crngState *state, unsigned int *result, unsigned dim) {
    uint32_t xid = blockIdx.z * blockDim.x + threadIdx.x;
    uint32_t id  = blockIdx.y*dim + xid;
    if(xid >= dim) return;

    crngState localState = state[id];
    unsigned int x = curand(&localState);
    state[id] = localState;
    result[id] = x;
}

unsigned int *gen_image_gpu(unsigned dim, unsigned int seed) {
    unsigned int *image = (unsigned int *)malloc(dim*dim*sizeof(unsigned int));
    unsigned int *image_d;
    crngState *state;
    
    cudaMalloc(&image_d, dim*dim*sizeof(unsigned int));
    dim3 dims(1, dim, (dim+WIDTH-1)/WIDTH);
    
    cudaMalloc(&state, WIDTH*sizeof(crngState));
    setup_curand<<< dims, WIDTH >>>(state, seed, dim);
    gen_image_kernel<<< dims, WIDTH >>>(state, image_d, dim);
    cudaMemcpy(image, image_d, dim*dim*sizeof(unsigned int), cudaMemcpyDeviceToHost);
    cudaFree(state);
    cudaFree(image_d);

    return image;
}

int main(int argc, char *argv[]) {
    if(argc != 3) {
        std::cout << "Usage: " << argv[0] << " <dim> <steps>\n";
        return 1;
    }
    int dim = atoi(argv[1]);
    int steps = atoi(argv[2]);

    unsigned int *img = gen_image_gpu(dim, steps);

    for(int i=0; i<dim; i += (dim+9)/10) {
        uint32_t id = i*dim + i;
        std::cout << i << ": " << img[id] << " " << img[id+1] << std::endl;
    }

    free(img);
    return 0;
}

	.file	"tmpxft_00307cd8_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj
	.type	_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj, @function
_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12setup_curandP24curandStatePhilox4_32_10mj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj, .-_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj
	.globl	_Z12setup_curandP24curandStatePhilox4_32_10mj
	.type	_Z12setup_curandP24curandStatePhilox4_32_10mj, @function
_Z12setup_curandP24curandStatePhilox4_32_10mj:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj
	.cfi_endproc
.LFE3876:
	.size	_Z12setup_curandP24curandStatePhilox4_32_10mj, .-_Z12setup_curandP24curandStatePhilox4_32_10mj
	.globl	_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj
	.type	_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj, @function
_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj:
.LFB3877:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3877:
	.size	_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj, .-_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj
	.globl	_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj
	.type	_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj, @function
_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj:
.LFB3878:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj
	.cfi_endproc
.LFE3878:
	.size	_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj, .-_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj
	.globl	_Z13gen_image_gpujj
	.type	_Z13gen_image_gpujj, @function
_Z13gen_image_gpujj:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edi, %ebp
	imull	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	salq	$2, %rbp
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rsp, %rdi
	movq	%rbp, %rsi
	movq	%rax, %r13
	call	cudaMalloc@PLT
	leal	63(%rbx), %eax
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	shrl	$6, %eax
	movl	$1, 16(%rsp)
	movl	%ebx, 20(%rsp)
	movl	%eax, 24(%rsp)
	call	cudaMalloc@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	salq	$6, %rdx
	movl	$1, %ecx
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	8(%rsp), %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	call	_Z59__device_stub__Z12setup_curandP24curandStatePhilox4_32_10mjP24curandStatePhilox4_32_10mj
.L14:
	movl	$67108865, %edx
	movq	16(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	24(%rsp), %esi
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, 36(%rsp)
	movq	%rdx, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z64__device_stub__Z16gen_image_kernelP24curandStatePhilox4_32_10PjjP24curandStatePhilox4_32_10Pjj
.L15:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	movq	%r13, %rax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z13gen_image_gpujj, .-_Z13gen_image_gpujj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Usage: "
.LC1:
	.string	" <dim> <steps>\n"
.LC2:
	.string	": "
.LC3:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%rcx
	.cfi_def_cfa_offset 64
	cmpl	$3, %edi
	je	.L19
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	0(%rbp), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %eax
	jmp	.L18
.L19:
	movq	8(%rsi), %rdi
	xorl	%r13d, %r13d
	xorl	%r15d, %r15d
	call	atoi@PLT
	movq	16(%rbp), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movl	%ebx, %edi
	movl	%eax, %esi
	call	_Z13gen_image_gpujj
	movl	$10, %ecx
	movq	%rax, %r12
	leal	9(%rbx), %eax
	cltd
	idivl	%ecx
	movl	%eax, %r14d
	movl	%eax, %ebp
	imull	%ebx, %r14d
	addl	%eax, %r14d
.L21:
	cmpl	%ebx, %r15d
	jge	.L24
	movl	%r15d, %esi
	leaq	_ZSt4cout(%rip), %rdi
	addl	%ebp, %r15d
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	%r13d, %eax
	movl	(%r12,%rax,4), %esi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	leal	1(%r13), %eax
	addl	%r14d, %r13d
	movl	(%r12,%rax,4), %esi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L21
.L24:
	movq	%r12, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L18:
	popq	%rdx
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj"
.LC5:
	.string	"_Z12setup_curandP24curandStatePhilox4_32_10mj"
.LC6:
	.string	"precalc_xorwow_matrix"
.LC7:
	.string	"precalc_xorwow_offset_matrix"
.LC8:
	.string	"mrg32k3aM1"
.LC9:
	.string	"mrg32k3aM2"
.LC10:
	.string	"mrg32k3aM1SubSeq"
.LC11:
	.string	"mrg32k3aM2SubSeq"
.LC12:
	.string	"mrg32k3aM1Seq"
.LC13:
	.string	"mrg32k3aM2Seq"
.LC14:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3880:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12setup_curandP24curandStatePhilox4_32_10mj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3880:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <stdlib.h>

#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define WIDTH 64

using crngState = hiprandStatePhilox4_32_10_t;

/* Each thread gets same seed, a different sequence
   number, no offset */
__global__ void setup_curand(crngState *state, unsigned long seed, unsigned dim) {
    uint32_t xid = blockIdx.z * blockDim.x + threadIdx.x;
    uint32_t id  = blockIdx.y*dim + xid;
    if(xid >= dim) return;

    //printf("blocks: %d %d %d / %d %d %d\n", blockIdx.x, blockIdx.y, blockIdx.z, gridDim.x, gridDim.y, gridDim.z);
    //printf("threads: %d %d %d / %d %d %d\n", threadIdx.x, threadIdx.y, threadIdx.z, blockDim.x, blockDim.y, blockDim.z);
    hiprand_init(seed, id, 0, &state[id]);
}

__global__ void gen_image_kernel(crngState *state, unsigned int *result, unsigned dim) {
    uint32_t xid = blockIdx.z * blockDim.x + threadIdx.x;
    uint32_t id  = blockIdx.y*dim + xid;
    if(xid >= dim) return;

    crngState localState = state[id];
    unsigned int x = hiprand(&localState);
    state[id] = localState;
    result[id] = x;
}

unsigned int *gen_image_gpu(unsigned dim, unsigned int seed) {
    unsigned int *image = (unsigned int *)malloc(dim*dim*sizeof(unsigned int));
    unsigned int *image_d;
    crngState *state;
    
    hipMalloc(&image_d, dim*dim*sizeof(unsigned int));
    dim3 dims(1, dim, (dim+WIDTH-1)/WIDTH);
    
    hipMalloc(&state, WIDTH*sizeof(crngState));
    setup_curand<<< dims, WIDTH >>>(state, seed, dim);
    gen_image_kernel<<< dims, WIDTH >>>(state, image_d, dim);
    hipMemcpy(image, image_d, dim*dim*sizeof(unsigned int), hipMemcpyDeviceToHost);
    hipFree(state);
    hipFree(image_d);

    return image;
}

int main(int argc, char *argv[]) {
    if(argc != 3) {
        std::cout << "Usage: " << argv[0] << " <dim> <steps>\n";
        return 1;
    }
    int dim = atoi(argv[1]);
    int steps = atoi(argv[2]);

    unsigned int *img = gen_image_gpu(dim, steps);

    for(int i=0; i<dim; i += (dim+9)/10) {
        uint32_t id = i*dim + i;
        std::cout << i << ": " << img[id] << " " << img[id+1] << std::endl;
    }

    free(img);
    return 0;
}

	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj # -- Begin function _Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
	.type	_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj,@function
_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj: # @_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12setup_curandP25hiprandStatePhilox4_32_10mj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj, .Lfunc_end0-_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj # -- Begin function _Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.type	_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj,@function
_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj: # @_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj, .Lfunc_end1-_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z13gen_image_gpujj             # -- Begin function _Z13gen_image_gpujj
	.type	_Z13gen_image_gpujj,@function
_Z13gen_image_gpujj:                    # @_Z13gen_image_gpujj
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, 20(%rsp)                  # 4-byte Spill
	movl	%edi, %r12d
	movabsq	$4294967360, %rbp               # imm = 0x100000040
	movl	%edi, %r14d
	imull	%r14d, %r14d
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leal	63(%r12), %r13d
	shrl	$6, %r13d
	movq	%r12, %r15
	shlq	$32, %r15
	orq	$1, %r15
	movq	%rsp, %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movq	%r15, %rdi
	movl	%r13d, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	(%rsp), %rdi
	movl	20(%rsp), %esi                  # 4-byte Reload
	movl	%r12d, %edx
	callq	_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
.LBB2_2:
	movq	%r15, %rdi
	movl	%r13d, %esi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r12d, %edx
	callq	_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
.LBB2_4:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z13gen_image_gpujj, .Lfunc_end2-_Z13gen_image_gpujj
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	cmpl	$3, %edi
	jne	.LBB3_1
# %bb.5:
	movq	8(%r14), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	16(%r14), %rdi
	callq	atoi
	movl	%ebx, %edi
	movl	%eax, %esi
	callq	_Z13gen_image_gpujj
	movq	%rax, %r14
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	testl	%ebx, %ebx
	jle	.LBB3_8
# %bb.6:                                # %.lr.ph
	movq	16(%rsp), %rax                  # 8-byte Reload
	leal	1(%rax), %ecx
	addl	$9, %eax
	movl	$3435973837, %r13d              # imm = 0xCCCCCCCD
	imulq	%rax, %r13
	shrq	$35, %r13
	imull	%r13d, %ecx
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	xorl	%ebp, %ebp
	movl	$1, %ebx
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	leal	-1(%rbx), %r12d
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.2, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r14,%r12,4), %esi
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r15
	movl	$.L.str.3, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %eax
	movl	(%r14,%rax,4), %esi
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addl	%r13d, %ebp
	addl	12(%rsp), %ebx                  # 4-byte Folded Reload
	cmpl	%ebp, 16(%rsp)                  # 4-byte Folded Reload
	jg	.LBB3_7
.LBB3_8:                                # %._crit_edge
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	jmp	.LBB3_9
.LBB3_1:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rbx
	testq	%rbx, %rbx
	je	.LBB3_2
# %bb.3:
	movq	%rbx, %rdi
	callq	strlen
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB3_4
.LBB3_2:
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cout(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_4:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$1, %eax
.LBB3_9:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12setup_curandP25hiprandStatePhilox4_32_10mj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12setup_curandP25hiprandStatePhilox4_32_10mj,@object # @_Z12setup_curandP25hiprandStatePhilox4_32_10mj
	.section	.rodata,"a",@progbits
	.globl	_Z12setup_curandP25hiprandStatePhilox4_32_10mj
	.p2align	3, 0x0
_Z12setup_curandP25hiprandStatePhilox4_32_10mj:
	.quad	_Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
	.size	_Z12setup_curandP25hiprandStatePhilox4_32_10mj, 8

	.type	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj,@object # @_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.globl	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.p2align	3, 0x0
_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj:
	.quad	_Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.size	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Usage: "
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" <dim> <steps>\n"
	.size	.L.str.1, 16

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	": "
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" "
	.size	.L.str.3, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12setup_curandP25hiprandStatePhilox4_32_10mj"
	.size	.L__unnamed_1, 47

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj"
	.size	.L__unnamed_2, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__setup_curandP25hiprandStatePhilox4_32_10mj
	.addrsig_sym _Z31__device_stub__gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12setup_curandP25hiprandStatePhilox4_32_10mj
	.addrsig_sym _Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12setup_curandP25hiprandStatePhilox4_32_10mj ; -- Begin function _Z12setup_curandP25hiprandStatePhilox4_32_10mj
	.globl	_Z12setup_curandP25hiprandStatePhilox4_32_10mj
	.p2align	8
	.type	_Z12setup_curandP25hiprandStatePhilox4_32_10mj,@function
_Z12setup_curandP25hiprandStatePhilox4_32_10mj: ; @_Z12setup_curandP25hiprandStatePhilox4_32_10mj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s4, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
	v_mad_u64_u32 v[0:1], null, 0xcd9e8d57, v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, s2, v1
	s_add_i32 s4, s2, 0x9e3779b9
	s_mul_hi_u32 s5, s3, 0xcd9e8d57
	s_add_i32 s6, s3, 0xbb67ae85
	v_xor3_b32 v5, s5, s4, v0
	v_mad_u64_u32 v[3:4], null, 0xd2511f53, v1, 0
	s_mul_i32 s4, s3, 0xcd9e8d57
	s_add_i32 s5, s3, 0x76cf5d0a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, 0xd2511f53, v5, 0
	v_xor_b32_e32 v6, s6, v4
	s_add_i32 s6, s2, 0x3c6ef372
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v1, s5, v1, v3
	v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v6, 0
	s_add_i32 s5, s3, 0x32370b8f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v3, s4, s6, v5
	v_mad_u64_u32 v[5:6], null, 0xcd9e8d57, v1, 0
	s_add_i32 s4, s2, 0xdaa66d2b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xd2511f53, v3, 0
	v_xor3_b32 v3, s4, v6, v4
	s_add_i32 s4, s3, 0xed9eba14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v6, s5, v8, v0
	v_mad_u64_u32 v[0:1], null, 0xd2511f53, v3, 0
	s_add_i32 s5, s2, 0x78dde6e4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xcd9e8d57, v6, 0
	v_xor3_b32 v1, s4, v1, v7
	s_add_i32 s4, s2, 0x1715609d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v8, s5, v4, v5
	v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v1, 0
	s_add_i32 s5, s3, 0xa9066899
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xd2511f53, v8, 0
	v_xor3_b32 v3, s4, v5, v3
	s_add_i32 s4, s3, 0x646e171e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v5, s5, v7, v0
	v_mad_u64_u32 v[0:1], null, 0xd2511f53, v3, 0
	s_add_i32 s5, s2, 0xb54cda56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xcd9e8d57, v5, 0
	v_xor3_b32 v1, s4, v1, v6
	s_add_i32 s4, s2, 0x5384540f
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v3, s5, v8, v4
	v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v1, 0
	s_add_i32 s5, s3, 0x1fd5c5a3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, 0xd2511f53, v3, 0
	v_mov_b32_e32 v3, 0
	v_xor3_b32 v1, s4, v5, v7
	s_add_i32 s4, s3, 0xdb3d7428
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v0, s5, v9, v0
	v_mad_u64_u32 v[9:10], null, 0xd2511f53, v1, 0
	s_add_i32 s5, s2, 0xf1bbcdc8
	v_mov_b32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, 0xcd9e8d57, v0, 0
	v_xor3_b32 v10, s4, v10, v8
	v_lshlrev_b64 v[7:8], 6, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v4, s5, v12, v4
	v_mad_u64_u32 v[5:6], null, 0xcd9e8d57, v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s0, v7
	v_mad_u64_u32 v[12:13], null, 0xd2511f53, v4, 0
	v_mov_b32_e32 v0, v3
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v8, vcc_lo
	s_add_i32 s0, s2, 0x8ff34781
	s_add_i32 s1, s3, 0x96a522ad
	v_xor3_b32 v4, s0, v11, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v7, v12
	v_xor3_b32 v6, s1, v9, v13
	global_store_b128 v[14:15], v[0:3], off
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	v_mov_b32_e32 v2, v3
	s_clause 0x2
	global_store_b128 v[14:15], v[4:7], off offset:16
	global_store_b128 v[14:15], v[0:3], off offset:32
	global_store_b32 v[14:15], v3, off offset:48
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12setup_curandP25hiprandStatePhilox4_32_10mj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12setup_curandP25hiprandStatePhilox4_32_10mj, .Lfunc_end0-_Z12setup_curandP25hiprandStatePhilox4_32_10mj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 772
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj ; -- Begin function _Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.globl	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
	.p2align	8
	.type	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj,@function
_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj: ; @_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s4, v1
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, s14, s4, v[1:2]
	v_mov_b32_e32 v15, 0
	v_lshlrev_b64 v[0:1], 6, v[14:15]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x2
	global_load_b32 v16, v[12:13], off offset:40
	global_load_b128 v[4:7], v[12:13], off offset:16
	global_load_b128 v[0:3], v[12:13], off
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v10, v6 :: v_dual_add_nc_u32 v17, 1, v16
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v9, v5
	v_mov_b32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_eq_u32_e32 4, v17
	s_cbranch_execz .LBB1_3
; %bb.2:
	global_load_b64 v[17:18], v[12:13], off offset:32
	s_waitcnt vmcnt(1)
	v_add_co_u32 v0, vcc_lo, v0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_add_nc_u32_e32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v19, 0, v8, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0xd2511f53, v0, 0
	v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v2, 0
	v_add_nc_u32_e32 v3, v19, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v9, v18, v9, v3
	v_xor3_b32 v11, v17, v11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
	v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
	v_add_nc_u32_e32 v9, 0x9e3779b9, v17
	v_add_nc_u32_e32 v11, 0xbb67ae85, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v20, v10, v9
	v_xor3_b32 v20, v22, v8, v11
	v_add_nc_u32_e32 v22, 0x3c6ef372, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
	v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
	v_add_nc_u32_e32 v20, 0x76cf5d0a, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v9, v9, v21, v20
	v_xor3_b32 v11, v11, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
	v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
	v_add_nc_u32_e32 v9, 0xdaa66d2b, v17
	v_add_nc_u32_e32 v11, 0x32370b8f, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v20, v10, v9
	v_xor3_b32 v20, v22, v8, v11
	v_add_nc_u32_e32 v22, 0x78dde6e4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
	v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
	v_add_nc_u32_e32 v20, 0xed9eba14, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v9, v9, v21, v20
	v_xor3_b32 v11, v11, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
	v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
	v_add_nc_u32_e32 v9, 0x1715609d, v17
	v_add_nc_u32_e32 v11, 0xa9066899, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v20, v10, v9
	v_xor3_b32 v20, v22, v8, v11
	v_add_nc_u32_e32 v22, 0xb54cda56, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
	v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
	v_add_nc_u32_e32 v20, 0x646e171e, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v9, v9, v21, v20
	v_xor3_b32 v11, v11, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
	v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
	v_add_nc_u32_e32 v9, 0x5384540f, v17
	v_add_nc_u32_e32 v11, 0x1fd5c5a3, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v9, v20, v10, v9
	v_xor3_b32 v10, v22, v8, v11
	v_add_nc_u32_e32 v11, 0xf1bbcdc8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[22:23], null, 0xd2511f53, v9, 0
	v_mad_u64_u32 v[8:9], null, 0xcd9e8d57, v10, 0
	v_add_nc_u32_e32 v10, 0xdb3d7428, v18
	v_add_nc_u32_e32 v18, 0x96a522ad, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v20, v23, v21, v10
	v_xor3_b32 v11, v9, v19, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xcd9e8d57, v20, 0
	v_mad_u64_u32 v[19:20], null, 0xd2511f53, v11, 0
	v_add_nc_u32_e32 v11, 0x8ff34781, v17
	v_mov_b32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v8, v11, v8, v10
	v_xor3_b32 v10, v18, v22, v20
	v_mov_b32_e32 v11, v19
.LBB1_3:                                ; %_Z7hiprandI25hiprandStatePhilox4_32_10EjPT_.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 1, v16
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v4, v6, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[14:15]
	v_cmp_eq_u32_e32 vcc_lo, 3, v16
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_clause 0x2
	global_store_b128 v[12:13], v[0:3], off
	global_store_b128 v[12:13], v[8:11], off offset:16
	global_store_b32 v[12:13], v17, off offset:40
	global_store_b32 v[4:5], v6, off
.LBB1_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj, .Lfunc_end1-_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 988
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12setup_curandP25hiprandStatePhilox4_32_10mj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12setup_curandP25hiprandStatePhilox4_32_10mj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
