__global__ void create_quote_index(char *file, long n, long *escape_index, long *quote_index, char *quote_carry_index, long quote_index_size) {
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;

  // We want to always calculate on 64-character boundaries, such that we can put
  // all bits of 64 characters into 1 long.
  long normal_chars_per_thread = (n+stride-1) / stride;
  long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
  long start = index * chars_per_thread;
  long end = start + chars_per_thread;

  // This will contain the bitmask of escaped characters
  long escaped = 0;

  // Temporary variable for storing the current bit index
  long bit_index = 0;

  int quote_count = 0;

  int final_loop_iteration = end;
  if (n < end) {
    final_loop_iteration = n;
  }

  for (long i = start; i < final_loop_iteration; i += 1) {
    long offsetInBlock = i % 64;

    // At the start of each boundary (including the first), set the escaped characters
    if (offsetInBlock == 0) {
      escaped = escape_index[i / 64];
    }

    if (file[i] == '"') {
      if ((escaped & (1L << offsetInBlock)) == 0) {
        bit_index = bit_index | (1L << offsetInBlock);
        quote_count++;
      }
    }

    // If we are at the end of a boundary, set our result. We do not do it
    // if we are at the end since that would reset our bit_index.
    if (offsetInBlock == 63L) {
      quote_index[i / 64] = bit_index;
      // Reset the bit index since we're starting over
      bit_index = 0;
    }
  }

  if (n < end && (final_loop_iteration - 1) % 64 != 63L && n - start > 0) {
    // In the final thread with data, we need to do this to make sure the last longs are actually set
    int final_index = (final_loop_iteration - 1) / 64;
    quote_index[final_index] = bit_index;
  }

  quote_carry_index[index] = quote_count & 1;
}

	.file	"tmpxft_00282b2a_00000000-6_create_quote_index.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l
	.type	_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l, @function
_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18create_quote_indexPclPlS0_S_l(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l, .-_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l
	.globl	_Z18create_quote_indexPclPlS0_S_l
	.type	_Z18create_quote_indexPclPlS0_S_l, @function
_Z18create_quote_indexPclPlS0_S_l:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z18create_quote_indexPclPlS0_S_lPclPlS0_S_l
	.cfi_endproc
.LFE2033:
	.size	_Z18create_quote_indexPclPlS0_S_l, .-_Z18create_quote_indexPclPlS0_S_l
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18create_quote_indexPclPlS0_S_l"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18create_quote_indexPclPlS0_S_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void create_quote_index(char *file, long n, long *escape_index, long *quote_index, char *quote_carry_index, long quote_index_size) {
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;

  // We want to always calculate on 64-character boundaries, such that we can put
  // all bits of 64 characters into 1 long.
  long normal_chars_per_thread = (n+stride-1) / stride;
  long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
  long start = index * chars_per_thread;
  long end = start + chars_per_thread;

  // This will contain the bitmask of escaped characters
  long escaped = 0;

  // Temporary variable for storing the current bit index
  long bit_index = 0;

  int quote_count = 0;

  int final_loop_iteration = end;
  if (n < end) {
    final_loop_iteration = n;
  }

  for (long i = start; i < final_loop_iteration; i += 1) {
    long offsetInBlock = i % 64;

    // At the start of each boundary (including the first), set the escaped characters
    if (offsetInBlock == 0) {
      escaped = escape_index[i / 64];
    }

    if (file[i] == '"') {
      if ((escaped & (1L << offsetInBlock)) == 0) {
        bit_index = bit_index | (1L << offsetInBlock);
        quote_count++;
      }
    }

    // If we are at the end of a boundary, set our result. We do not do it
    // if we are at the end since that would reset our bit_index.
    if (offsetInBlock == 63L) {
      quote_index[i / 64] = bit_index;
      // Reset the bit index since we're starting over
      bit_index = 0;
    }
  }

  if (n < end && (final_loop_iteration - 1) % 64 != 63L && n - start > 0) {
    // In the final thread with data, we need to do this to make sure the last longs are actually set
    int final_index = (final_loop_iteration - 1) / 64;
    quote_index[final_index] = bit_index;
  }

  quote_carry_index[index] = quote_count & 1;
}

	.text
	.file	"create_quote_index.hip"
	.globl	_Z33__device_stub__create_quote_indexPclPlS0_S_l # -- Begin function _Z33__device_stub__create_quote_indexPclPlS0_S_l
	.type	_Z33__device_stub__create_quote_indexPclPlS0_S_l,@function
_Z33__device_stub__create_quote_indexPclPlS0_S_l: # @_Z33__device_stub__create_quote_indexPclPlS0_S_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18create_quote_indexPclPlS0_S_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__create_quote_indexPclPlS0_S_l, .Lfunc_end0-_Z33__device_stub__create_quote_indexPclPlS0_S_l
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18create_quote_indexPclPlS0_S_l, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18create_quote_indexPclPlS0_S_l,@object # @_Z18create_quote_indexPclPlS0_S_l
	.section	.rodata,"a",@progbits
	.globl	_Z18create_quote_indexPclPlS0_S_l
	.p2align	3, 0x0
_Z18create_quote_indexPclPlS0_S_l:
	.quad	_Z33__device_stub__create_quote_indexPclPlS0_S_l
	.size	_Z18create_quote_indexPclPlS0_S_l, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18create_quote_indexPclPlS0_S_l"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__create_quote_indexPclPlS0_S_l
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18create_quote_indexPclPlS0_S_l
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18create_quote_indexPclPlS0_S_l ; -- Begin function _Z18create_quote_indexPclPlS0_S_l
	.globl	_Z18create_quote_indexPclPlS0_S_l
	.p2align	8
	.type	_Z18create_quote_indexPclPlS0_S_l,@function
_Z18create_quote_indexPclPlS0_S_l:      ; @_Z18create_quote_indexPclPlS0_S_l
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x30
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v6, 0
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s3, s14
	s_ashr_i32 s2, s12, 31
	s_add_u32 s13, s6, s12
	s_addc_u32 s16, s7, s2
	s_add_u32 s18, s13, -1
	s_addc_u32 s19, s16, -1
	s_add_u32 s12, s12, s2
	s_mov_b32 s3, s2
	s_addc_u32 s13, s2, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[12:13], s[12:13], s[2:3]
	v_cvt_f32_u32_e32 v1, s12
	v_cvt_f32_u32_e32 v2, s13
	s_sub_u32 s20, 0, s12
	s_subb_u32 s21, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0x4f800000, v1
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v1, v2, 0xcf800000, v1
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s16, v2
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s22, s20, s16
	s_mul_hi_u32 s24, s20, s17
	s_mul_i32 s23, s21, s17
	s_add_i32 s22, s24, s22
	s_mul_i32 s25, s20, s17
	s_add_i32 s22, s22, s23
	s_mul_hi_u32 s24, s17, s25
	s_mul_hi_u32 s26, s16, s25
	s_mul_i32 s23, s16, s25
	s_mul_hi_u32 s25, s17, s22
	s_mul_i32 s17, s17, s22
	s_mul_hi_u32 s27, s16, s22
	s_add_u32 s17, s24, s17
	s_addc_u32 s24, 0, s25
	s_add_u32 s17, s17, s23
	s_mul_i32 s22, s16, s22
	s_addc_u32 s17, s24, s26
	s_addc_u32 s23, s27, 0
	s_add_u32 s17, s17, s22
	s_addc_u32 s22, 0, s23
	v_add_co_u32 v1, s17, v1, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s17, 0
	s_addc_u32 s16, s16, s22
	v_readfirstlane_b32 s17, v1
	s_mul_i32 s22, s20, s16
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s23, s20, s17
	s_mul_i32 s21, s21, s17
	s_add_i32 s22, s23, s22
	s_mul_i32 s20, s20, s17
	s_add_i32 s22, s22, s21
	s_mul_hi_u32 s23, s16, s20
	s_mul_i32 s24, s16, s20
	s_mul_hi_u32 s20, s17, s20
	s_mul_hi_u32 s25, s17, s22
	s_mul_i32 s17, s17, s22
	s_mul_hi_u32 s21, s16, s22
	s_add_u32 s17, s20, s17
	s_addc_u32 s20, 0, s25
	s_add_u32 s17, s17, s24
	s_mul_i32 s22, s16, s22
	s_addc_u32 s17, s20, s23
	s_addc_u32 s20, s21, 0
	s_add_u32 s17, s17, s22
	s_addc_u32 s20, 0, s20
	v_add_co_u32 v1, s17, v1, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s17, 0
	s_addc_u32 s20, s16, s20
	s_ashr_i32 s16, s19, 31
	v_readfirstlane_b32 s21, v1
	s_add_u32 s18, s18, s16
	s_mov_b32 s17, s16
	s_addc_u32 s19, s19, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[18:19], s[18:19], s[16:17]
	s_mul_i32 s23, s18, s20
	s_mul_hi_u32 s24, s18, s21
	s_mul_hi_u32 s22, s18, s20
	s_mul_hi_u32 s26, s19, s21
	s_mul_i32 s21, s19, s21
	s_add_u32 s23, s24, s23
	s_addc_u32 s22, 0, s22
	s_mul_hi_u32 s25, s19, s20
	s_add_u32 s21, s23, s21
	s_mul_i32 s20, s19, s20
	s_addc_u32 s21, s22, s26
	s_addc_u32 s22, s25, 0
	s_add_u32 s20, s21, s20
	s_addc_u32 s21, 0, s22
	s_mul_i32 s25, s12, s20
	s_mul_hi_u32 s22, s12, s20
	s_mul_i32 s24, s12, s21
	v_sub_co_u32 v1, s18, s18, s25
	s_mul_i32 s23, s13, s20
	s_add_i32 s22, s22, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s22, s22, s23
	v_sub_co_u32 v2, s24, v1, s12
	s_sub_i32 s23, s19, s22
	s_cmp_lg_u32 s18, 0
	s_subb_u32 s23, s23, s13
	s_cmp_lg_u32 s24, 0
	v_readfirstlane_b32 s24, v2
	s_subb_u32 s23, s23, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s23, s13
	s_cselect_b32 s25, -1, 0
	s_cmp_ge_u32 s24, s12
	s_cselect_b32 s24, -1, 0
	s_cmp_eq_u32 s23, s13
	s_cselect_b32 s23, s24, s25
	s_add_u32 s24, s20, 1
	s_addc_u32 s25, s21, 0
	s_add_u32 s26, s20, 2
	s_addc_u32 s27, s21, 0
	s_cmp_lg_u32 s23, 0
	s_cselect_b32 s23, s26, s24
	s_cselect_b32 s24, s27, s25
	s_cmp_lg_u32 s18, 0
	v_readfirstlane_b32 s18, v1
	s_subb_u32 s19, s19, s22
	v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
	s_cmp_ge_u32 s19, s13
	s_cselect_b32 s22, -1, 0
	s_cmp_ge_u32 s18, s12
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s19, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v0, 31, v1
	s_cselect_b32 s12, s12, s22
	s_cmp_lg_u32 s12, 0
	s_cselect_b32 s13, s24, s21
	s_cselect_b32 s12, s23, s20
	s_xor_b64 s[2:3], s[16:17], s[2:3]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[12:13], s[12:13], s[2:3]
	s_sub_u32 s2, s12, s2
	s_subb_u32 s3, s13, s3
	s_add_u32 s2, s2, 63
	s_addc_u32 s3, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s12, s3, 31
	s_lshr_b32 s12, s12, 26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s2, s12
	s_addc_u32 s3, s3, 0
	s_and_not1_b32 s2, s2, 63
	v_mul_lo_u32 v4, s3, v1
	v_mul_lo_u32 v5, s2, v0
	v_mad_u64_u32 v[2:3], null, s2, v1, 0
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v4
	v_add_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_load_b64 s[2:3], s[0:1], 0x20
	s_mov_b32 s1, exec_lo
	v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[4:5]
	v_cndmask_b32_e32 v8, s6, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_cmpx_lt_i64_e64 v[2:3], v[8:9]
	s_cbranch_execz .LBB0_10
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, v3
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v6, v12
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v7, v13
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v11
	s_mov_b32 s0, exec_lo
	v_lshrrev_b32_e32 v14, 26, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v11, vcc_lo
	v_and_b32_e32 v16, 0xffffffc0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i64 v[19:20], 6, v[14:15]
	v_sub_co_u32 v16, vcc_lo, v10, v16
	v_sub_co_ci_u32_e32 v17, vcc_lo, v11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[19:20]
	v_cmpx_eq_u64_e32 0, v[16:17]
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v15, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v19, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v11, vcc_lo
	s_mov_b32 s13, exec_lo
	global_load_u8 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 34, v19
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[19:20], v16, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v22, v13, v20
	v_and_b32_e32 v21, v12, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[21:22]
	v_dual_cndmask_b32 v20, 0, v20 :: v_dual_cndmask_b32 v19, 0, v19
	v_add_co_ci_u32_e64 v18, s0, 0, v18, vcc_lo
	v_or_b32_e32 v7, v20, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_or_b32_e32 v6, v19, v6
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u64_e32 63, v[16:17]
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	global_store_b64 v[14:15], v[6:7], off
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v10, vcc_lo, v10, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i64_e32 vcc_lo, v[10:11], v[8:9]
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
; %bb.9:                                ; %._crit_edge.loopexit
	s_or_b32 exec_lo, exec_lo, s12
	v_and_b32_e32 v10, 1, v18
.LBB0_10:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v8, -1, v8
	v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[2:3]
	v_cmp_lt_i64_e64 s1, s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, 0x8000003f, v8
	v_cmp_ne_u32_e64 s0, 63, v9
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_ashrrev_i32_e32 v2, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 26, v2
	v_add_nc_u32_e32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 6, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b64 v[2:3], v[6:7], off
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v0, vcc_lo
	global_store_b8 v[1:2], v10, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18create_quote_indexPclPlS0_S_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18create_quote_indexPclPlS0_S_l, .Lfunc_end0-_Z18create_quote_indexPclPlS0_S_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1324
; NumSgprs: 30
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18create_quote_indexPclPlS0_S_l
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z18create_quote_indexPclPlS0_S_l.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
