/*This program implements the CUDA parallel version of matrix multiplication of two square matrices of equal size.
Shared Memory and thread granularity is used for optimizing performance.*/

#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>

#define TILE_WIDTH 8 /*Block Dimension of TILE_WIDTH x TILE_WIDTH*/
#define WIDTH 4096 /*WIdth of square Matrix*/
#define GRAN 2 /*Granularity - Number of blocks merged. Verified for powers of 2 i.e. 2, 4, 8, ...*/

void Matrix_Mul_gran(float *, float *, float *, int);

__global__ void Matrix_Mul_gran_Kernel(float* d_M, float* d_N, float* d_P, int Width)
{

int i, j, k;

/*allocate shared memory*/
__shared__ float ds_M[TILE_WIDTH*GRAN][TILE_WIDTH*GRAN];
__shared__ float ds_N[TILE_WIDTH*GRAN][TILE_WIDTH];

int bx, by, tx, ty, Row, Col;

/*Each thread evaluates multiple number of product elements depending on degree of granularity*/
float Pvalue[GRAN];

bx = blockIdx.x; by = blockIdx.y;
tx = threadIdx.x; ty = threadIdx.y;

Col = bx * TILE_WIDTH + tx;
Row = GRAN* by * TILE_WIDTH + ty;

for(i=0;i<GRAN;i++) Pvalue[i] = 0;
for (int m = 0; m < Width/TILE_WIDTH; m+=GRAN){
	/*Load shared memory*/
	for(i=0;i<GRAN;i++){
		ds_N[ty+i*TILE_WIDTH][tx] = d_N[Col+(m*TILE_WIDTH+ty+i*TILE_WIDTH)*Width];
		for(j=0;j<GRAN;j++){
			ds_M[ty+i*TILE_WIDTH][tx+j*TILE_WIDTH] = d_M[(Row+i*TILE_WIDTH)*Width + (m+j)*TILE_WIDTH+tx];
			}
		}
	__syncthreads();

	/*Evaluate product elements*/
	for(k=0;k<TILE_WIDTH*GRAN;k++){
		for(i=0;i<GRAN;i++){
			Pvalue[i] += ds_M[ty+i*TILE_WIDTH][k] * ds_N[k][tx];
			}
		}
	__syncthreads();
}

/*Write to device memory*/
for(i=0;i<GRAN;i++)
d_P[(Row+i*TILE_WIDTH)*Width+Col] = Pvalue[i];
}

int main(int argc, char** argv){

int W = WIDTH;
int i,j;
float *M, *N, *P;

struct timeval start, end;
long utime, seconds, useconds;    
	
M = (float*)malloc(W*W*sizeof(float));
N = (float*)malloc(W*W*sizeof(float));
P = (float*)malloc(W*W*sizeof(float));

/*Initialize the matrices to identity matrices. The result should be an identity matrix and thus can be verified easily*/
for(i =0;i<W;i++){
	for(j=0;j<W;j++){
		if(i==j){
			M[i*W+j]=1;
			N[i*W+j]=1;
			}
		else{
			M[i*W+j]=0;
			N[i*W+j]=0;
			}
	}
}

gettimeofday(&start, NULL);

/*Call function for matrix multiplication*/
Matrix_Mul_gran(M,N,P,W);
gettimeofday(&end, NULL);

seconds  = end.tv_sec  - start.tv_sec;
useconds = end.tv_usec - start.tv_usec;
utime = ((seconds) * 1000000 + useconds);

/*Print execution time in microseconds*/
printf("%d\t%ld\n", GRAN,utime);

free(M); free(N); free(P);

return 0;
}

/*Matrix multiplication function*/
void Matrix_Mul_gran(float *M, float *N, float *P, int W){
	int size = W*W*sizeof(float);
	float *Md, *Nd, *Pd;

	/*Initialize memory and copy data from host to device*/
	cudaMalloc((void**)&Md, size);
	cudaMemcpy(Md,M,size,cudaMemcpyHostToDevice);
	cudaMalloc((void**)&Nd, size);
	cudaMemcpy(Nd,N,size,cudaMemcpyHostToDevice);
	cudaMalloc((void**)&Pd, size);
	
	/*Launch Kernel*/
	/*Blocks along Grid Dimension 'Y' i.e. blockIdx.y are merged as per required granularity*/
	dim3 dimGrid(ceil(W/TILE_WIDTH), ceil(W/(TILE_WIDTH*GRAN)), 1);
	dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
	Matrix_Mul_gran_Kernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, W);

	/*Copy result from device to host and free device memory*/
	cudaMemcpy(P,Pd,size,cudaMemcpyDeviceToHost);
	cudaFree(Md); cudaFree(Nd); cudaFree(Pd); 
}

	.file	"tmpxft_00220361_00000000-6_matrix_granular.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i
	.type	_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22Matrix_Mul_gran_KernelPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i
	.globl	_Z22Matrix_Mul_gran_KernelPfS_S_i
	.type	_Z22Matrix_Mul_gran_KernelPfS_S_i, @function
_Z22Matrix_Mul_gran_KernelPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z22Matrix_Mul_gran_KernelPfS_S_i, .-_Z22Matrix_Mul_gran_KernelPfS_S_i
	.globl	_Z15Matrix_Mul_granPfS_S_i
	.type	_Z15Matrix_Mul_granPfS_S_i, @function
_Z15Matrix_Mul_granPfS_S_i:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%ecx, %ebx
	imull	%ecx, %ebx
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	sall	$2, %ebx
	leaq	8(%rsp), %rdi
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	movl	$8, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %esi
	idivl	%ecx
	movl	$16, %ecx
	movl	%eax, 32(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movabsq	$34359738376, %rdx
	movl	$1, %ecx
	movl	%eax, 36(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	call	_Z47__device_stub__Z22Matrix_Mul_gran_KernelPfS_S_iPfS_S_i
.L9:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z15Matrix_Mul_granPfS_S_i, .-_Z15Matrix_Mul_granPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d\t%ld\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$67108864, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r12
	xorl	%eax, %eax
.L13:
	movq	%rax, %rcx
	xorl	%edx, %edx
	salq	$14, %rcx
.L15:
	movss	.LC0(%rip), %xmm0
	cmpl	%eax, %edx
	je	.L14
	xorps	%xmm0, %xmm0
.L14:
	incl	%edx
	movss	%xmm0, 0(%rbp,%rcx)
	movss	%xmm0, (%rbx,%rcx)
	addq	$4, %rcx
	cmpl	$4096, %edx
	jne	.L15
	incq	%rax
	cmpq	$4096, %rax
	jne	.L13
	xorl	%esi, %esi
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	movl	$4096, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	_Z15Matrix_Mul_granPfS_S_i
	xorl	%esi, %esi
	leaq	24(%rsp), %rdi
	call	gettimeofday@PLT
	movq	24(%rsp), %rcx
	subq	8(%rsp), %rcx
	xorl	%eax, %eax
	movl	$2, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	imulq	$1000000, %rcx, %rcx
	addq	32(%rsp), %rcx
	subq	16(%rsp), %rcx
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z22Matrix_Mul_gran_KernelPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22Matrix_Mul_gran_KernelPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*This program implements the CUDA parallel version of matrix multiplication of two square matrices of equal size.
Shared Memory and thread granularity is used for optimizing performance.*/


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>

#define TILE_WIDTH 8 /*Block Dimension of TILE_WIDTH x TILE_WIDTH*/
#define WIDTH 4096 /*WIdth of square Matrix*/
#define GRAN 2 /*Granularity - Number of blocks merged. Verified for powers of 2 i.e. 2, 4, 8, ...*/

void Matrix_Mul_gran(float *, float *, float *, int);

__global__ void Matrix_Mul_gran_Kernel(float* d_M, float* d_N, float* d_P, int Width)
{

int i, j, k;

/*allocate shared memory*/
__shared__ float ds_M[TILE_WIDTH*GRAN][TILE_WIDTH*GRAN];
__shared__ float ds_N[TILE_WIDTH*GRAN][TILE_WIDTH];

int bx, by, tx, ty, Row, Col;

/*Each thread evaluates multiple number of product elements depending on degree of granularity*/
float Pvalue[GRAN];

bx = blockIdx.x; by = blockIdx.y;
tx = threadIdx.x; ty = threadIdx.y;

Col = bx * TILE_WIDTH + tx;
Row = GRAN* by * TILE_WIDTH + ty;

for(i=0;i<GRAN;i++) Pvalue[i] = 0;
for (int m = 0; m < Width/TILE_WIDTH; m+=GRAN){
	/*Load shared memory*/
	for(i=0;i<GRAN;i++){
		ds_N[ty+i*TILE_WIDTH][tx] = d_N[Col+(m*TILE_WIDTH+ty+i*TILE_WIDTH)*Width];
		for(j=0;j<GRAN;j++){
			ds_M[ty+i*TILE_WIDTH][tx+j*TILE_WIDTH] = d_M[(Row+i*TILE_WIDTH)*Width + (m+j)*TILE_WIDTH+tx];
			}
		}
	__syncthreads();

	/*Evaluate product elements*/
	for(k=0;k<TILE_WIDTH*GRAN;k++){
		for(i=0;i<GRAN;i++){
			Pvalue[i] += ds_M[ty+i*TILE_WIDTH][k] * ds_N[k][tx];
			}
		}
	__syncthreads();
}

/*Write to device memory*/
for(i=0;i<GRAN;i++)
d_P[(Row+i*TILE_WIDTH)*Width+Col] = Pvalue[i];
}

int main(int argc, char** argv){

int W = WIDTH;
int i,j;
float *M, *N, *P;

struct timeval start, end;
long utime, seconds, useconds;    
	
M = (float*)malloc(W*W*sizeof(float));
N = (float*)malloc(W*W*sizeof(float));
P = (float*)malloc(W*W*sizeof(float));

/*Initialize the matrices to identity matrices. The result should be an identity matrix and thus can be verified easily*/
for(i =0;i<W;i++){
	for(j=0;j<W;j++){
		if(i==j){
			M[i*W+j]=1;
			N[i*W+j]=1;
			}
		else{
			M[i*W+j]=0;
			N[i*W+j]=0;
			}
	}
}

gettimeofday(&start, NULL);

/*Call function for matrix multiplication*/
Matrix_Mul_gran(M,N,P,W);
gettimeofday(&end, NULL);

seconds  = end.tv_sec  - start.tv_sec;
useconds = end.tv_usec - start.tv_usec;
utime = ((seconds) * 1000000 + useconds);

/*Print execution time in microseconds*/
printf("%d\t%ld\n", GRAN,utime);

free(M); free(N); free(P);

return 0;
}

/*Matrix multiplication function*/
void Matrix_Mul_gran(float *M, float *N, float *P, int W){
	int size = W*W*sizeof(float);
	float *Md, *Nd, *Pd;

	/*Initialize memory and copy data from host to device*/
	hipMalloc((void**)&Md, size);
	hipMemcpy(Md,M,size,hipMemcpyHostToDevice);
	hipMalloc((void**)&Nd, size);
	hipMemcpy(Nd,N,size,hipMemcpyHostToDevice);
	hipMalloc((void**)&Pd, size);
	
	/*Launch Kernel*/
	/*Blocks along Grid Dimension 'Y' i.e. blockIdx.y are merged as per required granularity*/
	dim3 dimGrid(ceil(W/TILE_WIDTH), ceil(W/(TILE_WIDTH*GRAN)), 1);
	dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
	Matrix_Mul_gran_Kernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, W);

	/*Copy result from device to host and free device memory*/
	hipMemcpy(P,Pd,size,hipMemcpyDeviceToHost);
	hipFree(Md); hipFree(Nd); hipFree(Pd); 
}

	.text
	.file	"matrix_granular.hip"
	.globl	_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i # -- Begin function _Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
	.type	_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i,@function
_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i: # @_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22Matrix_Mul_gran_KernelPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i, .Lfunc_end0-_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %rbx
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %r14
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
	movl	$1065353216, %ecx               # imm = 0x3F800000
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rsi
	movq	%r14, %rdi
	xorl	%r8d, %r8d
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	movq	%r8, %r9
	shlq	$12, %r9
	addq	%r8, %r9
	xorl	%r10d, %r10d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r10, %r8
	jne	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=2
	movl	%ecx, (%rbx,%r9,4)
	movl	%ecx, (%r14,%r9,4)
	jmp	.LBB1_5
.LBB1_4:                                #   in Loop: Header=BB1_2 Depth=2
	movl	%eax, (%rsi,%r10,4)
	movl	%eax, (%rdi,%r10,4)
.LBB1_5:                                #   in Loop: Header=BB1_2 Depth=2
	incq	%r10
	cmpq	$4096, %r10                     # imm = 0x1000
	jne	.LBB1_2
# %bb.6:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r8
	addq	%rdx, %rdi
	addq	%rdx, %rsi
	cmpq	$4096, %r8                      # imm = 0x1000
	jne	.LBB1_1
# %bb.7:
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z15Matrix_Mul_granPfS_S_i
	movq	%rsp, %r13
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r13), %rax
	movq	8(%r13), %rcx
	subq	(%r12), %rax
	subq	8(%r12), %rcx
	imulq	$1000000, %rax, %rdx            # imm = 0xF4240
	addq	%rcx, %rdx
	movl	$.L.str, %edi
	movl	$2, %esi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z15Matrix_Mul_granPfS_S_i      # -- Begin function _Z15Matrix_Mul_granPfS_S_i
	.type	_Z15Matrix_Mul_granPfS_S_i,@function
_Z15Matrix_Mul_granPfS_S_i:             # @_Z15Matrix_Mul_granPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r15d
	movq	%rdx, %rbx
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	%ecx, %eax
	imull	%ecx, %eax
	shll	$2, %eax
	movslq	%eax, %r14
	leaq	16(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leal	7(%r15), %eax
	leal	15(%r15), %edi
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	cmovnsl	%r15d, %edi
	sarl	$3, %eax
	sarl	$4, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r15d, %ecx
	callq	_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
.LBB2_2:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z15Matrix_Mul_granPfS_S_i, .Lfunc_end2-_Z15Matrix_Mul_granPfS_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22Matrix_Mul_gran_KernelPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22Matrix_Mul_gran_KernelPfS_S_i,@object # @_Z22Matrix_Mul_gran_KernelPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z22Matrix_Mul_gran_KernelPfS_S_i
	.p2align	3, 0x0
_Z22Matrix_Mul_gran_KernelPfS_S_i:
	.quad	_Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
	.size	_Z22Matrix_Mul_gran_KernelPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d\t%ld\n"
	.size	.L.str, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22Matrix_Mul_gran_KernelPfS_S_i"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__Matrix_Mul_gran_KernelPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22Matrix_Mul_gran_KernelPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22Matrix_Mul_gran_KernelPfS_S_i ; -- Begin function _Z22Matrix_Mul_gran_KernelPfS_S_i
	.globl	_Z22Matrix_Mul_gran_KernelPfS_S_i
	.p2align	8
	.type	_Z22Matrix_Mul_gran_KernelPfS_S_i,@function
_Z22Matrix_Mul_gran_KernelPfS_S_i:      ; @_Z22Matrix_Mul_gran_KernelPfS_S_i
; %bb.0:                                ; %.preheader63
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 3, v1
	v_lshl_add_u32 v2, s15, 4, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 8
	s_cbranch_scc1 .LBB0_7
; %bb.1:                                ; %.preheader62.preheader
	s_ashr_i32 s3, s2, 31
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v6, 6, v5
	s_lshr_b32 s3, s3, 29
	v_lshl_add_u32 v7, v1, 2, 0x400
	v_mov_b32_e32 v4, 0
	v_lshlrev_b32_e32 v8, 2, v1
	s_add_i32 s3, s2, s3
	s_mov_b32 s8, 0
	s_ashr_i32 s3, s3, 3
.LBB0_2:                                ; %.preheader62
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_5 Depth 2
	s_lshl_b32 s9, s8, 3
	s_mov_b32 s11, -1
	s_or_b32 s10, s9, 8
	s_mov_b32 s12, 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, s12, v5
	v_add_nc_u32_e32 v11, s12, v2
	s_mov_b32 s12, 8
	v_add_nc_u32_e32 v12, s9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, v11, s2, v[1:2]
	v_mad_u64_u32 v[10:11], null, v12, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v12, s9, v9
	v_add_nc_u32_e32 v14, s10, v9
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[10:11]
	v_lshlrev_b64 v[11:12], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[14:15]
	v_add_co_u32 v9, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	global_load_b32 v9, v[9:10], off
	s_clause 0x1
	global_load_b32 v10, v[11:12], off
	global_load_b32 v11, v[13:14], off
	v_lshl_add_u32 v12, v16, 5, v8
	v_lshl_add_u32 v13, v16, 6, v8
	s_and_b32 vcc_lo, exec_lo, s11
	s_mov_b32 s11, 0
	s_waitcnt vmcnt(2)
	ds_store_b32 v12, v9 offset:1024
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v13, v10, v11 offset1:8
	s_cbranch_vccnz .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v9, v7
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ; %.preheader61
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v10, s9, v6
	s_add_i32 s9, s9, 4
	ds_load_b32 v12, v9
	ds_load_2addr_stride64_b32 v[10:11], v10 offset1:2
	v_add_nc_u32_e32 v9, 32, v9
	s_cmp_lg_u32 s9, 64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v4, v10, v12
	v_fmac_f32_e32 v3, v11, v12
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_8
.LBB0_7:
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
.LBB0_8:                                ; %.preheader
	v_mad_u64_u32 v[5:6], null, v2, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s2, 3, v5
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x1
	global_store_b32 v[5:6], v4, off
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22Matrix_Mul_gran_KernelPfS_S_i
		.amdhsa_group_segment_fixed_size 1536
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22Matrix_Mul_gran_KernelPfS_S_i, .Lfunc_end0-_Z22Matrix_Mul_gran_KernelPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1536 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1536
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22Matrix_Mul_gran_KernelPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22Matrix_Mul_gran_KernelPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
