/* Andrew Miller <amiller@dappervision.com>
 *
 * Cuda 512*512*512*4bytes test
 * 
 * According to the KinectFusion UIST 2011 paper, it's possible 
 * to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
 * 
 * This code is a simple benchmark accessing 512^3*2 short ints.
 * voxel has two 16-bit components. In this benchmark kernel, we
 * simply increment these values by a constant K. More than anything
 * it's a test of the memory bandwidth.
 *
 * On my GTX470 card, this kernel takes 10.7ms instead of ~2ms. Is there
 * a faster way to do this?
 *
 * Citation: http://dl.acm.org/citation.cfm?id=2047270 
 * Public gdocs pdf link: http://tinyurl.com/6xlznbx
 */

#include <stdio.h>
#include <cuda.h>
#include <sys/time.h>
#include <assert.h>

const int N_DATA = (512*512*512);
const int N_BYTES = (N_DATA*2);
const int N_GRID = 512*4;
const int N_BLOCK = 512;
const int N_CHUNK = 8;
const int N_FAN = N_DATA/N_GRID/N_BLOCK/N_CHUNK;
const int K = 13;
const int N_LOOPS = 10;

struct __align__(16) short8  {
    short s0, s1, s2, s3, s4, s5, s6, s7;
};

/*
  Each kernel processes several adjacent elements
  N_DATA = (N_GRID) * (N_FAN) * (N_BLOCK) * (N_CHUNK) = 512*512*512*2
 */

__device__ void _incr_short(short int &s) {
    s += K;
}

__global__ void copy_data_float(float4 *data) {
    for (int i = 0; i < N_BYTES / sizeof(float4); i ++) {
	float4 d = data[i];
    }
}

__global__ void incr_data3(short int *data) {
    // Outer loop skips by strides of N_BLOCK*N_CHUNK
    for (int i = 0; i < N_FAN; i++) {
	int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);
	int4 *dd = (int4 *) &data[idx];
	int4 d_ = *dd;
	short8 d = *((short8 *) &d_);
	_incr_short(d.s0);
	_incr_short(d.s1);
	_incr_short(d.s2);
	_incr_short(d.s3);
	_incr_short(d.s4);
	_incr_short(d.s5);
	_incr_short(d.s6);
	_incr_short(d.s7);
	*dd = *((int4 *) &d);
    }
}

/*
__global__ void incr_data1(short int *data) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    #pragma unroll
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short4 *d = (short4 *) data;
      d[(idx+j)/4].x += K;
      d[(idx+j)/4].y += K;
      d[(idx+j)/4].z += K;
      d[(idx+j)/4].w += K;
    }
  }
}



__global__ void copy_data1(short int *data, short int *out) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    #pragma unroll
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short4 *d = (short4 *) data;
      short4 *o = (short4 *) out;
      o[(idx+j)/4].x = d[(idx+j)/4].x;
      o[(idx+j)/4].y = d[(idx+j)/4].y;
      o[(idx+j)/4].z = d[(idx+j)/4].z;
      o[(idx+j)/4].w = d[(idx+j)/4].w;
    }
  }
}

__global__ void copy_data2(short int *data, short int *out) {
    // Outer loop skips by strides of N_BLOCK*N_CHUNK
    for (int i = 0; i < N_FAN; i++) {
	int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);
	int4 *dd = (int4 *) &data[idx];
	int4 *oo = (int4 *) &out[idx];
	short8 d = *((short8 *) dd);
	*oo = *((int4 *) &d);
    }
}

__global__ void incr_data2(short int *data) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short8 *d = (short8 *) data;
      d[(idx+j)/8].s0 += K;
      d[(idx+j)/8].s1 += K;
      d[(idx+j)/8].s2 += K;
      d[(idx+j)/8].s3 += K;
      d[(idx+j)/8].s4 += K;
      d[(idx+j)/8].s5 += K;
      d[(idx+j)/8].s6 += K;
      d[(idx+j)/8].s7 += K;
    }
  }
}
*/
int main(void) {
  short int *data_gpu;
  short int *data_gpuA;
  short int *data_cpu;
  
  cudaMalloc((void **) &data_gpu, N_BYTES);
  cudaMalloc((void **) &data_gpuA, N_BYTES);
  data_cpu = (short int *) calloc(N_BYTES, 1);
  cudaMemcpy(data_gpu, data_cpu, N_BYTES, cudaMemcpyHostToDevice);

  dim3 dimBlock(N_BLOCK,1,1);
  dim3 dimGrid(N_GRID,1,1);    

  cudaEvent_t e_start, e_stop;
  cudaEventCreate(&e_start);
  cudaEventCreate(&e_stop);
  cudaEventRecord(e_start);

  // Run the kernel several times
  for (int i = 0; i < N_LOOPS; i++) {
      incr_data3<<<dimGrid, dimBlock>>>(data_gpu);
      //incr_data3<<<dimGrid, dimBlock>>>(data_gpu, data_gpuA);
  }

  cudaEventRecord(e_stop);
  cudaEventSynchronize(e_stop);

  // Copy back to the host and check we have what we expect
  cudaMemcpy(data_cpu, data_gpu, N_BYTES, cudaMemcpyDeviceToHost);
  for (int i = 0; i < N_DATA; i++) {
      assert(data_cpu[i] == (short)N_LOOPS*K);
  }

  // Timing information
  float ms;
  cudaEventElapsedTime(&ms, e_start, e_stop);  
  printf("%d sweeps of %.1f megabytes in %.1fms (avg %.1fms)\n", 
	 N_LOOPS, N_BYTES/1000.0/1000.0, ms, ms/N_LOOPS);

  cudaFree(data_gpu);
  free(data_cpu);
  return 0;
}

	.file	"tmpxft_0030cf03_00000000-6_cuda_512mb_short.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11_incr_shortRs
	.type	_Z11_incr_shortRs, @function
_Z11_incr_shortRs:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z11_incr_shortRs, .-_Z11_incr_shortRs
	.globl	_Z41__device_stub__Z15copy_data_floatP6float4P6float4
	.type	_Z41__device_stub__Z15copy_data_floatP6float4P6float4, @function
_Z41__device_stub__Z15copy_data_floatP6float4P6float4:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z15copy_data_floatP6float4(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L4:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z41__device_stub__Z15copy_data_floatP6float4P6float4, .-_Z41__device_stub__Z15copy_data_floatP6float4P6float4
	.globl	_Z15copy_data_floatP6float4
	.type	_Z15copy_data_floatP6float4, @function
_Z15copy_data_floatP6float4:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z15copy_data_floatP6float4P6float4
	.cfi_endproc
.LFE2054:
	.size	_Z15copy_data_floatP6float4, .-_Z15copy_data_floatP6float4
	.globl	_Z30__device_stub__Z10incr_data3PsPs
	.type	_Z30__device_stub__Z10incr_data3PsPs, @function
_Z30__device_stub__Z10incr_data3PsPs:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10incr_data3Ps(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L10:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z30__device_stub__Z10incr_data3PsPs, .-_Z30__device_stub__Z10incr_data3PsPs
	.globl	_Z10incr_data3Ps
	.type	_Z10incr_data3Ps, @function
_Z10incr_data3Ps:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10incr_data3PsPs
	.cfi_endproc
.LFE2056:
	.size	_Z10incr_data3Ps, .-_Z10incr_data3Ps
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d sweeps of %.1f megabytes in %.1fms (avg %.1fms)\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$268435456, %esi
	movl	$10, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$268435456, %esi
	call	cudaMalloc@PLT
	movl	$1, %esi
	movl	$268435456, %edi
	call	calloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$268435456, %edx
	movq	%rax, %rsi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movl	$8388609, %eax
	leaq	32(%rsp), %rdi
	movl	$1, 56(%rsp)
	salq	$9, %rax
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	addq	$1536, %rax
	movq	%rax, 60(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L17:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	16(%rsp), %rdi
	call	_Z30__device_stub__Z10incr_data3PsPs
.L16:
	decl	%ebp
	jne	.L17
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$268435456, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movss	12(%rsp), %xmm1
	movb	$3, %al
	movsd	.LC1(%rip), %xmm0
	movl	$10, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movaps	%xmm1, %xmm2
	cvtss2sd	%xmm1, %xmm1
	divss	.LC0(%rip), %xmm2
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z10incr_data3Ps"
.LC4:
	.string	"_Z15copy_data_floatP6float4"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10incr_data3Ps(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15copy_data_floatP6float4(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1092616192
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	-1598689907
	.long	1081132791
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Andrew Miller <amiller@dappervision.com>
 *
 * Cuda 512*512*512*4bytes test
 * 
 * According to the KinectFusion UIST 2011 paper, it's possible 
 * to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
 * 
 * This code is a simple benchmark accessing 512^3*2 short ints.
 * voxel has two 16-bit components. In this benchmark kernel, we
 * simply increment these values by a constant K. More than anything
 * it's a test of the memory bandwidth.
 *
 * On my GTX470 card, this kernel takes 10.7ms instead of ~2ms. Is there
 * a faster way to do this?
 *
 * Citation: http://dl.acm.org/citation.cfm?id=2047270 
 * Public gdocs pdf link: http://tinyurl.com/6xlznbx
 */

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <assert.h>

const int N_DATA = (512*512*512);
const int N_BYTES = (N_DATA*2);
const int N_GRID = 512*4;
const int N_BLOCK = 512;
const int N_CHUNK = 8;
const int N_FAN = N_DATA/N_GRID/N_BLOCK/N_CHUNK;
const int K = 13;
const int N_LOOPS = 10;

struct __align__(16) short8  {
    short s0, s1, s2, s3, s4, s5, s6, s7;
};

/*
  Each kernel processes several adjacent elements
  N_DATA = (N_GRID) * (N_FAN) * (N_BLOCK) * (N_CHUNK) = 512*512*512*2
 */

__device__ void _incr_short(short int &s) {
    s += K;
}

__global__ void copy_data_float(float4 *data) {
    for (int i = 0; i < N_BYTES / sizeof(float4); i ++) {
	float4 d = data[i];
    }
}

__global__ void incr_data3(short int *data) {
    // Outer loop skips by strides of N_BLOCK*N_CHUNK
    for (int i = 0; i < N_FAN; i++) {
	int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);
	int4 *dd = (int4 *) &data[idx];
	int4 d_ = *dd;
	short8 d = *((short8 *) &d_);
	_incr_short(d.s0);
	_incr_short(d.s1);
	_incr_short(d.s2);
	_incr_short(d.s3);
	_incr_short(d.s4);
	_incr_short(d.s5);
	_incr_short(d.s6);
	_incr_short(d.s7);
	*dd = *((int4 *) &d);
    }
}

/*
__global__ void incr_data1(short int *data) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    #pragma unroll
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short4 *d = (short4 *) data;
      d[(idx+j)/4].x += K;
      d[(idx+j)/4].y += K;
      d[(idx+j)/4].z += K;
      d[(idx+j)/4].w += K;
    }
  }
}



__global__ void copy_data1(short int *data, short int *out) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    #pragma unroll
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short4 *d = (short4 *) data;
      short4 *o = (short4 *) out;
      o[(idx+j)/4].x = d[(idx+j)/4].x;
      o[(idx+j)/4].y = d[(idx+j)/4].y;
      o[(idx+j)/4].z = d[(idx+j)/4].z;
      o[(idx+j)/4].w = d[(idx+j)/4].w;
    }
  }
}

__global__ void copy_data2(short int *data, short int *out) {
    // Outer loop skips by strides of N_BLOCK*N_CHUNK
    for (int i = 0; i < N_FAN; i++) {
	int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);
	int4 *dd = (int4 *) &data[idx];
	int4 *oo = (int4 *) &out[idx];
	short8 d = *((short8 *) dd);
	*oo = *((int4 *) &d);
    }
}

__global__ void incr_data2(short int *data) {
  // Outer loop skips by strides of N_BLOCK*N_CHUNK
  for (int i = 0; i < N_FAN; i++) {
    int idx = blockIdx.x*(N_FAN*N_BLOCK*N_CHUNK) + i*(N_BLOCK*N_CHUNK) + threadIdx.x*(N_CHUNK);

    // Inner loop processes 16 bytes (8 short ints) at once (a chunk)
    for (int j = 0; j < N_CHUNK; j+=8, idx++) {
      short8 *d = (short8 *) data;
      d[(idx+j)/8].s0 += K;
      d[(idx+j)/8].s1 += K;
      d[(idx+j)/8].s2 += K;
      d[(idx+j)/8].s3 += K;
      d[(idx+j)/8].s4 += K;
      d[(idx+j)/8].s5 += K;
      d[(idx+j)/8].s6 += K;
      d[(idx+j)/8].s7 += K;
    }
  }
}
*/
int main(void) {
  short int *data_gpu;
  short int *data_gpuA;
  short int *data_cpu;
  
  hipMalloc((void **) &data_gpu, N_BYTES);
  hipMalloc((void **) &data_gpuA, N_BYTES);
  data_cpu = (short int *) calloc(N_BYTES, 1);
  hipMemcpy(data_gpu, data_cpu, N_BYTES, hipMemcpyHostToDevice);

  dim3 dimBlock(N_BLOCK,1,1);
  dim3 dimGrid(N_GRID,1,1);    

  hipEvent_t e_start, e_stop;
  hipEventCreate(&e_start);
  hipEventCreate(&e_stop);
  hipEventRecord(e_start);

  // Run the kernel several times
  for (int i = 0; i < N_LOOPS; i++) {
      incr_data3<<<dimGrid, dimBlock>>>(data_gpu);
      //incr_data3<<<dimGrid, dimBlock>>>(data_gpu, data_gpuA);
  }

  hipEventRecord(e_stop);
  hipEventSynchronize(e_stop);

  // Copy back to the host and check we have what we expect
  hipMemcpy(data_cpu, data_gpu, N_BYTES, hipMemcpyDeviceToHost);
  for (int i = 0; i < N_DATA; i++) {
      assert(data_cpu[i] == (short)N_LOOPS*K);
  }

  // Timing information
  float ms;
  hipEventElapsedTime(&ms, e_start, e_stop);  
  printf("%d sweeps of %.1f megabytes in %.1fms (avg %.1fms)\n", 
	 N_LOOPS, N_BYTES/1000.0/1000.0, ms, ms/N_LOOPS);

  hipFree(data_gpu);
  free(data_cpu);
  return 0;
}

	.text
	.file	"cuda_512mb_short.hip"
	.globl	_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE # -- Begin function _Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE
	.type	_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE,@function
_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE: # @_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15copy_data_floatP15HIP_vector_typeIfLj4EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE, .Lfunc_end0-_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__incr_data3Ps # -- Begin function _Z25__device_stub__incr_data3Ps
	.type	_Z25__device_stub__incr_data3Ps,@function
_Z25__device_stub__incr_data3Ps:        # @_Z25__device_stub__incr_data3Ps
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10incr_data3Ps, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__incr_data3Ps, .Lfunc_end1-_Z25__device_stub__incr_data3Ps
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x41200000                      # float 10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI2_1:
	.quad	0x4070c6f7a0b5ed8d              # double 268.43545599999999
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967808, %r14               # imm = 0x100000200
	leaq	8(%rsp), %r15
	movl	$268435456, %esi                # imm = 0x10000000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	hipMalloc
	movl	$268435456, %edi                # imm = 0x10000000
	movl	$1, %esi
	callq	calloc
	movq	%rax, %rbx
	movq	(%r15), %rdi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%rax, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$10, %ebp
	leaq	1536(%r14), %r15
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	movq	8(%rsp), %rdi
	callq	_Z25__device_stub__incr_data3Ps
.LBB2_3:                                #   in Loop: Header=BB2_1 Depth=1
	decl	%ebp
	jne	.LBB2_1
# %bb.4:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movss	(%r14), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	cvtss2sd	%xmm0, %xmm1
	divss	.LCPI2_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm2
	movsd	.LCPI2_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str, %edi
	movl	$10, %esi
	movb	$3, %al
	callq	printf
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15copy_data_floatP15HIP_vector_typeIfLj4EE, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10incr_data3Ps, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE,@object # @_Z15copy_data_floatP15HIP_vector_typeIfLj4EE
	.section	.rodata,"a",@progbits
	.globl	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE
	.p2align	3, 0x0
_Z15copy_data_floatP15HIP_vector_typeIfLj4EE:
	.quad	_Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE
	.size	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE, 8

	.type	_Z10incr_data3Ps,@object        # @_Z10incr_data3Ps
	.globl	_Z10incr_data3Ps
	.p2align	3, 0x0
_Z10incr_data3Ps:
	.quad	_Z25__device_stub__incr_data3Ps
	.size	_Z10incr_data3Ps, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d sweeps of %.1f megabytes in %.1fms (avg %.1fms)\n"
	.size	.L.str, 52

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15copy_data_floatP15HIP_vector_typeIfLj4EE"
	.size	.L__unnamed_1, 45

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10incr_data3Ps"
	.size	.L__unnamed_2, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__copy_data_floatP15HIP_vector_typeIfLj4EE
	.addrsig_sym _Z25__device_stub__incr_data3Ps
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15copy_data_floatP15HIP_vector_typeIfLj4EE
	.addrsig_sym _Z10incr_data3Ps
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE ; -- Begin function _Z15copy_data_floatP15HIP_vector_typeIfLj4EE
	.globl	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE
	.p2align	8
	.type	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE,@function
_Z15copy_data_floatP15HIP_vector_typeIfLj4EE: ; @_Z15copy_data_floatP15HIP_vector_typeIfLj4EE
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15copy_data_floatP15HIP_vector_typeIfLj4EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15copy_data_floatP15HIP_vector_typeIfLj4EE, .Lfunc_end0-_Z15copy_data_floatP15HIP_vector_typeIfLj4EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10incr_data3Ps        ; -- Begin function _Z10incr_data3Ps
	.globl	_Z10incr_data3Ps
	.p2align	8
	.type	_Z10incr_data3Ps,@function
_Z10incr_data3Ps:                       ; @_Z10incr_data3Ps
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 3, v0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v0, s15, 16, v0
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s2, v0
	s_addk_i32 s2, 0x1000
	s_cmp_eq_u32 s2, 0x10000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
	global_load_b128 v[1:4], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v7, v1, 13
	v_lshrrev_b32_e32 v1, 16, v1
	v_add_nc_u16 v8, v2, 13
	v_lshrrev_b32_e32 v9, 16, v4
	v_lshrrev_b32_e32 v10, 16, v3
	v_lshrrev_b32_e32 v2, 16, v2
	v_add_nc_u16 v3, v3, 13
	v_add_nc_u16 v4, v4, 13
	v_add_nc_u16 v9, v9, 13
	v_add_nc_u16 v10, v10, 13
	v_add_nc_u16 v2, v2, 13
	v_add_nc_u16 v1, v1, 13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_perm_b32 v4, v9, v4, 0x5040100
	v_perm_b32 v3, v10, v3, 0x5040100
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_perm_b32 v2, v2, v8, 0x5040100
	v_perm_b32 v1, v1, v7, 0x5040100
	global_store_b128 v[5:6], v[1:4], off
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10incr_data3Ps
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10incr_data3Ps, .Lfunc_end1-_Z10incr_data3Ps
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15copy_data_floatP15HIP_vector_typeIfLj4EE
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z15copy_data_floatP15HIP_vector_typeIfLj4EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10incr_data3Ps
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10incr_data3Ps.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
