/*
 * File: Histogram
 * Author: Roberts Slisans
 * Date: 03/24/2015 16:00
 * Last updated: 03/24/2014 17:32
 */

#include <stdio.h>
#include <assert.h>



/**
 * KERNEL cuAdd() - Takes 2 input arrays of same size N and adds them into C.
 * Locations are found by computing the global index of each thread.
 * @return 
 */
__global__ void cuAdd(int *a,int *b,int *c, int N)
{
	// 1D global index
    int offset = blockDim.x * blockIdx.x + threadIdx.x;
    if(offset < N)
    {
        c[offset] = a[offset] + b[offset];
    }
}

/**
 * KERNEL cuMult() - Takes two 2D matrices and multiplies them
 * @param a - 1st Matrix
 * @param b - 2nd Matrix
 * @param c - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
__global__ void cuMult(int *a, int *b, int *c, int wA, int wB, int hA)
{
    // global index
    int gidx = blockDim.x * blockIdx.x + threadIdx.x;  // col
    int gidy = blockDim.y * blockIdx.y + threadIdx.y;  // row
    
    if(gidx < wB && gidy < hA)
    {
        int sum = 0;
        for(int k=0; k<wA; k++)
        {
            // Multiply row of A by column of B
            sum += a[gidy*wA + k] * b[k*wB +gidx];
        }
        c[gidy * wB + gidx] = sum;
    }
}

/**
 * KERNEL cuMultOpti() - Takes two 2D matrices and multiplies them optimally
 * @param a - 1st Matrix
 * @param b - 2nd Matrix
 * @param c - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
__global__ void cuMultOpti(
        int *a,
        int *b,
        int *c,
        int wA,
        int wB,
        int hA)
{
#define blockTile 16
    /* Blocksize is 16x16 */
    /* Allocate shared memory */
    __shared__ int aBlock[blockTile][blockTile];
    __shared__ int bBlock[blockTile][blockTile];
    
    /* Calculate global index X, Y*/
    int gidx = blockDim.x * blockIdx.x + threadIdx.x;  // column
    int gidy = blockDim.y * blockIdx.y + threadIdx.y;   // row
    
    /* Assign shared memory and sync  */
    /* Warning, wA*gidy may be out of bounds */
    aBlock[threadIdx.x][threadIdx.y] = a[gidy*wA + threadIdx.x];
    bBlock[threadIdx.x][threadIdx.y] = b[threadIdx.y*wB + gidx];
    
    /* Make sure all of the threads have cached the memory */
    __syncthreads();
    
    /* Check if global IDs are within limits */
    if(gidx < wB && gidy < hA)
    {
        int sum = 0;
        for(int k=0; k<wA; k++)
        {
            sum += aBlock[threadIdx.y][k] * bBlock[k][threadIdx.x];
        }
        // c [gidy][gidx]
        c[gidy * wB + gidx] = sum;
        
    }
}

/**
 * HOST h_MatrixMult_Naive() - Takes two 2D matrices and multiplies them naively
 * @param a wA.hA - 1st Matrix
 * @param b wB.wA - 2nd Matrix
 * @param c hA.wB - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
void h_MatrixMult_Naive(
        int *a,
        int *b,
        int *c,
        int wA,
        int wB,
        int hA)
{
    // Iterate through all rows of a
    for(int i=0; i<hA; i++)
    {
        // Iterate through all columns of b
        for(int j=0; j<wB; j++)
        {
            // Calculate all of c[i][j] products
            int sum = 0;
            for(int k=0; k<wA; k++)
            {
                sum += a[i*wA + k] * b[k*wB + j];
            }
            assert(i*wB + j < hA*wB);
            // Index - row i of column j with column width of wB
            c[i * wB + j] = sum;
        }
    }
}



/**
 * ENTRY main() - Tests <<<>>>cuMult() kernel: Initializes memory and data on
 * the host, then memory on the device. Copies the data from host to device,
 * executes kernel with memory device pointers, copies result back to host,
 * displays results for error checking and frees allocated memory.
 * @return 
 */
int main(int argc, char ** argv)
{
    // width A
    int wA = 320;
    // height A
    int hA = 640;
    
    // width B
    int wB = 320;
    // height B
    int hB = wA;
    
    // value A
    int aValue = 1;
    // value B
    int bValue = 2;
    
    /* Fetch the test parameters */
    if(argc < 6)
    {
        printf("Using default parameters: 320 640 320 1 2\n");
    }
    else
    {
        wA = atoi(argv[1]);
        hA = atoi(argv[2]);
        wB = atoi(argv[3]);
        hB = wA;
        aValue = atoi(argv[4]);
        bValue = atoi(argv[5]);
    }
    /**
     *  Neutral - both for host and device */
    
    int wC = wB;
    int hC = hA;

    size_t size_a = sizeof(int) * wA * hA;
    size_t size_b = sizeof(int) * wB * hB;
    size_t size_c = sizeof(int) * wC * hC;
	
    
    // host 
    int *a, *b, *c, *hh_c;
    a = (int *) malloc(size_a);
    b = (int *) malloc(size_b);
    c = (int *) malloc(size_c);
    /* Host test memory */
    hh_c = (int *) malloc(size_c);
    
    assert(hh_c != NULL);
    
    /**
     *  Device specific */
    
    // device
    int *_a, *_b, *_c;
    cudaMalloc( (void **) &_a, size_a );
    cudaMalloc( (void **) &_b, size_b );
    cudaMalloc( (void **) &_c, size_c );

    /**
     Neutral */
    // initialize A
    for(int i=0; i < hA * wA; i++)
    {
        a[i] = aValue;
    }
    
    // initialize B
    for(int i=0; i < hB * wB; i++)
    {
        b[i] = bValue;
    }
    
    /**
     Device*/
    
    // copy data to GPU
    cudaMemcpy(_a, a, size_a, cudaMemcpyHostToDevice);
    cudaMemcpy(_b, b, size_b, cudaMemcpyHostToDevice);

    // x : col , y: row
    dim3 blockSize(16,16);
    // (N.x + blockSize.x - 1)/blockSize.x, (N.y + blockSize.y -1)/blockSize.y)
    dim3 gridSize((wC+15)/16, (hC+15)/16);
        
    // kernel execution
    cuMult<<< gridSize, blockSize >>>(_a, _b, _c, wA, wB, hA);
    //cuMultOpti<<< gridSize, blockSize >>>(_a, _b, _c, wA, wB, hA);

    // copy data back to CPU
    cudaMemcpy(c, _c, size_c, cudaMemcpyDeviceToHost);
    
    // compare with cpu results
    /**
     Host*/
    
    h_MatrixMult_Naive(a, b, hh_c, wA, wB, hA);
    
    // Check first and last memory location
    printf("Start: %d. Finish: %d.\n",c[2], c[wC * hC - 1]);
    
    /* Check */
    // Naive check
    int k = 0;
    while(c[k] == c[k+1])
        k++;
    printf("EQ Test: Breakpoint @ %d\n",k);
    // Device - Host check
    k = 0;
    while(c[k] == hh_c[k])
        k++;
    printf("H2D Test: Breakpoint @ %d\n",k);

    // release resources
    cudaFree(_a);
    cudaFree(_b);
    cudaFree(_c);

    free(a);
    free(b);
    free(c);
    free(hh_c);

    return 0;
}

	.file	"tmpxft_002f4982_00000000-6_Histogram.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18h_MatrixMult_NaivePiS_S_iii
	.type	_Z18h_MatrixMult_NaivePiS_S_iii, @function
_Z18h_MatrixMult_NaivePiS_S_iii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%r8d, %rax
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	salq	$2, %rax
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movq	%rax, -16(%rsp)
	movq	%rsi, -8(%rsp)
	xorl	%esi, %esi
.L3:
	cmpl	%r9d, %r11d
	jge	.L2
	movslq	%r10d, %rax
	leaq	(%rdx,%rax,4), %r15
	movslq	%esi, %rax
	leaq	(%rdi,%rax,4), %r14
	xorl	%eax, %eax
.L8:
	cmpl	%eax, %r8d
	jle	.L5
	movq	-8(%rsp), %rcx
	xorl	%ebp, %ebp
	leaq	(%rcx,%rax,4), %r12
	xorl	%ecx, %ecx
.L6:
	cmpl	%ecx, %ebx
	jle	.L11
	movl	(%r14,%rcx,4), %r13d
	imull	(%r12), %r13d
	incq	%rcx
	addl	%r13d, %ebp
	movq	-16(%rsp), %r13
	addq	%r13, %r12
	jmp	.L6
.L11:
	movl	%ebp, (%r15,%rax,4)
	incq	%rax
	jmp	.L8
.L5:
	incl	%r11d
	addl	%r8d, %r10d
	addl	%ebx, %esi
	jmp	.L3
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z18h_MatrixMult_NaivePiS_S_iii, .-_Z18h_MatrixMult_NaivePiS_S_iii
	.globl	_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i
	.type	_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i, @function
_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5cuAddPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i, .-_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i
	.globl	_Z5cuAddPiS_S_i
	.type	_Z5cuAddPiS_S_i, @function
_Z5cuAddPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z5cuAddPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z5cuAddPiS_S_i, .-_Z5cuAddPiS_S_i
	.globl	_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii
	.type	_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii, @function
_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z6cuMultPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L17:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii, .-_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii
	.globl	_Z6cuMultPiS_S_iii
	.type	_Z6cuMultPiS_S_iii, @function
_Z6cuMultPiS_S_iii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2056:
	.size	_Z6cuMultPiS_S_iii, .-_Z6cuMultPiS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Using default parameters: 320 640 320 1 2\n"
.LC1:
	.string	"Start: %d. Finish: %d.\n"
.LC2:
	.string	"EQ Test: Breakpoint @ %d\n"
.LC3:
	.string	"H2D Test: Breakpoint @ %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	cmpl	$5, %edi
	jg	.L23
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movl	$1, %r15d
	movl	$320, %r12d
	call	__printf_chk@PLT
	movl	$640, %r13d
	movl	$2, %edx
	movl	$320, %ebp
	jmp	.L24
.L23:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %r13d
	call	atoi@PLT
	movq	32(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movq	40(%rbx), %rdi
	movl	%eax, %r15d
	call	atoi@PLT
	movl	%eax, %edx
.L24:
	movslq	%ebp, %rax
	movslq	%r13d, %rcx
	movl	%edx, 44(%rsp)
	movq	%rax, %rsi
	imulq	%rcx, %rsi
	leaq	0(,%rsi,4), %rbx
	movslq	%r12d, %rsi
	imulq	%rsi, %rax
	movq	%rbx, %rdi
	movq	%rbx, 16(%rsp)
	imulq	%rsi, %rcx
	salq	$2, %rax
	movq	%rax, 24(%rsp)
	leaq	0(,%rcx,4), %rax
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	24(%rsp), %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	16(%rsp), %rsi
	leaq	56(%rsp), %rdi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%ebp, %ecx
	movl	44(%rsp), %edx
	xorl	%eax, %eax
	imull	%r13d, %ecx
.L25:
	cmpl	%eax, %ecx
	jle	.L36
	movl	%r15d, (%r14,%rax,4)
	incq	%rax
	jmp	.L25
.L36:
	movl	%ebp, %ecx
	xorl	%eax, %eax
	imull	%r12d, %ecx
.L27:
	cmpl	%eax, %ecx
	jle	.L37
	movq	8(%rsp), %rsi
	movl	%edx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L27
.L37:
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	leal	15(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %ecx
	cltd
	movl	$1, %esi
	idivl	%ecx
	movl	%eax, 92(%rsp)
	leal	15(%r13), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 96(%rsp)
	movq	92(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%r13d, %r9d
	movl	%r12d, %r8d
	movq	56(%rsp), %rdi
	movl	%ebp, %ecx
	call	_Z32__device_stub__Z6cuMultPiS_S_iiiPiS_S_iii
.L29:
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdx
	movl	%r13d, %r9d
	movl	%r12d, %r8d
	movq	8(%rsp), %rsi
	movl	%ebp, %ecx
	movq	%r14, %rdi
	call	_Z18h_MatrixMult_NaivePiS_S_iii
	movq	(%rsp), %rax
	movl	8(%rbx), %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movl	-4(%rbx,%rax), %ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L30:
	movl	(%rbx,%rax,4), %ecx
	movq	%rax, %rdx
	incq	%rax
	cmpl	(%rbx,%rax,4), %ecx
	je	.L30
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L31:
	movq	32(%rsp), %rsi
	movl	(%rbx,%rax,4), %ecx
	movq	%rax, %rdx
	incq	%rax
	cmpl	-4(%rsi,%rax,4), %ecx
	je	.L31
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.text
	.globl	_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii
	.type	_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10cuMultOptiPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L38:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii
	.globl	_Z10cuMultOptiPiS_S_iii
	.type	_Z10cuMultOptiPiS_S_iii, @function
_Z10cuMultOptiPiS_S_iii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z10cuMultOptiPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2058:
	.size	_Z10cuMultOptiPiS_S_iii, .-_Z10cuMultOptiPiS_S_iii
	.section	.rodata.str1.1
.LC4:
	.string	"_Z10cuMultOptiPiS_S_iii"
.LC5:
	.string	"_Z6cuMultPiS_S_iii"
.LC6:
	.string	"_Z5cuAddPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10cuMultOptiPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6cuMultPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5cuAddPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * File: Histogram
 * Author: Roberts Slisans
 * Date: 03/24/2015 16:00
 * Last updated: 03/24/2014 17:32
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>



/**
 * KERNEL cuAdd() - Takes 2 input arrays of same size N and adds them into C.
 * Locations are found by computing the global index of each thread.
 * @return 
 */
__global__ void cuAdd(int *a,int *b,int *c, int N)
{
	// 1D global index
    int offset = blockDim.x * blockIdx.x + threadIdx.x;
    if(offset < N)
    {
        c[offset] = a[offset] + b[offset];
    }
}

/**
 * KERNEL cuMult() - Takes two 2D matrices and multiplies them
 * @param a - 1st Matrix
 * @param b - 2nd Matrix
 * @param c - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
__global__ void cuMult(int *a, int *b, int *c, int wA, int wB, int hA)
{
    // global index
    int gidx = blockDim.x * blockIdx.x + threadIdx.x;  // col
    int gidy = blockDim.y * blockIdx.y + threadIdx.y;  // row
    
    if(gidx < wB && gidy < hA)
    {
        int sum = 0;
        for(int k=0; k<wA; k++)
        {
            // Multiply row of A by column of B
            sum += a[gidy*wA + k] * b[k*wB +gidx];
        }
        c[gidy * wB + gidx] = sum;
    }
}

/**
 * KERNEL cuMultOpti() - Takes two 2D matrices and multiplies them optimally
 * @param a - 1st Matrix
 * @param b - 2nd Matrix
 * @param c - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
__global__ void cuMultOpti(
        int *a,
        int *b,
        int *c,
        int wA,
        int wB,
        int hA)
{
#define blockTile 16
    /* Blocksize is 16x16 */
    /* Allocate shared memory */
    __shared__ int aBlock[blockTile][blockTile];
    __shared__ int bBlock[blockTile][blockTile];
    
    /* Calculate global index X, Y*/
    int gidx = blockDim.x * blockIdx.x + threadIdx.x;  // column
    int gidy = blockDim.y * blockIdx.y + threadIdx.y;   // row
    
    /* Assign shared memory and sync  */
    /* Warning, wA*gidy may be out of bounds */
    aBlock[threadIdx.x][threadIdx.y] = a[gidy*wA + threadIdx.x];
    bBlock[threadIdx.x][threadIdx.y] = b[threadIdx.y*wB + gidx];
    
    /* Make sure all of the threads have cached the memory */
    __syncthreads();
    
    /* Check if global IDs are within limits */
    if(gidx < wB && gidy < hA)
    {
        int sum = 0;
        for(int k=0; k<wA; k++)
        {
            sum += aBlock[threadIdx.y][k] * bBlock[k][threadIdx.x];
        }
        // c [gidy][gidx]
        c[gidy * wB + gidx] = sum;
        
    }
}

/**
 * HOST h_MatrixMult_Naive() - Takes two 2D matrices and multiplies them naively
 * @param a wA.hA - 1st Matrix
 * @param b wB.wA - 2nd Matrix
 * @param c hA.wB - Result Matrix
 * @param wA - length of A and depth of B
 * @param wB - length of matrix B and C
 * @param hA - depth of matrix A and C
 */
void h_MatrixMult_Naive(
        int *a,
        int *b,
        int *c,
        int wA,
        int wB,
        int hA)
{
    // Iterate through all rows of a
    for(int i=0; i<hA; i++)
    {
        // Iterate through all columns of b
        for(int j=0; j<wB; j++)
        {
            // Calculate all of c[i][j] products
            int sum = 0;
            for(int k=0; k<wA; k++)
            {
                sum += a[i*wA + k] * b[k*wB + j];
            }
            assert(i*wB + j < hA*wB);
            // Index - row i of column j with column width of wB
            c[i * wB + j] = sum;
        }
    }
}



/**
 * ENTRY main() - Tests <<<>>>cuMult() kernel: Initializes memory and data on
 * the host, then memory on the device. Copies the data from host to device,
 * executes kernel with memory device pointers, copies result back to host,
 * displays results for error checking and frees allocated memory.
 * @return 
 */
int main(int argc, char ** argv)
{
    // width A
    int wA = 320;
    // height A
    int hA = 640;
    
    // width B
    int wB = 320;
    // height B
    int hB = wA;
    
    // value A
    int aValue = 1;
    // value B
    int bValue = 2;
    
    /* Fetch the test parameters */
    if(argc < 6)
    {
        printf("Using default parameters: 320 640 320 1 2\n");
    }
    else
    {
        wA = atoi(argv[1]);
        hA = atoi(argv[2]);
        wB = atoi(argv[3]);
        hB = wA;
        aValue = atoi(argv[4]);
        bValue = atoi(argv[5]);
    }
    /**
     *  Neutral - both for host and device */
    
    int wC = wB;
    int hC = hA;

    size_t size_a = sizeof(int) * wA * hA;
    size_t size_b = sizeof(int) * wB * hB;
    size_t size_c = sizeof(int) * wC * hC;
	
    
    // host 
    int *a, *b, *c, *hh_c;
    a = (int *) malloc(size_a);
    b = (int *) malloc(size_b);
    c = (int *) malloc(size_c);
    /* Host test memory */
    hh_c = (int *) malloc(size_c);
    
    assert(hh_c != NULL);
    
    /**
     *  Device specific */
    
    // device
    int *_a, *_b, *_c;
    hipMalloc( (void **) &_a, size_a );
    hipMalloc( (void **) &_b, size_b );
    hipMalloc( (void **) &_c, size_c );

    /**
     Neutral */
    // initialize A
    for(int i=0; i < hA * wA; i++)
    {
        a[i] = aValue;
    }
    
    // initialize B
    for(int i=0; i < hB * wB; i++)
    {
        b[i] = bValue;
    }
    
    /**
     Device*/
    
    // copy data to GPU
    hipMemcpy(_a, a, size_a, hipMemcpyHostToDevice);
    hipMemcpy(_b, b, size_b, hipMemcpyHostToDevice);

    // x : col , y: row
    dim3 blockSize(16,16);
    // (N.x + blockSize.x - 1)/blockSize.x, (N.y + blockSize.y -1)/blockSize.y)
    dim3 gridSize((wC+15)/16, (hC+15)/16);
        
    // kernel execution
    cuMult<<< gridSize, blockSize >>>(_a, _b, _c, wA, wB, hA);
    //cuMultOpti<<< gridSize, blockSize >>>(_a, _b, _c, wA, wB, hA);

    // copy data back to CPU
    hipMemcpy(c, _c, size_c, hipMemcpyDeviceToHost);
    
    // compare with cpu results
    /**
     Host*/
    
    h_MatrixMult_Naive(a, b, hh_c, wA, wB, hA);
    
    // Check first and last memory location
    printf("Start: %d. Finish: %d.\n",c[2], c[wC * hC - 1]);
    
    /* Check */
    // Naive check
    int k = 0;
    while(c[k] == c[k+1])
        k++;
    printf("EQ Test: Breakpoint @ %d\n",k);
    // Device - Host check
    k = 0;
    while(c[k] == hh_c[k])
        k++;
    printf("H2D Test: Breakpoint @ %d\n",k);

    // release resources
    hipFree(_a);
    hipFree(_b);
    hipFree(_c);

    free(a);
    free(b);
    free(c);
    free(hh_c);

    return 0;
}

	.text
	.file	"Histogram.hip"
	.globl	_Z20__device_stub__cuAddPiS_S_i # -- Begin function _Z20__device_stub__cuAddPiS_S_i
	.type	_Z20__device_stub__cuAddPiS_S_i,@function
_Z20__device_stub__cuAddPiS_S_i:        # @_Z20__device_stub__cuAddPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5cuAddPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__cuAddPiS_S_i, .Lfunc_end0-_Z20__device_stub__cuAddPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__cuMultPiS_S_iii # -- Begin function _Z21__device_stub__cuMultPiS_S_iii
	.type	_Z21__device_stub__cuMultPiS_S_iii,@function
_Z21__device_stub__cuMultPiS_S_iii:     # @_Z21__device_stub__cuMultPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6cuMultPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__cuMultPiS_S_iii, .Lfunc_end1-_Z21__device_stub__cuMultPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__cuMultOptiPiS_S_iii # -- Begin function _Z25__device_stub__cuMultOptiPiS_S_iii
	.type	_Z25__device_stub__cuMultOptiPiS_S_iii,@function
_Z25__device_stub__cuMultOptiPiS_S_iii: # @_Z25__device_stub__cuMultOptiPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10cuMultOptiPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__cuMultOptiPiS_S_iii, .Lfunc_end2-_Z25__device_stub__cuMultOptiPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18h_MatrixMult_NaivePiS_S_iii # -- Begin function _Z18h_MatrixMult_NaivePiS_S_iii
	.type	_Z18h_MatrixMult_NaivePiS_S_iii,@function
_Z18h_MatrixMult_NaivePiS_S_iii:        # @_Z18h_MatrixMult_NaivePiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, -36(%rsp)                 # 4-byte Spill
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%r9d, %r9d
	jle	.LBB3_7
# %bb.1:                                # %.preheader27.lr.ph
	movslq	-36(%rsp), %rax                 # 4-byte Folded Reload
	movl	%r9d, %r8d
	movl	%eax, %r10d
	movl	%ecx, %r11d
	movq	%rax, -32(%rsp)                 # 8-byte Spill
	leaq	(,%rax,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB3_2:                                # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
                                        #       Child Loop BB3_9 Depth 3
	cmpl	$0, -36(%rsp)                   # 4-byte Folded Reload
	jle	.LBB3_6
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r12
	movq	%r15, %rax
	imulq	-32(%rsp), %rax                 # 8-byte Folded Reload
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%rax,4), %r13
	movq	-16(%rsp), %rdi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB3_4:                                # %.preheader
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_9 Depth 3
	testl	%ecx, %ecx
	jle	.LBB3_5
# %bb.8:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_4 Depth=2
	xorl	%esi, %esi
	movq	%rdi, %rbp
	xorl	%edx, %edx
.LBB3_9:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        #     Parent Loop BB3_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%rbp), %r9d
	imull	(%r12,%rsi,4), %r9d
	addl	%r9d, %edx
	incq	%rsi
	addq	%rbx, %rbp
	cmpq	%rsi, %r11
	jne	.LBB3_9
	jmp	.LBB3_10
.LBB3_5:                                #   in Loop: Header=BB3_4 Depth=2
	xorl	%edx, %edx
.LBB3_10:                               # %._crit_edge
                                        #   in Loop: Header=BB3_4 Depth=2
	movl	%edx, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rdi
	cmpq	%r10, %rax
	jne	.LBB3_4
.LBB3_6:                                # %._crit_edge31
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%r15
	addl	%ecx, %r14d
	cmpq	%r8, %r15
	jne	.LBB3_2
.LBB3_7:                                # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z18h_MatrixMult_NaivePiS_S_iii, .Lfunc_end3-_Z18h_MatrixMult_NaivePiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$5, %edi
	jg	.LBB4_2
# %bb.1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$640, %r14d                     # imm = 0x280
	movl	$320, %r15d                     # imm = 0x140
	movl	$1, %ebp
	movl	$2, %r13d
	movl	$320, %r12d                     # imm = 0x140
	jmp	.LBB4_3
.LBB4_2:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r12d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %r15d
	movq	32(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	40(%rbx), %rdi
	callq	atoi
	movl	%eax, %r13d
.LBB4_3:
	movl	%r12d, 4(%rsp)                  # 4-byte Spill
	movq	%r14, 48(%rsp)                  # 8-byte Spill
	movslq	%r12d, %rcx
	movslq	%r14d, %rax
	movq	%rcx, %r14
	imulq	%rax, %r14
	shlq	$2, %r14
	movq	%r15, 40(%rsp)                  # 8-byte Spill
	movslq	%r15d, %rbx
	shlq	$2, %rbx
	imulq	%rbx, %rcx
	movq	%rcx, %r15
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	imulq	%rax, %rbx
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r12
	leaq	24(%rsp), %rdi
	movq	%r14, 64(%rsp)                  # 8-byte Spill
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%rbx, 80(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movq	56(%rsp), %rbx                  # 8-byte Reload
	callq	hipMalloc
	movl	4(%rsp), %eax                   # 4-byte Reload
	movl	%eax, %edx
	imull	48(%rsp), %eax                  # 4-byte Folded Reload
	testl	%eax, %eax
	jle	.LBB4_6
# %bb.4:                                # %.lr.ph.preheader
	movl	%eax, %eax
	xorl	%ecx, %ecx
.LBB4_5:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebp, (%rbx,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_5
.LBB4_6:                                # %.preheader
	movl	%edx, %eax
	imull	40(%rsp), %eax                  # 4-byte Folded Reload
	testl	%eax, %eax
	movq	72(%rsp), %r14                  # 8-byte Reload
	jle	.LBB4_9
# %bb.7:                                # %.lr.ph91.preheader
	movl	%eax, %eax
	xorl	%ecx, %ecx
.LBB4_8:                                # %.lr.ph91
                                        # =>This Inner Loop Header: Depth=1
	movl	%r13d, (%r14,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_8
.LBB4_9:                                # %._crit_edge
	movq	24(%rsp), %rdi
	movq	%rbx, %rsi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movq	%r14, %rsi
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rbp                  # 8-byte Reload
	leal	15(%rbp), %eax
	leal	30(%rbp), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$4, %ecx
	movq	48(%rsp), %r13                  # 8-byte Reload
	leal	15(%r13), %eax
	leal	30(%r13), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$4, %edi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_11
# %bb.10:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx                   # 4-byte Reload
	movl	%ebp, %r8d
	movl	%r13d, %r9d
	callq	_Z21__device_stub__cuMultPiS_S_iii
.LBB4_11:
	movq	8(%rsp), %rsi
	movq	%r15, %rdi
	movq	80(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	4(%rsp), %ecx                   # 4-byte Reload
	movl	%ebp, %r8d
	movl	%r13d, %r9d
	callq	_Z18h_MatrixMult_NaivePiS_S_iii
	movl	8(%r15), %esi
	imull	%ebp, %r13d
	movslq	%r13d, %rax
	movl	-4(%r15,%rax,4), %edx
	xorl	%r13d, %r13d
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%r15), %eax
.LBB4_12:                               # =>This Inner Loop Header: Depth=1
	movq	%r13, %rcx
	incq	%r13
	cmpl	4(%r15,%rcx,4), %eax
	je	.LBB4_12
# %bb.13:
	decl	%r13d
	xorl	%ebp, %ebp
	movl	$.L.str.2, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
.LBB4_14:                               # =>This Inner Loop Header: Depth=1
	movq	%rbp, %rax
	movl	(%r15,%rbp,4), %ecx
	incq	%rbp
	cmpl	(%r12,%rax,4), %ecx
	je	.LBB4_14
# %bb.15:
	decl	%ebp
	movl	$.L.str.3, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5cuAddPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6cuMultPiS_S_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10cuMultOptiPiS_S_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5cuAddPiS_S_i,@object         # @_Z5cuAddPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z5cuAddPiS_S_i
	.p2align	3, 0x0
_Z5cuAddPiS_S_i:
	.quad	_Z20__device_stub__cuAddPiS_S_i
	.size	_Z5cuAddPiS_S_i, 8

	.type	_Z6cuMultPiS_S_iii,@object      # @_Z6cuMultPiS_S_iii
	.globl	_Z6cuMultPiS_S_iii
	.p2align	3, 0x0
_Z6cuMultPiS_S_iii:
	.quad	_Z21__device_stub__cuMultPiS_S_iii
	.size	_Z6cuMultPiS_S_iii, 8

	.type	_Z10cuMultOptiPiS_S_iii,@object # @_Z10cuMultOptiPiS_S_iii
	.globl	_Z10cuMultOptiPiS_S_iii
	.p2align	3, 0x0
_Z10cuMultOptiPiS_S_iii:
	.quad	_Z25__device_stub__cuMultOptiPiS_S_iii
	.size	_Z10cuMultOptiPiS_S_iii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Start: %d. Finish: %d.\n"
	.size	.L.str.1, 24

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"EQ Test: Breakpoint @ %d\n"
	.size	.L.str.2, 26

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"H2D Test: Breakpoint @ %d\n"
	.size	.L.str.3, 27

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5cuAddPiS_S_i"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6cuMultPiS_S_iii"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10cuMultOptiPiS_S_iii"
	.size	.L__unnamed_3, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Using default parameters: 320 640 320 1 2"
	.size	.Lstr, 42

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__cuAddPiS_S_i
	.addrsig_sym _Z21__device_stub__cuMultPiS_S_iii
	.addrsig_sym _Z25__device_stub__cuMultOptiPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5cuAddPiS_S_i
	.addrsig_sym _Z6cuMultPiS_S_iii
	.addrsig_sym _Z10cuMultOptiPiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5cuAddPiS_S_i         ; -- Begin function _Z5cuAddPiS_S_i
	.globl	_Z5cuAddPiS_S_i
	.p2align	8
	.type	_Z5cuAddPiS_S_i,@function
_Z5cuAddPiS_S_i:                        ; @_Z5cuAddPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5cuAddPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5cuAddPiS_S_i, .Lfunc_end0-_Z5cuAddPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6cuMultPiS_S_iii      ; -- Begin function _Z6cuMultPiS_S_iii
	.globl	_Z6cuMultPiS_S_iii
	.p2align	8
	.type	_Z6cuMultPiS_S_iii,@function
_Z6cuMultPiS_S_iii:                     ; @_Z6cuMultPiS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s4
	v_mov_b32_e32 v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_add_i32 s4, s4, -1
	s_cmp_eq_u32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v8, v[3:4], off
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s5, v5
	s_cbranch_scc0 .LBB1_3
	s_branch .LBB1_5
.LBB1_4:
	v_mov_b32_e32 v2, 0
.LBB1_5:                                ; %Flow54
	v_mad_u64_u32 v[3:4], null, v1, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6cuMultPiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6cuMultPiS_S_iii, .Lfunc_end1-_Z6cuMultPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10cuMultOptiPiS_S_iii ; -- Begin function _Z10cuMultOptiPiS_S_iii
	.globl	_Z10cuMultOptiPiS_S_iii
	.p2align	8
	.type	_Z10cuMultOptiPiS_S_iii,@function
_Z10cuMultOptiPiS_S_iii:                ; @_Z10cuMultOptiPiS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_load_b128 s[8:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, v0, s4, v[4:5]
	v_mov_b32_e32 v6, 0
	v_mad_u64_u32 v[7:8], null, v3, s5, v[1:2]
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v8, v6
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	global_load_b32 v2, v[5:6], off
	global_load_b32 v5, v[7:8], off
	v_lshlrev_b32_e32 v6, 2, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, v4, 6, v6
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v6, v2, v5 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_6
; %bb.1:                                ; %.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 6, v3
	v_lshl_add_u32 v4, v4, 2, 0x400
.LBB2_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v7, v3
	ds_load_b32 v8, v4
	v_add_nc_u32_e32 v4, 64, v4
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s4, 0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, v8, v7, v[2:3]
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v3, 4, v3
	s_cbranch_scc0 .LBB2_3
	s_branch .LBB2_5
.LBB2_4:
	v_mov_b32_e32 v2, 0
.LBB2_5:                                ; %Flow54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v0, s5, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10cuMultOptiPiS_S_iii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10cuMultOptiPiS_S_iii, .Lfunc_end2-_Z10cuMultOptiPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5cuAddPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5cuAddPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6cuMultPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6cuMultPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10cuMultOptiPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10cuMultOptiPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
