/***
  Implementation of Spatial Transformer Networks[1]

  Under Simplified BSD License
  by Che-Wei Lin

  [1] Max Jaderberg et al. Spatial Transformer Networks. NIPS 2015
***/

__global__ void AffineForward(const float* bottom_data,
    const int* bs, const float* affine, const int len, float* top_data) {
    // bs = bottomSize

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bs[0];
    int w = (index / bs[0]) % bs[1];
    int c = (index / bs[0] / bs[1]) % bs[2];
    int n = index / bs[0] / bs[1] / bs[2];

    // get current affine start index
    const float* a = affine + n*6;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bs[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bs[0]-0.5); //-1~1

    float w_new = ((a[0]*nw + a[2]*nh + a[4])/2.0+0.5)*(float)bs[1];
    float h_new = ((a[1]*nw + a[3]*nh + a[5])/2.0+0.5)*(float)bs[0];

    // calc neighbor pixel index, if > size or < size, do
    float v = 0.0;
    for (int x = floor(w_new); x <= ceil(w_new); x++) {
      for (int y = floor(h_new); y <= ceil(h_new); y++) {
        if (x < 0 || x>= bs[1] || y < 0 || y >= bs[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*len/bs[3] + c*bs[1]*bs[0] + x*bs[0] + y];
        }
        top_data[index] += v * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
      }
    }

}

__global__ void AffineBackward(const float* bottom_data,
    const int* bs, const float* affine, const int len, const float* top_data, const float* top_diff, float* bottom_diff1, float* bottom_diff2) {
    // bs = bottomSize

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bs[0];
    int w = (index / bs[0]) % bs[1];
    int c = (index / bs[0] / bs[1]) % bs[2];
    int n = index / bs[0] / bs[1] / bs[2];

    // get current affine start index
    const float* a = affine + n*6;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bs[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bs[0]-0.5); //-1~1

    float w_new = ((a[0]*nw + a[2]*nh + a[4])/2.0+0.5)*(float)bs[1];
    float h_new = ((a[1]*nw + a[3]*nh + a[5])/2.0+0.5)*(float)bs[0];

    float u = 0.0;
    float dx = 0.0;
    float dy = 0.0;
    for (int x = max(floor(w_new),0.0); x <= min(ceil(w_new),(float)bs[1]); x++) {
      for (int y = max(floor(h_new),0.0); y <= min(ceil(h_new),(float)bs[0]); y++) {
          u = bottom_data[n*bs[2]*bs[1]*bs[0] + c*bs[1]*bs[0] + x*bs[0] + y];
          atomicAdd(bottom_diff1 + (n*bs[2]*bs[1]*bs[0] + c*bs[1]*bs[0] + x*bs[0] + y),  top_diff[index] * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y))  );
          dx += u * (1-abs(h_new - (float)y)) * ((float)x >= w_new ? 1.0:-1.0 );
          dy += u * (1-abs(w_new - (float)x)) * ((float)y >= h_new ? 1.0:-1.0 );
      }
    }
    
    atomicAdd((bottom_diff2+n*6)+0, nw *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+2, nh *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+4, 1.0*dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+1, nw *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+3, nh *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+5, 1.0*dy*top_diff[index]);
}
	.file	"tmpxft_0022830d_00000000-6_affine.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.type	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf, @function
_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13AffineForwardPKfPKiS0_iPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf, .-_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.type	_Z13AffineForwardPKfPKiS0_iPf, @function
_Z13AffineForwardPKfPKiS0_iPf:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.cfi_endproc
.LFE2033:
	.size	_Z13AffineForwardPKfPKiS0_iPf, .-_Z13AffineForwardPKfPKiS0_iPf
	.globl	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.type	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_, @function
_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_, .-_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, @function
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.cfi_endproc
.LFE2035:
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .-_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_"
.LC1:
	.string	"_Z13AffineForwardPKfPKiS0_iPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13AffineForwardPKfPKiS0_iPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/***
  Implementation of Spatial Transformer Networks[1]

  Under Simplified BSD License
  by Che-Wei Lin

  [1] Max Jaderberg et al. Spatial Transformer Networks. NIPS 2015
***/

__global__ void AffineForward(const float* bottom_data,
    const int* bs, const float* affine, const int len, float* top_data) {
    // bs = bottomSize

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bs[0];
    int w = (index / bs[0]) % bs[1];
    int c = (index / bs[0] / bs[1]) % bs[2];
    int n = index / bs[0] / bs[1] / bs[2];

    // get current affine start index
    const float* a = affine + n*6;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bs[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bs[0]-0.5); //-1~1

    float w_new = ((a[0]*nw + a[2]*nh + a[4])/2.0+0.5)*(float)bs[1];
    float h_new = ((a[1]*nw + a[3]*nh + a[5])/2.0+0.5)*(float)bs[0];

    // calc neighbor pixel index, if > size or < size, do
    float v = 0.0;
    for (int x = floor(w_new); x <= ceil(w_new); x++) {
      for (int y = floor(h_new); y <= ceil(h_new); y++) {
        if (x < 0 || x>= bs[1] || y < 0 || y >= bs[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*len/bs[3] + c*bs[1]*bs[0] + x*bs[0] + y];
        }
        top_data[index] += v * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
      }
    }

}

__global__ void AffineBackward(const float* bottom_data,
    const int* bs, const float* affine, const int len, const float* top_data, const float* top_diff, float* bottom_diff1, float* bottom_diff2) {
    // bs = bottomSize

    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bs[0];
    int w = (index / bs[0]) % bs[1];
    int c = (index / bs[0] / bs[1]) % bs[2];
    int n = index / bs[0] / bs[1] / bs[2];

    // get current affine start index
    const float* a = affine + n*6;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bs[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bs[0]-0.5); //-1~1

    float w_new = ((a[0]*nw + a[2]*nh + a[4])/2.0+0.5)*(float)bs[1];
    float h_new = ((a[1]*nw + a[3]*nh + a[5])/2.0+0.5)*(float)bs[0];

    float u = 0.0;
    float dx = 0.0;
    float dy = 0.0;
    for (int x = max(floor(w_new),0.0); x <= min(ceil(w_new),(float)bs[1]); x++) {
      for (int y = max(floor(h_new),0.0); y <= min(ceil(h_new),(float)bs[0]); y++) {
          u = bottom_data[n*bs[2]*bs[1]*bs[0] + c*bs[1]*bs[0] + x*bs[0] + y];
          atomicAdd(bottom_diff1 + (n*bs[2]*bs[1]*bs[0] + c*bs[1]*bs[0] + x*bs[0] + y),  top_diff[index] * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y))  );
          dx += u * (1-abs(h_new - (float)y)) * ((float)x >= w_new ? 1.0:-1.0 );
          dy += u * (1-abs(w_new - (float)x)) * ((float)y >= h_new ? 1.0:-1.0 );
      }
    }
    
    atomicAdd((bottom_diff2+n*6)+0, nw *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+2, nh *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+4, 1.0*dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+1, nw *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+3, nh *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*6)+5, 1.0*dy*top_diff[index]);
}
	.text
	.file	"affine.hip"
	.globl	_Z28__device_stub__AffineForwardPKfPKiS0_iPf # -- Begin function _Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.type	_Z28__device_stub__AffineForwardPKfPKiS0_iPf,@function
_Z28__device_stub__AffineForwardPKfPKiS0_iPf: # @_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13AffineForwardPKfPKiS0_iPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__AffineForwardPKfPKiS0_iPf, .Lfunc_end0-_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_ # -- Begin function _Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.type	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@function
_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_: # @_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .Lfunc_end1-_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13AffineForwardPKfPKiS0_iPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13AffineForwardPKfPKiS0_iPf,@object # @_Z13AffineForwardPKfPKiS0_iPf
	.section	.rodata,"a",@progbits
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.p2align	3, 0x0
_Z13AffineForwardPKfPKiS0_iPf:
	.quad	_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.size	_Z13AffineForwardPKfPKiS0_iPf, 8

	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@object # @_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.p2align	3, 0x0
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_:
	.quad	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13AffineForwardPKfPKiS0_iPf"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_"
	.size	.L__unnamed_2, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.addrsig_sym _Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13AffineForwardPKfPKiS0_iPf
	.addrsig_sym _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13AffineForwardPKfPKiS0_iPf ; -- Begin function _Z13AffineForwardPKfPKiS0_iPf
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.p2align	8
	.type	_Z13AffineForwardPKfPKiS0_iPf,@function
_Z13AffineForwardPKfPKiS0_iPf:          ; @_Z13AffineForwardPKfPKiS0_iPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s10, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s10, v4
	s_cbranch_execz .LBB0_11
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[8:9], s[6:7], 0x0
	s_load_b32 s11, s[6:7], 0x8
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s12, s8, 31
	v_cvt_f32_i32_e32 v17, s9
	s_add_i32 s13, s8, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, s12
	v_cvt_f32_u32_e32 v0, s13
	s_sub_i32 s14, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v1, s14, v0
	s_ashr_i32 s14, s9, 31
	s_add_i32 s15, s9, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s15, s15, s14
	v_cvt_f32_u32_e32 v3, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v0, v1
	v_rcp_iflag_f32_e32 v3, v3
	v_add_nc_u32_e32 v2, v4, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v0, v0, v1
	v_xor_b32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v1, v0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v2, v1
	v_add_nc_u32_e32 v2, 1, v0
	v_subrev_nc_u32_e32 v6, s13, v1
	v_cmp_le_u32_e32 vcc_lo, s13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_xor_b32_e32 v6, s12, v5
	s_sub_i32 s12, 0, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v1
	v_cvt_u32_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_lo_u32 v2, s12, v1
	s_ashr_i32 s12, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s13, s11, s12
	v_xor_b32_e32 v0, v0, v6
	s_xor_b32 s13, s13, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v1, v2
	v_sub_nc_u32_e32 v8, v0, v6
	v_cvt_f32_u32_e32 v6, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v8
	v_rcp_iflag_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_lo_u32 v12, v8, s8
	v_add_nc_u32_e32 v3, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v3, v0
	v_xor_b32_e32 v0, s14, v0
	s_sub_i32 s14, 0, s13
	v_sub_nc_u32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v2, v1
	v_cvt_f32_i32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v1, s15
	v_sub_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s15, v2
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	v_cndmask_b32_e32 v2, v2, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v9, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v9
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	v_mul_lo_u32 v11, v9, s9
	v_cvt_u32_f32_e32 v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v11
	v_mul_lo_u32 v3, s14, v2
	v_cvt_f32_i32_e32 v11, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v8, v8
	v_div_scale_f32 v14, null, v11, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v1, v2, v3
	v_add_nc_u32_e32 v3, v9, v0
	v_div_scale_f32 v13, null, v17, v17, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v14
	v_rcp_f32_e32 v15, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_xor_b32_e32 v2, v3, v0
	v_xor_b32_e32 v0, s12, v0
	s_mov_b32 s12, 0
	v_mul_hi_u32 v1, v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v14, v16, 1.0
	v_fma_f32 v18, -v13, v15, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v16, v19, v16
	v_mul_lo_u32 v3, v1, s13
	v_fmac_f32_e32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v2, v3
	v_subrev_nc_u32_e32 v6, s13, v2
	v_cmp_le_u32_e32 vcc_lo, s13, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s13, v2
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_xor_b32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v1, v0
	v_mul_lo_u32 v0, v10, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b128 v[0:3], v[6:7], off
	global_load_b64 v[6:7], v[6:7], off offset:16
	v_div_scale_f32 v20, vcc_lo, v8, v17, v8
	v_div_scale_f32 v18, s2, v12, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v20, v15
	v_mul_f32_e32 v21, v18, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v13, v19, v20
	v_fma_f32 v23, -v14, v21, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v22, v15
	v_fmac_f32_e32 v21, v23, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v13, v19, v20
	v_fma_f32 v14, -v14, v21, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v13, v13, v15, v19
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v14, v14, v16, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v8, v13, v17, v8
	v_cvt_f64_f32_e32 v[17:18], v17
	v_div_fixup_f32 v12, v14, v11, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[14:15], v8
	v_cvt_f64_f32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -0.5
	v_add_f64 v[12:13], v[12:13], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[14:15], v[14:15]
	v_add_f64 v[12:13], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v14, v[12:13]
	v_cvt_f32_f64_e32 v12, v[15:16]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v14
	v_fmac_f32_e32 v2, v0, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v6, v2
	v_cvt_f64_f32_e32 v[15:16], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], 0.5, 0.5
	v_mul_f64 v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v6, v[15:16]
	v_floor_f32_e32 v0, v6
	v_ceil_f32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v0, v0
	v_cvt_f32_i32_e32 v13, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, v8, v13
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.2:                                ; %.lr.ph84
	v_mul_f32_e32 v2, v3, v14
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, v1, v12
	v_cvt_f64_f32_e32 v[11:12], v11
	v_add_f32_e32 v1, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[1:2], v1
	v_fma_f64 v[1:2], v[1:2], 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[1:2], v[1:2], v[11:12]
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_cvt_f32_f64_e32 v3, v[1:2]
	v_mul_lo_u32 v1, v10, s11
	v_mul_lo_u32 v10, v10, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v9, v1
	v_mad_u64_u32 v[1:2], null, v7, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v10
	v_add_nc_u32_e32 v14, v10, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, s8, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v11
	v_xor_b32_e32 v11, v14, v7
	v_floor_f32_e32 v2, v3
	v_ceil_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v9, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v12, vcc_lo
	v_cvt_f32_i32_e32 v10, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, v5, v10
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_and_saveexec_b32 s10, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v12, v[1:2], off
	v_sub_f32_e32 v13, v6, v13
	v_cmp_lt_i32_e64 s0, -1, v0
	v_cmp_gt_i32_e64 s1, s9, v0
	v_dual_mov_b32 v14, v10 :: v_dual_mov_b32 v15, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e64 v13, 1.0, |v13|
	s_mov_b32 s11, 0
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v16, 0
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_9
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_lt_i32_e64 s2, -1, v15
	v_cmp_gt_i32_e64 s3, s8, v15
	v_mov_b32_e32 v16, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, s1, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_load_b32 s2, s[6:7], 0xc
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s14, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_xor_b32 s15, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v16, s15
	s_sub_i32 s2, 0, s15
	v_rcp_iflag_f32_e32 v16, v16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v16, 0x4f7ffffe, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v16, v16
	v_mul_lo_u32 v17, s2, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v16, v17
	v_add_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v11, v16
	v_mul_lo_u32 v17, v16, s15
	v_add_nc_u32_e32 v18, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v11, v17
	v_subrev_nc_u32_e32 v19, s15, v17
	v_cmp_le_u32_e64 s2, s15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v18, s2
	v_cndmask_b32_e64 v17, v17, v19, s2
	v_xor_b32_e32 v19, s14, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, 1, v16
	v_cmp_le_u32_e64 s2, s15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, v16, v18, s2
	v_xor_b32_e32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v16, v16, v19
	v_add3_u32 v16, v4, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v16, s2, s4, v16
	v_add_co_ci_u32_e64 v17, s2, s5, v17, s2
	global_load_b32 v16, v[16:17], off
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_9:                                ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v16, v13, v16 :: v_dual_add_nc_u32 v15, 1, v15
	v_sub_f32_e32 v17, v3, v14
	v_cvt_f32_i32_e32 v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e64 v17, 1.0, |v17|
	v_cmp_nge_f32_e64 s2, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v17, v16
	s_or_b32 s11, s2, s11
	global_store_b32 v[1:2], v12, off
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_5
.LBB0_10:                               ; %Flow103
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, 1, v0
	v_add_nc_u32_e32 v4, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v13, v0
	v_cmp_nge_f32_e64 s0, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s12, s0, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_3
.LBB0_11:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13AffineForwardPKfPKiS0_iPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13AffineForwardPKfPKiS0_iPf, .Lfunc_end0-_Z13AffineForwardPKfPKiS0_iPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1764
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_ ; -- Begin function _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.p2align	8
	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@function
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_: ; @_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v4
	s_cbranch_execz .LBB1_25
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[12:13], s[6:7], 0x0
	s_load_b32 s14, s[6:7], 0x8
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s12, 31
	v_cvt_f32_i32_e32 v21, s13
	s_add_i32 s9, s12, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s9, s8
	v_cvt_f32_u32_e32 v0, s9
	s_sub_i32 s10, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v1, s10, v0
	s_ashr_i32 s10, s13, 31
	s_add_i32 s11, s13, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s11, s11, s10
	v_cvt_f32_u32_e32 v3, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v0, v1
	v_rcp_iflag_f32_e32 v3, v3
	v_add_nc_u32_e32 v2, v4, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v0, v0, v1
	v_xor_b32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v1, v0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v2, v1
	v_add_nc_u32_e32 v2, 1, v0
	v_subrev_nc_u32_e32 v6, s9, v1
	v_cmp_le_u32_e32 vcc_lo, s9, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_xor_b32_e32 v6, s8, v5
	s_sub_i32 s8, 0, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s9, v1
	v_cvt_u32_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_lo_u32 v2, s8, v1
	s_ashr_i32 s8, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s9, s14, s8
	v_xor_b32_e32 v0, v0, v6
	s_xor_b32 s9, s9, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v1, v2
	v_sub_nc_u32_e32 v11, v0, v6
	v_cvt_f32_u32_e32 v6, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v11
	v_rcp_iflag_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_lo_u32 v13, v11, s12
	v_add_nc_u32_e32 v3, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v3, v0
	v_xor_b32_e32 v0, s10, v0
	s_sub_i32 s10, 0, s9
	v_mul_hi_u32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v1, s11
	v_sub_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s11, v2
	v_cmp_le_u32_e32 vcc_lo, s11, v2
	v_cndmask_b32_e32 v2, v2, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v10, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, v10, s13
	v_ashrrev_i32_e32 v0, 31, v10
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	v_cvt_u32_f32_e32 v2, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, v11, v12
	v_sub_nc_u32_e32 v12, v4, v13
	v_mul_lo_u32 v3, s10, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v13, v11
	v_cvt_f32_i32_e32 v11, s12
	v_cvt_f32_i32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v21, v21, v13
	v_div_scale_f32 v15, null, v11, v11, v12
	v_mul_hi_u32 v1, v2, v3
	v_add_nc_u32_e32 v3, v10, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v17, v14
	v_rcp_f32_e32 v18, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v14, v17, 1.0
	v_fma_f32 v20, -v15, v18, 1.0
	v_add_nc_u32_e32 v1, v2, v1
	v_xor_b32_e32 v2, v3, v0
	v_xor_b32_e32 v0, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v17, v19, v17 :: v_dual_fmac_f32 v18, v20, v18
	v_mul_hi_u32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v1, s9
	v_sub_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s9, v2
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v16, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v16, 6
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_add_co_u32 v8, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
	s_clause 0x1
	global_load_b128 v[0:3], v[8:9], off
	global_load_b64 v[8:9], v[8:9], off offset:16
	v_div_scale_f32 v22, vcc_lo, v13, v21, v13
	v_div_scale_f32 v19, s2, v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v20, v22, v17 :: v_dual_mul_f32 v23, v19, v18
	v_fma_f32 v24, -v14, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v15, v23, v19
	v_dual_fmac_f32 v20, v24, v17 :: v_dual_fmac_f32 v23, v25, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, -v14, v20, v22
	v_fma_f32 v15, -v15, v23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v14, v14, v17, v20
	s_mov_b32 vcc_lo, s2
	v_cvt_f64_f32_e32 v[19:20], v21
	v_div_fmas_f32 v15, v15, v18, v23
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x28
	s_load_b64 s[2:3], s[0:1], 0x38
	v_div_fixup_f32 v14, v14, v21, v13
	s_mov_b32 s0, exec_lo
	v_div_fixup_f32 v12, v15, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[14:15], v14
	v_cvt_f64_f32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -0.5
	v_add_f64 v[12:13], v[12:13], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], v[14:15]
	v_add_f64 v[12:13], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v14, v[14:15]
                                        ; implicit-def: $vgpr15
	v_cvt_f32_f64_e32 v13, v[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v13
	v_fmac_f32_e32 v2, v0, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v8, v2
	v_cvt_f64_f32_e32 v[17:18], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], 0.5, 0.5
	v_mul_f64 v[17:18], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v18, v[17:18]
                                        ; implicit-def: $vgpr17
	v_floor_f32_e32 v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[19:20], v0
	v_max_f64 v[19:20], v[19:20], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v0, v[19:20]
	v_ceil_f32_e32 v19, v18
	v_min_f32_e32 v2, v19, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v8, v0
	v_cmpx_ge_f32_e32 v2, v8
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.2:                                ; %.lr.ph138
	v_mul_f32_e32 v2, v3, v13
	v_cvt_f64_f32_e32 v[11:12], v11
	v_mul_lo_u32 v3, v16, s14
	v_mov_b32_e32 v15, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v17, 0 :: v_dual_fmac_f32 v2, v1, v14
	v_dual_mov_b32 v22, 0 :: v_dual_add_f32 v1, v9, v2
	v_mov_b32_e32 v9, s12
	v_sub_nc_u32_e32 v3, v10, v3
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[1:2], v1
	v_fma_f64 v[1:2], v[1:2], 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[1:2], v[1:2], v[11:12]
	v_mov_b32_e32 v11, s13
	v_cvt_f32_f64_e32 v20, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v1, v20
	v_ceil_f32_e32 v12, v20
	v_cvt_f64_f32_e32 v[1:2], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f32_e32 v23, v12, v12
	v_max_f64 v[1:2], v[1:2], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v21, v[1:2]
	v_lshlrev_b64 v[1:2], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	v_cvt_f32_i32_e32 v24, v21
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
	v_cvt_f32_i32_e32 v10, v9
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f32_e32 v10, v23, v10
	v_cmpx_ge_f32_e32 v10, v24
	s_cbranch_execz .LBB1_9
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_sub_f32_e32 v10, v18, v8
	v_cmp_ge_f32_e32 vcc_lo, v8, v18
	v_mov_b32_e32 v26, v24
	v_mov_b32_e32 v8, v21
	s_mov_b32 s14, 0
	v_sub_f32_e64 v25, 1.0, |v10|
.LBB1_5:                                ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
	global_load_b64 v[10:11], v22, s[6:7] offset:4
	s_mov_b32 s15, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[27:28], null, v11, v16, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v27, v10, v[0:1]
	v_mad_u64_u32 v[27:28], null, v11, v9, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[9:10], 2, v[27:28]
	global_load_b32 v28, v[1:2], off
	v_add_co_u32 v11, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s0, s5, v10, s0
	v_add_co_u32 v9, s0, s10, v9
	v_add_co_ci_u32_e64 v10, s0, s11, v10, s0
	global_load_b32 v27, v[11:12], off
	global_load_b32 v12, v[9:10], off
	v_sub_f32_e32 v11, v20, v26
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v29, v25, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e64 v28, 1.0, |v11|
	v_mul_f32_e32 v29, v28, v29
.LBB1_6:                                ; %atomicrmw.start188
                                        ;   Parent Loop BB1_3 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v12, v29
	global_atomic_cmpswap_b32 v11, v[9:10], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s0, v11, v12
	v_mov_b32_e32 v12, v11
	s_or_b32 s15, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_6
; %bb.7:                                ; %atomicrmw.end187
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b32 v9, v22, s[6:7]
	v_mul_f32_e32 v10, v28, v27
	v_mul_f32_e32 v12, v25, v27
	v_cvt_f64_f32_e32 v[29:30], v17
	v_cvt_f64_f32_e32 v[31:32], v15
	v_cmp_ge_f32_e64 s0, v26, v20
	v_cvt_f64_f32_e32 v[10:11], v10
	v_cvt_f64_f32_e32 v[27:28], v12
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, 0x80000000, v11
	v_xor_b32_e32 v15, 0x80000000, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, v27, v27, s0
	v_dual_cndmask_b32 v10, v10, v10 :: v_dual_cndmask_b32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v15, v28, s0
	v_add_f64 v[10:11], v[10:11], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[27:28], v[31:32]
	v_cvt_f32_f64_e32 v17, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v15, v[26:27]
	v_cvt_f32_i32_e32 v26, v8
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v10, v9
	v_min_f32_e32 v10, v23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nge_f32_e64 s0, v10, v26
	s_or_b32 s14, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_5
; %bb.8:                                ; %._crit_edge.loopexit
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	global_load_b32 v11, v22, s[6:7] offset:4
.LBB1_9:                                ; %Flow221
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v0, 1, v0
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v10, v11
	v_max_f32_e32 v12, v19, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v8, v0
	v_min_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nge_f32_e32 vcc_lo, v10, v8
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_3
; %bb.10:                               ; %Flow222
	s_or_b32 exec_lo, exec_lo, s12
.LBB1_11:                               ; %Flow223
	s_and_not1_saveexec_b32 s0, s1
; %bb.12:                               ; %.._crit_edge139_crit_edge
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v15, 0
; %bb.13:                               ; %._crit_edge139
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
	v_mul_f32_e32 v6, v17, v14
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v6, v6, v4
.LBB1_14:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_14
; %bb.15:                               ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off offset:8
	v_mul_f32_e32 v6, v17, v13
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, v6, v4
.LBB1_16:                               ; %atomicrmw.start158
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_16
; %bb.17:                               ; %atomicrmw.end157
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off offset:16
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v6, v17, v4
.LBB1_18:                               ; %atomicrmw.start164
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_18
; %bb.19:                               ; %atomicrmw.end163
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off offset:4
	v_mul_f32_e32 v6, v15, v14
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, v6, v4
.LBB1_20:                               ; %atomicrmw.start170
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off offset:4 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_20
; %bb.21:                               ; %atomicrmw.end169
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off offset:12
	v_mul_f32_e32 v6, v15, v13
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, v6, v4
.LBB1_22:                               ; %atomicrmw.start176
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off offset:12 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_22
; %bb.23:                               ; %atomicrmw.end175
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off offset:20
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v15, v2
.LBB1_24:                               ; %atomicrmw.start182
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:20 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_24
.LBB1_25:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .Lfunc_end1-_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2336
; NumSgprs: 18
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13AffineForwardPKfPKiS0_iPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13AffineForwardPKfPKiS0_iPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
