#include <math.h>
#include <stdio.h>
#include <stdlib.h>

__global__ void playGame(int *gridIn, int intpitch, int width, int height){
	unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y; //row index
	unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x; //column index
	
	int tx = threadIdx.x; // For shared memory
	int ty = threadIdx.y;
	extern __shared__ int s_data[];
	int sharedMemDim_x = blockDim.x+2;
	
	/*
	s_data[tx] = 					gridIn[(height-1)*intpitch + width - 1];//NW1 	iy =  0, ix =  0, tx =  0 
	s_data[tx] = 					gridIn[(height-1)*intpitch + ix - 1];	//NW2	iy =  0, ix >  0, tx =  0 
	s_data[tx] = 					gridIn[(iy-1)*intpitch + width - 1];	//NW3 	iy >  0, ix =  0, tx =  0
	s_data[tx] = 					gridIn[(iy-1)*intpitch + ix - 1];	//NW4 	iy >  0, ix >  0, tx =  0 
	s_data[tx + 1] = 				gridIn[(height-1)*intpitch + ix];	//N1  	iy =  0, ix >= 0, tx >= 0 
	s_data[tx + 1] = 				gridIn[(iy-1)*intpitch + ix];		//N2  	iy >  0, ix >= 0, tx >= 0
	s_data[tx + 2] = 				gridIn[(height-1)*intpitch];		//NE1 	iy =  0, ix =  l, tx >= 0 
	s_data[tx + 2] = 				gridIn[(height-1)*intpitch + ix + 1];	//NE2 	iy =  0, ix <  l, tx =  l
	s_data[tx + 2] = 				gridIn[(iy-1)*intpitch];		//NE3 	iy >  0, ix =  l, tx >= 0 
	s_data[tx + 2] = 				gridIn[(iy-1)*intpitch + ix + 1];	//NE4 	iy >  0, ix <  l, tx =  l
	s_data[(ty+1)*sharedMemDim_x + tx] = 		gridIn[iy*intpitch + width - 1];	//W1  	iy >= 0, ix =  0, tx =  0
	s_data[(ty+1)*sharedMemDim_x + tx] = 		gridIn[iy*intpitch + ix - 1];     	//W2  	iy >= 0, ix >  0, tx =  0
	s_data[(ty+1)*sharedMemDim_x + tx + 1] = 	gridIn[iy*intpitch + ix];    		//itself
	s_data[(ty+1)*sharedMemDim_x + tx + 2] = 	gridIn[iy*intpitch];     		//E1  	iy >= 0, ix =  l, tx >= 0
	s_data[(ty+1)*sharedMemDim_x + tx + 2] = 	gridIn[iy*intpitch + ix + 1];     	//E2  	iy >= 0, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 2] =	gridIn[0];				//SE1 	iy =  l, ix =  l, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[ix + 1];				//SE2 	iy =  l, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[(iy+1)*intpitch];		//SE3 	iy <  l, ix =  l, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[(iy+1)*intpitch + ix + 1];	//SE4 	iy <  l, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 1] =	gridIn[ix];				//S1  	iy =  l, ix >= 0, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 1] =	gridIn[(iy + 1)*intpitch + ix];		//S2  	iy <  l, ix >= 0, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[width - 1];			//SW1 	iy =  l, ix =  0, tx =  0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[ix - 1];				//SW2 	iy =  l, ix >  0, tx =  0 
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[(iy+1)*intpitch + width - 1];	//SW3 	iy <  l, ix =  0, tx =  0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[(iy+1)*intpitch + ix - 1];	//SW4 	iy <  l, ix >  0, tx =  0

	
	2D block logic
	NW: ((ty == 0) && ((tx == 0) || (tx == 1)))
	N:  ((ty == 0) && (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx = 0)) || (blockDim.x == 1))
	NE: ((ty == 0) && ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)))

	W:  (tx == 0)

	SW: ((ty == height-1) && ((tx == 0) || (tx == 1)))
	S:  ((ty == height-1) && (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
	SE: ((ty == height-1) && ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)))

	E:  ((tx == blockDim.x-1) || (ix = width-1))
	*/

	if ((iy < height) && (ix < width)){
		if (ty == 0){
			if (iy == 0){
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx == 0)) || (blockDim.x == 1))
					s_data[tx + 1] = gridIn[(height-1)*intpitch + ix];					//N1

				if ((tx==0) || (tx == 1)){
					if (ix == 0)
						s_data[tx] = gridIn[(height-1)*intpitch + width - 1];				//NW1
					else	
						s_data[tx] = gridIn[(height-1)*intpitch + ix - 1];				//NW2
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[tx + 2] = gridIn[(height-1)*intpitch];					//NE1 
					else
						s_data[tx + 2] = gridIn[(height-1)*intpitch + ix + 1];				//NE2
				}
			}
			else{
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx == 0)) || (blockDim.x == 1))
					s_data[tx + 1] = gridIn[(iy-1)*intpitch + ix];						//N2

				if ((tx==0) || (tx == 1)){
					if (ix == 0)
						s_data[tx] = gridIn[(iy-1)*intpitch + width - 1];				//NW3
					else
						s_data[tx] = gridIn[(iy-1)*intpitch + ix - 1];					//NW4
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[tx + 2] = gridIn[(iy-1)*intpitch];					//NE3 
					else
						s_data[tx + 2] = gridIn[(iy-1)*intpitch + ix + 1];				//NE4
				}
			}
		}

		if ((ty == blockDim.y-1) || (iy == height-1)){
			if (iy == height-1){
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
					s_data[(ty+2)*sharedMemDim_x + tx + 1] = gridIn[ix];					//S1
	
				if ((tx == 0) || (tx == 1)){
					if (ix == 0)
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[width - 1];				//SW1
					else
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[ix - 1];				//SW2
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[0];				//SE1 
					else
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[ix + 1];			//SE2
				}
			}
			else{
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
					s_data[(ty+2)*sharedMemDim_x + tx + 1] = gridIn[(iy + 1)*intpitch + ix];		//S2

				if ((tx == 0) || (tx == 1)){
					if (ix == 0)
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[(iy+1)*intpitch + width - 1];	//SW3
					else
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[(iy+1)*intpitch + ix - 1];		//SW4
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[(iy+1)*intpitch];		//SE3 
					else
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[(iy+1)*intpitch + ix + 1];	//SE4
				}
			}
		}

		if (tx == 0){
			if (ix == 0)
				s_data[(ty+1)*sharedMemDim_x] = gridIn[iy*intpitch + width - 1];				//W1
			else
				s_data[(ty+1)*sharedMemDim_x] = gridIn[iy*intpitch + ix - 1];  			   		//W2
		}

		if ((tx == blockDim.x-1) || (ix == width-1)){
			if (ix == width-1)
				s_data[(ty+1)*sharedMemDim_x + tx + 2] = gridIn[iy*intpitch];					//E1
			else
				s_data[(ty+1)*sharedMemDim_x + tx + 2] = gridIn[iy*intpitch + ix + 1];     			//E2
		}
	
		s_data[(ty+1)*sharedMemDim_x + tx + 1] = gridIn[iy*intpitch + ix];    						//itself
	}
	__syncthreads();

	/*if ((blockIdx.y == 0) && (blockIdx.x == 0) && (threadIdx.x == 0) && (threadIdx.y == 0)){
		int sharedMemDim_y = blockDim.y+2;		
		printf("block_y: %d, block_x: %d\n", 0, 0);
		for(int i=0; i<sharedMemDim_y; i++){
			for(int j=0; j<sharedMemDim_x; j++){
				printf("%d ", s_data[i*sharedMemDim_x + j]);
			}
			
			printf("\n");
		}

		printf("\n");
	}*/

	if ((ix<width) && (iy<height)){
		int sum = (	
				s_data[ty*sharedMemDim_x + tx		] +	//NW
				s_data[ty*sharedMemDim_x + tx + 1	] +	//N
				s_data[ty*sharedMemDim_x + tx + 2	] +	//NE
				s_data[(ty+1)*sharedMemDim_x + tx	] +	//W
				s_data[(ty+1)*sharedMemDim_x + tx + 2	] +	//E
				s_data[(ty+2)*sharedMemDim_x + tx	] +	//SW
				s_data[(ty+2)*sharedMemDim_x + tx + 1	] +	//S
				s_data[(ty+2)*sharedMemDim_x + tx + 2	]	//SE   
                           );
		if ((s_data[(ty+1)*sharedMemDim_x + tx + 1] == 1) && (sum != 2) && (sum != 3))
			gridIn[iy*intpitch + ix] = 0;
		else if ((s_data[(ty+1)*sharedMemDim_x + tx + 1] == 0) && (sum == 3))
			gridIn[iy*intpitch + ix] = 1;
	}
}

	.file	"tmpxft_0033b27b_00000000-6_GameOfLife.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z8playGamePiiiiPiiii
	.type	_Z30__device_stub__Z8playGamePiiiiPiiii, @function
_Z30__device_stub__Z8playGamePiiiiPiiii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8playGamePiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z30__device_stub__Z8playGamePiiiiPiiii, .-_Z30__device_stub__Z8playGamePiiiiPiiii
	.globl	_Z8playGamePiiii
	.type	_Z8playGamePiiii, @function
_Z8playGamePiiii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8playGamePiiiiPiiii
	.cfi_endproc
.LFE2052:
	.size	_Z8playGamePiiii, .-_Z8playGamePiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8playGamePiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8playGamePiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>

__global__ void playGame(int *gridIn, int intpitch, int width, int height){
	unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y; //row index
	unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x; //column index
	
	int tx = threadIdx.x; // For shared memory
	int ty = threadIdx.y;
	extern __shared__ int s_data[];
	int sharedMemDim_x = blockDim.x+2;
	
	/*
	s_data[tx] = 					gridIn[(height-1)*intpitch + width - 1];//NW1 	iy =  0, ix =  0, tx =  0 
	s_data[tx] = 					gridIn[(height-1)*intpitch + ix - 1];	//NW2	iy =  0, ix >  0, tx =  0 
	s_data[tx] = 					gridIn[(iy-1)*intpitch + width - 1];	//NW3 	iy >  0, ix =  0, tx =  0
	s_data[tx] = 					gridIn[(iy-1)*intpitch + ix - 1];	//NW4 	iy >  0, ix >  0, tx =  0 
	s_data[tx + 1] = 				gridIn[(height-1)*intpitch + ix];	//N1  	iy =  0, ix >= 0, tx >= 0 
	s_data[tx + 1] = 				gridIn[(iy-1)*intpitch + ix];		//N2  	iy >  0, ix >= 0, tx >= 0
	s_data[tx + 2] = 				gridIn[(height-1)*intpitch];		//NE1 	iy =  0, ix =  l, tx >= 0 
	s_data[tx + 2] = 				gridIn[(height-1)*intpitch + ix + 1];	//NE2 	iy =  0, ix <  l, tx =  l
	s_data[tx + 2] = 				gridIn[(iy-1)*intpitch];		//NE3 	iy >  0, ix =  l, tx >= 0 
	s_data[tx + 2] = 				gridIn[(iy-1)*intpitch + ix + 1];	//NE4 	iy >  0, ix <  l, tx =  l
	s_data[(ty+1)*sharedMemDim_x + tx] = 		gridIn[iy*intpitch + width - 1];	//W1  	iy >= 0, ix =  0, tx =  0
	s_data[(ty+1)*sharedMemDim_x + tx] = 		gridIn[iy*intpitch + ix - 1];     	//W2  	iy >= 0, ix >  0, tx =  0
	s_data[(ty+1)*sharedMemDim_x + tx + 1] = 	gridIn[iy*intpitch + ix];    		//itself
	s_data[(ty+1)*sharedMemDim_x + tx + 2] = 	gridIn[iy*intpitch];     		//E1  	iy >= 0, ix =  l, tx >= 0
	s_data[(ty+1)*sharedMemDim_x + tx + 2] = 	gridIn[iy*intpitch + ix + 1];     	//E2  	iy >= 0, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 2] =	gridIn[0];				//SE1 	iy =  l, ix =  l, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[ix + 1];				//SE2 	iy =  l, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[(iy+1)*intpitch];		//SE3 	iy <  l, ix =  l, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 2] = 	gridIn[(iy+1)*intpitch + ix + 1];	//SE4 	iy <  l, ix <  l, tx =  l
	s_data[(ty+2)*sharedMemDim_x + tx + 1] =	gridIn[ix];				//S1  	iy =  l, ix >= 0, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx + 1] =	gridIn[(iy + 1)*intpitch + ix];		//S2  	iy <  l, ix >= 0, tx >= 0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[width - 1];			//SW1 	iy =  l, ix =  0, tx =  0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[ix - 1];				//SW2 	iy =  l, ix >  0, tx =  0 
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[(iy+1)*intpitch + width - 1];	//SW3 	iy <  l, ix =  0, tx =  0
	s_data[(ty+2)*sharedMemDim_x + tx] = 		gridIn[(iy+1)*intpitch + ix - 1];	//SW4 	iy <  l, ix >  0, tx =  0

	
	2D block logic
	NW: ((ty == 0) && ((tx == 0) || (tx == 1)))
	N:  ((ty == 0) && (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx = 0)) || (blockDim.x == 1))
	NE: ((ty == 0) && ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)))

	W:  (tx == 0)

	SW: ((ty == height-1) && ((tx == 0) || (tx == 1)))
	S:  ((ty == height-1) && (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
	SE: ((ty == height-1) && ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)))

	E:  ((tx == blockDim.x-1) || (ix = width-1))
	*/

	if ((iy < height) && (ix < width)){
		if (ty == 0){
			if (iy == 0){
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx == 0)) || (blockDim.x == 1))
					s_data[tx + 1] = gridIn[(height-1)*intpitch + ix];					//N1

				if ((tx==0) || (tx == 1)){
					if (ix == 0)
						s_data[tx] = gridIn[(height-1)*intpitch + width - 1];				//NW1
					else	
						s_data[tx] = gridIn[(height-1)*intpitch + ix - 1];				//NW2
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[tx + 2] = gridIn[(height-1)*intpitch];					//NE1 
					else
						s_data[tx + 2] = gridIn[(height-1)*intpitch + ix + 1];				//NE2
				}
			}
			else{
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width - 1) && (tx == 0)) || (blockDim.x == 1))
					s_data[tx + 1] = gridIn[(iy-1)*intpitch + ix];						//N2

				if ((tx==0) || (tx == 1)){
					if (ix == 0)
						s_data[tx] = gridIn[(iy-1)*intpitch + width - 1];				//NW3
					else
						s_data[tx] = gridIn[(iy-1)*intpitch + ix - 1];					//NW4
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[tx + 2] = gridIn[(iy-1)*intpitch];					//NE3 
					else
						s_data[tx + 2] = gridIn[(iy-1)*intpitch + ix + 1];				//NE4
				}
			}
		}

		if ((ty == blockDim.y-1) || (iy == height-1)){
			if (iy == height-1){
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
					s_data[(ty+2)*sharedMemDim_x + tx + 1] = gridIn[ix];					//S1
	
				if ((tx == 0) || (tx == 1)){
					if (ix == 0)
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[width - 1];				//SW1
					else
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[ix - 1];				//SW2
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[0];				//SE1 
					else
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[ix + 1];			//SE2
				}
			}
			else{
				if (((tx != 0) && (tx != blockDim.x-1) && (ix != width-1)) || ((ix == width-1) && (tx == 0)) || (blockDim.x == 1))
					s_data[(ty+2)*sharedMemDim_x + tx + 1] = gridIn[(iy + 1)*intpitch + ix];		//S2

				if ((tx == 0) || (tx == 1)){
					if (ix == 0)
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[(iy+1)*intpitch + width - 1];	//SW3
					else
						s_data[(ty+2)*sharedMemDim_x + tx] = gridIn[(iy+1)*intpitch + ix - 1];		//SW4
				}

				if ((tx == blockDim.x-1) ||  (tx == blockDim.x-2) || (ix == width-1) || (ix == width-2)){
					if (ix == width-1)
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[(iy+1)*intpitch];		//SE3 
					else
						s_data[(ty+2)*sharedMemDim_x + tx + 2] = gridIn[(iy+1)*intpitch + ix + 1];	//SE4
				}
			}
		}

		if (tx == 0){
			if (ix == 0)
				s_data[(ty+1)*sharedMemDim_x] = gridIn[iy*intpitch + width - 1];				//W1
			else
				s_data[(ty+1)*sharedMemDim_x] = gridIn[iy*intpitch + ix - 1];  			   		//W2
		}

		if ((tx == blockDim.x-1) || (ix == width-1)){
			if (ix == width-1)
				s_data[(ty+1)*sharedMemDim_x + tx + 2] = gridIn[iy*intpitch];					//E1
			else
				s_data[(ty+1)*sharedMemDim_x + tx + 2] = gridIn[iy*intpitch + ix + 1];     			//E2
		}
	
		s_data[(ty+1)*sharedMemDim_x + tx + 1] = gridIn[iy*intpitch + ix];    						//itself
	}
	__syncthreads();

	/*if ((blockIdx.y == 0) && (blockIdx.x == 0) && (threadIdx.x == 0) && (threadIdx.y == 0)){
		int sharedMemDim_y = blockDim.y+2;		
		printf("block_y: %d, block_x: %d\n", 0, 0);
		for(int i=0; i<sharedMemDim_y; i++){
			for(int j=0; j<sharedMemDim_x; j++){
				printf("%d ", s_data[i*sharedMemDim_x + j]);
			}
			
			printf("\n");
		}

		printf("\n");
	}*/

	if ((ix<width) && (iy<height)){
		int sum = (	
				s_data[ty*sharedMemDim_x + tx		] +	//NW
				s_data[ty*sharedMemDim_x + tx + 1	] +	//N
				s_data[ty*sharedMemDim_x + tx + 2	] +	//NE
				s_data[(ty+1)*sharedMemDim_x + tx	] +	//W
				s_data[(ty+1)*sharedMemDim_x + tx + 2	] +	//E
				s_data[(ty+2)*sharedMemDim_x + tx	] +	//SW
				s_data[(ty+2)*sharedMemDim_x + tx + 1	] +	//S
				s_data[(ty+2)*sharedMemDim_x + tx + 2	]	//SE   
                           );
		if ((s_data[(ty+1)*sharedMemDim_x + tx + 1] == 1) && (sum != 2) && (sum != 3))
			gridIn[iy*intpitch + ix] = 0;
		else if ((s_data[(ty+1)*sharedMemDim_x + tx + 1] == 0) && (sum == 3))
			gridIn[iy*intpitch + ix] = 1;
	}
}

	.text
	.file	"GameOfLife.hip"
	.globl	_Z23__device_stub__playGamePiiii # -- Begin function _Z23__device_stub__playGamePiiii
	.type	_Z23__device_stub__playGamePiiii,@function
_Z23__device_stub__playGamePiiii:       # @_Z23__device_stub__playGamePiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8playGamePiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__playGamePiiii, .Lfunc_end0-_Z23__device_stub__playGamePiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8playGamePiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8playGamePiiii,@object        # @_Z8playGamePiiii
	.section	.rodata,"a",@progbits
	.globl	_Z8playGamePiiii
	.p2align	3, 0x0
_Z8playGamePiiii:
	.quad	_Z23__device_stub__playGamePiiii
	.size	_Z8playGamePiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8playGamePiiii"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__playGamePiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8playGamePiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8playGamePiiii        ; -- Begin function _Z8playGamePiiii
	.globl	_Z8playGamePiiii
	.p2align	8
	.type	_Z8playGamePiiii,@function
_Z8playGamePiiii:                       ; @_Z8playGamePiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[8:9], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s13, s2, 16
	s_and_b32 s7, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s13, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s7, v[4:5]
	s_add_i32 s10, s7, 2
	v_cmp_gt_u32_e32 vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s5, v1
	s_and_b32 s11, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s11
	s_cbranch_execz .LBB0_108
; %bb.1:
	s_mov_b32 s2, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_52
; %bb.2:
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cmp_ne_u32_e64 s0, 0, v4
                                        ; implicit-def: $vgpr5_vgpr6
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s15, exec_lo, s3
	s_cbranch_execz .LBB0_24
; %bb.3:
	s_mov_b32 s1, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr16
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s2
; %bb.4:
	s_add_i32 s1, s7, -1
	s_add_i32 s16, s5, -1
	v_cmp_eq_u32_e64 s1, s1, v4
	v_cmp_eq_u32_e64 s2, s16, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_and_b32 s1, s1, exec_lo
; %bb.5:                                ; %Flow475
	s_or_saveexec_b32 s2, s17
	v_mov_b32_e32 v2, s16
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.6:                                ; %._crit_edge363
	s_add_i32 s16, s5, -1
	s_or_b32 s1, s1, exec_lo
	v_mov_b32_e32 v2, s16
; %bb.7:                                ; %Flow476
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s1
; %bb.8:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, v1, v2
	s_and_b32 s1, vcc_lo, s1
	s_cmp_eq_u32 s7, 1
	s_cselect_b32 s16, -1, 0
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s1, s16, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s3, s3, s1
; %bb.9:                                ; %Flow477
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v2, -1, v0
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v2, s4, v[1:2]
	v_mov_b32_e32 v6, 0
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s8, v5
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b32 v5, v[5:6], off
	v_lshl_add_u32 v6, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5 offset:4
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 2, v4
	s_cbranch_execz .LBB0_13
; %bb.12:                               ; %.sink.split392
	v_cmp_eq_u32_e64 s1, 0, v1
	v_mul_lo_u32 v5, v2, s4
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v1, s5, s1
	v_add3_u32 v5, v7, v5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, s1, s8, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b32 v5, v[5:6], off
	v_lshl_add_u32 v6, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s1, s7, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $sgpr16
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e64 s1, v4
	s_xor_b32 s17, exec_lo, s3
; %bb.14:
	s_add_i32 s1, s7, -2
	s_add_i32 s16, s5, -1
	v_cmp_eq_u32_e64 s1, s1, v4
	v_cmp_eq_u32_e64 s2, s16, v1
	s_add_i32 s3, s5, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s3, s3, v1
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s1, exec_lo
; %bb.15:                               ; %Flow491
	s_or_saveexec_b32 s1, s17
	v_mov_b32_e32 v7, s16
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.16:                               ; %._crit_edge
	s_add_i32 s3, s5, -1
	s_or_b32 s2, s2, exec_lo
	v_mov_b32_e32 v7, s3
; %bb.17:                               ; %Flow492
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB0_23
; %bb.18:
	v_mul_lo_u32 v5, v2, s4
	v_cmp_ne_u32_e64 s1, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s1
	s_xor_b32 s1, exec_lo, s3
; %bb.19:
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v1, v5, 1
	v_mov_b32_e32 v6, 0
; %bb.20:                               ; %Flow473
	s_and_not1_saveexec_b32 s1, s1
; %bb.21:
	v_mov_b32_e32 v6, 0
; %bb.22:                               ; %Flow474
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_23:                               ; %Flow493
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s1, exec_lo
.LBB0_24:                               ; %Flow490
	s_and_not1_saveexec_b32 s3, s15
	s_cbranch_execz .LBB0_50
; %bb.25:
	s_mov_b32 s1, 0
	s_mov_b32 s15, 0
                                        ; implicit-def: $sgpr16
	s_and_saveexec_b32 s17, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s17
; %bb.26:
	s_add_i32 s0, s7, -1
	s_add_i32 s16, s5, -1
	v_cmp_eq_u32_e64 s0, s0, v4
	v_cmp_eq_u32_e64 s1, s16, v1
	s_mov_b32 s15, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_b32 s1, s0, exec_lo
; %bb.27:                               ; %Flow484
	s_or_saveexec_b32 s0, s17
	v_mov_b32_e32 v2, s16
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.28:                               ; %._crit_edge370
	s_add_i32 s16, s5, -1
	s_or_b32 s1, s1, exec_lo
	v_mov_b32_e32 v2, s16
; %bb.29:                               ; %Flow485
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s16, s1
; %bb.30:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, v1, v2
	s_and_b32 s0, vcc_lo, s0
	s_cmp_eq_u32 s7, 1
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_and_not1_b32 s1, s15, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s15, s1, s0
; %bb.31:                               ; %Flow486
	s_or_b32 exec_lo, exec_lo, s16
	s_and_saveexec_b32 s0, s15
	s_cbranch_execz .LBB0_33
; %bb.32:
	s_add_i32 s1, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s1, s4, v[1:2]
	v_mov_b32_e32 v6, 0
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_lshl_add_u32 v5, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:4
.LBB0_33:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 2, v4
	s_cbranch_execz .LBB0_39
; %bb.34:
	s_add_i32 s1, s6, -1
	s_mov_b32 s15, exec_lo
	s_mul_i32 s1, s1, s4
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s15, exec_lo, s15
; %bb.35:
	v_add3_u32 v5, s1, -1, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
; %bb.36:                               ; %Flow482
	s_and_not1_saveexec_b32 s15, s15
; %bb.37:
	s_add_i32 s16, s1, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s17, s16, 31
	s_lshl_b64 s[16:17], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_add_u32 s1, s8, s16
	s_addc_u32 s17, s9, s17
	s_add_u32 s16, s1, -4
	s_addc_u32 s17, s17, -1
	v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; %bb.38:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b32 v2, v[5:6], off
	v_lshl_add_u32 v5, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2
.LBB0_39:                               ; %Flow483
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s7, -1
                                        ; implicit-def: $sgpr15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v4
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s16, exec_lo, s1
; %bb.40:
	s_add_i32 s0, s7, -2
	s_add_i32 s15, s5, -1
	v_cmp_eq_u32_e32 vcc_lo, s0, v4
	v_cmp_eq_u32_e64 s0, s15, v1
	s_add_i32 s1, s5, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, s1, v1
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
; %bb.41:                               ; %Flow495
	s_or_saveexec_b32 s1, s16
	v_mov_b32_e32 v2, s15
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.42:                               ; %._crit_edge369
	s_add_i32 s15, s5, -1
	s_or_b32 s0, s0, exec_lo
	v_mov_b32_e32 v2, s15
; %bb.43:                               ; %Flow496
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, s2
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_49
; %bb.44:
	s_add_i32 s0, s6, -1
	s_mov_b32 s1, exec_lo
	s_mul_i32 s0, s0, s4
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_ne_u32_e64 v1, v2
	s_xor_b32 s1, exec_lo, s1
; %bb.45:
	v_add3_u32 v5, s0, 1, v1
	v_mov_b32_e32 v6, 0
; %bb.46:                               ; %Flow479
	s_and_not1_saveexec_b32 s16, s1
; %bb.47:
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v5, s0
; %bb.48:                               ; %Flow480
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s2, exec_lo
.LBB0_49:                               ; %Flow497
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s2, s0, s1
.LBB0_50:                               ; %Flow494
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_52
; %bb.51:                               ; %.sink.split396
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_lshl_add_u32 v5, v4, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:8
.LBB0_52:
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s13, s13, -1
	s_add_i32 s1, s6, -1
	v_cmp_eq_u32_e32 vcc_lo, s13, v3
	v_cmp_eq_u32_e64 s0, s1, v0
	v_cmp_ne_u32_e64 s1, s1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_97
; %bb.53:
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cmp_ne_u32_e64 s0, 0, v4
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s3, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s3
	s_cbranch_execz .LBB0_75
; %bb.54:
	s_mov_b32 s1, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr14
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s2
; %bb.55:
	s_add_i32 s1, s7, -1
	s_add_i32 s14, s5, -1
	v_cmp_eq_u32_e64 s1, s1, v4
	v_cmp_eq_u32_e64 s2, s14, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_and_b32 s1, s1, exec_lo
; %bb.56:                               ; %Flow452
	s_or_saveexec_b32 s2, s15
	v_mov_b32_e32 v2, s14
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.57:                               ; %._crit_edge365
	s_add_i32 s14, s5, -1
	s_or_b32 s1, s1, exec_lo
	v_mov_b32_e32 v2, s14
; %bb.58:                               ; %Flow453
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s1
; %bb.59:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, v1, v2
	s_and_b32 s1, vcc_lo, s1
	s_cmp_eq_u32 s7, 1
	s_cselect_b32 s14, -1, 0
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s1, s14, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s3, s3, s1
; %bb.60:                               ; %Flow454
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_62
; %bb.61:
	v_mul_lo_u32 v2, s4, v0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v2, s4, v1
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s8, v5
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b32 v2, v[5:6], off
	v_add_nc_u32_e32 v5, 2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v5, s10, v5, v4
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:4
.LBB0_62:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 2, v4
	s_cbranch_execz .LBB0_64
; %bb.63:                               ; %.sink.split403
	v_cmp_eq_u32_e64 s1, 0, v1
	v_mad_u64_u32 v[5:6], null, s4, v0, s[4:5]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v1, s5, s1
	v_add3_u32 v5, v2, v5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, s1, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b32 v2, v[5:6], off
	v_add_nc_u32_e32 v5, 2, v3
	v_mad_u32_u24 v5, s10, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2
.LBB0_64:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s1, s7, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $sgpr14
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e64 s1, v4
	s_xor_b32 s15, exec_lo, s3
; %bb.65:
	s_add_i32 s1, s7, -2
	s_add_i32 s14, s5, -1
	v_cmp_eq_u32_e64 s1, s1, v4
	v_cmp_eq_u32_e64 s2, s14, v1
	s_add_i32 s3, s5, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s3, s3, v1
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s1, exec_lo
; %bb.66:                               ; %Flow464
	s_or_saveexec_b32 s1, s15
	v_mov_b32_e32 v2, s14
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.67:                               ; %._crit_edge364
	s_add_i32 s3, s5, -1
	s_or_b32 s2, s2, exec_lo
	v_mov_b32_e32 v2, s3
; %bb.68:                               ; %Flow465
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB0_74
; %bb.69:
	v_mad_u64_u32 v[7:8], null, s4, v0, s[4:5]
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_ne_u32_e64 v1, v2
	s_xor_b32 s3, exec_lo, s3
; %bb.70:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v1, v7, 1
	v_mov_b32_e32 v6, 0
                                        ; implicit-def: $vgpr7_vgpr8
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s8, v5
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
; %bb.71:                               ; %Flow450
	s_and_not1_saveexec_b32 s3, s3
; %bb.72:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[7:8]
	v_add_co_u32 v5, s1, s8, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
; %bb.73:                               ; %Flow451
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
.LBB0_74:                               ; %Flow466
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s1, exec_lo
.LBB0_75:                               ; %Flow463
	s_and_not1_saveexec_b32 s3, s13
	s_cbranch_execz .LBB0_95
; %bb.76:
	s_mov_b32 s1, 0
	s_mov_b32 s13, 0
                                        ; implicit-def: $sgpr14
	s_and_saveexec_b32 s15, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s15
; %bb.77:
	s_add_i32 s0, s7, -1
	s_add_i32 s14, s5, -1
	v_cmp_eq_u32_e64 s0, s0, v4
	v_cmp_eq_u32_e64 s1, s14, v1
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_b32 s1, s0, exec_lo
; %bb.78:                               ; %Flow457
	s_or_saveexec_b32 s0, s15
	v_mov_b32_e32 v2, s14
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.79:                               ; %._crit_edge368
	s_add_i32 s14, s5, -1
	s_or_b32 s1, s1, exec_lo
	v_mov_b32_e32 v2, s14
; %bb.80:                               ; %Flow458
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s14, s1
; %bb.81:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, v1, v2
	s_and_b32 s0, vcc_lo, s0
	s_cmp_eq_u32 s7, 1
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_and_not1_b32 s1, s13, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s13, s1, s0
; %bb.82:                               ; %Flow459
	s_or_b32 exec_lo, exec_lo, s14
	s_and_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_84
; %bb.83:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_add_nc_u32_e32 v5, 2, v3
	v_mad_u32_u24 v5, s10, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:4
.LBB0_84:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 2, v4
	s_cbranch_execz .LBB0_86
; %bb.85:                               ; %.sink.split400
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, -1, v1
	s_ashr_i32 s15, s5, 31
	s_mov_b32 s14, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[14:15], s[14:15], 2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_add_u32 s1, s8, s14
	s_addc_u32 s13, s9, s15
	s_add_u32 s1, s1, -4
	s_addc_u32 s13, s13, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e64 v6, v5, s13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v2, s1, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_add_nc_u32_e32 v5, 2, v3
	v_mad_u32_u24 v5, s10, v5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2
.LBB0_86:
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s7, -1
                                        ; implicit-def: $sgpr13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v4
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s14, exec_lo, s1
; %bb.87:
	s_add_i32 s0, s7, -2
	s_add_i32 s13, s5, -1
	v_cmp_eq_u32_e32 vcc_lo, s0, v4
	v_cmp_eq_u32_e64 s0, s13, v1
	s_add_i32 s1, s5, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, s1, v1
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
; %bb.88:                               ; %Flow468
	s_or_saveexec_b32 s1, s14
	v_mov_b32_e32 v2, s13
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.89:                               ; %._crit_edge367
	s_add_i32 s13, s5, -1
	s_or_b32 s0, s0, exec_lo
	v_mov_b32_e32 v2, s13
; %bb.90:                               ; %Flow469
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s13, s2
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_94
; %bb.91:
	v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 v1, v2
; %bb.92:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, v2, 4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
; %bb.93:                               ; %Flow456
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s2, exec_lo
.LBB0_94:                               ; %Flow470
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s1, s13, exec_lo
	s_or_b32 s2, s0, s1
.LBB0_95:                               ; %Flow467
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_97
; %bb.96:                               ; %.sink.split410
	global_load_b32 v2, v[5:6], off
	v_add_nc_u32_e32 v5, 2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v5, s10, v5, v4
	v_lshl_add_u32 v5, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:8
.LBB0_97:
	s_or_b32 exec_lo, exec_lo, s6
	v_mul_lo_u32 v5, v0, s4
	v_add_nc_u32_e32 v2, 1, v3
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_99
; %bb.98:                               ; %.sink.split418
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_mov_b32_e32 v7, 0
	v_cndmask_b32_e64 v6, v1, s5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v6, v5, -1
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	v_mul_u32_u24_e32 v7, s10, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v7, v7, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
.LBB0_99:
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s7, -1
	s_add_i32 s1, s5, -1
	v_cmp_ne_u32_e64 s0, s0, v4
	v_cmp_ne_u32_e32 vcc_lo, s1, v1
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
; %bb.100:                              ; %._crit_edge366
	v_mul_u32_u24_e32 v6, s10, v2
                                        ; implicit-def: $vgpr2
; %bb.101:                              ; %Flow448
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_107
; %bb.102:
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_104
; %bb.103:
	v_add3_u32 v6, v1, v5, 1
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v7, v[6:7], off
	v_mad_u32_u24 v6, s10, v2, v4
	v_lshl_add_u32 v8, v6, 2, 0
	v_mul_u32_u24_e32 v6, s10, v2
                                        ; implicit-def: $vgpr2
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v7 offset:8
.LBB0_104:                              ; %Flow446
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_106
; %bb.105:
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v7, v[6:7], off
	v_mad_u32_u24 v6, s10, v2, v4
	v_lshl_add_u32 v8, v6, 2, 0
	v_mul_u32_u24_e32 v6, s10, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v7 offset:8
.LBB0_106:                              ; %Flow447
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_107:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, v5, v1
	v_add_nc_u32_e32 v5, v4, v6
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, v5, 2, 0
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v2, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2 offset:4
.LBB0_108:                              ; %Flow499
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB0_113
; %bb.109:
	v_mad_u32_u24 v2, s10, v3, v4
	s_lshl_b32 s0, s7, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, v2, 2, 0
	ds_load_2addr_b32 v[4:5], v2 offset1:1
	v_add3_u32 v6, v2, 8, s0
	v_add3_u32 v8, v6, 8, s0
	ds_load_b32 v9, v2 offset:8
	ds_load_2addr_b32 v[2:3], v6 offset1:1
	ds_load_b32 v10, v6 offset:8
	ds_load_2addr_b32 v[6:7], v8 offset1:1
	ds_load_b32 v8, v8 offset:8
	s_waitcnt lgkmcnt(5)
	v_add_nc_u32_e32 v4, v5, v4
	s_waitcnt lgkmcnt(3)
	v_cmp_ne_u32_e32 vcc_lo, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v4, v9, v2
	s_waitcnt lgkmcnt(1)
	v_add3_u32 v2, v2, v10, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v2, v7, v8
	v_and_b32_e32 v2, -2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 2, v2
	v_mov_b32_e32 v2, 0
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, s0, -1
	s_and_saveexec_b32 s2, s0
; %bb.110:
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cmp_eq_u32_e64 s0, 3, v4
	v_mov_b32_e32 v2, 1
	s_and_not1_b32 s1, s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s0
; %bb.111:                              ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_113
; %bb.112:                              ; %.sink.split425
	v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_113:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8playGamePiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8playGamePiiii, .Lfunc_end0-_Z8playGamePiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3532
; NumSgprs: 20
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8playGamePiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z8playGamePiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
