/*  \file TestExceptions.cu
	\author Gregory Diamos <gregory.diamos@gatech.edu>
	\date Tuesday November 9, 2010
	\brief A CUDA assembly test for unstructured control 
		flow mimicking exceptions.
*/

#include <cstdlib>

const unsigned int threads = 512;
const unsigned int iterations = 100;

__device__ unsigned int output[threads];
__device__ unsigned int input[threads];

extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		if(threadIdx.x == id)
		{
			goto Function_1_Begin;
		}
		else
		{
			goto Function_2_Begin;
		}

	Function_1_Begin:
		if(input[threadIdx.x] != id) goto Catch_Label;
		
		result = input[threadIdx.x];
		goto Function_Return;

	Function_2_Begin:
		if(input[threadIdx.x] == id) goto Catch_Label;
		
		result = threadIdx.x;
		goto Function_Return;

	Function_Return:
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) ^ threadIdx.x;
		}
		
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;

}

extern "C" __global__ void exception_in_loop(int iterations)
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		goto Function_Begin;

	Function_Begin:
		for(unsigned int i = 0; i < threadIdx.x; ++i)
		{
			if(input[i] > blockDim.x) goto Catch_Label;
			result += input[i];
		}
		
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) ^ threadIdx.x;
		}
		
		goto Function_Return;



	Function_Return:	
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;
}

extern "C" __global__ void exception_in_conditional()
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		goto Function_Begin;

	Function_Begin:
		if(input[threadIdx.x] > 0)
		{
			if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
			result = input[threadIdx.x];
		}
		
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) + threadIdx.x;
		}
		
		goto Function_Return;

	Function_Return:	
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;
}

int main(int argc, char** argv)
{
	unsigned int* in;

	srand(0);

	cudaGetSymbolAddress((void**)&in, "input");

	unsigned int refIn[threads];

	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = i;
	}
	
	cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
		cudaMemcpyHostToDevice);
	
	exception_in_divergent_call<<<1, threads>>>(0);
	
	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = std::rand() % threads;
	}
	
	cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
		cudaMemcpyHostToDevice);
	
	exception_in_loop<<<1, threads>>>(iterations);
	
	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = std::rand() & 1;
	}
	
	cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
		cudaMemcpyHostToDevice);
	
	exception_in_conditional<<<1, threads>>>();
}



	.file	"tmpxft_002994e0_00000000-6_TestExceptions.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z27exception_in_divergent_calljj
	.type	_Z46__device_stub__Z27exception_in_divergent_calljj, @function
_Z46__device_stub__Z27exception_in_divergent_calljj:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	exception_in_divergent_call(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z46__device_stub__Z27exception_in_divergent_calljj, .-_Z46__device_stub__Z27exception_in_divergent_calljj
	.globl	exception_in_divergent_call
	.type	exception_in_divergent_call, @function
exception_in_divergent_call:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z27exception_in_divergent_calljj
	.cfi_endproc
.LFE2034:
	.size	exception_in_divergent_call, .-exception_in_divergent_call
	.globl	_Z36__device_stub__Z17exception_in_loopii
	.type	_Z36__device_stub__Z17exception_in_loopii, @function
_Z36__device_stub__Z17exception_in_loopii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	exception_in_loop(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L8:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z36__device_stub__Z17exception_in_loopii, .-_Z36__device_stub__Z17exception_in_loopii
	.globl	exception_in_loop
	.type	exception_in_loop, @function
exception_in_loop:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z17exception_in_loopii
	.cfi_endproc
.LFE2036:
	.size	exception_in_loop, .-exception_in_loop
	.globl	_Z43__device_stub__Z24exception_in_conditionalvv
	.type	_Z43__device_stub__Z24exception_in_conditionalvv, @function
_Z43__device_stub__Z24exception_in_conditionalvv:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	exception_in_conditional(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L13:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z43__device_stub__Z24exception_in_conditionalvv, .-_Z43__device_stub__Z24exception_in_conditionalvv
	.globl	exception_in_conditional
	.type	exception_in_conditional, @function
exception_in_conditional:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z24exception_in_conditionalvv
	.cfi_endproc
.LFE2038:
	.size	exception_in_conditional, .-exception_in_conditional
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"input"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$2104, %rsp
	.cfi_def_cfa_offset 2128
	movq	%fs:40, %rax
	movq	%rax, 2088(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rbx
	call	srand@PLT
	leaq	8(%rsp), %rdi
	leaq	.LC0(%rip), %rsi
	call	cudaGetSymbolAddress@PLT
	xorl	%eax, %eax
.L19:
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	cmpq	$512, %rax
	jne	.L19
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$2048, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	xorl	%edi, %edi
	call	_Z46__device_stub__Z27exception_in_divergent_calljj
.L20:
	xorl	%ebp, %ebp
.L21:
	call	rand@PLT
	andl	$511, %eax
	movl	%eax, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	$512, %rbp
	jne	.L21
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$2048, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movl	$100, %edi
	call	_Z36__device_stub__Z17exception_in_loopii
.L22:
	xorl	%ebp, %ebp
.L23:
	call	rand@PLT
	andl	$1, %eax
	movl	%eax, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	$512, %rbp
	jne	.L23
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$2048, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	call	_Z43__device_stub__Z24exception_in_conditionalvv
.L24:
	movq	2088(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$2104, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"exception_in_conditional"
.LC2:
	.string	"exception_in_loop"
.LC3:
	.string	"exception_in_divergent_call"
.LC4:
	.string	"output"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	exception_in_conditional(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	exception_in_loop(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	exception_in_divergent_call(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$2048, %r9d
	leaq	_ZL6output(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2048, %r9d
	leaq	_ZL5input(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5input
	.comm	_ZL5input,2048,32
	.local	_ZL6output
	.comm	_ZL6output,2048,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*  \file TestExceptions.cu
	\author Gregory Diamos <gregory.diamos@gatech.edu>
	\date Tuesday November 9, 2010
	\brief A CUDA assembly test for unstructured control 
		flow mimicking exceptions.
*/


#include <hip/hip_runtime.h>
#include <cstdlib>

const unsigned int threads = 512;
const unsigned int iterations = 100;

__device__ unsigned int output[threads];
__device__ unsigned int input[threads];

extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		if(threadIdx.x == id)
		{
			goto Function_1_Begin;
		}
		else
		{
			goto Function_2_Begin;
		}

	Function_1_Begin:
		if(input[threadIdx.x] != id) goto Catch_Label;
		
		result = input[threadIdx.x];
		goto Function_Return;

	Function_2_Begin:
		if(input[threadIdx.x] == id) goto Catch_Label;
		
		result = threadIdx.x;
		goto Function_Return;

	Function_Return:
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) ^ threadIdx.x;
		}
		
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;

}

extern "C" __global__ void exception_in_loop(int iterations)
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		goto Function_Begin;

	Function_Begin:
		for(unsigned int i = 0; i < threadIdx.x; ++i)
		{
			if(input[i] > blockDim.x) goto Catch_Label;
			result += input[i];
		}
		
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) ^ threadIdx.x;
		}
		
		goto Function_Return;



	Function_Return:	
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;
}

extern "C" __global__ void exception_in_conditional()
{
	goto Try_Label;
	
	Try_Label:
		unsigned int result = 0;
		goto Function_Begin;

	Function_Begin:
		if(input[threadIdx.x] > 0)
		{
			if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
			result = input[threadIdx.x];
		}
		
		for(unsigned int i = 0; i < iterations; ++i)
		{
			result = (result >> 1) + threadIdx.x;
		}
		
		goto Function_Return;

	Function_Return:	
		output[threadIdx.x] = result;
		return;

	Catch_Label:
		output[threadIdx.x] = (unsigned int)-1; // error occurred
		return;
}

int main(int argc, char** argv)
{
	unsigned int* in;

	srand(0);

	hipGetSymbolAddress((void**)&in, HIP_SYMBOL("input"));

	unsigned int refIn[threads];

	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = i;
	}
	
	hipMemcpy(in, refIn, threads * sizeof(unsigned int),
		hipMemcpyHostToDevice);
	
	exception_in_divergent_call<<<1, threads>>>(0);
	
	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = std::rand() % threads;
	}
	
	hipMemcpy(in, refIn, threads * sizeof(unsigned int),
		hipMemcpyHostToDevice);
	
	exception_in_loop<<<1, threads>>>(iterations);
	
	for(unsigned int i = 0; i < threads; i++)
	{
		refIn[i] = std::rand() & 1;
	}
	
	hipMemcpy(in, refIn, threads * sizeof(unsigned int),
		hipMemcpyHostToDevice);
	
	exception_in_conditional<<<1, threads>>>();
}



	.text
	.file	"TestExceptions.hip"
	.globl	__device_stub__exception_in_divergent_call # -- Begin function __device_stub__exception_in_divergent_call
	.type	__device_stub__exception_in_divergent_call,@function
__device_stub__exception_in_divergent_call: # @__device_stub__exception_in_divergent_call
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$exception_in_divergent_call, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__exception_in_divergent_call, .Lfunc_end0-__device_stub__exception_in_divergent_call
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__exception_in_loop # -- Begin function __device_stub__exception_in_loop
	.type	__device_stub__exception_in_loop,@function
__device_stub__exception_in_loop:       # @__device_stub__exception_in_loop
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$exception_in_loop, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__exception_in_loop, .Lfunc_end1-__device_stub__exception_in_loop
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__exception_in_conditional # -- Begin function __device_stub__exception_in_conditional
	.type	__device_stub__exception_in_conditional,@function
__device_stub__exception_in_conditional: # @__device_stub__exception_in_conditional
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$exception_in_conditional, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__exception_in_conditional, .Lfunc_end2-__device_stub__exception_in_conditional
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$2064, %rsp                     # imm = 0x810
	.cfi_def_cfa_offset 2096
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	srand
	leaq	8(%rsp), %rdi
	movl	$.L.str, %esi
	callq	hipGetSymbolAddress
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ebx, 16(%rsp,%rbx,4)
	incq	%rbx
	cmpq	$512, %rbx                      # imm = 0x200
	jne	.LBB3_1
# %bb.2:
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movq	8(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	511(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.11:
	xorl	%edi, %edi
	callq	__device_stub__exception_in_divergent_call
.LBB3_3:                                # %.preheader52
	xorl	%r15d, %r15d
.LBB3_4:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	andl	$511, %eax                      # imm = 0x1FF
	movl	%eax, 16(%rsp,%r15,4)
	incq	%r15
	cmpq	$512, %r15                      # imm = 0x200
	jne	.LBB3_4
# %bb.5:
	movq	8(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.12:
	movl	$100, %edi
	callq	__device_stub__exception_in_loop
.LBB3_6:                                # %.preheader
	xorl	%r15d, %r15d
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	andl	$1, %eax
	movl	%eax, 16(%rsp,%r15,4)
	incq	%r15
	cmpq	$512, %r15                      # imm = 0x200
	jne	.LBB3_7
# %bb.8:
	movq	8(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	callq	__device_stub__exception_in_conditional
.LBB3_10:
	xorl	%eax, %eax
	addq	$2064, %rsp                     # imm = 0x810
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$exception_in_divergent_call, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$exception_in_loop, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$exception_in_conditional, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$output, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$2048, %r9d                     # imm = 0x800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$input, %esi
	movl	$.L.str, %edx
	movl	$.L.str, %ecx
	movl	$2048, %r9d                     # imm = 0x800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	output,@object                  # @output
	.local	output
	.comm	output,2048,16
	.type	input,@object                   # @input
	.local	input
	.comm	input,2048,16
	.type	exception_in_divergent_call,@object # @exception_in_divergent_call
	.section	.rodata,"a",@progbits
	.globl	exception_in_divergent_call
	.p2align	3, 0x0
exception_in_divergent_call:
	.quad	__device_stub__exception_in_divergent_call
	.size	exception_in_divergent_call, 8

	.type	exception_in_loop,@object       # @exception_in_loop
	.globl	exception_in_loop
	.p2align	3, 0x0
exception_in_loop:
	.quad	__device_stub__exception_in_loop
	.size	exception_in_loop, 8

	.type	exception_in_conditional,@object # @exception_in_conditional
	.globl	exception_in_conditional
	.p2align	3, 0x0
exception_in_conditional:
	.quad	__device_stub__exception_in_conditional
	.size	exception_in_conditional, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"input"
	.size	.L.str, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"exception_in_divergent_call"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"exception_in_loop"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"exception_in_conditional"
	.size	.L__unnamed_3, 25

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"output"
	.size	.L__unnamed_4, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__exception_in_divergent_call
	.addrsig_sym __device_stub__exception_in_loop
	.addrsig_sym __device_stub__exception_in_conditional
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym output
	.addrsig_sym input
	.addrsig_sym exception_in_divergent_call
	.addrsig_sym exception_in_loop
	.addrsig_sym exception_in_conditional
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	exception_in_divergent_call ; -- Begin function exception_in_divergent_call
	.globl	exception_in_divergent_call
	.p2align	8
	.type	exception_in_divergent_call,@function
exception_in_divergent_call:            ; @exception_in_divergent_call
; %bb.0:
	s_load_b32 s0, s[0:1], 0x0
	s_mov_b32 s2, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $vgpr2
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 s0, v0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v2, v0 :: v_dual_lshlrev_b32 v1, 2, v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, input@rel32@lo+4
	s_addc_u32 s3, s3, input@rel32@hi+12
	s_mov_b32 s4, -1
	global_load_b32 v1, v1, s[2:3]
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	v_mov_b32_e32 v1, 0
	s_and_b32 s2, vcc_lo, exec_lo
.LBB0_2:                                ; %Flow
	s_or_saveexec_b32 s3, s1
	v_mov_b32_e32 v3, s4
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_7
; %bb.3:
	s_mov_b32 s1, 0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, input@rel32@lo+4
	s_addc_u32 s5, s5, input@rel32@hi+12
	s_lshl_b64 s[6:7], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s4, s6, s4
	s_addc_u32 s5, s7, s5
	s_load_b32 s4, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s4, s0
	s_cbranch_scc0 .LBB0_5
; %bb.4:                                ; %._crit_edge
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, -1
	s_branch .LBB0_6
.LBB0_5:
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr4
.LBB0_6:                                ; %Flow16
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v2, s0
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s0, s1
.LBB0_7:                                ; %Flow15
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.preheader
	s_movk_i32 s1, 0x64
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v1, 1, v2
	s_add_i32 s1, s1, -1
	s_cmp_eq_u32 s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v2, v1, v0
	s_cbranch_scc0 .LBB0_9
; %bb.10:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v3, v2
.LBB0_11:                               ; %Flow17
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, output@rel32@lo+4
	s_addc_u32 s1, s1, output@rel32@hi+12
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel exception_in_divergent_call
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 4
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	exception_in_divergent_call, .Lfunc_end0-exception_in_divergent_call
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 10
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	exception_in_loop       ; -- Begin function exception_in_loop
	.globl	exception_in_loop
	.p2align	8
	.type	exception_in_loop,@function
exception_in_loop:                      ; @exception_in_loop
; %bb.0:
	v_mov_b32_e32 v3, 4
	v_mov_b32_e32 v1, 0
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB1_7
; %bb.1:                                ; %.lr.ph
	s_load_b32 s6, s[0:1], 0x14
	v_mov_b32_e32 v2, v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, input@rel32@lo+4
	s_addc_u32 s3, s3, input@rel32@hi+12
	s_mov_b32 s7, 0
                                        ; implicit-def: $sgpr8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_load_b32 s9, s[2:3], 0x0
	s_or_b32 s8, s8, exec_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_u32 s9, s6
	s_cbranch_scc1 .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v2, -1, v2
	s_add_i32 s7, s9, s7
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_and_not1_b32 s8, s8, exec_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_mov_b32 s9, 4
	s_and_b32 s10, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s8, s10
	s_branch .LBB1_5
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s9, 7
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $sgpr2_sgpr3
.LBB1_5:                                ; %Flow38
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s9
	v_mov_b32_e32 v1, s7
	s_and_b32 s10, exec_lo, s8
	s_or_b32 s5, s10, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_2
; %bb.6:                                ; %Flow39
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_7:                                ; %Flow40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v2, -1
	s_mov_b32 s3, -1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 7, v3
	s_cbranch_execz .LBB1_13
; %bb.8:                                ; %LeafBlock
	v_mov_b32_e32 v2, -1
	s_mov_b32 s4, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 4, v3
	s_cbranch_execz .LBB1_12
; %bb.9:                                ; %.preheader
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB1_11
.LBB1_10:                               ; %.lr.ph24
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v1, 1, v1
	s_add_i32 s0, s0, -1
	s_cmp_lg_u32 s0, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	s_cbranch_scc1 .LBB1_10
.LBB1_11:                               ; %Flow35
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v1
	s_mov_b32 s4, exec_lo
.LBB1_12:                               ; %Flow37
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s3, s4, exec_lo
.LBB1_13:                               ; %Flow36
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB1_15
; %bb.14:                               ; %.sink.split
	v_lshlrev_b32_e32 v0, 2, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, output@rel32@lo+4
	s_addc_u32 s1, s1, output@rel32@hi+12
	global_store_b32 v0, v2, s[0:1]
.LBB1_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel exception_in_loop
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 11
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	exception_in_loop, .Lfunc_end1-exception_in_loop
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 13
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 13
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	exception_in_conditional ; -- Begin function exception_in_conditional
	.globl	exception_in_conditional
	.p2align	8
	.type	exception_in_conditional,@function
exception_in_conditional:               ; @exception_in_conditional
; %bb.0:
	v_lshlrev_b32_e32 v1, 2, v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, input@rel32@lo+4
	s_addc_u32 s3, s3, input@rel32@hi+12
                                        ; implicit-def: $sgpr4
	global_load_b32 v2, v1, s[2:3]
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s2, 0, v2
	v_cmpx_ne_u32_e32 0, v2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b32 s0, s[0:1], 0xc
	s_mov_b32 s4, -1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, s0, v2
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s1, vcc_lo, exec_lo
	s_or_b32 s2, s0, s1
.LBB2_2:                                ; %Flow8
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v3, s4
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_6
; %bb.3:                                ; %.preheader
	s_movk_i32 s1, 0x64
.LBB2_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v2, 1, v2
	s_add_i32 s1, s1, -1
	s_cmp_lg_u32 s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v0
	s_cbranch_scc1 .LBB2_4
; %bb.5:                                ; %Flow
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v3, v2
.LBB2_6:                                ; %Flow9
	s_or_b32 exec_lo, exec_lo, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, output@rel32@lo+4
	s_addc_u32 s1, s1, output@rel32@hi+12
	global_store_b32 v1, v3, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel exception_in_conditional
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 5
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	exception_in_conditional, .Lfunc_end2-exception_in_conditional
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 200
; NumSgprs: 7
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 7
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	output                  ; @output
	.type	output,@object
	.section	.bss,"aw",@nobits
	.globl	output
	.p2align	4, 0x0
output:
	.zero	2048
	.size	output, 2048

	.protected	input                   ; @input
	.type	input,@object
	.globl	input
	.p2align	4, 0x0
input:
	.zero	2048
	.size	input, 2048

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym output
	.addrsig_sym input
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 4
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           exception_in_divergent_call
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         exception_in_divergent_call.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           exception_in_loop
    .private_segment_fixed_size: 0
    .sgpr_count:     13
    .sgpr_spill_count: 0
    .symbol:         exception_in_loop.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           exception_in_conditional
    .private_segment_fixed_size: 0
    .sgpr_count:     7
    .sgpr_spill_count: 0
    .symbol:         exception_in_conditional.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
