#define N_W 128
#define N_H 128
#define N_D 128

extern "C"   // ensure function name to be exactly "vadd"
{
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void reduction_min_kernel( double *input, double *output ){
    __shared__ double sh_data[256];

    unsigned int tid = threadIdx.x;
    unsigned int i   = blockIdx.x * blockDim.x  + threadIdx.x;
    sh_data[tid] = min( input[i], input[i + blockDim.x*gridDim.x ] ) ;
    __syncthreads();

    for( unsigned int s = blockDim.x/2; s>0; s >>= 1){
      if ( tid < s ) sh_data[tid] = min( sh_data[tid], sh_data[tid+s] );
      __syncthreads();
    }

    if ( tid == 0 ) output[ blockIdx.x ] = sh_data[0];
  }

  __device__ void writeBound(  const int boundAxis,
                  double *cnsv_1, double *cnsv_2, double *cnsv_3, double *cnsv_4, double *cnsv_5,
                  double *bound_1, double *bound_2, double *bound_3, double *bound_4, double *bound_5,
                  const int t_j, const int t_i, const int t_k, const int tid ){
    int boundId;
    if ( boundAxis == 1 ) boundId = t_i + t_k*N_H;  //X BOUNDERIES
    if ( boundAxis == 2 ) boundId = t_j + t_k*N_W;   //Y BOUNDERIES
    if ( boundAxis == 3 ) boundId = t_j + t_i*N_W;   //Z BOUNDERIES
    bound_1[boundId] = cnsv_1[tid];
    bound_2[boundId] = cnsv_2[tid];
    bound_3[boundId] = cnsv_3[tid];
    bound_4[boundId] = cnsv_4[tid];
    bound_5[boundId] = cnsv_5[tid];
  }

  __global__ void setBounderies(
         double* cnsv_1, double* cnsv_2, double* cnsv_3, double* cnsv_4, double* cnsv_5,
         double* bound_1_l, double* bound_1_r, double* bound_1_d, double* bound_1_u, double* bound_1_b, double *bound_1_t,
         double* bound_2_l, double* bound_2_r, double* bound_2_d, double* bound_2_u, double* bound_2_b, double *bound_2_t,
         double* bound_3_l, double* bound_3_r, double* bound_3_d, double* bound_3_u, double* bound_3_b, double *bound_3_t,
         double* bound_4_l, double* bound_4_r, double* bound_4_d, double* bound_4_u, double* bound_4_b, double *bound_4_t,
         double* bound_5_l, double* bound_5_r, double* bound_5_d, double* bound_5_u, double* bound_5_b, double *bound_5_t ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    bool boundBlock = false;
    if ( blockIdx.x==0 || blockIdx.y==0 || blockIdx.z==0 ) boundBlock = true;
    if ( blockIdx.x==(gridDim.x-1) || blockIdx.y==(gridDim.y-1) || blockIdx.z==(gridDim.z-1) ) boundBlock = true;

    if ( !boundBlock ) return;

    if ( t_j==0 )
      writeBound( 1, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_l, bound_2_l, bound_3_l, bound_4_l, bound_5_l,
        t_j, t_i, t_k, tid );
    if ( t_j==(N_W-1) )
      writeBound( 1, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_r, bound_2_r, bound_3_r, bound_4_r, bound_5_r,
        t_j, t_i, t_k, tid );

    if ( t_i==0 )
      writeBound( 2, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_d, bound_2_d, bound_3_d, bound_4_d, bound_5_d,
        t_j, t_i, t_k, tid );
    if ( t_i==(N_H-1) )
      writeBound( 2, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_u, bound_2_u, bound_3_u, bound_4_u, bound_5_u,
        t_j, t_i, t_k, tid );

    if ( t_k==0 )
      writeBound( 3, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_b, bound_2_b, bound_3_b, bound_4_b, bound_5_b,
        t_j, t_i, t_k, tid );
    if ( t_k==(N_D-1) )
      writeBound( 3, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_t, bound_2_t, bound_3_t, bound_4_t, bound_5_t,
        t_j, t_i, t_k, tid );
  }

  __device__ double hll_interFlux( double val_l, double val_r, double F_l, double F_r, double s_l, double s_r ){
    if ( s_l > 0 ) return F_l;
    if ( s_r < 0 ) return F_r;
    return ( s_r*F_l - s_l*F_r + s_l*s_r*( val_r - val_l ) ) / ( s_r - s_l );
  }

  __device__ void writeInterFlux(const int coord, int tid,
          double rho_l, double rho_r, double vx_l, double vx_r, double vy_l, double vy_r, double vz_l, double vz_r, double E_l, double E_r,
          double p_l, double p_r, double s_l, double s_r, double *iFlx_1, double *iFlx_2, double *iFlx_3, double *iFlx_4, double *iFlx_5  ){

    // Adjacent fluxes from left and center cell
    double F_l, F_r;

    //iFlx rho
    if ( coord == 1 ){
      F_l = rho_l * vx_l;
      F_r = rho_r * vx_r;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vy_l;
      F_r = rho_r * vy_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vz_l;
      F_r = rho_r * vz_r;
    }
    iFlx_1[tid] = hll_interFlux( rho_l, rho_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vx
    if ( coord == 1 ){
      F_l = rho_l * vx_l * vx_l + p_l;
      F_r = rho_r * vx_r * vx_r + p_r;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vx_l * vy_l;
      F_r = rho_r * vx_r * vy_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vx_l * vz_l;
      F_r = rho_r * vx_r * vz_r;
    }
    iFlx_2[tid] = hll_interFlux( rho_l*vx_l, rho_r*vx_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vy
    if ( coord == 1 ){
      F_l = rho_l * vy_l * vx_l ;
      F_r = rho_r * vy_r * vx_r ;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vy_l * vy_l + p_l;
      F_r = rho_r * vy_r * vy_r + p_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vy_l * vz_l;
      F_r = rho_r * vy_r * vz_r;
    }
    iFlx_3[tid] = hll_interFlux( rho_l*vy_l, rho_r*vy_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vz
    if ( coord == 1 ){
      F_l = rho_l * vz_l * vx_l ;
      F_r = rho_r * vz_r * vx_r ;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vz_l * vy_l ;
      F_r = rho_r * vz_r * vy_r ;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vz_l * vz_l + p_l ;
      F_r = rho_r * vz_r * vz_r + p_r ;
    }
    iFlx_4[tid] = hll_interFlux( rho_l*vz_l, rho_r*vz_r, F_l, F_r, s_l, s_r );

    //iFlx E
    if ( coord == 1 ){
      F_l = vx_l * ( E_l + p_l ) ;
      F_r = vx_r * ( E_r + p_r ) ;
    }
    else if ( coord == 2 ){
      F_l = vy_l * ( E_l + p_l ) ;
      F_r = vy_r * ( E_r + p_r ) ;
    }
    else if ( coord == 3 ){
      F_l = vz_l * ( E_l + p_l ) ;
      F_r = vz_r * ( E_r + p_r ) ;
    }
    iFlx_5[tid] = hll_interFlux( E_l, E_r, F_l, F_r, s_l, s_r );
  }
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void setInterFlux_hll( const int coord, const double gamma, const double dx, const double dy, const double dz,
  			 double* cnsv_1, double* cnsv_2, double* cnsv_3, double* cnsv_4, double* cnsv_5,
         double* iFlx_1, double* iFlx_2, double* iFlx_3, double* iFlx_4, double* iFlx_5,
         double* bound_1_l, double* bound_2_l, double* bound_3_l, double* bound_4_l, double* bound_5_l,
         double* bound_1_r, double* bound_2_r, double* bound_3_r, double* bound_4_r, double* bound_5_r,
         double* iFlx_1_bnd, double* iFlx_2_bnd, double* iFlx_3_bnd, double* iFlx_4_bnd, double* iFlx_5_bnd,
         double* times ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    int tid_adj, boundId;
    double v2;
    double rho_l, vx_l, vy_l, vz_l, E_l, p_l;
    double rho_c, vx_c, vy_c, vz_c, E_c, p_c;

    //Set adjacent id
    if ( coord == 1 ){
      if ( t_j == 0) tid_adj = (t_j) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = (t_j-1) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    if ( coord == 2 ){
      if ( t_i == 0) tid_adj = t_j + (t_i)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + (t_i-1)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    if ( coord == 3 ){
      if ( t_k == 0) tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k-1)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    //Read adjacent and center conservatives
    rho_l = cnsv_1[ tid_adj ];
    rho_c = cnsv_1[ tid ];

    vx_l = cnsv_2[ tid_adj ] / rho_l;
    vx_c = cnsv_2[ tid ] / rho_c;

    vy_l = cnsv_3[ tid_adj ] / rho_l;
    vy_c = cnsv_3[ tid ] / rho_c;

    vz_l = cnsv_4[ tid_adj ] / rho_l;
    vz_c = cnsv_4[ tid ] / rho_c;

    E_l = cnsv_5[ tid_adj ];
    E_c = cnsv_5[ tid ];

    //Load and apply boundery conditions
    if ( coord == 1 ){
      boundId = t_i + t_k*N_H;
      if ( t_j == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }
    if ( coord == 2 ){
      boundId = t_j + t_k*N_W;
      if ( t_i == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }
    if ( coord == 3 ){
      boundId = t_j + t_i*N_W;
      if ( t_k == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }


  //   //Boundary bounce condition
  //     if ( t_j == 0 ) vx_l = -vx_c;
  //       //Boundary bounce condition
  //     if ( t_i == 0 ) vy_l = -vy_c;
  //     //Boundary bounce condition
  //     if ( t_k == 0 ) vz_l = -vz_c;

    v2    = vx_l*vx_l + vy_l*vy_l + vz_l*vz_l;
    p_l   = ( E_l - rho_l*v2/2 ) * (gamma-1);

    v2    = vx_c*vx_c + vy_c*vy_c + vz_c*vz_c;
    p_c   = ( E_c - rho_c*v2/2 ) * (gamma-1);

    double cs_l, cs_c, s_l, s_c;
    cs_l = sqrt( p_l * gamma / rho_l );
    cs_c = sqrt( p_c * gamma / rho_c );

    if ( coord == 1 ){
      s_l = min( vx_l - cs_l, vx_c - cs_c );
      s_c = max( vx_l + cs_l, vx_c + cs_c );
      //Use v2 to save time minimum
      v2 = dx / ( abs( vx_c ) + cs_c );
      v2 = min( v2, dy / ( abs( vy_c ) + cs_c ) );
      v2 = min( v2, dz / ( abs( vz_c ) + cs_c ) );
      times[ tid ] = v2;
    }

    else if ( coord == 2 ){
      s_l = min( vy_l - cs_l, vy_c - cs_c );
      s_c = max( vy_l + cs_l, vy_c + cs_c );
    }

    else if ( coord == 3 ){
      s_l = min( vz_l - cs_l, vz_c - cs_c );
      s_c = max( vz_l + cs_l, vz_c + cs_c );
    }

    writeInterFlux( coord, tid, rho_l, rho_c, vx_l, vx_c, vy_l, vy_c, vz_l, vz_c, E_l, E_c,
            p_l, p_c, s_l, s_c, iFlx_1, iFlx_2, iFlx_3, iFlx_4, iFlx_5  );

    //Get iFlux_r for most right cell
    // if ( blockIdx.x!=(gridDim.x-1) || blockIdx.y!=(gridDim.y-1) || blockIdx.z!=(gridDim.z-1) ) return;

    if ( coord == 1 ){
      if ( t_j != (N_W-1) ) return;
    }
    if ( coord == 2 ){
      if ( t_i != (N_H-1) ) return;
    }
    if ( coord == 3 ){
      if ( t_k != (N_D-1) ) return;
    }

    rho_l = rho_c;
    vx_l = vx_c;
    vy_l = vy_c;
    vz_l = vz_c;
    E_l = E_c;
    p_l = p_c;
    cs_l = cs_c;

    //Load Bounderies for right part of the box_size
    rho_c = bound_1_r[boundId];
    vx_c  = bound_2_r[boundId] / rho_c;
    vy_c  = bound_3_r[boundId] / rho_c;
    vz_c  = bound_4_r[boundId] / rho_c;
    E_c   = bound_5_r[boundId];

    v2    = vx_c*vx_c + vy_c*vy_c + vz_c*vz_c;
    p_c   = ( E_c - rho_c*v2/2 ) * (gamma-1);
    cs_c = sqrt( p_c * gamma / rho_c );
    if ( coord == 1 ){
      s_l = min( vx_l - cs_l, vx_c - cs_c );
      s_c = max( vx_l + cs_l, vx_c + cs_c );
    }

    else if ( coord == 2 ){
      s_l = min( vy_l - cs_l, vy_c - cs_c );
      s_c = max( vy_l + cs_l, vy_c + cs_c );
    }

    else if ( coord == 3 ){
      s_l = min( vz_l - cs_l, vz_c - cs_c );
      s_c = max( vz_l + cs_l, vz_c + cs_c );
    }

    writeInterFlux( coord, boundId, rho_l, rho_c, vx_l, vx_c, vy_l, vy_c, vz_l, vz_c, E_l, E_c,
            p_l, p_c, s_l, s_c, iFlx_1_bnd, iFlx_2_bnd, iFlx_3_bnd, iFlx_4_bnd, iFlx_5_bnd  );
  }
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

  __global__ void getInterFlux_hll( const int coord, const double dt,  const double gamma,
         const double dx, const double dy, const double dz,
         double* cnsv_adv_1, double* cnsv_adv_2, double* cnsv_adv_3, double* cnsv_adv_4, double* cnsv_adv_5,
         double* iFlx_1, double* iFlx_2, double* iFlx_3, double* iFlx_4, double* iFlx_5,
         double* iFlx_1_bnd, double* iFlx_2_bnd, double* iFlx_3_bnd, double* iFlx_4_bnd, double* iFlx_5_bnd ){
  			//  double* gForceX, double* gForceY, double* gForceZ, double* gravWork ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    int tid_adj, boundId;
    double iFlx1_l, iFlx2_l, iFlx3_l, iFlx4_l, iFlx5_l;
    double iFlx1_r, iFlx2_r, iFlx3_r, iFlx4_r, iFlx5_r;
    double delta;

    //Set adjacent id
    if ( coord == 1 ){
      if ( t_j == N_W-1 ) tid_adj = (t_j) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = (t_j+1) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dx;
    }
    if ( coord == 2 ){
      if ( t_i == N_H-1 ) tid_adj = t_j + (t_i)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + (t_i+1)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dy;
    }
    if ( coord == 3 ){
      if ( t_k == N_D-1) tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k+1)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dz;
    }

    //Read inter-cell fluxes
    iFlx1_l = iFlx_1[ tid ];
    iFlx1_r = iFlx_1[ tid_adj ];

    iFlx2_l = iFlx_2[ tid ];
    iFlx2_r = iFlx_2[ tid_adj ];

    iFlx3_l = iFlx_3[ tid ];
    iFlx3_r = iFlx_3[ tid_adj ];

    iFlx4_l = iFlx_4[ tid ];
    iFlx4_r = iFlx_4[ tid_adj ];

    iFlx5_l = iFlx_5[ tid ];
    iFlx5_r = iFlx_5[ tid_adj ];

    if ( coord == 1 ){
      boundId = t_i + t_k*N_H;
      if ( t_j == (N_W-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    if ( coord == 2 ){
      boundId = t_j + t_k*N_W;
      if ( t_i == (N_H-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    if ( coord == 3 ){
      boundId = t_j + t_i*N_W;
      if ( t_k == (N_D-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    //Load and apply boundery conditions
    // if ( coord == 1 ){
    //   boundId = t_i + t_k*N_H;
    //   if ( t_j == (N_W-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }
    // if ( coord == 2 ){
    //   boundId = t_j + t_k*N_W;
    //   if ( t_i == (N_H-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }
    // if ( coord == 3 ){
    //   boundId = t_j + t_i*N_W;
    //   if ( t_k == (N_D-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }

    //Advance the consv values
    // cnsv_1[ tid ] = cnsv_1[ tid ] - delta*( iFlx1_r - iFlx1_l );
    // cnsv_2[ tid ] = cnsv_2[ tid ] - delta*( iFlx2_r - iFlx2_l ) + dt*gForceX[tid]*50;
    // cnsv_3[ tid ] = cnsv_3[ tid ] - delta*( iFlx3_r - iFlx3_l ) + dt*gForceY[tid]*50;
    // cnsv_4[ tid ] = cnsv_4[ tid ] - delta*( iFlx4_r - iFlx4_l ) + dt*gForceZ[tid]*50;
    // cnsv_5[ tid ] = cnsv_5[ tid ] - delta*( iFlx5_r - iFlx5_l ) + dt*gravWork[tid]*50;

    if ( coord == 1 ){
      cnsv_adv_1[ tid ] = -delta*( iFlx1_r - iFlx1_l );
      cnsv_adv_2[ tid ] = -delta*( iFlx2_r - iFlx2_l );
      cnsv_adv_3[ tid ] = -delta*( iFlx3_r - iFlx3_l );
      cnsv_adv_4[ tid ] = -delta*( iFlx4_r - iFlx4_l );
      cnsv_adv_5[ tid ] = -delta*( iFlx5_r - iFlx5_l );
    }
    else{
      cnsv_adv_1[ tid ] = cnsv_adv_1[ tid ] - delta*( iFlx1_r - iFlx1_l );
      cnsv_adv_2[ tid ] = cnsv_adv_2[ tid ] - delta*( iFlx2_r - iFlx2_l );
      cnsv_adv_3[ tid ] = cnsv_adv_3[ tid ] - delta*( iFlx3_r - iFlx3_l );
      cnsv_adv_4[ tid ] = cnsv_adv_4[ tid ] - delta*( iFlx4_r - iFlx4_l );
      cnsv_adv_5[ tid ] = cnsv_adv_5[ tid ] - delta*( iFlx5_r - iFlx5_l );
    }
  }

  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void reduction_kernel( double *input, double *output ){
    __shared__ double sh_data[256];

    unsigned int tid = threadIdx.x;
    unsigned int i   = blockIdx.x * blockDim.x  + threadIdx.x;
    sh_data[tid] = input[i] + input[i + blockDim.x*gridDim.x ] ;
    __syncthreads();

    for( unsigned int s = blockDim.x/2; s>0; s >>= 1){
      if ( tid < s ) sh_data[tid] += sh_data[tid+s];
      __syncthreads();
    }

    if ( tid == 0 ) output[ blockIdx.x ] = sh_data[0];
  }
  __global__ void copyDtoD( double *src, double *dst ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    dst[tid] = src[tid];
  }
  __global__ void addDtoD(
      double *dst_1, double *dst_2, double *dst_3, double *dst_4, double *dst_5,
      double *sum_1, double *sum_2, double *sum_3, double *sum_4, double *sum_5 ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    dst_1[tid] = dst_1[tid] + sum_1[tid];
    dst_2[tid] = dst_2[tid] + sum_2[tid];
    dst_3[tid] = dst_3[tid] + sum_3[tid];
    dst_4[tid] = dst_4[tid] + sum_4[tid];
    dst_5[tid] = dst_5[tid] + sum_5[tid];
  }
}

	.file	"tmpxft_0036a2b0_00000000-6_hydro_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	writeBound
	.type	writeBound, @function
writeBound:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	writeBound, .-writeBound
	.globl	hll_interFlux
	.type	hll_interFlux, @function
hll_interFlux:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	hll_interFlux, .-hll_interFlux
	.globl	writeInterFlux
	.type	writeInterFlux, @function
writeInterFlux:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	writeInterFlux, .-writeInterFlux
	.globl	_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_
	.type	_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_, @function
_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduction_min_kernel(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_, .-_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_
	.globl	reduction_min_kernel
	.type	reduction_min_kernel, @function
reduction_min_kernel:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z20reduction_min_kernelPdS_PdS_
	.cfi_endproc
.LFE2036:
	.size	reduction_min_kernel, .-reduction_min_kernel
	.globl	_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$648, %rsp
	.cfi_def_cfa_offset 656
	movq	656(%rsp), %rax
	movq	%rdi, 280(%rsp)
	leaq	304(%rsp), %rdi
	movq	%rsi, 272(%rsp)
	leaq	316(%rsp), %rsi
	movq	%rax, 232(%rsp)
	movq	664(%rsp), %rax
	movq	%rdx, 264(%rsp)
	leaq	288(%rsp), %rdx
	movq	%rax, 224(%rsp)
	movq	672(%rsp), %rax
	movq	%rcx, 256(%rsp)
	leaq	296(%rsp), %rcx
	movq	%rax, 216(%rsp)
	movq	680(%rsp), %rax
	movq	%r8, 248(%rsp)
	movq	%rax, 208(%rsp)
	movq	688(%rsp), %rax
	movq	%r9, 240(%rsp)
	movq	%rax, 200(%rsp)
	movq	696(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	704(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	712(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	720(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	728(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	736(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	744(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	752(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	760(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	768(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	776(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	784(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	792(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	800(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	808(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	816(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	824(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	832(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	840(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	848(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	856(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	864(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	872(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	880(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 632(%rsp)
	xorl	%eax, %eax
	leaq	280(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 480(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 488(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 496(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 504(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 512(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 520(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 528(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 536(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 544(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 552(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 560(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 568(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 576(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 584(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 592(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 600(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 608(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 616(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 624(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 304(%rsp)
	movl	$1, 312(%rsp)
	movq	%rax, 316(%rsp)
	movl	$1, 324(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	296(%rsp)
	.cfi_def_cfa_offset 664
	leaq	setBounderies(%rip), %rdi
	pushq	296(%rsp)
	.cfi_def_cfa_offset 672
	movq	332(%rsp), %rcx
	movl	340(%rsp), %r8d
	movq	320(%rsp), %rsi
	movl	328(%rsp), %edx
	leaq	368(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 664
	popq	%rdx
	.cfi_def_cfa_offset 656
.L14:
	movq	632(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$648, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	setBounderies
	.type	setBounderies, @function
setBounderies:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z101__device_stub__Z13setBounderiesPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2038:
	.size	setBounderies, .-setBounderies
	.globl	_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$584, %rsp
	.cfi_def_cfa_offset 592
	movq	592(%rsp), %rax
	movl	%edi, 252(%rsp)
	leaq	272(%rsp), %rdi
	movq	%rsi, 208(%rsp)
	leaq	284(%rsp), %rsi
	movq	%rax, 168(%rsp)
	movq	600(%rsp), %rax
	movq	%rdx, 200(%rsp)
	leaq	256(%rsp), %rdx
	movq	%rax, 160(%rsp)
	movq	608(%rsp), %rax
	movq	%rcx, 192(%rsp)
	leaq	264(%rsp), %rcx
	movq	%rax, 152(%rsp)
	movq	616(%rsp), %rax
	movq	%r8, 184(%rsp)
	movq	%rax, 144(%rsp)
	movq	624(%rsp), %rax
	movq	%r9, 176(%rsp)
	movq	%rax, 136(%rsp)
	movq	632(%rsp), %rax
	movsd	%xmm0, 240(%rsp)
	movq	%rax, 128(%rsp)
	movq	640(%rsp), %rax
	movsd	%xmm1, 232(%rsp)
	movq	%rax, 120(%rsp)
	movq	648(%rsp), %rax
	movsd	%xmm2, 224(%rsp)
	movq	%rax, 112(%rsp)
	movq	656(%rsp), %rax
	movsd	%xmm3, 216(%rsp)
	movq	%rax, 104(%rsp)
	movq	664(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	672(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	680(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	688(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	696(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	704(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	712(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	720(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	728(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	736(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	744(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	752(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 568(%rsp)
	xorl	%eax, %eax
	leaq	252(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 480(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 488(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 496(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 504(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 512(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 520(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 528(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 536(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 544(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 552(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 560(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 272(%rsp)
	movl	$1, 280(%rsp)
	movq	%rax, 284(%rsp)
	movl	$1, 292(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	264(%rsp)
	.cfi_def_cfa_offset 600
	leaq	setInterFlux_hll(%rip), %rdi
	pushq	264(%rsp)
	.cfi_def_cfa_offset 608
	movq	300(%rsp), %rcx
	movl	308(%rsp), %r8d
	movq	288(%rsp), %rsi
	movl	296(%rsp), %edx
	leaq	336(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 600
	popq	%rdx
	.cfi_def_cfa_offset 592
.L19:
	movq	568(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$584, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	setInterFlux_hll
	.type	setInterFlux_hll, @function
setInterFlux_hll:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z91__device_stub__Z16setInterFlux_hlliddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2040:
	.size	setInterFlux_hll, .-setInterFlux_hll
	.globl	_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$424, %rsp
	.cfi_def_cfa_offset 432
	movq	432(%rsp), %rax
	movl	%edi, 172(%rsp)
	leaq	192(%rsp), %rdi
	movq	%rsi, 120(%rsp)
	leaq	204(%rsp), %rsi
	movq	%rax, 80(%rsp)
	movq	440(%rsp), %rax
	movq	%rdx, 112(%rsp)
	leaq	176(%rsp), %rdx
	movq	%rax, 72(%rsp)
	movq	448(%rsp), %rax
	movq	%rcx, 104(%rsp)
	leaq	184(%rsp), %rcx
	movq	%rax, 64(%rsp)
	movq	456(%rsp), %rax
	movq	%r8, 96(%rsp)
	movq	%rax, 56(%rsp)
	movq	464(%rsp), %rax
	movq	%r9, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	472(%rsp), %rax
	movsd	%xmm0, 160(%rsp)
	movq	%rax, 40(%rsp)
	movq	480(%rsp), %rax
	movsd	%xmm1, 152(%rsp)
	movq	%rax, 32(%rsp)
	movq	488(%rsp), %rax
	movsd	%xmm2, 144(%rsp)
	movq	%rax, 24(%rsp)
	movq	496(%rsp), %rax
	movsd	%xmm3, 136(%rsp)
	movq	%rax, 16(%rsp)
	movq	504(%rsp), %rax
	movsd	%xmm4, 128(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 408(%rsp)
	xorl	%eax, %eax
	leaq	172(%rsp), %rax
	movl	$1, 200(%rsp)
	movq	%rax, 240(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 400(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 192(%rsp)
	movq	%rax, 204(%rsp)
	movl	$1, 212(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	184(%rsp)
	.cfi_def_cfa_offset 440
	leaq	getInterFlux_hll(%rip), %rdi
	pushq	184(%rsp)
	.cfi_def_cfa_offset 448
	movq	220(%rsp), %rcx
	movl	228(%rsp), %r8d
	movq	208(%rsp), %rsi
	movl	216(%rsp), %edx
	leaq	256(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 440
	popq	%rdx
	.cfi_def_cfa_offset 432
.L24:
	movq	408(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$424, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	getInterFlux_hll
	.type	getInterFlux_hll, @function
getInterFlux_hll:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z70__device_stub__Z16getInterFlux_hllidddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_idddddPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2042:
	.size	getInterFlux_hll, .-getInterFlux_hll
	.globl	_Z38__device_stub__Z16reduction_kernelPdS_PdS_
	.type	_Z38__device_stub__Z16reduction_kernelPdS_PdS_, @function
_Z38__device_stub__Z16reduction_kernelPdS_PdS_:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	reduction_kernel(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L29:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z38__device_stub__Z16reduction_kernelPdS_PdS_, .-_Z38__device_stub__Z16reduction_kernelPdS_PdS_
	.globl	reduction_kernel
	.type	reduction_kernel, @function
reduction_kernel:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z16reduction_kernelPdS_PdS_
	.cfi_endproc
.LFE2044:
	.size	reduction_kernel, .-reduction_kernel
	.globl	_Z29__device_stub__Z8copyDtoDPdS_PdS_
	.type	_Z29__device_stub__Z8copyDtoDPdS_PdS_, @function
_Z29__device_stub__Z8copyDtoDPdS_PdS_:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	copyDtoD(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L34:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z29__device_stub__Z8copyDtoDPdS_PdS_, .-_Z29__device_stub__Z8copyDtoDPdS_PdS_
	.globl	copyDtoD
	.type	copyDtoD, @function
copyDtoD:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8copyDtoDPdS_PdS_
	.cfi_endproc
.LFE2046:
	.size	copyDtoD, .-copyDtoD
	.globl	_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_
	.type	_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_, @function
_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_:
.LFB2047:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	addDtoD(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L39:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2047:
	.size	_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_, .-_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_
	.globl	addDtoD
	.type	addDtoD, @function
addDtoD:
.LFB2048:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z7addDtoDPdS_S_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2048:
	.size	addDtoD, .-addDtoD
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"addDtoD"
.LC1:
	.string	"copyDtoD"
.LC2:
	.string	"reduction_kernel"
.LC3:
	.string	"getInterFlux_hll"
.LC4:
	.string	"setInterFlux_hll"
.LC5:
	.string	"setBounderies"
.LC6:
	.string	"reduction_min_kernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2050:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	addDtoD(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	copyDtoD(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduction_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	getInterFlux_hll(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	setInterFlux_hll(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	setBounderies(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	reduction_min_kernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2050:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define N_W 128
#define N_H 128
#define N_D 128

extern "C"   // ensure function name to be exactly "vadd"
{
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void reduction_min_kernel( double *input, double *output ){
    __shared__ double sh_data[256];

    unsigned int tid = threadIdx.x;
    unsigned int i   = blockIdx.x * blockDim.x  + threadIdx.x;
    sh_data[tid] = min( input[i], input[i + blockDim.x*gridDim.x ] ) ;
    __syncthreads();

    for( unsigned int s = blockDim.x/2; s>0; s >>= 1){
      if ( tid < s ) sh_data[tid] = min( sh_data[tid], sh_data[tid+s] );
      __syncthreads();
    }

    if ( tid == 0 ) output[ blockIdx.x ] = sh_data[0];
  }

  __device__ void writeBound(  const int boundAxis,
                  double *cnsv_1, double *cnsv_2, double *cnsv_3, double *cnsv_4, double *cnsv_5,
                  double *bound_1, double *bound_2, double *bound_3, double *bound_4, double *bound_5,
                  const int t_j, const int t_i, const int t_k, const int tid ){
    int boundId;
    if ( boundAxis == 1 ) boundId = t_i + t_k*N_H;  //X BOUNDERIES
    if ( boundAxis == 2 ) boundId = t_j + t_k*N_W;   //Y BOUNDERIES
    if ( boundAxis == 3 ) boundId = t_j + t_i*N_W;   //Z BOUNDERIES
    bound_1[boundId] = cnsv_1[tid];
    bound_2[boundId] = cnsv_2[tid];
    bound_3[boundId] = cnsv_3[tid];
    bound_4[boundId] = cnsv_4[tid];
    bound_5[boundId] = cnsv_5[tid];
  }

  __global__ void setBounderies(
         double* cnsv_1, double* cnsv_2, double* cnsv_3, double* cnsv_4, double* cnsv_5,
         double* bound_1_l, double* bound_1_r, double* bound_1_d, double* bound_1_u, double* bound_1_b, double *bound_1_t,
         double* bound_2_l, double* bound_2_r, double* bound_2_d, double* bound_2_u, double* bound_2_b, double *bound_2_t,
         double* bound_3_l, double* bound_3_r, double* bound_3_d, double* bound_3_u, double* bound_3_b, double *bound_3_t,
         double* bound_4_l, double* bound_4_r, double* bound_4_d, double* bound_4_u, double* bound_4_b, double *bound_4_t,
         double* bound_5_l, double* bound_5_r, double* bound_5_d, double* bound_5_u, double* bound_5_b, double *bound_5_t ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    bool boundBlock = false;
    if ( blockIdx.x==0 || blockIdx.y==0 || blockIdx.z==0 ) boundBlock = true;
    if ( blockIdx.x==(gridDim.x-1) || blockIdx.y==(gridDim.y-1) || blockIdx.z==(gridDim.z-1) ) boundBlock = true;

    if ( !boundBlock ) return;

    if ( t_j==0 )
      writeBound( 1, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_l, bound_2_l, bound_3_l, bound_4_l, bound_5_l,
        t_j, t_i, t_k, tid );
    if ( t_j==(N_W-1) )
      writeBound( 1, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_r, bound_2_r, bound_3_r, bound_4_r, bound_5_r,
        t_j, t_i, t_k, tid );

    if ( t_i==0 )
      writeBound( 2, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_d, bound_2_d, bound_3_d, bound_4_d, bound_5_d,
        t_j, t_i, t_k, tid );
    if ( t_i==(N_H-1) )
      writeBound( 2, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_u, bound_2_u, bound_3_u, bound_4_u, bound_5_u,
        t_j, t_i, t_k, tid );

    if ( t_k==0 )
      writeBound( 3, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_b, bound_2_b, bound_3_b, bound_4_b, bound_5_b,
        t_j, t_i, t_k, tid );
    if ( t_k==(N_D-1) )
      writeBound( 3, cnsv_1, cnsv_2, cnsv_3, cnsv_4, cnsv_5,
        bound_1_t, bound_2_t, bound_3_t, bound_4_t, bound_5_t,
        t_j, t_i, t_k, tid );
  }

  __device__ double hll_interFlux( double val_l, double val_r, double F_l, double F_r, double s_l, double s_r ){
    if ( s_l > 0 ) return F_l;
    if ( s_r < 0 ) return F_r;
    return ( s_r*F_l - s_l*F_r + s_l*s_r*( val_r - val_l ) ) / ( s_r - s_l );
  }

  __device__ void writeInterFlux(const int coord, int tid,
          double rho_l, double rho_r, double vx_l, double vx_r, double vy_l, double vy_r, double vz_l, double vz_r, double E_l, double E_r,
          double p_l, double p_r, double s_l, double s_r, double *iFlx_1, double *iFlx_2, double *iFlx_3, double *iFlx_4, double *iFlx_5  ){

    // Adjacent fluxes from left and center cell
    double F_l, F_r;

    //iFlx rho
    if ( coord == 1 ){
      F_l = rho_l * vx_l;
      F_r = rho_r * vx_r;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vy_l;
      F_r = rho_r * vy_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vz_l;
      F_r = rho_r * vz_r;
    }
    iFlx_1[tid] = hll_interFlux( rho_l, rho_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vx
    if ( coord == 1 ){
      F_l = rho_l * vx_l * vx_l + p_l;
      F_r = rho_r * vx_r * vx_r + p_r;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vx_l * vy_l;
      F_r = rho_r * vx_r * vy_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vx_l * vz_l;
      F_r = rho_r * vx_r * vz_r;
    }
    iFlx_2[tid] = hll_interFlux( rho_l*vx_l, rho_r*vx_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vy
    if ( coord == 1 ){
      F_l = rho_l * vy_l * vx_l ;
      F_r = rho_r * vy_r * vx_r ;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vy_l * vy_l + p_l;
      F_r = rho_r * vy_r * vy_r + p_r;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vy_l * vz_l;
      F_r = rho_r * vy_r * vz_r;
    }
    iFlx_3[tid] = hll_interFlux( rho_l*vy_l, rho_r*vy_r, F_l, F_r, s_l, s_r );

    //iFlx rho * vz
    if ( coord == 1 ){
      F_l = rho_l * vz_l * vx_l ;
      F_r = rho_r * vz_r * vx_r ;
    }
    else if ( coord == 2 ){
      F_l = rho_l * vz_l * vy_l ;
      F_r = rho_r * vz_r * vy_r ;
    }
    else if ( coord == 3 ){
      F_l = rho_l * vz_l * vz_l + p_l ;
      F_r = rho_r * vz_r * vz_r + p_r ;
    }
    iFlx_4[tid] = hll_interFlux( rho_l*vz_l, rho_r*vz_r, F_l, F_r, s_l, s_r );

    //iFlx E
    if ( coord == 1 ){
      F_l = vx_l * ( E_l + p_l ) ;
      F_r = vx_r * ( E_r + p_r ) ;
    }
    else if ( coord == 2 ){
      F_l = vy_l * ( E_l + p_l ) ;
      F_r = vy_r * ( E_r + p_r ) ;
    }
    else if ( coord == 3 ){
      F_l = vz_l * ( E_l + p_l ) ;
      F_r = vz_r * ( E_r + p_r ) ;
    }
    iFlx_5[tid] = hll_interFlux( E_l, E_r, F_l, F_r, s_l, s_r );
  }
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void setInterFlux_hll( const int coord, const double gamma, const double dx, const double dy, const double dz,
  			 double* cnsv_1, double* cnsv_2, double* cnsv_3, double* cnsv_4, double* cnsv_5,
         double* iFlx_1, double* iFlx_2, double* iFlx_3, double* iFlx_4, double* iFlx_5,
         double* bound_1_l, double* bound_2_l, double* bound_3_l, double* bound_4_l, double* bound_5_l,
         double* bound_1_r, double* bound_2_r, double* bound_3_r, double* bound_4_r, double* bound_5_r,
         double* iFlx_1_bnd, double* iFlx_2_bnd, double* iFlx_3_bnd, double* iFlx_4_bnd, double* iFlx_5_bnd,
         double* times ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    int tid_adj, boundId;
    double v2;
    double rho_l, vx_l, vy_l, vz_l, E_l, p_l;
    double rho_c, vx_c, vy_c, vz_c, E_c, p_c;

    //Set adjacent id
    if ( coord == 1 ){
      if ( t_j == 0) tid_adj = (t_j) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = (t_j-1) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    if ( coord == 2 ){
      if ( t_i == 0) tid_adj = t_j + (t_i)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + (t_i-1)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    if ( coord == 3 ){
      if ( t_k == 0) tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k-1)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
    }
    //Read adjacent and center conservatives
    rho_l = cnsv_1[ tid_adj ];
    rho_c = cnsv_1[ tid ];

    vx_l = cnsv_2[ tid_adj ] / rho_l;
    vx_c = cnsv_2[ tid ] / rho_c;

    vy_l = cnsv_3[ tid_adj ] / rho_l;
    vy_c = cnsv_3[ tid ] / rho_c;

    vz_l = cnsv_4[ tid_adj ] / rho_l;
    vz_c = cnsv_4[ tid ] / rho_c;

    E_l = cnsv_5[ tid_adj ];
    E_c = cnsv_5[ tid ];

    //Load and apply boundery conditions
    if ( coord == 1 ){
      boundId = t_i + t_k*N_H;
      if ( t_j == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }
    if ( coord == 2 ){
      boundId = t_j + t_k*N_W;
      if ( t_i == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }
    if ( coord == 3 ){
      boundId = t_j + t_i*N_W;
      if ( t_k == 0) {
        rho_l = bound_1_l[boundId];
        vx_l  = bound_2_l[boundId] / rho_l;
        vy_l  = bound_3_l[boundId] / rho_l;
        vz_l  = bound_4_l[boundId] / rho_l;
        E_l   = bound_5_l[boundId];
      }
    }


  //   //Boundary bounce condition
  //     if ( t_j == 0 ) vx_l = -vx_c;
  //       //Boundary bounce condition
  //     if ( t_i == 0 ) vy_l = -vy_c;
  //     //Boundary bounce condition
  //     if ( t_k == 0 ) vz_l = -vz_c;

    v2    = vx_l*vx_l + vy_l*vy_l + vz_l*vz_l;
    p_l   = ( E_l - rho_l*v2/2 ) * (gamma-1);

    v2    = vx_c*vx_c + vy_c*vy_c + vz_c*vz_c;
    p_c   = ( E_c - rho_c*v2/2 ) * (gamma-1);

    double cs_l, cs_c, s_l, s_c;
    cs_l = sqrt( p_l * gamma / rho_l );
    cs_c = sqrt( p_c * gamma / rho_c );

    if ( coord == 1 ){
      s_l = min( vx_l - cs_l, vx_c - cs_c );
      s_c = max( vx_l + cs_l, vx_c + cs_c );
      //Use v2 to save time minimum
      v2 = dx / ( abs( vx_c ) + cs_c );
      v2 = min( v2, dy / ( abs( vy_c ) + cs_c ) );
      v2 = min( v2, dz / ( abs( vz_c ) + cs_c ) );
      times[ tid ] = v2;
    }

    else if ( coord == 2 ){
      s_l = min( vy_l - cs_l, vy_c - cs_c );
      s_c = max( vy_l + cs_l, vy_c + cs_c );
    }

    else if ( coord == 3 ){
      s_l = min( vz_l - cs_l, vz_c - cs_c );
      s_c = max( vz_l + cs_l, vz_c + cs_c );
    }

    writeInterFlux( coord, tid, rho_l, rho_c, vx_l, vx_c, vy_l, vy_c, vz_l, vz_c, E_l, E_c,
            p_l, p_c, s_l, s_c, iFlx_1, iFlx_2, iFlx_3, iFlx_4, iFlx_5  );

    //Get iFlux_r for most right cell
    // if ( blockIdx.x!=(gridDim.x-1) || blockIdx.y!=(gridDim.y-1) || blockIdx.z!=(gridDim.z-1) ) return;

    if ( coord == 1 ){
      if ( t_j != (N_W-1) ) return;
    }
    if ( coord == 2 ){
      if ( t_i != (N_H-1) ) return;
    }
    if ( coord == 3 ){
      if ( t_k != (N_D-1) ) return;
    }

    rho_l = rho_c;
    vx_l = vx_c;
    vy_l = vy_c;
    vz_l = vz_c;
    E_l = E_c;
    p_l = p_c;
    cs_l = cs_c;

    //Load Bounderies for right part of the box_size
    rho_c = bound_1_r[boundId];
    vx_c  = bound_2_r[boundId] / rho_c;
    vy_c  = bound_3_r[boundId] / rho_c;
    vz_c  = bound_4_r[boundId] / rho_c;
    E_c   = bound_5_r[boundId];

    v2    = vx_c*vx_c + vy_c*vy_c + vz_c*vz_c;
    p_c   = ( E_c - rho_c*v2/2 ) * (gamma-1);
    cs_c = sqrt( p_c * gamma / rho_c );
    if ( coord == 1 ){
      s_l = min( vx_l - cs_l, vx_c - cs_c );
      s_c = max( vx_l + cs_l, vx_c + cs_c );
    }

    else if ( coord == 2 ){
      s_l = min( vy_l - cs_l, vy_c - cs_c );
      s_c = max( vy_l + cs_l, vy_c + cs_c );
    }

    else if ( coord == 3 ){
      s_l = min( vz_l - cs_l, vz_c - cs_c );
      s_c = max( vz_l + cs_l, vz_c + cs_c );
    }

    writeInterFlux( coord, boundId, rho_l, rho_c, vx_l, vx_c, vy_l, vy_c, vz_l, vz_c, E_l, E_c,
            p_l, p_c, s_l, s_c, iFlx_1_bnd, iFlx_2_bnd, iFlx_3_bnd, iFlx_4_bnd, iFlx_5_bnd  );
  }
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

  __global__ void getInterFlux_hll( const int coord, const double dt,  const double gamma,
         const double dx, const double dy, const double dz,
         double* cnsv_adv_1, double* cnsv_adv_2, double* cnsv_adv_3, double* cnsv_adv_4, double* cnsv_adv_5,
         double* iFlx_1, double* iFlx_2, double* iFlx_3, double* iFlx_4, double* iFlx_5,
         double* iFlx_1_bnd, double* iFlx_2_bnd, double* iFlx_3_bnd, double* iFlx_4_bnd, double* iFlx_5_bnd ){
  			//  double* gForceX, double* gForceY, double* gForceZ, double* gravWork ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    int tid_adj, boundId;
    double iFlx1_l, iFlx2_l, iFlx3_l, iFlx4_l, iFlx5_l;
    double iFlx1_r, iFlx2_r, iFlx3_r, iFlx4_r, iFlx5_r;
    double delta;

    //Set adjacent id
    if ( coord == 1 ){
      if ( t_j == N_W-1 ) tid_adj = (t_j) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = (t_j+1) + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dx;
    }
    if ( coord == 2 ){
      if ( t_i == N_H-1 ) tid_adj = t_j + (t_i)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + (t_i+1)*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dy;
    }
    if ( coord == 3 ){
      if ( t_k == N_D-1) tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      else tid_adj = t_j + t_i*blockDim.x*gridDim.x + (t_k+1)*blockDim.x*gridDim.x*blockDim.y*gridDim.y;
      delta = dt / dz;
    }

    //Read inter-cell fluxes
    iFlx1_l = iFlx_1[ tid ];
    iFlx1_r = iFlx_1[ tid_adj ];

    iFlx2_l = iFlx_2[ tid ];
    iFlx2_r = iFlx_2[ tid_adj ];

    iFlx3_l = iFlx_3[ tid ];
    iFlx3_r = iFlx_3[ tid_adj ];

    iFlx4_l = iFlx_4[ tid ];
    iFlx4_r = iFlx_4[ tid_adj ];

    iFlx5_l = iFlx_5[ tid ];
    iFlx5_r = iFlx_5[ tid_adj ];

    if ( coord == 1 ){
      boundId = t_i + t_k*N_H;
      if ( t_j == (N_W-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    if ( coord == 2 ){
      boundId = t_j + t_k*N_W;
      if ( t_i == (N_H-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    if ( coord == 3 ){
      boundId = t_j + t_i*N_W;
      if ( t_k == (N_D-1) ) {
        iFlx1_r = iFlx_1_bnd[boundId];
        iFlx2_r = iFlx_2_bnd[boundId];
        iFlx3_r = iFlx_3_bnd[boundId];
        iFlx4_r = iFlx_4_bnd[boundId];
        iFlx5_r = iFlx_5_bnd[boundId];
      }
    }
    //Load and apply boundery conditions
    // if ( coord == 1 ){
    //   boundId = t_i + t_k*N_H;
    //   if ( t_j == (N_W-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }
    // if ( coord == 2 ){
    //   boundId = t_j + t_k*N_W;
    //   if ( t_i == (N_H-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }
    // if ( coord == 3 ){
    //   boundId = t_j + t_i*N_W;
    //   if ( t_k == (N_D-1) ) {
    //     iFlx1_r = iFlx_1_bnd[boundId];
    //     iFlx2_r = iFlx_2_bnd[boundId];
    //     iFlx3_r = iFlx_3_bnd[boundId];
    //     iFlx4_r = iFlx_4_bnd[boundId];
    //     iFlx5_r = iFlx_5_bnd[boundId];
    //   }
    // }

    //Advance the consv values
    // cnsv_1[ tid ] = cnsv_1[ tid ] - delta*( iFlx1_r - iFlx1_l );
    // cnsv_2[ tid ] = cnsv_2[ tid ] - delta*( iFlx2_r - iFlx2_l ) + dt*gForceX[tid]*50;
    // cnsv_3[ tid ] = cnsv_3[ tid ] - delta*( iFlx3_r - iFlx3_l ) + dt*gForceY[tid]*50;
    // cnsv_4[ tid ] = cnsv_4[ tid ] - delta*( iFlx4_r - iFlx4_l ) + dt*gForceZ[tid]*50;
    // cnsv_5[ tid ] = cnsv_5[ tid ] - delta*( iFlx5_r - iFlx5_l ) + dt*gravWork[tid]*50;

    if ( coord == 1 ){
      cnsv_adv_1[ tid ] = -delta*( iFlx1_r - iFlx1_l );
      cnsv_adv_2[ tid ] = -delta*( iFlx2_r - iFlx2_l );
      cnsv_adv_3[ tid ] = -delta*( iFlx3_r - iFlx3_l );
      cnsv_adv_4[ tid ] = -delta*( iFlx4_r - iFlx4_l );
      cnsv_adv_5[ tid ] = -delta*( iFlx5_r - iFlx5_l );
    }
    else{
      cnsv_adv_1[ tid ] = cnsv_adv_1[ tid ] - delta*( iFlx1_r - iFlx1_l );
      cnsv_adv_2[ tid ] = cnsv_adv_2[ tid ] - delta*( iFlx2_r - iFlx2_l );
      cnsv_adv_3[ tid ] = cnsv_adv_3[ tid ] - delta*( iFlx3_r - iFlx3_l );
      cnsv_adv_4[ tid ] = cnsv_adv_4[ tid ] - delta*( iFlx4_r - iFlx4_l );
      cnsv_adv_5[ tid ] = cnsv_adv_5[ tid ] - delta*( iFlx5_r - iFlx5_l );
    }
  }

  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  __global__ void reduction_kernel( double *input, double *output ){
    __shared__ double sh_data[256];

    unsigned int tid = threadIdx.x;
    unsigned int i   = blockIdx.x * blockDim.x  + threadIdx.x;
    sh_data[tid] = input[i] + input[i + blockDim.x*gridDim.x ] ;
    __syncthreads();

    for( unsigned int s = blockDim.x/2; s>0; s >>= 1){
      if ( tid < s ) sh_data[tid] += sh_data[tid+s];
      __syncthreads();
    }

    if ( tid == 0 ) output[ blockIdx.x ] = sh_data[0];
  }
  __global__ void copyDtoD( double *src, double *dst ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    dst[tid] = src[tid];
  }
  __global__ void addDtoD(
      double *dst_1, double *dst_2, double *dst_3, double *dst_4, double *dst_5,
      double *sum_1, double *sum_2, double *sum_3, double *sum_4, double *sum_5 ){
    int t_j = blockIdx.x*blockDim.x + threadIdx.x;
    int t_i = blockIdx.y*blockDim.y + threadIdx.y;
    int t_k = blockIdx.z*blockDim.z + threadIdx.z;
    int tid = t_j + t_i*blockDim.x*gridDim.x + t_k*blockDim.x*gridDim.x*blockDim.y*gridDim.y;

    dst_1[tid] = dst_1[tid] + sum_1[tid];
    dst_2[tid] = dst_2[tid] + sum_2[tid];
    dst_3[tid] = dst_3[tid] + sum_3[tid];
    dst_4[tid] = dst_4[tid] + sum_4[tid];
    dst_5[tid] = dst_5[tid] + sum_5[tid];
  }
}

	.text
	.file	"hydro_kernels.hip"
	.globl	__device_stub__reduction_min_kernel # -- Begin function __device_stub__reduction_min_kernel
	.type	__device_stub__reduction_min_kernel,@function
__device_stub__reduction_min_kernel:    # @__device_stub__reduction_min_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduction_min_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__reduction_min_kernel, .Lfunc_end0-__device_stub__reduction_min_kernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__setBounderies    # -- Begin function __device_stub__setBounderies
	.type	__device_stub__setBounderies,@function
__device_stub__setBounderies:           # @__device_stub__setBounderies
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$384, %rsp                      # imm = 0x180
	.cfi_def_cfa_offset 432
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	512(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	520(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	528(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	536(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	544(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	552(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	560(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	568(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	576(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	584(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	592(%rsp), %rax
	movq	%rax, 208(%rbx)
	leaq	600(%rsp), %rax
	movq	%rax, 216(%rbx)
	leaq	608(%rsp), %rax
	movq	%rax, 224(%rbx)
	leaq	616(%rsp), %rax
	movq	%rax, 232(%rbx)
	leaq	624(%rsp), %rax
	movq	%rax, 240(%rbx)
	leaq	632(%rsp), %rax
	movq	%rax, 248(%rbx)
	leaq	640(%rsp), %rax
	movq	%rax, 256(%rbx)
	leaq	648(%rsp), %rax
	movq	%rax, 264(%rbx)
	leaq	656(%rsp), %rax
	movq	%rax, 272(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$setBounderies, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$400, %rsp                      # imm = 0x190
	.cfi_adjust_cfa_offset -400
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__setBounderies, .Lfunc_end1-__device_stub__setBounderies
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__setInterFlux_hll # -- Begin function __device_stub__setInterFlux_hll
	.type	__device_stub__setInterFlux_hll,@function
__device_stub__setInterFlux_hll:        # @__device_stub__setInterFlux_hll
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$384, %rsp                      # imm = 0x180
	.cfi_def_cfa_offset 432
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	88(%rsp), %rdi
	movsd	%xmm0, (%rdi)
	leaq	80(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	72(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	64(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	56(%rsp), %r15
	movq	%rsi, (%r15)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%r11, 24(%rbx)
	movq	%r14, 32(%rbx)
	movq	%r15, 40(%rbx)
	movq	%rsi, 48(%rbx)
	movq	%rdx, 56(%rbx)
	movq	%rcx, 64(%rbx)
	movq	%r8, 72(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	512(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	520(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	528(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	536(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	544(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	552(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	560(%rsp), %rax
	movq	%rax, 208(%rbx)
	leaq	568(%rsp), %rax
	movq	%rax, 216(%rbx)
	leaq	576(%rsp), %rax
	movq	%rax, 224(%rbx)
	leaq	584(%rsp), %rax
	movq	%rax, 232(%rbx)
	leaq	592(%rsp), %rax
	movq	%rax, 240(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$setInterFlux_hll, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$400, %rsp                      # imm = 0x190
	.cfi_adjust_cfa_offset -400
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__setInterFlux_hll, .Lfunc_end2-__device_stub__setInterFlux_hll
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__getInterFlux_hll # -- Begin function __device_stub__getInterFlux_hll
	.type	__device_stub__getInterFlux_hll,@function
__device_stub__getInterFlux_hll:        # @__device_stub__getInterFlux_hll
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$320, %rsp                      # imm = 0x140
	.cfi_def_cfa_offset 368
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	104(%rsp), %rdi
	movsd	%xmm0, (%rdi)
	leaq	96(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	88(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	80(%rsp), %r14
	movsd	%xmm3, (%r14)
	leaq	72(%rsp), %r15
	movsd	%xmm4, (%r15)
	leaq	64(%rsp), %r12
	movq	%rsi, (%r12)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	144(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%r11, 24(%rbx)
	movq	%r14, 32(%rbx)
	movq	%r15, 40(%rbx)
	movq	%r12, 48(%rbx)
	movq	%rsi, 56(%rbx)
	movq	%rdx, 64(%rbx)
	movq	%rcx, 72(%rbx)
	movq	%r8, 80(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	128(%rsp), %r14
	leaq	112(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$getInterFlux_hll, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$336, %rsp                      # imm = 0x150
	.cfi_adjust_cfa_offset -336
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__getInterFlux_hll, .Lfunc_end3-__device_stub__getInterFlux_hll
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__reduction_kernel # -- Begin function __device_stub__reduction_kernel
	.type	__device_stub__reduction_kernel,@function
__device_stub__reduction_kernel:        # @__device_stub__reduction_kernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$reduction_kernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__reduction_kernel, .Lfunc_end4-__device_stub__reduction_kernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__copyDtoD         # -- Begin function __device_stub__copyDtoD
	.type	__device_stub__copyDtoD,@function
__device_stub__copyDtoD:                # @__device_stub__copyDtoD
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$copyDtoD, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__copyDtoD, .Lfunc_end5-__device_stub__copyDtoD
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__addDtoD          # -- Begin function __device_stub__addDtoD
	.type	__device_stub__addDtoD,@function
__device_stub__addDtoD:                 # @__device_stub__addDtoD
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$addDtoD, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	__device_stub__addDtoD, .Lfunc_end6-__device_stub__addDtoD
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduction_min_kernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$setBounderies, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$setInterFlux_hll, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$getInterFlux_hll, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$reduction_kernel, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$copyDtoD, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$addDtoD, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	reduction_min_kernel,@object    # @reduction_min_kernel
	.section	.rodata,"a",@progbits
	.globl	reduction_min_kernel
	.p2align	3, 0x0
reduction_min_kernel:
	.quad	__device_stub__reduction_min_kernel
	.size	reduction_min_kernel, 8

	.type	setBounderies,@object           # @setBounderies
	.globl	setBounderies
	.p2align	3, 0x0
setBounderies:
	.quad	__device_stub__setBounderies
	.size	setBounderies, 8

	.type	setInterFlux_hll,@object        # @setInterFlux_hll
	.globl	setInterFlux_hll
	.p2align	3, 0x0
setInterFlux_hll:
	.quad	__device_stub__setInterFlux_hll
	.size	setInterFlux_hll, 8

	.type	getInterFlux_hll,@object        # @getInterFlux_hll
	.globl	getInterFlux_hll
	.p2align	3, 0x0
getInterFlux_hll:
	.quad	__device_stub__getInterFlux_hll
	.size	getInterFlux_hll, 8

	.type	reduction_kernel,@object        # @reduction_kernel
	.globl	reduction_kernel
	.p2align	3, 0x0
reduction_kernel:
	.quad	__device_stub__reduction_kernel
	.size	reduction_kernel, 8

	.type	copyDtoD,@object                # @copyDtoD
	.globl	copyDtoD
	.p2align	3, 0x0
copyDtoD:
	.quad	__device_stub__copyDtoD
	.size	copyDtoD, 8

	.type	addDtoD,@object                 # @addDtoD
	.globl	addDtoD
	.p2align	3, 0x0
addDtoD:
	.quad	__device_stub__addDtoD
	.size	addDtoD, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"reduction_min_kernel"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"setBounderies"
	.size	.L__unnamed_2, 14

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"setInterFlux_hll"
	.size	.L__unnamed_3, 17

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"getInterFlux_hll"
	.size	.L__unnamed_4, 17

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"reduction_kernel"
	.size	.L__unnamed_5, 17

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"copyDtoD"
	.size	.L__unnamed_6, 9

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"addDtoD"
	.size	.L__unnamed_7, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__reduction_min_kernel
	.addrsig_sym __device_stub__setBounderies
	.addrsig_sym __device_stub__setInterFlux_hll
	.addrsig_sym __device_stub__getInterFlux_hll
	.addrsig_sym __device_stub__reduction_kernel
	.addrsig_sym __device_stub__copyDtoD
	.addrsig_sym __device_stub__addDtoD
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym reduction_min_kernel
	.addrsig_sym setBounderies
	.addrsig_sym setInterFlux_hll
	.addrsig_sym getInterFlux_hll
	.addrsig_sym reduction_kernel
	.addrsig_sym copyDtoD
	.addrsig_sym addDtoD
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	reduction_min_kernel    ; -- Begin function reduction_min_kernel
	.globl	reduction_min_kernel
	.p2align	8
	.type	reduction_min_kernel,@function
reduction_min_kernel:                   ; @reduction_min_kernel
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_mad_u64_u32 v[3:4], null, s6, s5, v[1:2]
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(1)
	v_max_f64 v[1:2], v[1:2], v[1:2]
	s_waitcnt vmcnt(0)
	v_max_f64 v[3:4], v[3:4], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f64 v[2:3], v[1:2], v[3:4]
	v_lshlrev_b32_e32 v1, 3, v0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshl_add_u32 v2, s0, 3, v1
	ds_load_b64 v[2:3], v2
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(1)
	v_max_f64 v[2:3], v[2:3], v[2:3]
	s_waitcnt lgkmcnt(0)
	v_max_f64 v[4:5], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f64 v[2:3], v[4:5], v[2:3]
	ds_store_b64 v1, v[2:3]
.LBB0_4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB0_1
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduction_min_kernel
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	reduction_min_kernel, .Lfunc_end0-reduction_min_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	setBounderies           ; -- Begin function setBounderies
	.globl	setBounderies
	.p2align	8
	.type	setBounderies,@function
setBounderies:                          ; @setBounderies
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x118
	s_add_u32 s4, s0, 0x118
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s6, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, s6
	s_cselect_b32 s6, -1, 0
	s_add_i32 s7, s3, -1
	s_cmp_eq_u32 s14, s7
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s6, s7
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB1_2
; %bb.1:
	s_load_b32 s4, s[4:5], 0x8
	s_cmp_eq_u32 s13, 0
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cselect_b32 s6, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s5, s6
	s_cmp_eq_u32 s15, 0
	s_cselect_b32 s6, -1, 0
	s_or_b32 s5, s6, s5
	s_waitcnt lgkmcnt(0)
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, s4
	s_cselect_b32 s4, -1, 0
	s_or_b32 s6, s5, s4
.LBB1_2:                                ; %Flow284
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB1_26
; %bb.3:                                ; %NodeBlock
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x124
	s_load_b512 s[16:31], s[0:1], 0x0
	s_load_b512 s[52:67], s[0:1], 0x40
	v_bfe_u32 v6, v0, 20, 10
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b512 s[68:83], s[0:1], 0x80
	s_load_b512 s[36:51], s[0:1], 0xc0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_lshr_b32 s6, s4, 16
	s_and_b32 s5, s5, 0xffff
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[4:5], null, s15, s5, v[6:7]
	v_mad_u64_u32 v[0:1], null, s14, s6, v[2:3]
	s_mul_i32 s3, s3, s6
	s_mul_i32 s2, s2, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s13, s4, v[3:4]
	v_mad_u64_u32 v[5:6], null, s3, v4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s2, v5, v[1:2]
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0x7e, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_7
; %bb.4:                                ; %LeafBlock261
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0x7f, v1
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v9, v4, 7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s28, v9
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s60, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s61, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s72, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s73, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s22, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s36, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s37, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, s24, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_u32 v7, vcc_lo, s48, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s49, v10, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
.LBB1_6:                                ; %Flow281
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_7:                                ; %Flow283
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB1_11
; %bb.8:                                ; %LeafBlock
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_10
; %bb.9:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v9, v4, 7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s26, v9
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_ci_u32_e32 v12, vcc_lo, s27, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s58, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s59, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s70, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s71, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s22, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s82, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s83, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, s24, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_u32 v7, vcc_lo, s46, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s47, v10, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
.LBB1_10:                               ; %Flow282
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_11:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x100
	s_load_b64 s[0:1], s[0:1], 0x110
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0x7e, v0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_15
; %bb.12:                               ; %LeafBlock265
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0x7f, v0
	s_cbranch_execz .LBB1_14
; %bb.13:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v9, v4, 7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s52, v9
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_ci_u32_e32 v12, vcc_lo, s53, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s64, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s65, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s76, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s77, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s22, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s40, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s41, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, s24, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
.LBB1_14:                               ; %Flow278
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_15:                               ; %Flow280
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB1_19
; %bb.16:                               ; %LeafBlock263
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_18
; %bb.17:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v9, v4, 7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s16, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s30, v9
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_ci_u32_e32 v12, vcc_lo, s31, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s62, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s63, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s74, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s75, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s22, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[13:14], off
	v_add_co_u32 v11, vcc_lo, s38, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s39, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, s24, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s25, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_u32 v7, vcc_lo, s50, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s51, v10, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
.LBB1_18:                               ; %Flow279
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_19:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0x7e, v4
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_23
; %bb.20:                               ; %LeafBlock271
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0x7f, v4
	s_cbranch_execz .LBB1_22
; %bb.21:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v0, v0, 7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v4, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s56, v0
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s68, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s69, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s80, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s81, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s44, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s45, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB1_22:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr2_vgpr3
.LBB1_23:                               ; %Flow276
	s_waitcnt lgkmcnt(0)
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_26
; %bb.24:                               ; %LeafBlock269
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_26
; %bb.25:
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshl_add_u32 v0, v0, 7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v4, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s54, v0
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s55, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s66, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s67, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s78, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s79, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s42, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s43, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB1_26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel setBounderies
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 536
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 84
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	setBounderies, .Lfunc_end1-setBounderies
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2140
; NumSgprs: 86
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 86
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	setInterFlux_hll        ; -- Begin function setInterFlux_hll
	.globl	setInterFlux_hll
	.p2align	8
	.type	setInterFlux_hll,@function
setInterFlux_hll:                       ; @setInterFlux_hll
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x104
	s_load_b64 s[4:5], s[0:1], 0xf8
	s_load_b32 s28, s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s2, 16
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[16:17], null, s14, s6, v[1:2]
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[17:18], null, s15, s3, v[0:1]
	s_mul_i32 s3, s4, s2
	v_mad_u64_u32 v[18:19], null, s13, s2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v4, s3, v16
	s_mul_i32 s2, s3, s5
	s_cmp_eq_u32 s28, 1
	s_mul_i32 s2, s2, s6
	s_cselect_b32 s31, -1, 0
	v_mul_lo_u32 v3, s2, v17
	s_cmp_lg_u32 s28, 1
                                        ; implicit-def: $vgpr1
	s_cselect_b32 s29, -1, 0
	v_add_nc_u32_e32 v2, v4, v18
	s_and_b32 vcc_lo, exec_lo, s29
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v2
	s_cbranch_vccnz .LBB2_6
; %bb.1:
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u32_e32 0, v18
	s_xor_b32 s4, exec_lo, s4
; %bb.2:
	v_add_nc_u32_e32 v1, -1, v0
; %bb.3:                                ; %Flow675
	s_and_not1_saveexec_b32 s4, s4
; %bb.4:
	v_add_nc_u32_e32 v1, v3, v4
; %bb.5:                                ; %Flow676
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_6:
	s_cmp_eq_u32 s28, 2
	s_cselect_b32 s33, -1, 0
	s_cmp_lg_u32 s28, 2
	s_cselect_b32 s30, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB2_12
; %bb.7:
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_ne_u32_e32 0, v16
	s_xor_b32 s4, exec_lo, s4
; %bb.8:
	v_subrev_nc_u32_e32 v1, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v1, v1, v18, v3
; %bb.9:                                ; %Flow672
	s_and_not1_saveexec_b32 s3, s4
; %bb.10:
	v_add_nc_u32_e32 v1, v3, v18
; %bb.11:                               ; %Flow673
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_12:
	s_cmp_eq_u32 s28, 3
	s_cselect_b32 s34, -1, 0
	s_cmp_lg_u32 s28, 3
	s_cbranch_scc1 .LBB2_16
; %bb.13:
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v17
; %bb.14:
	v_subrev_nc_u32_e32 v1, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v2
; %bb.15:                               ; %Flow670
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
.LBB2_16:
	s_load_b512 s[4:19], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b512 s[36:51], s[0:1], 0x48
	v_lshlrev_b64 v[8:9], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v9, vcc_lo
	v_add_co_u32 v3, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v9, vcc_lo
	v_add_co_u32 v5, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v9, vcc_lo
	global_load_b64 v[26:27], v[1:2], off
	global_load_b64 v[12:13], v[3:4], off
	v_add_co_u32 v1, vcc_lo, s18, v8
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v9, vcc_lo
	global_load_b64 v[14:15], v[5:6], off
	global_load_b64 v[24:25], v[1:2], off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s12, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v20, vcc_lo
	v_add_co_u32 v2, vcc_lo, s14, v19
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v20, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v19
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v20, vcc_lo
	v_add_co_u32 v21, vcc_lo, s18, v19
	v_add_co_ci_u32_e32 v22, vcc_lo, s19, v20, vcc_lo
	global_load_b64 v[10:11], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_u32 v0, vcc_lo, s36, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s36, v19
	v_add_co_ci_u32_e32 v9, vcc_lo, s37, v20, vcc_lo
	global_load_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[21:22], off
	s_clause 0x1
	global_load_b64 v[22:23], v[0:1], off
	global_load_b64 v[0:1], v[8:9], off
	s_load_b512 s[12:27], s[0:1], 0x88
	s_waitcnt vmcnt(8)
	v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[12:13]
	v_div_scale_f64 v[44:45], vcc_lo, v[12:13], v[26:27], v[12:13]
	s_waitcnt vmcnt(7)
	v_div_scale_f64 v[30:31], null, v[26:27], v[26:27], v[14:15]
	s_waitcnt vmcnt(6)
	v_div_scale_f64 v[32:33], null, v[26:27], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_rcp_f64_e32 v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_fma_f64 v[8:9], -v[28:29], v[34:35], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[8:9], v[34:35], v[8:9], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[36:37], v[40:41], v[36:37]
	v_fma_f64 v[36:37], v[38:39], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], -v[28:29], v[8:9], 1.0
	v_fma_f64 v[40:41], -v[30:31], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], -v[32:33], v[36:37], 1.0
	v_fma_f64 v[8:9], v[8:9], v[38:39], v[8:9]
	v_div_scale_f64 v[38:39], s2, v[14:15], v[26:27], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[34:35], v[34:35], v[40:41], v[34:35]
	v_div_scale_f64 v[40:41], s3, v[24:25], v[26:27], v[24:25]
	v_fma_f64 v[36:37], v[36:37], v[42:43], v[36:37]
	v_mul_f64 v[42:43], v[44:45], v[8:9]
	v_mul_f64 v[46:47], v[38:39], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[48:49], v[40:41], v[36:37]
	v_fma_f64 v[28:29], -v[28:29], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], -v[30:31], v[46:47], v[38:39]
	v_fma_f64 v[32:33], -v[32:33], v[48:49], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[28:29], v[8:9], v[42:43]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[30:31], v[30:31], v[34:35], v[46:47]
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[32:33], v[32:33], v[36:37], v[48:49]
	s_and_not1_b32 vcc_lo, exec_lo, s31
	v_div_fixup_f64 v[28:29], v[8:9], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[30:31], v[30:31], v[26:27], v[14:15]
	v_div_fixup_f64 v[36:37], v[32:33], v[26:27], v[24:25]
	s_cbranch_vccnz .LBB2_20
; %bb.17:
	v_lshl_add_u32 v21, v17, 7, v16
	s_mov_b32 s35, exec_lo
	v_cmpx_eq_u32_e32 0, v18
	s_cbranch_execz .LBB2_19
; %bb.18:
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[21:22]
	v_add_co_u32 v12, vcc_lo, s48, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s49, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, s50, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s51, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v22, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v23, vcc_lo, s13, v9, vcc_lo
	global_load_b64 v[26:27], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off
	v_add_co_u32 v14, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v9, vcc_lo
	global_load_b64 v[24:25], v[22:23], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b64 v[22:23], v[8:9], off
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[12:13]
	v_div_scale_f64 v[44:45], vcc_lo, v[12:13], v[26:27], v[12:13]
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[30:31], null, v[26:27], v[26:27], v[24:25]
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[32:33], null, v[26:27], v[26:27], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_rcp_f64_e32 v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_fma_f64 v[8:9], -v[28:29], v[34:35], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[8:9], v[34:35], v[8:9], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[36:37], v[40:41], v[36:37]
	v_fma_f64 v[36:37], v[38:39], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], -v[28:29], v[8:9], 1.0
	v_fma_f64 v[40:41], -v[30:31], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], -v[32:33], v[36:37], 1.0
	v_fma_f64 v[8:9], v[8:9], v[38:39], v[8:9]
	v_div_scale_f64 v[38:39], s2, v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[34:35], v[34:35], v[40:41], v[34:35]
	v_div_scale_f64 v[40:41], s3, v[14:15], v[26:27], v[14:15]
	v_fma_f64 v[36:37], v[36:37], v[42:43], v[36:37]
	v_mul_f64 v[42:43], v[44:45], v[8:9]
	v_mul_f64 v[46:47], v[38:39], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[48:49], v[40:41], v[36:37]
	v_fma_f64 v[28:29], -v[28:29], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], -v[30:31], v[46:47], v[38:39]
	v_fma_f64 v[32:33], -v[32:33], v[48:49], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[28:29], v[8:9], v[42:43]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[30:31], v[30:31], v[34:35], v[46:47]
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[32:33], v[32:33], v[36:37], v[48:49]
	v_div_fixup_f64 v[28:29], v[8:9], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[30:31], v[30:31], v[26:27], v[24:25]
	v_div_fixup_f64 v[36:37], v[32:33], v[26:27], v[14:15]
.LBB2_19:                               ; %Flow668
	s_or_b32 exec_lo, exec_lo, s35
	s_branch .LBB2_21
.LBB2_20:
                                        ; implicit-def: $vgpr21
.LBB2_21:
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB2_25
; %bb.22:
	v_lshl_add_u32 v21, v17, 7, v18
	s_mov_b32 s35, exec_lo
	v_cmpx_eq_u32_e32 0, v16
	s_cbranch_execz .LBB2_24
; %bb.23:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[21:22]
	v_add_co_u32 v12, vcc_lo, s48, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s49, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, s50, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s51, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v22, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v23, vcc_lo, s13, v9, vcc_lo
	global_load_b64 v[26:27], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off
	v_add_co_u32 v14, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v9, vcc_lo
	global_load_b64 v[24:25], v[22:23], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b64 v[22:23], v[8:9], off
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[12:13]
	v_div_scale_f64 v[44:45], vcc_lo, v[12:13], v[26:27], v[12:13]
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[30:31], null, v[26:27], v[26:27], v[24:25]
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[32:33], null, v[26:27], v[26:27], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_rcp_f64_e32 v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_fma_f64 v[8:9], -v[28:29], v[34:35], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[8:9], v[34:35], v[8:9], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[36:37], v[40:41], v[36:37]
	v_fma_f64 v[36:37], v[38:39], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], -v[28:29], v[8:9], 1.0
	v_fma_f64 v[40:41], -v[30:31], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], -v[32:33], v[36:37], 1.0
	v_fma_f64 v[8:9], v[8:9], v[38:39], v[8:9]
	v_div_scale_f64 v[38:39], s2, v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[34:35], v[34:35], v[40:41], v[34:35]
	v_div_scale_f64 v[40:41], s3, v[14:15], v[26:27], v[14:15]
	v_fma_f64 v[36:37], v[36:37], v[42:43], v[36:37]
	v_mul_f64 v[42:43], v[44:45], v[8:9]
	v_mul_f64 v[46:47], v[38:39], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[48:49], v[40:41], v[36:37]
	v_fma_f64 v[28:29], -v[28:29], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], -v[30:31], v[46:47], v[38:39]
	v_fma_f64 v[32:33], -v[32:33], v[48:49], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[28:29], v[8:9], v[42:43]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[30:31], v[30:31], v[34:35], v[46:47]
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[32:33], v[32:33], v[36:37], v[48:49]
	v_div_fixup_f64 v[28:29], v[8:9], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[30:31], v[30:31], v[26:27], v[24:25]
	v_div_fixup_f64 v[36:37], v[32:33], v[26:27], v[14:15]
.LBB2_24:                               ; %Flow667
	s_or_b32 exec_lo, exec_lo, s35
.LBB2_25:
	v_cndmask_b32_e64 v54, 0, 1, s34
	s_and_not1_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccnz .LBB2_29
; %bb.26:
	v_lshl_add_u32 v21, v16, 7, v18
	s_mov_b32 s35, exec_lo
	v_cmpx_eq_u32_e32 0, v17
	s_cbranch_execz .LBB2_28
; %bb.27:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[21:22]
	v_add_co_u32 v12, vcc_lo, s48, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s49, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, s50, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s51, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v22, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v23, vcc_lo, s13, v9, vcc_lo
	global_load_b64 v[26:27], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off
	v_add_co_u32 v14, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v9, vcc_lo
	global_load_b64 v[24:25], v[22:23], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	global_load_b64 v[22:23], v[8:9], off
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[12:13]
	v_div_scale_f64 v[44:45], vcc_lo, v[12:13], v[26:27], v[12:13]
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[30:31], null, v[26:27], v[26:27], v[24:25]
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[32:33], null, v[26:27], v[26:27], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_rcp_f64_e32 v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_fma_f64 v[8:9], -v[28:29], v[34:35], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[8:9], v[34:35], v[8:9], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[36:37], v[40:41], v[36:37]
	v_fma_f64 v[36:37], v[38:39], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], -v[28:29], v[8:9], 1.0
	v_fma_f64 v[40:41], -v[30:31], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], -v[32:33], v[36:37], 1.0
	v_fma_f64 v[8:9], v[8:9], v[38:39], v[8:9]
	v_div_scale_f64 v[38:39], s2, v[24:25], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[34:35], v[34:35], v[40:41], v[34:35]
	v_div_scale_f64 v[40:41], s3, v[14:15], v[26:27], v[14:15]
	v_fma_f64 v[36:37], v[36:37], v[42:43], v[36:37]
	v_mul_f64 v[42:43], v[44:45], v[8:9]
	v_mul_f64 v[46:47], v[38:39], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[48:49], v[40:41], v[36:37]
	v_fma_f64 v[28:29], -v[28:29], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], -v[30:31], v[46:47], v[38:39]
	v_fma_f64 v[32:33], -v[32:33], v[48:49], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[28:29], v[8:9], v[42:43]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[30:31], v[30:31], v[34:35], v[46:47]
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[32:33], v[32:33], v[36:37], v[48:49]
	v_div_fixup_f64 v[28:29], v[8:9], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[30:31], v[30:31], v[26:27], v[24:25]
	v_div_fixup_f64 v[36:37], v[32:33], v[26:27], v[14:15]
.LBB2_28:                               ; %Flow666
	s_or_b32 exec_lo, exec_lo, s35
.LBB2_29:
	s_waitcnt vmcnt(4)
	v_div_scale_f64 v[8:9], null, v[10:11], v[10:11], v[2:3]
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], v[6:7]
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[32:33], null, v[10:11], v[10:11], v[4:5]
	v_div_scale_f64 v[48:49], s3, v[4:5], v[10:11], v[4:5]
	s_load_b256 s[48:55], s[0:1], 0xc8
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[12:15], s[0:1], 0xe8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[14:15], v[8:9]
	v_rcp_f64_e32 v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[40:41], v[32:33]
	v_fma_f64 v[34:35], -v[8:9], v[14:15], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[38:39], -v[12:13], v[24:25], 1.0
	v_fma_f64 v[14:15], v[14:15], v[34:35], v[14:15]
	v_fma_f64 v[34:35], -v[32:33], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[24:25], v[38:39], v[24:25]
	v_fma_f64 v[38:39], -v[8:9], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[40:41], v[34:35], v[40:41]
	v_fma_f64 v[42:43], -v[12:13], v[24:25], 1.0
	v_div_scale_f64 v[40:41], vcc_lo, v[2:3], v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[14:15], v[38:39], v[14:15]
	v_div_scale_f64 v[38:39], s2, v[6:7], v[10:11], v[6:7]
	v_fma_f64 v[24:25], v[24:25], v[42:43], v[24:25]
	v_fma_f64 v[42:43], -v[32:33], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[44:45], v[40:41], v[14:15]
	v_mul_f64 v[46:47], v[38:39], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[34:35], v[42:43], v[34:35]
	v_fma_f64 v[8:9], -v[8:9], v[44:45], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], -v[12:13], v[46:47], v[38:39]
	v_mul_f64 v[38:39], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[44:45]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[12:13], v[12:13], v[24:25], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], -v[32:33], v[38:39], v[48:49]
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f64 v[2:3], v[8:9], v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[6:7], v[12:13], v[10:11], v[6:7]
	v_mul_f64 v[12:13], v[30:31], v[30:31]
	v_div_fmas_f64 v[14:15], v[14:15], v[34:35], v[38:39]
	v_add_f64 v[34:35], s[4:5], -1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[24:25], v[6:7], v[6:7]
	v_fma_f64 v[12:13], v[28:29], v[28:29], v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[8:9], v[14:15], v[10:11], v[4:5]
	v_fma_f64 v[4:5], v[2:3], v[2:3], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[36:37], v[36:37], v[12:13]
	v_fma_f64 v[4:5], v[8:9], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[26:27], v[12:13]
	v_mul_f64 v[4:5], v[10:11], v[4:5]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], -0.5, v[22:23]
	v_fma_f64 v[4:5], v[4:5], -0.5, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[40:41], v[34:35], v[12:13]
	v_mul_f64 v[4:5], v[34:35], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[40:41], s[4:5]
	v_mul_f64 v[14:15], v[4:5], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[24:25], null, v[26:27], v[26:27], v[12:13]
	v_div_scale_f64 v[48:49], vcc_lo, v[12:13], v[26:27], v[12:13]
	v_div_scale_f64 v[32:33], null, v[10:11], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[38:39], v[24:25]
	v_rcp_f64_e32 v[42:43], v[32:33]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[24:25], v[38:39], 1.0
	v_fma_f64 v[46:47], -v[32:33], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[38:39], v[44:45], v[38:39]
	v_fma_f64 v[42:43], v[42:43], v[46:47], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[44:45], -v[24:25], v[38:39], 1.0
	v_fma_f64 v[46:47], -v[32:33], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[38:39], v[44:45], v[38:39]
	v_div_scale_f64 v[44:45], s2, v[14:15], v[10:11], v[14:15]
	v_fma_f64 v[42:43], v[42:43], v[46:47], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[46:47], v[48:49], v[38:39]
	v_mul_f64 v[50:51], v[44:45], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[24:25], v[46:47], v[48:49]
	v_fma_f64 v[32:33], -v[32:33], v[50:51], v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[24:25], v[24:25], v[38:39], v[46:47]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[32:33], v[32:33], v[42:43], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[24:25], v[26:27], v[12:13]
	v_div_fixup_f64 v[14:15], v[32:33], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[12:13]
	v_cmp_gt_f64_e64 s2, 0x10000000, v[14:15]
	v_cndmask_b32_e64 v24, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v24, 8, v24
	v_ldexp_f64 v[12:13], v[12:13], v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v25, 0, 1, s2
	v_lshlrev_b32_e32 v25, 8, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[14:15], v[14:15], v25
	v_rsq_f64_e32 v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_rsq_f64_e32 v[32:33], v[14:15]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[38:39], v[12:13], v[24:25]
	v_mul_f64 v[24:25], v[24:25], 0.5
	v_mul_f64 v[42:43], v[14:15], v[32:33]
	v_mul_f64 v[32:33], v[32:33], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[44:45], -v[24:25], v[38:39], 0.5
	v_fma_f64 v[46:47], -v[32:33], v[42:43], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[38:39], v[44:45], v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[44:45], v[24:25]
	v_fma_f64 v[42:43], v[42:43], v[46:47], v[42:43]
	v_fma_f64 v[32:33], v[32:33], v[46:47], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], -v[38:39], v[38:39], v[12:13]
	v_fma_f64 v[46:47], -v[42:43], v[42:43], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[44:45], v[24:25], v[38:39]
	v_fma_f64 v[42:43], v[46:47], v[32:33], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[44:45], -v[38:39], v[38:39], v[12:13]
	v_fma_f64 v[46:47], -v[42:43], v[42:43], v[14:15]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[24:25], v[44:45], v[24:25], v[38:39]
	v_cndmask_b32_e64 v38, 0, 0xffffff80, vcc_lo
	v_cndmask_b32_e64 v39, 0, 0xffffff80, s2
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x260
	v_cmp_class_f64_e64 s2, v[14:15], 0x260
	v_fma_f64 v[32:33], v[46:47], v[32:33], v[42:43]
	v_ldexp_f64 v[24:25], v[24:25], v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[32:33], v[32:33], v39
	v_dual_cndmask_b32 v24, v24, v12 :: v_dual_cndmask_b32 v25, v25, v13
	s_and_b32 vcc_lo, exec_lo, s29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v33, v33, v15, s2
	v_cndmask_b32_e64 v32, v32, v14, s2
	s_cbranch_vccz .LBB2_33
; %bb.30:
	s_and_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccz .LBB2_34
; %bb.31:
	s_and_not1_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccnz .LBB2_35
; %bb.32:
	v_add_f64 v[12:13], v[36:37], -v[24:25]
	v_add_f64 v[14:15], v[8:9], -v[32:33]
	v_add_f64 v[38:39], v[36:37], v[24:25]
	v_add_f64 v[42:43], v[8:9], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[12:13], v[12:13], v[14:15]
	v_max_f64 v[14:15], v[38:39], v[42:43]
	s_branch .LBB2_36
.LBB2_33:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
	s_branch .LBB2_40
.LBB2_34:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
	s_branch .LBB2_37
.LBB2_35:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
.LBB2_36:                               ; %Flow662
	s_mov_b32 s0, 0
.LBB2_37:                               ; %Flow663
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_39
; %bb.38:
	v_add_f64 v[12:13], v[30:31], -v[24:25]
	v_add_f64 v[14:15], v[6:7], -v[32:33]
	v_add_f64 v[38:39], v[30:31], v[24:25]
	v_add_f64 v[42:43], v[6:7], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[12:13], v[12:13], v[14:15]
	v_max_f64 v[14:15], v[38:39], v[42:43]
.LBB2_39:                               ; %Flow664
	s_mov_b32 s0, 0
.LBB2_40:                               ; %Flow665
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_42
; %bb.41:
	v_add_f64 v[12:13], |v[2:3]|, v[32:33]
	v_add_f64 v[14:15], |v[6:7]|, v[32:33]
	v_add_f64 v[44:45], |v[8:9]|, v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[38:39], null, v[12:13], v[12:13], s[6:7]
	v_div_scale_f64 v[42:43], null, v[14:15], v[14:15], s[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[50:51], null, v[44:45], v[44:45], s[10:11]
	v_div_scale_f64 v[65:66], s1, s[10:11], v[44:45], s[10:11]
	v_rcp_f64_e32 v[46:47], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[48:49], v[42:43]
	v_rcp_f64_e32 v[57:58], v[50:51]
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[52:53], -v[38:39], v[46:47], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[55:56], -v[42:43], v[48:49], 1.0
	v_fma_f64 v[46:47], v[46:47], v[52:53], v[46:47]
	v_fma_f64 v[52:53], -v[50:51], v[57:58], 1.0
	v_fma_f64 v[48:49], v[48:49], v[55:56], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[55:56], -v[38:39], v[46:47], 1.0
	v_fma_f64 v[52:53], v[57:58], v[52:53], v[57:58]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[59:60], -v[42:43], v[48:49], 1.0
	v_div_scale_f64 v[57:58], vcc_lo, s[6:7], v[12:13], s[6:7]
	v_fma_f64 v[46:47], v[46:47], v[55:56], v[46:47]
	v_div_scale_f64 v[55:56], s0, s[8:9], v[14:15], s[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[48:49], v[48:49], v[59:60], v[48:49]
	v_fma_f64 v[59:60], -v[50:51], v[52:53], 1.0
	v_mul_f64 v[61:62], v[57:58], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[63:64], v[55:56], v[48:49]
	v_fma_f64 v[52:53], v[52:53], v[59:60], v[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], -v[38:39], v[61:62], v[57:58]
	v_fma_f64 v[42:43], -v[42:43], v[63:64], v[55:56]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[55:56], v[65:66], v[52:53]
	v_div_fmas_f64 v[38:39], v[38:39], v[46:47], v[61:62]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[42:43], v[42:43], v[48:49], v[63:64]
	v_fma_f64 v[46:47], -v[50:51], v[55:56], v[65:66]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[12:13], v[38:39], v[12:13], s[6:7]
	v_div_fixup_f64 v[14:15], v[42:43], v[14:15], s[8:9]
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f64 v[38:39], v[46:47], v[52:53], v[55:56]
	v_add_f64 v[42:43], v[28:29], -v[24:25]
	v_add_f64 v[46:47], v[2:3], -v[32:33]
	v_add_f64 v[24:25], v[28:29], v[24:25]
	v_min_f64 v[14:15], v[12:13], v[14:15]
	v_div_fixup_f64 v[38:39], v[38:39], v[44:45], s[10:11]
	v_add_f64 v[44:45], v[2:3], v[32:33]
	v_min_f64 v[12:13], v[42:43], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_f64 v[38:39], v[14:15], v[38:39]
	v_max_f64 v[14:15], v[24:25], v[44:45]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v24, vcc_lo, s14, v19
	v_add_co_ci_u32_e32 v25, vcc_lo, s15, v20, vcc_lo
	global_store_b64 v[24:25], v[38:39], off
.LBB2_42:
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccz .LBB2_46
; %bb.43:                               ; %NodeBlock
	s_cmp_lt_i32 s28, 3
	s_cbranch_scc1 .LBB2_47
; %bb.44:                               ; %LeafBlock525
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_48
; %bb.45:
	v_mul_f64 v[48:49], v[26:27], v[36:37]
	v_mul_f64 v[44:45], v[10:11], v[8:9]
	s_branch .LBB2_49
.LBB2_46:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr48_vgpr49
	s_branch .LBB2_55
.LBB2_47:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr48_vgpr49
	s_branch .LBB2_50
.LBB2_48:
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr48_vgpr49
.LBB2_49:                               ; %Flow657
	s_mov_b32 s0, 0
.LBB2_50:                               ; %Flow659
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_54
; %bb.51:                               ; %LeafBlock
	s_cmp_lg_u32 s28, 2
	s_cbranch_scc1 .LBB2_53
; %bb.52:
	v_mul_f64 v[48:49], v[26:27], v[30:31]
	v_mul_f64 v[44:45], v[10:11], v[6:7]
	s_branch .LBB2_54
.LBB2_53:
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr48_vgpr49
.LBB2_54:                               ; %Flow660
	s_mov_b32 s0, 0
.LBB2_55:                               ; %Flow661
	v_mul_f64 v[42:43], v[26:27], v[28:29]
	v_mul_f64 v[24:25], v[10:11], v[2:3]
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_57
; %bb.56:
	v_mul_f64 v[44:45], v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v49, v43 :: v_dual_mov_b32 v48, v42
.LBB2_57:
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_nlt_f64_e64 s0, 0, v[12:13]
	v_dual_mov_b32 v38, v48 :: v_dual_mov_b32 v39, v49
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_61
; %bb.58:
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v38, v44 :: v_dual_mov_b32 v39, v45
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_60
; %bb.59:
	v_mul_f64 v[38:39], v[12:13], v[44:45]
	v_mul_f64 v[46:47], v[12:13], v[14:15]
	v_add_f64 v[50:51], v[10:11], -v[26:27]
	v_add_f64 v[52:53], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[14:15], v[48:49], -v[38:39]
	v_fma_f64 v[38:39], v[50:51], v[46:47], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[46:47], null, v[52:53], v[52:53], v[38:39]
	v_rcp_f64_e32 v[50:51], v[46:47]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[55:56], -v[46:47], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[55:56], v[50:51]
	v_fma_f64 v[55:56], -v[46:47], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[55:56], v[50:51]
	v_div_scale_f64 v[55:56], vcc_lo, v[38:39], v[52:53], v[38:39]
	v_mul_f64 v[57:58], v[55:56], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[46:47], -v[46:47], v[57:58], v[55:56]
	v_div_fmas_f64 v[46:47], v[46:47], v[50:51], v[57:58]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[38:39], v[46:47], v[52:53], v[38:39]
.LBB2_60:                               ; %Flow656
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_61:                               ; %hll_interFlux.exit.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v46, vcc_lo, s38, v19
	v_add_co_ci_u32_e32 v47, vcc_lo, s39, v20, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[46:47], v[38:39], off
	s_cbranch_vccz .LBB2_65
; %bb.62:                               ; %NodeBlock531
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_66
; %bb.63:                               ; %LeafBlock529
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_67
; %bb.64:
	v_mul_f64 v[50:51], v[10:11], v[2:3]
	v_mul_f64 v[46:47], v[42:43], v[36:37]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[38:39], v[50:51], v[8:9]
	s_branch .LBB2_68
.LBB2_65:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr38_vgpr39
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr50_vgpr51
	s_branch .LBB2_76
.LBB2_66:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr38_vgpr39
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr50_vgpr51
	s_branch .LBB2_69
.LBB2_67:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr38_vgpr39
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr50_vgpr51
.LBB2_68:                               ; %Flow650
	s_mov_b32 s3, 0
.LBB2_69:                               ; %Flow649
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_71
; %bb.70:                               ; %LeafBlock527
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr38_vgpr39
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr50_vgpr51
.LBB2_71:                               ; %Flow651
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_73
; %bb.72:                               ; %._crit_edge167.i
	v_mul_f64 v[50:51], v[10:11], v[2:3]
	v_dual_mov_b32 v38, v44 :: v_dual_mov_b32 v39, v45
	v_dual_mov_b32 v46, v48 :: v_dual_mov_b32 v47, v49
	s_mov_b32 s1, 0
.LBB2_73:                               ; %Flow652
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_75
; %bb.74:
	v_mul_f64 v[50:51], v[10:11], v[2:3]
	v_mul_f64 v[46:47], v[42:43], v[30:31]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[38:39], v[50:51], v[6:7]
.LBB2_75:                               ; %Flow653
	s_mov_b32 s1, 0
.LBB2_76:                               ; %Flow654
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_78
; %bb.77:
	v_mul_f64 v[50:51], v[10:11], v[2:3]
	v_fma_f64 v[46:47], v[28:29], v[42:43], v[40:41]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[2:3], v[50:51], v[4:5]
.LBB2_78:
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v45, v47
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_82
; %bb.79:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v45, v39 :: v_dual_mov_b32 v44, v38
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_81
; %bb.80:
	v_mul_f64 v[44:45], v[12:13], v[38:39]
	v_mul_f64 v[48:49], v[12:13], v[14:15]
	v_add_f64 v[42:43], v[50:51], -v[42:43]
	v_add_f64 v[50:51], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[14:15], v[46:47], -v[44:45]
	v_fma_f64 v[42:43], v[48:49], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[44:45], null, v[50:51], v[50:51], v[42:43]
	v_rcp_f64_e32 v[48:49], v[44:45]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[52:53], -v[44:45], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	v_fma_f64 v[52:53], -v[44:45], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	v_div_scale_f64 v[52:53], vcc_lo, v[42:43], v[50:51], v[42:43]
	v_mul_f64 v[55:56], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[44:45], v[55:56], v[52:53]
	v_div_fmas_f64 v[44:45], v[44:45], v[48:49], v[55:56]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[44:45], v[44:45], v[50:51], v[42:43]
.LBB2_81:                               ; %Flow648
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_82:                               ; %hll_interFlux.exit159.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mul_f64 v[48:49], v[26:27], v[30:31]
	v_add_co_u32 v42, vcc_lo, s40, v19
	v_add_co_ci_u32_e32 v43, vcc_lo, s41, v20, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[42:43], v[44:45], off
	s_cbranch_vccz .LBB2_86
; %bb.83:                               ; %NodeBlock537
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_87
; %bb.84:                               ; %LeafBlock535
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_88
; %bb.85:
	v_mul_f64 v[50:51], v[10:11], v[6:7]
	v_mul_f64 v[44:45], v[48:49], v[36:37]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[42:43], v[50:51], v[8:9]
	s_branch .LBB2_89
.LBB2_86:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr42_vgpr43
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr50_vgpr51
	s_branch .LBB2_97
.LBB2_87:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr42_vgpr43
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr50_vgpr51
	s_branch .LBB2_90
.LBB2_88:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr42_vgpr43
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr50_vgpr51
.LBB2_89:                               ; %Flow642
	s_mov_b32 s3, 0
.LBB2_90:                               ; %Flow641
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_92
; %bb.91:                               ; %LeafBlock533
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr42_vgpr43
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr50_vgpr51
.LBB2_92:                               ; %Flow643
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_94
; %bb.93:                               ; %._crit_edge166.i
	v_mul_f64 v[50:51], v[10:11], v[6:7]
	v_dual_mov_b32 v43, v39 :: v_dual_mov_b32 v42, v38
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v45, v47
	s_mov_b32 s1, 0
.LBB2_94:                               ; %Flow644
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_96
; %bb.95:
	v_mul_f64 v[50:51], v[10:11], v[6:7]
	v_fma_f64 v[44:45], v[30:31], v[48:49], v[40:41]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[42:43], v[6:7], v[50:51], v[4:5]
.LBB2_96:                               ; %Flow645
	s_mov_b32 s1, 0
.LBB2_97:                               ; %Flow646
	v_mul_f64 v[38:39], v[10:11], v[6:7]
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_99
; %bb.98:
	v_mul_f64 v[50:51], v[10:11], v[6:7]
	v_mul_f64 v[44:45], v[28:29], v[48:49]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[42:43], v[2:3], v[50:51]
.LBB2_99:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v47, v45 :: v_dual_mov_b32 v46, v44
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_103
; %bb.100:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v47, v43 :: v_dual_mov_b32 v46, v42
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_102
; %bb.101:
	v_mul_f64 v[46:47], v[12:13], v[42:43]
	v_mul_f64 v[52:53], v[12:13], v[14:15]
	v_add_f64 v[48:49], v[50:51], -v[48:49]
	v_add_f64 v[50:51], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[46:47], v[14:15], v[44:45], -v[46:47]
	v_fma_f64 v[46:47], v[52:53], v[48:49], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[48:49], null, v[50:51], v[50:51], v[46:47]
	v_rcp_f64_e32 v[52:53], v[48:49]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[55:56], -v[48:49], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[52:53], v[55:56], v[52:53]
	v_fma_f64 v[55:56], -v[48:49], v[52:53], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[52:53], v[55:56], v[52:53]
	v_div_scale_f64 v[55:56], vcc_lo, v[46:47], v[50:51], v[46:47]
	v_mul_f64 v[57:58], v[55:56], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], -v[48:49], v[57:58], v[55:56]
	v_div_fmas_f64 v[48:49], v[48:49], v[52:53], v[57:58]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[46:47], v[48:49], v[50:51], v[46:47]
.LBB2_102:                              ; %Flow640
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_103:                              ; %hll_interFlux.exit161.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mul_f64 v[50:51], v[26:27], v[36:37]
	v_add_co_u32 v26, vcc_lo, s42, v19
	v_add_co_ci_u32_e32 v27, vcc_lo, s43, v20, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[26:27], v[46:47], off
	s_cbranch_vccz .LBB2_107
; %bb.104:                              ; %NodeBlock543
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_108
; %bb.105:                              ; %LeafBlock541
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_109
; %bb.106:
	v_mul_f64 v[52:53], v[10:11], v[8:9]
	v_fma_f64 v[48:49], v[36:37], v[50:51], v[40:41]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[46:47], v[8:9], v[52:53], v[4:5]
	s_branch .LBB2_110
.LBB2_107:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr48_vgpr49
                                        ; implicit-def: $vgpr52_vgpr53
	s_branch .LBB2_118
.LBB2_108:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr48_vgpr49
                                        ; implicit-def: $vgpr52_vgpr53
	s_branch .LBB2_111
.LBB2_109:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr48_vgpr49
                                        ; implicit-def: $vgpr52_vgpr53
.LBB2_110:                              ; %Flow634
	s_mov_b32 s3, 0
.LBB2_111:                              ; %Flow633
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_113
; %bb.112:                              ; %LeafBlock539
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr46_vgpr47
                                        ; implicit-def: $vgpr48_vgpr49
                                        ; implicit-def: $vgpr52_vgpr53
.LBB2_113:                              ; %Flow635
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_115
; %bb.114:                              ; %._crit_edge.i
	v_mul_f64 v[52:53], v[10:11], v[8:9]
	v_dual_mov_b32 v47, v43 :: v_dual_mov_b32 v46, v42
	v_dual_mov_b32 v49, v45 :: v_dual_mov_b32 v48, v44
	s_mov_b32 s1, 0
.LBB2_115:                              ; %Flow636
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_117
; %bb.116:
	v_mul_f64 v[52:53], v[10:11], v[8:9]
	v_mul_f64 v[48:49], v[30:31], v[50:51]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[46:47], v[6:7], v[52:53]
.LBB2_117:                              ; %Flow637
	s_mov_b32 s1, 0
.LBB2_118:                              ; %Flow638
	v_mul_f64 v[26:27], v[10:11], v[8:9]
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_120
; %bb.119:
	v_mul_f64 v[52:53], v[10:11], v[8:9]
	v_mul_f64 v[48:49], v[28:29], v[50:51]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[46:47], v[2:3], v[52:53]
.LBB2_120:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v42, v48 :: v_dual_mov_b32 v43, v49
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_124
; %bb.121:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v42, v46 :: v_dual_mov_b32 v43, v47
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_123
; %bb.122:
	v_mul_f64 v[42:43], v[12:13], v[46:47]
	v_mul_f64 v[44:45], v[12:13], v[14:15]
	v_add_f64 v[50:51], v[52:53], -v[50:51]
	v_add_f64 v[52:53], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[14:15], v[48:49], -v[42:43]
	v_fma_f64 v[42:43], v[44:45], v[50:51], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[44:45], null, v[52:53], v[52:53], v[42:43]
	v_rcp_f64_e32 v[50:51], v[44:45]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[55:56], -v[44:45], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[55:56], v[50:51]
	v_fma_f64 v[55:56], -v[44:45], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[55:56], v[50:51]
	v_div_scale_f64 v[55:56], vcc_lo, v[42:43], v[52:53], v[42:43]
	v_mul_f64 v[57:58], v[55:56], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[44:45], v[57:58], v[55:56]
	v_div_fmas_f64 v[44:45], v[44:45], v[50:51], v[57:58]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[42:43], v[44:45], v[52:53], v[42:43]
.LBB2_123:                              ; %Flow632
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_124:                              ; %hll_interFlux.exit163.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v44, vcc_lo, s44, v19
	v_add_co_ci_u32_e32 v45, vcc_lo, s45, v20, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[44:45], v[42:43], off
	s_cbranch_vccz .LBB2_129
; %bb.125:                              ; %NodeBlock549
	s_cmp_lt_i32 s28, 3
	s_cbranch_scc1 .LBB2_130
; %bb.126:                              ; %LeafBlock547
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v45, v47
	v_dual_mov_b32 v42, v48 :: v_dual_mov_b32 v43, v49
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_128
; %bb.127:
	v_add_f64 v[42:43], v[22:23], v[40:41]
	v_add_f64 v[44:45], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[42:43], v[36:37], v[42:43]
	v_mul_f64 v[44:45], v[8:9], v[44:45]
.LBB2_128:                              ; %Flow626
	s_mov_b32 s1, 0
	s_branch .LBB2_131
.LBB2_129:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr42_vgpr43
	s_branch .LBB2_136
.LBB2_130:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr42_vgpr43
.LBB2_131:                              ; %Flow628
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_135
; %bb.132:                              ; %LeafBlock545
	s_cmp_lg_u32 s28, 2
	s_cbranch_scc1 .LBB2_134
; %bb.133:
	v_add_f64 v[36:37], v[22:23], v[40:41]
	v_add_f64 v[42:43], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[48:49], v[30:31], v[36:37]
	v_mul_f64 v[46:47], v[6:7], v[42:43]
.LBB2_134:                              ; %Flow627
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v45, v47
	v_dual_mov_b32 v42, v48 :: v_dual_mov_b32 v43, v49
.LBB2_135:                              ; %Flow629
	s_mov_b32 s1, 0
.LBB2_136:                              ; %Flow630
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_138
; %bb.137:
	v_add_f64 v[30:31], v[22:23], v[40:41]
	v_add_f64 v[36:37], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[42:43], v[28:29], v[30:31]
	v_mul_f64 v[44:45], v[2:3], v[36:37]
.LBB2_138:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_142
; %bb.139:
	s_mov_b32 s0, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_141
; %bb.140:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[28:29], v[12:13], v[44:45]
	v_mul_f64 v[30:31], v[12:13], v[14:15]
	v_add_f64 v[22:23], v[0:1], -v[22:23]
	v_add_f64 v[36:37], v[14:15], -v[12:13]
	v_fma_f64 v[28:29], v[14:15], v[42:43], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[30:31], v[28:29]
	v_div_scale_f64 v[28:29], null, v[36:37], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[30:31], v[28:29]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[28:29], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[40:41], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], -v[28:29], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[40:41], v[30:31]
	v_div_scale_f64 v[40:41], vcc_lo, v[22:23], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[42:43], v[40:41], v[30:31]
	v_fma_f64 v[28:29], -v[28:29], v[42:43], v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[42:43]
	v_div_fixup_f64 v[44:45], v[28:29], v[36:37], v[22:23]
.LBB2_141:                              ; %Flow624
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v42, v44 :: v_dual_mov_b32 v43, v45
.LBB2_142:                              ; %writeInterFlux.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_ne_u32_e32 vcc_lo, 0x7f, v18
	v_cmp_ne_u32_e64 s0, 0x7f, v16
	v_cmp_ne_u32_e64 s1, 0x7f, v17
	s_and_b32 s2, s31, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s33, s0
	v_add_co_u32 v16, vcc_lo, s46, v19
	s_or_b32 s0, s2, s0
	s_and_b32 s1, s34, s1
	v_add_co_ci_u32_e32 v17, vcc_lo, s47, v20, vcc_lo
	s_or_b32 s0, s0, s1
	s_mov_b32 s2, -1
	s_xor_b32 s0, s0, -1
	global_store_b64 v[16:17], v[42:43], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_257
; %bb.143:
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[21:22]
	v_add_co_u32 v18, vcc_lo, s18, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s19, v17, vcc_lo
	v_add_co_u32 v20, vcc_lo, s20, v16
	v_add_co_ci_u32_e32 v21, vcc_lo, s21, v17, vcc_lo
	v_add_co_u32 v22, vcc_lo, s22, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, s23, v17, vcc_lo
	global_load_b64 v[36:37], v[18:19], off
	global_load_b64 v[20:21], v[20:21], off
	global_load_b64 v[22:23], v[22:23], off
	v_add_co_u32 v18, vcc_lo, s24, v16
	v_add_co_ci_u32_e32 v19, vcc_lo, s25, v17, vcc_lo
	global_load_b64 v[30:31], v[18:19], off
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[28:29], null, v[36:37], v[36:37], v[20:21]
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[40:41], null, v[36:37], v[36:37], v[22:23]
	v_div_scale_f64 v[55:56], s0, v[22:23], v[36:37], v[22:23]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[44:45], null, v[36:37], v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[18:19], v[28:29]
	v_rcp_f64_e32 v[42:43], v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[50:51], v[44:45]
	v_fma_f64 v[46:47], -v[28:29], v[18:19], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[48:49], -v[40:41], v[42:43], 1.0
	v_fma_f64 v[18:19], v[18:19], v[46:47], v[18:19]
	v_fma_f64 v[46:47], -v[44:45], v[50:51], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[42:43], v[48:49], v[42:43]
	v_fma_f64 v[48:49], -v[28:29], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[50:51], v[46:47], v[50:51]
	v_fma_f64 v[52:53], -v[40:41], v[42:43], 1.0
	v_div_scale_f64 v[50:51], vcc_lo, v[20:21], v[36:37], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[48:49], v[18:19], v[48:49], v[18:19]
	v_add_co_u32 v18, s1, s26, v16
	v_fma_f64 v[42:43], v[42:43], v[52:53], v[42:43]
	v_add_co_ci_u32_e64 v19, s1, s27, v17, s1
	v_fma_f64 v[52:53], -v[44:45], v[46:47], 1.0
	v_div_scale_f64 v[61:62], s1, v[30:31], v[36:37], v[30:31]
	global_load_b64 v[18:19], v[18:19], off
	v_mul_f64 v[57:58], v[50:51], v[48:49]
	v_mul_f64 v[59:60], v[55:56], v[42:43]
	v_fma_f64 v[46:47], v[46:47], v[52:53], v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], -v[28:29], v[57:58], v[50:51]
	v_fma_f64 v[40:41], -v[40:41], v[59:60], v[55:56]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[50:51], v[61:62], v[46:47]
	v_div_fmas_f64 v[48:49], v[28:29], v[48:49], v[57:58]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[28:29], v[40:41], v[42:43], v[59:60]
	s_mov_b32 vcc_lo, s1
	v_fma_f64 v[40:41], -v[44:45], v[50:51], v[61:62]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[20:21], v[48:49], v[36:37], v[20:21]
	v_div_fixup_f64 v[28:29], v[28:29], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[22:23], v[40:41], v[46:47], v[50:51]
	v_mul_f64 v[40:41], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[30:31], v[22:23], v[36:37], v[30:31]
	v_fma_f64 v[22:23], v[20:21], v[20:21], v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[30:31], v[30:31], v[22:23]
	v_mul_f64 v[22:23], v[36:37], v[22:23]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], -0.5, v[18:19]
	v_mul_f64 v[22:23], v[34:35], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[34:35], v[22:23], s[4:5]
	v_div_scale_f64 v[40:41], null, v[36:37], v[36:37], v[34:35]
	v_div_scale_f64 v[46:47], vcc_lo, v[34:35], v[36:37], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[42:43], v[40:41]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[40:41], v[42:43], 1.0
	v_fma_f64 v[42:43], v[42:43], v[44:45], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[40:41], v[42:43], 1.0
	v_fma_f64 v[42:43], v[42:43], v[44:45], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[44:45], v[46:47], v[42:43]
	v_fma_f64 v[40:41], -v[40:41], v[44:45], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[40:41], v[40:41], v[42:43], v[44:45]
	v_div_fixup_f64 v[34:35], v[40:41], v[36:37], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[34:35]
	v_cndmask_b32_e64 v40, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v40, 8, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[34:35], v[34:35], v40
	v_rsq_f64_e32 v[40:41], v[34:35]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[42:43], v[34:35], v[40:41]
	v_mul_f64 v[40:41], v[40:41], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[40:41], v[42:43], 0.5
	v_fma_f64 v[42:43], v[42:43], v[44:45], v[42:43]
	v_fma_f64 v[40:41], v[40:41], v[44:45], v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[42:43], v[42:43], v[34:35]
	v_fma_f64 v[42:43], v[44:45], v[40:41], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], -v[42:43], v[42:43], v[34:35]
	v_fma_f64 v[40:41], v[44:45], v[40:41], v[42:43]
	v_cndmask_b32_e64 v42, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[34:35], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[40:41], v[40:41], v42
	v_dual_cndmask_b32 v35, v41, v35 :: v_dual_cndmask_b32 v34, v40, v34
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccz .LBB2_148
; %bb.144:
	s_and_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccz .LBB2_149
; %bb.145:
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	s_cbranch_vccnz .LBB2_147
; %bb.146:
	v_add_f64 v[12:13], v[8:9], -v[32:33]
	v_add_f64 v[14:15], v[30:31], -v[34:35]
	v_add_f64 v[40:41], v[8:9], v[32:33]
	v_add_f64 v[42:43], v[30:31], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[12:13], v[12:13], v[14:15]
	v_max_f64 v[14:15], v[40:41], v[42:43]
.LBB2_147:                              ; %Flow618
	s_mov_b32 s0, 0
	s_branch .LBB2_150
.LBB2_148:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
	s_branch .LBB2_153
.LBB2_149:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
.LBB2_150:                              ; %Flow619
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_152
; %bb.151:
	v_add_f64 v[12:13], v[6:7], -v[32:33]
	v_add_f64 v[14:15], v[28:29], -v[34:35]
	v_add_f64 v[40:41], v[6:7], v[32:33]
	v_add_f64 v[42:43], v[28:29], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[12:13], v[12:13], v[14:15]
	v_max_f64 v[14:15], v[40:41], v[42:43]
.LBB2_152:                              ; %Flow620
	s_mov_b32 s2, 0
.LBB2_153:                              ; %Flow621
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_155
; %bb.154:
	v_add_f64 v[12:13], v[2:3], -v[32:33]
	v_add_f64 v[14:15], v[20:21], -v[34:35]
	v_add_f64 v[32:33], v[2:3], v[32:33]
	v_add_f64 v[34:35], v[20:21], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[12:13], v[12:13], v[14:15]
	v_max_f64 v[14:15], v[32:33], v[34:35]
.LBB2_155:
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccz .LBB2_159
; %bb.156:                              ; %NodeBlock555
	s_cmp_lt_i32 s28, 3
	s_cbranch_scc1 .LBB2_160
; %bb.157:                              ; %LeafBlock553
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_161
; %bb.158:
	v_mul_f64 v[40:41], v[36:37], v[30:31]
	s_branch .LBB2_162
.LBB2_159:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr40_vgpr41
                                        ; implicit-def: $vgpr42_vgpr43
	s_branch .LBB2_169
.LBB2_160:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr40_vgpr41
                                        ; implicit-def: $vgpr42_vgpr43
	s_branch .LBB2_163
.LBB2_161:
                                        ; implicit-def: $vgpr40_vgpr41
.LBB2_162:                              ; %Flow613
	v_dual_mov_b32 v43, v27 :: v_dual_mov_b32 v42, v26
	s_mov_b32 s0, 0
.LBB2_163:                              ; %Flow615
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_168
; %bb.164:                              ; %LeafBlock551
	s_cmp_lg_u32 s28, 2
	s_cbranch_scc1 .LBB2_166
; %bb.165:
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	s_branch .LBB2_167
.LBB2_166:
                                        ; implicit-def: $vgpr40_vgpr41
.LBB2_167:                              ; %Flow614
	v_dual_mov_b32 v43, v39 :: v_dual_mov_b32 v42, v38
.LBB2_168:                              ; %Flow616
	s_mov_b32 s0, 0
.LBB2_169:                              ; %Flow617
	v_mul_f64 v[34:35], v[36:37], v[20:21]
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_171
; %bb.170:
	v_mul_f64 v[40:41], v[36:37], v[20:21]
	v_dual_mov_b32 v43, v25 :: v_dual_mov_b32 v42, v24
.LBB2_171:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_nlt_f64_e64 s0, 0, v[12:13]
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_175
; %bb.172:
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v32, v40 :: v_dual_mov_b32 v33, v41
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_174
; %bb.173:
	v_mul_f64 v[32:33], v[12:13], v[40:41]
	v_mul_f64 v[44:45], v[12:13], v[14:15]
	v_add_f64 v[10:11], v[36:37], -v[10:11]
	v_add_f64 v[46:47], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[14:15], v[42:43], -v[32:33]
	v_fma_f64 v[10:11], v[10:11], v[44:45], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[32:33], null, v[46:47], v[46:47], v[10:11]
	v_rcp_f64_e32 v[44:45], v[32:33]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[48:49], -v[32:33], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[44:45], v[48:49], v[44:45]
	v_fma_f64 v[48:49], -v[32:33], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[44:45], v[44:45], v[48:49], v[44:45]
	v_div_scale_f64 v[48:49], vcc_lo, v[10:11], v[46:47], v[10:11]
	v_mul_f64 v[50:51], v[48:49], v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], -v[32:33], v[50:51], v[48:49]
	v_div_fmas_f64 v[32:33], v[32:33], v[44:45], v[50:51]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[32:33], v[32:33], v[46:47], v[10:11]
.LBB2_174:                              ; %Flow612
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_175:                              ; %hll_interFlux.exit.i404
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v10, vcc_lo, s48, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s49, v17, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[10:11], v[32:33], off
	s_cbranch_vccz .LBB2_179
; %bb.176:                              ; %NodeBlock561
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_180
; %bb.177:                              ; %LeafBlock559
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_181
; %bb.178:
	v_mul_f64 v[44:45], v[36:37], v[20:21]
	v_mul_f64 v[32:33], v[24:25], v[8:9]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[10:11], v[44:45], v[30:31]
	s_branch .LBB2_182
.LBB2_179:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr44_vgpr45
	s_branch .LBB2_190
.LBB2_180:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr44_vgpr45
	s_branch .LBB2_183
.LBB2_181:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr44_vgpr45
.LBB2_182:                              ; %Flow606
	s_mov_b32 s3, 0
.LBB2_183:                              ; %Flow605
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_185
; %bb.184:                              ; %LeafBlock557
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr44_vgpr45
.LBB2_185:                              ; %Flow607
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_187
; %bb.186:                              ; %._crit_edge167.i428
	v_mul_f64 v[44:45], v[36:37], v[20:21]
	v_dual_mov_b32 v10, v40 :: v_dual_mov_b32 v11, v41
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	s_mov_b32 s1, 0
.LBB2_187:                              ; %Flow608
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_189
; %bb.188:
	v_mul_f64 v[44:45], v[36:37], v[20:21]
	v_mul_f64 v[32:33], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[10:11], v[44:45], v[28:29]
.LBB2_189:                              ; %Flow609
	s_mov_b32 s1, 0
.LBB2_190:                              ; %Flow610
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_192
; %bb.191:
	v_fma_f64 v[32:33], v[2:3], v[24:25], v[4:5]
	v_fma_f64 v[10:11], v[20:21], v[34:35], v[22:23]
	v_dual_mov_b32 v45, v35 :: v_dual_mov_b32 v44, v34
.LBB2_192:
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v35, v33 :: v_dual_mov_b32 v34, v32
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_196
; %bb.193:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v34, v10
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_195
; %bb.194:
	v_mul_f64 v[34:35], v[12:13], v[10:11]
	v_mul_f64 v[40:41], v[12:13], v[14:15]
	v_add_f64 v[24:25], v[44:45], -v[24:25]
	v_add_f64 v[42:43], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], v[14:15], v[32:33], -v[34:35]
	v_fma_f64 v[24:25], v[40:41], v[24:25], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[34:35], null, v[42:43], v[42:43], v[24:25]
	v_rcp_f64_e32 v[40:41], v[34:35]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[34:35], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[40:41], v[44:45], v[40:41]
	v_fma_f64 v[44:45], -v[34:35], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], v[40:41], v[44:45], v[40:41]
	v_div_scale_f64 v[44:45], vcc_lo, v[24:25], v[42:43], v[24:25]
	v_mul_f64 v[46:47], v[44:45], v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], -v[34:35], v[46:47], v[44:45]
	v_div_fmas_f64 v[34:35], v[34:35], v[40:41], v[46:47]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[34:35], v[34:35], v[42:43], v[24:25]
.LBB2_195:                              ; %Flow604
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_196:                              ; %hll_interFlux.exit159.i409
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v24, vcc_lo, s50, v16
	v_add_co_ci_u32_e32 v25, vcc_lo, s51, v17, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[24:25], v[34:35], off
	s_cbranch_vccz .LBB2_200
; %bb.197:                              ; %NodeBlock567
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_201
; %bb.198:                              ; %LeafBlock565
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_202
; %bb.199:
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	v_mul_f64 v[34:35], v[38:39], v[8:9]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[24:25], v[40:41], v[30:31]
	s_branch .LBB2_203
.LBB2_200:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr40_vgpr41
	s_branch .LBB2_211
.LBB2_201:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr40_vgpr41
	s_branch .LBB2_204
.LBB2_202:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr40_vgpr41
.LBB2_203:                              ; %Flow598
	s_mov_b32 s3, 0
.LBB2_204:                              ; %Flow597
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_206
; %bb.205:                              ; %LeafBlock563
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr40_vgpr41
.LBB2_206:                              ; %Flow599
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_208
; %bb.207:                              ; %._crit_edge166.i426
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	v_dual_mov_b32 v25, v11 :: v_dual_mov_b32 v24, v10
	v_dual_mov_b32 v35, v33 :: v_dual_mov_b32 v34, v32
	s_mov_b32 s1, 0
.LBB2_208:                              ; %Flow600
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_210
; %bb.209:
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	v_fma_f64 v[34:35], v[6:7], v[38:39], v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[24:25], v[28:29], v[40:41], v[22:23]
.LBB2_210:                              ; %Flow601
	s_mov_b32 s1, 0
.LBB2_211:                              ; %Flow602
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_213
; %bb.212:
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	v_mul_f64 v[34:35], v[2:3], v[38:39]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[24:25], v[20:21], v[40:41]
.LBB2_213:
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v10, v34 :: v_dual_mov_b32 v11, v35
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_217
; %bb.214:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v10, v24 :: v_dual_mov_b32 v11, v25
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_216
; %bb.215:
	v_mul_f64 v[10:11], v[12:13], v[24:25]
	v_mul_f64 v[32:33], v[12:13], v[14:15]
	v_add_f64 v[38:39], v[40:41], -v[38:39]
	v_add_f64 v[40:41], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[14:15], v[34:35], -v[10:11]
	v_fma_f64 v[10:11], v[32:33], v[38:39], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[32:33], null, v[40:41], v[40:41], v[10:11]
	v_rcp_f64_e32 v[38:39], v[32:33]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[38:39], v[42:43], v[38:39]
	v_fma_f64 v[42:43], -v[32:33], v[38:39], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[38:39], v[42:43], v[38:39]
	v_div_scale_f64 v[42:43], vcc_lo, v[10:11], v[40:41], v[10:11]
	v_mul_f64 v[44:45], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], -v[32:33], v[44:45], v[42:43]
	v_div_fmas_f64 v[32:33], v[32:33], v[38:39], v[44:45]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[10:11], v[32:33], v[40:41], v[10:11]
.LBB2_216:                              ; %Flow596
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_217:                              ; %hll_interFlux.exit161.i414
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v32, vcc_lo, s52, v16
	v_add_co_ci_u32_e32 v33, vcc_lo, s53, v17, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[32:33], v[10:11], off
	s_cbranch_vccz .LBB2_221
; %bb.218:                              ; %NodeBlock573
	s_cmp_lt_i32 s28, 3
	s_mov_b32 s1, 0
	s_cbranch_scc1 .LBB2_222
; %bb.219:                              ; %LeafBlock571
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_223
; %bb.220:
	v_mul_f64 v[38:39], v[36:37], v[30:31]
	v_fma_f64 v[32:33], v[8:9], v[26:27], v[4:5]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[10:11], v[30:31], v[38:39], v[22:23]
	s_branch .LBB2_224
.LBB2_221:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr38_vgpr39
	s_branch .LBB2_232
.LBB2_222:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr38_vgpr39
	s_branch .LBB2_225
.LBB2_223:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr38_vgpr39
.LBB2_224:                              ; %Flow590
	s_mov_b32 s3, 0
.LBB2_225:                              ; %Flow589
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_227
; %bb.226:                              ; %LeafBlock569
	s_cmp_lg_u32 s28, 2
	s_mov_b32 s1, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr38_vgpr39
.LBB2_227:                              ; %Flow591
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_229
; %bb.228:                              ; %._crit_edge.i424
	v_mul_f64 v[38:39], v[36:37], v[30:31]
	v_dual_mov_b32 v10, v24 :: v_dual_mov_b32 v11, v25
	v_dual_mov_b32 v32, v34 :: v_dual_mov_b32 v33, v35
	s_mov_b32 s1, 0
.LBB2_229:                              ; %Flow592
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_231
; %bb.230:
	v_mul_f64 v[38:39], v[36:37], v[30:31]
	v_mul_f64 v[32:33], v[6:7], v[26:27]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[10:11], v[28:29], v[38:39]
.LBB2_231:                              ; %Flow593
	s_mov_b32 s1, 0
.LBB2_232:                              ; %Flow594
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_234
; %bb.233:
	v_mul_f64 v[38:39], v[36:37], v[30:31]
	v_mul_f64 v[32:33], v[2:3], v[26:27]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[10:11], v[20:21], v[38:39]
.LBB2_234:
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v24, v32 :: v_dual_mov_b32 v25, v33
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_238
; %bb.235:
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v25, v11 :: v_dual_mov_b32 v24, v10
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_237
; %bb.236:
	v_mul_f64 v[24:25], v[12:13], v[10:11]
	v_mul_f64 v[34:35], v[12:13], v[14:15]
	v_add_f64 v[26:27], v[38:39], -v[26:27]
	v_add_f64 v[36:37], v[14:15], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[14:15], v[32:33], -v[24:25]
	v_fma_f64 v[24:25], v[34:35], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[26:27], null, v[36:37], v[36:37], v[24:25]
	v_rcp_f64_e32 v[34:35], v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[38:39], -v[26:27], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], v[34:35], v[38:39], v[34:35]
	v_fma_f64 v[38:39], -v[26:27], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], v[34:35], v[38:39], v[34:35]
	v_div_scale_f64 v[38:39], vcc_lo, v[24:25], v[36:37], v[24:25]
	v_mul_f64 v[40:41], v[38:39], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[26:27], v[40:41], v[38:39]
	v_div_fmas_f64 v[26:27], v[26:27], v[34:35], v[40:41]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[24:25], v[26:27], v[36:37], v[24:25]
.LBB2_237:                              ; %Flow588
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_238:                              ; %hll_interFlux.exit163.i419
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v26, vcc_lo, s54, v16
	v_add_co_ci_u32_e32 v27, vcc_lo, s55, v17, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s29
	global_store_b64 v[26:27], v[24:25], off
	s_cbranch_vccz .LBB2_243
; %bb.239:                              ; %NodeBlock579
	s_cmp_lt_i32 s28, 3
	s_cbranch_scc1 .LBB2_244
; %bb.240:                              ; %LeafBlock577
	v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
	v_dual_mov_b32 v24, v32 :: v_dual_mov_b32 v25, v33
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB2_242
; %bb.241:
	v_add_f64 v[24:25], v[0:1], v[4:5]
	v_add_f64 v[26:27], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[8:9], v[24:25]
	v_mul_f64 v[26:27], v[30:31], v[26:27]
.LBB2_242:                              ; %Flow581
	s_mov_b32 s1, 0
	s_branch .LBB2_245
.LBB2_243:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr24_vgpr25
	s_branch .LBB2_250
.LBB2_244:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr24_vgpr25
.LBB2_245:                              ; %Flow583
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_249
; %bb.246:                              ; %LeafBlock575
	s_cmp_lg_u32 s28, 2
	s_cbranch_scc1 .LBB2_248
; %bb.247:
	v_add_f64 v[8:9], v[0:1], v[4:5]
	v_add_f64 v[10:11], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[6:7], v[8:9]
	v_mul_f64 v[10:11], v[28:29], v[10:11]
.LBB2_248:                              ; %Flow582
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
	v_dual_mov_b32 v24, v32 :: v_dual_mov_b32 v25, v33
.LBB2_249:                              ; %Flow584
	s_mov_b32 s1, 0
.LBB2_250:                              ; %Flow586
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_252
; %bb.251:
	v_add_f64 v[4:5], v[0:1], v[4:5]
	v_add_f64 v[6:7], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[2:3], v[4:5]
	v_mul_f64 v[26:27], v[20:21], v[6:7]
.LBB2_252:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_256
; %bb.253:
	s_mov_b32 s0, exec_lo
	v_cmpx_ngt_f64_e32 0, v[14:15]
	s_cbranch_execz .LBB2_255
; %bb.254:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[2:3], v[12:13], v[26:27]
	v_mul_f64 v[4:5], v[12:13], v[14:15]
	v_add_f64 v[0:1], v[18:19], -v[0:1]
	v_add_f64 v[6:7], v[14:15], -v[12:13]
	v_fma_f64 v[2:3], v[14:15], v[24:25], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[4:5], v[2:3]
	v_div_scale_f64 v[2:3], null, v[6:7], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
	v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[4:5]
	v_fma_f64 v[2:3], -v[2:3], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[10:11]
	v_div_fixup_f64 v[26:27], v[2:3], v[6:7], v[0:1]
.LBB2_255:                              ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v24, v26 :: v_dual_mov_b32 v25, v27
.LBB2_256:                              ; %writeInterFlux.exit430
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
	global_store_b64 v[0:1], v[24:25], off
.LBB2_257:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel setInterFlux_hll
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 504
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 67
		.amdhsa_next_free_sgpr 56
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	setInterFlux_hll, .Lfunc_end2-setInterFlux_hll
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9684
; NumSgprs: 58
; NumVgprs: 67
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 58
; NumVGPRsForWavesPerEU: 67
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	getInterFlux_hll        ; -- Begin function getInterFlux_hll
	.globl	getInterFlux_hll
	.p2align	8
	.type	getInterFlux_hll,@function
getInterFlux_hll:                       ; @getInterFlux_hll
; %bb.0:
	s_clause 0x4
	s_load_b64 s[2:3], s[0:1], 0xb4
	s_load_b32 s10, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0xa8
	s_load_b64 s[6:7], s[0:1], 0x8
	s_load_b512 s[16:31], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s9, s2, 16
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[0:1], null, s14, s9, v[3:4]
	s_and_b32 s8, s2, 0xffff
	v_mad_u64_u32 v[5:6], null, s15, s3, v[4:5]
	s_mul_i32 s2, s4, s8
	v_mad_u64_u32 v[3:4], null, s13, s8, v[2:3]
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v6, s2, v0
	s_mul_i32 s2, s2, s5
	s_cmp_eq_u32 s10, 1
	s_mul_i32 s2, s2, s9
	s_cselect_b32 s33, -1, 0
	v_mul_lo_u32 v8, s2, v5
	s_cmp_lg_u32 s10, 1
	v_cmp_eq_u32_e64 s2, 0x7f, v3
	v_add_nc_u32_e32 v4, v6, v3
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_2
; %bb.1:
	v_div_scale_f64 v[1:2], null, s[16:17], s[16:17], s[6:7]
	v_add_nc_u32_e32 v6, 0x7f, v6
	v_add_nc_u32_e32 v7, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v7, v6, s2
	v_add_nc_u32_e32 v18, v8, v6
	v_rcp_f64_e32 v[9:10], v[1:2]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, s[6:7], s[16:17], s[6:7]
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], -v[1:2], v[13:14], v[11:12]
	v_div_fmas_f64 v[1:2], v[1:2], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[1:2], s[16:17], s[6:7]
	s_branch .LBB3_3
.LBB3_2:
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr1_vgpr2
.LBB3_3:
	s_cmp_eq_u32 s10, 2
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s10, 2
	s_cbranch_scc1 .LBB3_9
; %bb.4:
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr6
	v_cmpx_ne_u32_e32 0x7f, v0
	s_xor_b32 s11, exec_lo, s11
; %bb.5:
	v_mad_u64_u32 v[6:7], null, s8, v0, s[8:9]
; %bb.6:                                ; %Flow330
	s_and_not1_saveexec_b32 s11, s11
; %bb.7:
	s_mul_i32 s12, s8, 0x7f
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
; %bb.8:
	s_or_b32 exec_lo, exec_lo, s11
	v_div_scale_f64 v[1:2], null, s[18:19], s[18:19], s[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s4
	v_add3_u32 v18, v8, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[1:2]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, s[6:7], s[18:19], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[1:2], -v[1:2], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[1:2], v[1:2], v[9:10], v[13:14]
	v_div_fixup_f64 v[1:2], v[1:2], s[18:19], s[6:7]
.LBB3_9:
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s34, -1, 0
	s_cmp_lg_u32 s10, 3
	s_cbranch_scc1 .LBB3_15
; %bb.10:
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr6
	v_cmpx_ne_u32_e32 0x7f, v5
	s_xor_b32 s10, exec_lo, s10
; %bb.11:
	v_mad_u64_u32 v[6:7], null, s8, v5, s[8:9]
; %bb.12:                               ; %Flow327
	s_and_not1_saveexec_b32 s10, s10
; %bb.13:
	s_mulk_i32 s8, 0x7f
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s8
; %bb.14:
	s_or_b32 exec_lo, exec_lo, s10
	v_div_scale_f64 v[1:2], null, s[20:21], s[20:21], s[6:7]
	s_mul_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s9
	v_mad_u64_u32 v[18:19], null, s4, v6, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[1:2]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[1:2], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, s[6:7], s[20:21], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[1:2], -v[1:2], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[1:2], v[1:2], v[9:10], v[13:14]
	v_div_fixup_f64 v[1:2], v[1:2], s[20:21], s[6:7]
.LBB3_15:
	s_load_b512 s[4:19], s[0:1], 0x58
	v_add_nc_u32_e32 v6, v8, v4
	v_ashrrev_i32_e32 v19, 31, v18
	s_load_b128 s[36:39], s[0:1], 0x98
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[26:27], 3, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v14, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v7, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	v_add_co_u32 v18, vcc_lo, s4, v26
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v27, vcc_lo
	v_add_co_u32 v20, vcc_lo, s6, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v27, vcc_lo
	v_add_co_u32 v22, vcc_lo, s8, v26
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v27, vcc_lo
	v_add_co_u32 v24, vcc_lo, s10, v26
	v_add_co_ci_u32_e32 v25, vcc_lo, s11, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0x7f, v3
	v_add_co_u32 v26, s0, s12, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v27, s0, s13, v27, s0
	s_and_b32 s1, s33, vcc_lo
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_17
; %bb.16:
	v_lshl_add_u32 v18, v5, 7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[26:27], 3, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s14, v26
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v27, vcc_lo
	v_add_co_u32 v20, vcc_lo, s16, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v27, vcc_lo
	v_add_co_u32 v22, vcc_lo, s18, v26
	v_add_co_ci_u32_e32 v23, vcc_lo, s19, v27, vcc_lo
	v_add_co_u32 v24, vcc_lo, s36, v26
	v_add_co_ci_u32_e32 v25, vcc_lo, s37, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, s38, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s39, v27, vcc_lo
.LBB3_17:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 0x7f, v0
	s_and_b32 s1, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_19
; %bb.18:
	v_lshl_add_u32 v18, v5, 7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[26:27], 3, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s14, v26
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v27, vcc_lo
	v_add_co_u32 v20, vcc_lo, s16, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v27, vcc_lo
	v_add_co_u32 v22, vcc_lo, s18, v26
	v_add_co_ci_u32_e32 v23, vcc_lo, s19, v27, vcc_lo
	v_add_co_u32 v24, vcc_lo, s36, v26
	v_add_co_ci_u32_e32 v25, vcc_lo, s37, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, s38, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s39, v27, vcc_lo
.LBB3_19:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 0x7f, v5
	s_and_b32 s1, s34, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_21
; %bb.20:
	v_lshl_add_u32 v3, v0, 7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v4, vcc_lo
	v_add_co_u32 v20, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v4, vcc_lo
	v_add_co_u32 v22, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v23, vcc_lo, s19, v4, vcc_lo
	v_add_co_u32 v24, vcc_lo, s36, v3
	v_add_co_ci_u32_e32 v25, vcc_lo, s37, v4, vcc_lo
	v_add_co_u32 v26, vcc_lo, s38, v3
	v_add_co_ci_u32_e32 v27, vcc_lo, s39, v4, vcc_lo
.LBB3_21:
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b64 v[3:4], v[18:19], off
	global_load_b64 v[18:19], v[20:21], off
	global_load_b64 v[22:23], v[22:23], off
	global_load_b64 v[24:25], v[24:25], off
	global_load_b64 v[26:27], v[26:27], off
	s_and_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s0, -1
	s_waitcnt vmcnt(4)
	v_add_f64 v[20:21], v[3:4], -v[8:9]
	s_waitcnt vmcnt(3)
	v_add_f64 v[18:19], v[18:19], -v[10:11]
	s_waitcnt vmcnt(2)
	v_add_f64 v[10:11], v[22:23], -v[12:13]
	s_waitcnt vmcnt(1)
	v_add_f64 v[8:9], v[24:25], -v[14:15]
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[26:27], -v[16:17]
	s_cbranch_vccz .LBB3_23
; %bb.22:
	v_add_co_u32 v12, vcc_lo, s22, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s25, v7, vcc_lo
	global_load_b64 v[14:15], v[12:13], off
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[1:2], v[20:21], v[14:15]
	global_store_b64 v[12:13], v[14:15], off
	global_load_b64 v[12:13], v[16:17], off
	v_add_co_u32 v14, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s27, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[1:2], v[18:19], v[12:13]
	global_store_b64 v[16:17], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off
	v_add_co_u32 v16, vcc_lo, s28, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s29, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[1:2], v[10:11], v[12:13]
	global_store_b64 v[14:15], v[12:13], off
	global_load_b64 v[12:13], v[16:17], off
	v_add_co_u32 v14, vcc_lo, s30, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s31, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[1:2], v[8:9], v[12:13]
	global_store_b64 v[16:17], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[1:2], v[3:4], v[12:13]
	global_store_b64 v[14:15], v[12:13], off
.LBB3_23:                               ; %Flow
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_25
; %bb.24:
	v_mul_f64 v[12:13], v[20:21], -v[1:2]
	v_mul_f64 v[14:15], v[18:19], -v[1:2]
	v_mul_f64 v[10:11], v[10:11], -v[1:2]
	v_mul_f64 v[8:9], v[8:9], -v[1:2]
	v_mul_f64 v[0:1], v[3:4], -v[1:2]
	v_add_co_u32 v2, vcc_lo, s22, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v17, vcc_lo, s27, v7, vcc_lo
	v_add_co_u32 v18, vcc_lo, s28, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, s29, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s30, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s31, v7, vcc_lo
	global_store_b64 v[2:3], v[12:13], off
	global_store_b64 v[4:5], v[14:15], off
	global_store_b64 v[16:17], v[10:11], off
	global_store_b64 v[18:19], v[8:9], off
	global_store_b64 v[6:7], v[0:1], off
.LBB3_25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel getInterFlux_hll
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 424
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	getInterFlux_hll, .Lfunc_end3-getInterFlux_hll
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1748
; NumSgprs: 42
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	reduction_kernel        ; -- Begin function reduction_kernel
	.globl	reduction_kernel
	.p2align	8
	.type	reduction_kernel,@function
reduction_kernel:                       ; @reduction_kernel
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_cmp_lt_u32 s5, 2
	v_mad_u64_u32 v[3:4], null, s6, s5, v[1:2]
	v_mov_b32_e32 v4, v2
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[1:2], v[3:4]
	v_lshlrev_b32_e32 v1, 3, v0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB4_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_1 Depth=1
	v_lshl_add_u32 v2, s0, 3, v1
	ds_load_b64 v[2:3], v2
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB4_4:                                ;   in Loop: Header=BB4_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB4_1
.LBB4_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_7
; %bb.6:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB4_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel reduction_kernel
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	reduction_kernel, .Lfunc_end4-reduction_kernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	copyDtoD                ; -- Begin function copyDtoD
	.globl	copyDtoD
	.p2align	8
	.type	copyDtoD,@function
copyDtoD:                               ; @copyDtoD
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x1c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_bfe_u32 v1, v0, 20, 10
	s_mov_b32 s2, s13
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s5, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s4, 16
	v_and_b32_e32 v0, 0x3ff, v0
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s7, s[14:15]
	v_mad_u64_u32 v[4:5], null, v3, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v4, s6, s[2:3]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel copyDtoD
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	copyDtoD, .Lfunc_end5-copyDtoD
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	addDtoD                 ; -- Begin function addDtoD
	.globl	addDtoD
	.p2align	8
	.type	addDtoD,@function
addDtoD:                                ; @addDtoD
; %bb.0:
	s_clause 0x1
	s_load_b64 s[20:21], s[0:1], 0x5c
	s_load_b64 s[4:5], s[0:1], 0x50
	v_bfe_u32 v1, v0, 20, 10
	s_mov_b32 s2, s13
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s21, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s20, 16
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
	v_mad_u64_u32 v[4:5], null, v3, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v4, s4, s[2:3]
	s_and_b32 s2, s20, 0xffff
	s_load_b512 s[4:19], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v1, vcc_lo
	global_load_b64 v[6:7], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_co_u32 v6, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v1, vcc_lo
	global_store_b64 v[2:3], v[4:5], off
	global_load_b64 v[2:3], v[6:7], off
	global_load_b64 v[4:5], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v1, vcc_lo
	global_store_b64 v[6:7], v[2:3], off
	global_load_b64 v[2:3], v[4:5], off
	global_load_b64 v[6:7], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_co_u32 v6, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[6:7], off
	global_load_b64 v[4:5], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_co_u32 v4, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b64 v[6:7], v[2:3], off
	global_load_b64 v[2:3], v[4:5], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	global_store_b64 v[4:5], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel addDtoD
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	addDtoD, .Lfunc_end6-addDtoD
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           reduction_min_kernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         reduction_min_kernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         144
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         152
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         160
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         168
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         176
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         184
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         192
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         200
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         208
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         216
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         224
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         232
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         240
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         248
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         256
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         264
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         272
        .size:           8
        .value_kind:     global_buffer
      - .offset:         280
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         284
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         288
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         292
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         294
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         296
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         298
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         300
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         302
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         320
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         328
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         336
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         344
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 536
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           setBounderies
    .private_segment_fixed_size: 0
    .sgpr_count:     86
    .sgpr_spill_count: 0
    .symbol:         setBounderies.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         144
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         152
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         160
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         168
        .size:           8
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...

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