#include <stdio.h>

struct AoS {
	float x;
	float y;
};

struct SoA {
	float* x;
	float* y;
};

void misalignedReadHost(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	for (int offsetIdx = offset, idx = 0; offsetIdx < count; offsetIdx++, idx++) {
		arrayC[idx] = arrayA[offsetIdx] + arrayB[offsetIdx];
	}
}

void misalignedWriteHost(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	for (int offsetIdx = offset, idx = 0; offsetIdx < count; offsetIdx++, idx++) {
		arrayC[offsetIdx] = arrayA[idx] + arrayB[idx];
	}
}

__global__
void arrayOfStructuresTest(AoS* arrayA, AoS* arrayB, int count) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;

	if (idx < count) {
		arrayB[idx].x = arrayA[idx].x * 2;
		arrayB[idx].y = arrayA[idx].y * 2;
	}
}

__global__
void structureOfArraysTest(SoA* structureA, SoA* structureB, int count) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;

	if (idx < count) {
		structureB->x[idx] = structureA->x[idx] * 2;
		structureB->y[idx] = structureA->y[idx] * 2; 
	}
}

__global__
void misalignedReadDevice(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
	int offsetIdx = idx + offset;

	if (offsetIdx < count) {
		arrayC[idx] = arrayA[offsetIdx] + arrayB[offsetIdx];
	}
}

__global__
void misalignedWriteDevice(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
	int offsetIdx = idx + offset;

	if (offsetIdx < count) {
		arrayC[offsetIdx] = arrayA[idx] + arrayB[idx];
	}
}

int main(void) {
	printf("\n");
	
	int count = 1 << 16;
	dim3 block = (512);
	dim3 grid = ((count + block.x - 1) / block.x);

	int offset = 11;

	float* h_a = (float*)malloc(count*sizeof(float));
	float* h_b = (float*)malloc(count*sizeof(float));

	for (int x = 0; x < count; x++) {
		h_a[x] = x * 2;
		h_b[x] = (x * 2) + 1;
	}

	float* h_result = (float*)malloc(count*sizeof(float));
	float* d_result = (float*)malloc(count*sizeof(float));

	misalignedReadHost(h_a, h_b, h_result, count, offset);

	float *d_a, *d_b, *d_c;
	cudaMalloc((float**)&d_a, count*sizeof(float));
	cudaMemcpy(d_a, h_a, count*sizeof(float), cudaMemcpyHostToDevice);
	cudaMalloc((float**)&d_b, count*sizeof(float));
	cudaMemcpy(d_b, h_b, count*sizeof(float), cudaMemcpyHostToDevice);

	cudaMalloc((float**)&d_c, count*sizeof(float));

	misalignedReadDevice<<<grid,block>>>(d_a, d_b, d_c, count, offset);
	cudaDeviceSynchronize();

	cudaMemcpy(d_result, d_c, count*sizeof(float), cudaMemcpyDeviceToHost);

	bool indexFailed = false;
	for (int x = 0; x < count; x++) {
		if (h_result[x] != d_result[x]) {
			printf("error on index %d: %f, %f\n", x, h_result[x], d_result[x]);
			indexFailed = true;
		}
	}

	if (!indexFailed) {
		printf("all indices passed successfully\n");
	}

	return 0;
}
	.file	"tmpxft_00399cab_00000000-6_memory_access_patterns.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18misalignedReadHostPfS_S_ii
	.type	_Z18misalignedReadHostPfS_S_ii, @function
_Z18misalignedReadHostPfS_S_ii:
.LFB2027:
	.cfi_startproc
	endbr64
	movslq	%r8d, %r8
.L3:
	cmpl	%r8d, %ecx
	jle	.L6
	movss	(%rdi,%r8,4), %xmm0
	addss	(%rsi,%r8,4), %xmm0
	addq	$4, %rdx
	incq	%r8
	movss	%xmm0, -4(%rdx)
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z18misalignedReadHostPfS_S_ii, .-_Z18misalignedReadHostPfS_S_ii
	.globl	_Z19misalignedWriteHostPfS_S_ii
	.type	_Z19misalignedWriteHostPfS_S_ii, @function
_Z19misalignedWriteHostPfS_S_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	movslq	%r8d, %r8
	xorl	%eax, %eax
.L8:
	cmpl	%r8d, %ecx
	jle	.L10
	movss	(%rdi,%rax), %xmm0
	addss	(%rsi,%rax), %xmm0
	addq	$4, %rax
	movss	%xmm0, (%rdx,%r8,4)
	incq	%r8
	jmp	.L8
.L10:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z19misalignedWriteHostPfS_S_ii, .-_Z19misalignedWriteHostPfS_S_ii
	.globl	_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i
	.type	_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i, @function
_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z21arrayOfStructuresTestP3AoSS0_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L11:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i, .-_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i
	.globl	_Z21arrayOfStructuresTestP3AoSS0_i
	.type	_Z21arrayOfStructuresTestP3AoSS0_i, @function
_Z21arrayOfStructuresTestP3AoSS0_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z21arrayOfStructuresTestP3AoSS0_iP3AoSS0_i
	.cfi_endproc
.LFE2055:
	.size	_Z21arrayOfStructuresTestP3AoSS0_i, .-_Z21arrayOfStructuresTestP3AoSS0_i
	.globl	_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i
	.type	_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i, @function
_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z21structureOfArraysTestP3SoAS0_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L16:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i, .-_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i
	.globl	_Z21structureOfArraysTestP3SoAS0_i
	.type	_Z21structureOfArraysTestP3SoAS0_i, @function
_Z21structureOfArraysTestP3SoAS0_i:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z21structureOfArraysTestP3SoAS0_iP3SoAS0_i
	.cfi_endproc
.LFE2057:
	.size	_Z21structureOfArraysTestP3SoAS0_i, .-_Z21structureOfArraysTestP3SoAS0_i
	.globl	_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii
	.type	_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii, @function
_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20misalignedReadDevicePfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L21:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii, .-_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii
	.globl	_Z20misalignedReadDevicePfS_S_ii
	.type	_Z20misalignedReadDevicePfS_S_ii, @function
_Z20misalignedReadDevicePfS_S_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2059:
	.size	_Z20misalignedReadDevicePfS_S_ii, .-_Z20misalignedReadDevicePfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n"
.LC1:
	.string	"error on index %d: %f, %f\n"
.LC2:
	.string	"all indices passed successfully\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$262144, %edi
	movabsq	$4294967297, %rax
	movl	$1, 52(%rsp)
	movq	%rax, 36(%rsp)
	addq	$127, %rax
	movq	%rax, 44(%rsp)
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L27:
	leal	(%rax,%rax), %edx
	cvtsi2ssl	%edx, %xmm0
	incl	%edx
	movss	%xmm0, 0(%rbp,%rax,4)
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$65536, %rax
	jne	.L27
	movl	$262144, %edi
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$65536, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$11, %r8d
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	_Z18misalignedReadHostPfS_S_ii
	leaq	8(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movl	$512, 32(%rsp)
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$65536, %ecx
	movl	$11, %r8d
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z20misalignedReadDevicePfS_S_iiPfS_S_ii
.L28:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rsi
	movq	%r13, %rdi
	xorl	%ebx, %ebx
	movl	$2, %ecx
	movl	$262144, %edx
	leaq	.LC1(%rip), %rbp
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L31:
	movss	(%r12,%rbx,4), %xmm0
	movss	0(%r13,%rbx,4), %xmm1
	ucomiss	%xmm1, %xmm0
	jp	.L34
	je	.L29
.L34:
	movl	%ebx, %edx
	movq	%rbp, %rsi
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
	movb	$1, %al
.L29:
	incq	%rbx
	cmpq	$65536, %rbx
	jne	.L31
	testb	%al, %al
	jne	.L32
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L32:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.text
	.globl	_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii
	.type	_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii, @function
_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21misalignedWriteDevicePfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L38:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii, .-_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii
	.globl	_Z21misalignedWriteDevicePfS_S_ii
	.type	_Z21misalignedWriteDevicePfS_S_ii, @function
_Z21misalignedWriteDevicePfS_S_ii:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21misalignedWriteDevicePfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2061:
	.size	_Z21misalignedWriteDevicePfS_S_ii, .-_Z21misalignedWriteDevicePfS_S_ii
	.section	.rodata.str1.1
.LC3:
	.string	"_Z21misalignedWriteDevicePfS_S_ii"
.LC4:
	.string	"_Z20misalignedReadDevicePfS_S_ii"
.LC5:
	.string	"_Z21structureOfArraysTestP3SoAS0_i"
.LC6:
	.string	"_Z21arrayOfStructuresTestP3AoSS0_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21misalignedWriteDevicePfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20misalignedReadDevicePfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21structureOfArraysTestP3SoAS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21arrayOfStructuresTestP3AoSS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

struct AoS {
	float x;
	float y;
};

struct SoA {
	float* x;
	float* y;
};

void misalignedReadHost(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	for (int offsetIdx = offset, idx = 0; offsetIdx < count; offsetIdx++, idx++) {
		arrayC[idx] = arrayA[offsetIdx] + arrayB[offsetIdx];
	}
}

void misalignedWriteHost(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	for (int offsetIdx = offset, idx = 0; offsetIdx < count; offsetIdx++, idx++) {
		arrayC[offsetIdx] = arrayA[idx] + arrayB[idx];
	}
}

__global__
void arrayOfStructuresTest(AoS* arrayA, AoS* arrayB, int count) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;

	if (idx < count) {
		arrayB[idx].x = arrayA[idx].x * 2;
		arrayB[idx].y = arrayA[idx].y * 2;
	}
}

__global__
void structureOfArraysTest(SoA* structureA, SoA* structureB, int count) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;

	if (idx < count) {
		structureB->x[idx] = structureA->x[idx] * 2;
		structureB->y[idx] = structureA->y[idx] * 2; 
	}
}

__global__
void misalignedReadDevice(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
	int offsetIdx = idx + offset;

	if (offsetIdx < count) {
		arrayC[idx] = arrayA[offsetIdx] + arrayB[offsetIdx];
	}
}

__global__
void misalignedWriteDevice(float* arrayA, float* arrayB, float* arrayC, int count, int offset) {
	int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
	int offsetIdx = idx + offset;

	if (offsetIdx < count) {
		arrayC[offsetIdx] = arrayA[idx] + arrayB[idx];
	}
}

int main(void) {
	printf("\n");
	
	int count = 1 << 16;
	dim3 block = (512);
	dim3 grid = ((count + block.x - 1) / block.x);

	int offset = 11;

	float* h_a = (float*)malloc(count*sizeof(float));
	float* h_b = (float*)malloc(count*sizeof(float));

	for (int x = 0; x < count; x++) {
		h_a[x] = x * 2;
		h_b[x] = (x * 2) + 1;
	}

	float* h_result = (float*)malloc(count*sizeof(float));
	float* d_result = (float*)malloc(count*sizeof(float));

	misalignedReadHost(h_a, h_b, h_result, count, offset);

	float *d_a, *d_b, *d_c;
	hipMalloc((float**)&d_a, count*sizeof(float));
	hipMemcpy(d_a, h_a, count*sizeof(float), hipMemcpyHostToDevice);
	hipMalloc((float**)&d_b, count*sizeof(float));
	hipMemcpy(d_b, h_b, count*sizeof(float), hipMemcpyHostToDevice);

	hipMalloc((float**)&d_c, count*sizeof(float));

	misalignedReadDevice<<<grid,block>>>(d_a, d_b, d_c, count, offset);
	hipDeviceSynchronize();

	hipMemcpy(d_result, d_c, count*sizeof(float), hipMemcpyDeviceToHost);

	bool indexFailed = false;
	for (int x = 0; x < count; x++) {
		if (h_result[x] != d_result[x]) {
			printf("error on index %d: %f, %f\n", x, h_result[x], d_result[x]);
			indexFailed = true;
		}
	}

	if (!indexFailed) {
		printf("all indices passed successfully\n");
	}

	return 0;
}
	.text
	.file	"memory_access_patterns.hip"
	.globl	_Z18misalignedReadHostPfS_S_ii  # -- Begin function _Z18misalignedReadHostPfS_S_ii
	.type	_Z18misalignedReadHostPfS_S_ii,@function
_Z18misalignedReadHostPfS_S_ii:         # @_Z18misalignedReadHostPfS_S_ii
	.cfi_startproc
# %bb.0:
                                        # kill: def $ecx killed $ecx def $rcx
	subl	%r8d, %ecx
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movslq	%r8d, %r8
	leaq	(%rdi,%r8,4), %rax
	leaq	(%rsi,%r8,4), %rsi
	xorl	%edi, %edi
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rdi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%rsi,%rdi,4), %xmm0
	movss	%xmm0, (%rdx,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %rcx
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z18misalignedReadHostPfS_S_ii, .Lfunc_end0-_Z18misalignedReadHostPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19misalignedWriteHostPfS_S_ii # -- Begin function _Z19misalignedWriteHostPfS_S_ii
	.type	_Z19misalignedWriteHostPfS_S_ii,@function
_Z19misalignedWriteHostPfS_S_ii:        # @_Z19misalignedWriteHostPfS_S_ii
	.cfi_startproc
# %bb.0:
                                        # kill: def $ecx killed $ecx def $rcx
	subl	%r8d, %ecx
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movslq	%r8d, %rax
	leaq	(%rdx,%rax,4), %rax
	xorl	%edx, %edx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rdi,%rdx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%rsi,%rdx,4), %xmm0
	movss	%xmm0, (%rax,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z19misalignedWriteHostPfS_S_ii, .Lfunc_end1-_Z19misalignedWriteHostPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i # -- Begin function _Z36__device_stub__arrayOfStructuresTestP3AoSS0_i
	.type	_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i,@function
_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i: # @_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21arrayOfStructuresTestP3AoSS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i, .Lfunc_end2-_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__structureOfArraysTestP3SoAS0_i # -- Begin function _Z36__device_stub__structureOfArraysTestP3SoAS0_i
	.type	_Z36__device_stub__structureOfArraysTestP3SoAS0_i,@function
_Z36__device_stub__structureOfArraysTestP3SoAS0_i: # @_Z36__device_stub__structureOfArraysTestP3SoAS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21structureOfArraysTestP3SoAS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z36__device_stub__structureOfArraysTestP3SoAS0_i, .Lfunc_end3-_Z36__device_stub__structureOfArraysTestP3SoAS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__misalignedReadDevicePfS_S_ii # -- Begin function _Z35__device_stub__misalignedReadDevicePfS_S_ii
	.type	_Z35__device_stub__misalignedReadDevicePfS_S_ii,@function
_Z35__device_stub__misalignedReadDevicePfS_S_ii: # @_Z35__device_stub__misalignedReadDevicePfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20misalignedReadDevicePfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z35__device_stub__misalignedReadDevicePfS_S_ii, .Lfunc_end4-_Z35__device_stub__misalignedReadDevicePfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__misalignedWriteDevicePfS_S_ii # -- Begin function _Z36__device_stub__misalignedWriteDevicePfS_S_ii
	.type	_Z36__device_stub__misalignedWriteDevicePfS_S_ii,@function
_Z36__device_stub__misalignedWriteDevicePfS_S_ii: # @_Z36__device_stub__misalignedWriteDevicePfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21misalignedWriteDevicePfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z36__device_stub__misalignedWriteDevicePfS_S_ii, .Lfunc_end5-_Z36__device_stub__misalignedWriteDevicePfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$10, %edi
	callq	putchar@PLT
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %r12
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB6_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	leal	1(%rax), %ecx
	xorps	%xmm1, %xmm1
	cvtsi2ss	%ecx, %xmm1
	movss	%xmm0, (%r12,%rax,2)
	movss	%xmm1, (%r15,%rax,2)
	addq	$2, %rax
	cmpq	$131072, %rax                   # imm = 0x20000
	jne	.LBB6_1
# %bb.2:
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %rbx
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %r14
	movl	$11, %eax
.LBB6_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r12,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%r15,%rax,4), %xmm0
	movss	%xmm0, -44(%rbx,%rax,4)
	incq	%rax
	cmpq	$65536, %rax                    # imm = 0x10000
	jne	.LBB6_3
# %bb.4:                                # %_Z18misalignedReadHostPfS_S_ii.exit
	leaq	24(%rsp), %r13
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r12
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	movabsq	$4294967424, %rdi               # imm = 0x100000080
	leaq	384(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$65536, %ecx                    # imm = 0x10000
	movl	$11, %r8d
	callq	_Z35__device_stub__misalignedReadDevicePfS_S_ii
.LBB6_6:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	xorl	%eax, %eax
.LBB6_7:                                # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	(%r14,%r15,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm1, %xmm0
	jne	.LBB6_8
	jnp	.LBB6_9
.LBB6_8:                                #   in Loop: Header=BB6_7 Depth=1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.1, %edi
	movl	%r15d, %esi
	movb	$2, %al
	callq	printf
	movb	$1, %al
.LBB6_9:                                #   in Loop: Header=BB6_7 Depth=1
	incq	%r15
	cmpq	$65536, %r15                    # imm = 0x10000
	jne	.LBB6_7
# %bb.10:
	testb	$1, %al
	jne	.LBB6_12
# %bb.11:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB6_12:
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21arrayOfStructuresTestP3AoSS0_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21structureOfArraysTestP3SoAS0_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20misalignedReadDevicePfS_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21misalignedWriteDevicePfS_S_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21arrayOfStructuresTestP3AoSS0_i,@object # @_Z21arrayOfStructuresTestP3AoSS0_i
	.section	.rodata,"a",@progbits
	.globl	_Z21arrayOfStructuresTestP3AoSS0_i
	.p2align	3, 0x0
_Z21arrayOfStructuresTestP3AoSS0_i:
	.quad	_Z36__device_stub__arrayOfStructuresTestP3AoSS0_i
	.size	_Z21arrayOfStructuresTestP3AoSS0_i, 8

	.type	_Z21structureOfArraysTestP3SoAS0_i,@object # @_Z21structureOfArraysTestP3SoAS0_i
	.globl	_Z21structureOfArraysTestP3SoAS0_i
	.p2align	3, 0x0
_Z21structureOfArraysTestP3SoAS0_i:
	.quad	_Z36__device_stub__structureOfArraysTestP3SoAS0_i
	.size	_Z21structureOfArraysTestP3SoAS0_i, 8

	.type	_Z20misalignedReadDevicePfS_S_ii,@object # @_Z20misalignedReadDevicePfS_S_ii
	.globl	_Z20misalignedReadDevicePfS_S_ii
	.p2align	3, 0x0
_Z20misalignedReadDevicePfS_S_ii:
	.quad	_Z35__device_stub__misalignedReadDevicePfS_S_ii
	.size	_Z20misalignedReadDevicePfS_S_ii, 8

	.type	_Z21misalignedWriteDevicePfS_S_ii,@object # @_Z21misalignedWriteDevicePfS_S_ii
	.globl	_Z21misalignedWriteDevicePfS_S_ii
	.p2align	3, 0x0
_Z21misalignedWriteDevicePfS_S_ii:
	.quad	_Z36__device_stub__misalignedWriteDevicePfS_S_ii
	.size	_Z21misalignedWriteDevicePfS_S_ii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"error on index %d: %f, %f\n"
	.size	.L.str.1, 27

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21arrayOfStructuresTestP3AoSS0_i"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21structureOfArraysTestP3SoAS0_i"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z20misalignedReadDevicePfS_S_ii"
	.size	.L__unnamed_3, 33

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z21misalignedWriteDevicePfS_S_ii"
	.size	.L__unnamed_4, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"all indices passed successfully"
	.size	.Lstr, 32

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__arrayOfStructuresTestP3AoSS0_i
	.addrsig_sym _Z36__device_stub__structureOfArraysTestP3SoAS0_i
	.addrsig_sym _Z35__device_stub__misalignedReadDevicePfS_S_ii
	.addrsig_sym _Z36__device_stub__misalignedWriteDevicePfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21arrayOfStructuresTestP3AoSS0_i
	.addrsig_sym _Z21structureOfArraysTestP3SoAS0_i
	.addrsig_sym _Z20misalignedReadDevicePfS_S_ii
	.addrsig_sym _Z21misalignedWriteDevicePfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21arrayOfStructuresTestP3AoSS0_i ; -- Begin function _Z21arrayOfStructuresTestP3AoSS0_i
	.globl	_Z21arrayOfStructuresTestP3AoSS0_i
	.p2align	8
	.type	_Z21arrayOfStructuresTestP3AoSS0_i,@function
_Z21arrayOfStructuresTestP3AoSS0_i:     ; @_Z21arrayOfStructuresTestP3AoSS0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v2, v2, v2 :: v_dual_add_f32 v3, v3, v3
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21arrayOfStructuresTestP3AoSS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21arrayOfStructuresTestP3AoSS0_i, .Lfunc_end0-_Z21arrayOfStructuresTestP3AoSS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21structureOfArraysTestP3SoAS0_i ; -- Begin function _Z21structureOfArraysTestP3SoAS0_i
	.globl	_Z21structureOfArraysTestP3SoAS0_i
	.p2align	8
	.type	_Z21structureOfArraysTestP3SoAS0_i,@function
_Z21structureOfArraysTestP3SoAS0_i:     ; @_Z21structureOfArraysTestP3SoAS0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b128 s[0:3], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v4, v4
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[2:3], v6, off
	v_add_co_u32 v0, vcc_lo, s2, v0
	global_load_b32 v2, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v2
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21structureOfArraysTestP3SoAS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z21structureOfArraysTestP3SoAS0_i, .Lfunc_end1-_Z21structureOfArraysTestP3SoAS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20misalignedReadDevicePfS_S_ii ; -- Begin function _Z20misalignedReadDevicePfS_S_ii
	.globl	_Z20misalignedReadDevicePfS_S_ii
	.p2align	8
	.type	_Z20misalignedReadDevicePfS_S_ii,@function
_Z20misalignedReadDevicePfS_S_ii:       ; @_Z20misalignedReadDevicePfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_add_nc_u32_e32 v2, s3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v3, v[2:3], off
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v4, v3
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20misalignedReadDevicePfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z20misalignedReadDevicePfS_S_ii, .Lfunc_end2-_Z20misalignedReadDevicePfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21misalignedWriteDevicePfS_S_ii ; -- Begin function _Z21misalignedWriteDevicePfS_S_ii
	.globl	_Z21misalignedWriteDevicePfS_S_ii
	.p2align	8
	.type	_Z21misalignedWriteDevicePfS_S_ii,@function
_Z21misalignedWriteDevicePfS_S_ii:      ; @_Z21misalignedWriteDevicePfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_add_nc_u32_e32 v0, s3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v2, v[1:2], off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21misalignedWriteDevicePfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z21misalignedWriteDevicePfS_S_ii, .Lfunc_end3-_Z21misalignedWriteDevicePfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21arrayOfStructuresTestP3AoSS0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21arrayOfStructuresTestP3AoSS0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21structureOfArraysTestP3SoAS0_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21structureOfArraysTestP3SoAS0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20misalignedReadDevicePfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20misalignedReadDevicePfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21misalignedWriteDevicePfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21misalignedWriteDevicePfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
