#include <stdio.h>
#include <cuda_runtime.h>

__global__ void Kernel

(
    double* u1,
    double* v1,
    double a,
    double b,
    double eta,
    double d_u1,
    double d_v1,
    double dt,
    double D,
    int N
)

{
      
    int tidx = threadIdx.x;
    int tidy = threadIdx.y;
    int bidx = blockIdx.x;
    int bidy = blockIdx.y;
    int bdimx = blockDim.x;
    int bdimy = blockDim.y;

    int x = tidx+bidx*bdimx;
    int y = tidy+bidy*bdimy;
    int id = x + y*N;
    
    double u1_c,v1_c;
    
    u1_c=u1[id];
    v1_c=v1[id];

    //lap_Du1R
    double u1_l,u1_r,u1_u,u1_d,lap_Du1;
    if(x==0)   u1_l=u1[id+(N-1)];
    else       u1_l=u1[id-1]; 
    if(x==N-1) u1_r=u1[id-(N-1)];
    else       u1_r=u1[id+1];
    if(y==0)   u1_u=u1[id+N*(N-1)];
    else       u1_u=u1[id-N];
    if(y==N-1) u1_d=u1[id-N*(N-1)];
    else       u1_d=u1[id+N];
    lap_Du1=u1_l+u1_r+u1_u+u1_d-u1_c*4.0;

    //lap_Du1I
    double v1_l,v1_r,v1_u,v1_d,lap_Dv1;
    if(x==0)   v1_l=v1[id+(N-1)];
    else       v1_l=v1[id-1]; 
    if(x==N-1) v1_r=v1[id-(N-1)];
    else       v1_r=v1[id+1];
    if(y==0)   v1_u=v1[id+N*(N-1)];
    else       v1_u=v1[id-N]; 
    if(y==N-1) v1_d=v1[id-N*(N-1)];
    else       v1_d=v1[id+N];
    lap_Dv1=v1_l+v1_r+v1_u+v1_d-v1_c*4.0;


    //reaction
    double react_u1,react_v1;
    react_u1=eta*( a-(b+1.0)*u1_c + u1_c*u1_c*v1_c );
    react_v1=eta*( b*u1_c - u1_c*u1_c*v1_c );

    //main
    u1[id] = u1_c+dt*react_u1+d_u1*D*lap_Du1;
    v1[id] = v1_c+dt*react_v1+d_v1*D*lap_Dv1;
  

}

	.file	"tmpxft_00345720_00000000-6_Brusselator_2D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi
	.type	_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi, @function
_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rcx
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movl	%edx, 4(%rsp)
	leaq	88(%rsp), %rdx
	movsd	%xmm0, 56(%rsp)
	movsd	%xmm1, 48(%rsp)
	movsd	%xmm2, 40(%rsp)
	movsd	%xmm3, 32(%rsp)
	movsd	%xmm4, 24(%rsp)
	movsd	%xmm5, 16(%rsp)
	movsd	%xmm6, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z6KernelPdS_dddddddi(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi, .-_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi
	.globl	_Z6KernelPdS_dddddddi
	.type	_Z6KernelPdS_dddddddi, @function
_Z6KernelPdS_dddddddi:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z6KernelPdS_dddddddiPdS_dddddddi
	.cfi_endproc
.LFE2052:
	.size	_Z6KernelPdS_dddddddi, .-_Z6KernelPdS_dddddddi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6KernelPdS_dddddddi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6KernelPdS_dddddddi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

__global__ void Kernel

(
    double* u1,
    double* v1,
    double a,
    double b,
    double eta,
    double d_u1,
    double d_v1,
    double dt,
    double D,
    int N
)

{
      
    int tidx = threadIdx.x;
    int tidy = threadIdx.y;
    int bidx = blockIdx.x;
    int bidy = blockIdx.y;
    int bdimx = blockDim.x;
    int bdimy = blockDim.y;

    int x = tidx+bidx*bdimx;
    int y = tidy+bidy*bdimy;
    int id = x + y*N;
    
    double u1_c,v1_c;
    
    u1_c=u1[id];
    v1_c=v1[id];

    //lap_Du1R
    double u1_l,u1_r,u1_u,u1_d,lap_Du1;
    if(x==0)   u1_l=u1[id+(N-1)];
    else       u1_l=u1[id-1]; 
    if(x==N-1) u1_r=u1[id-(N-1)];
    else       u1_r=u1[id+1];
    if(y==0)   u1_u=u1[id+N*(N-1)];
    else       u1_u=u1[id-N];
    if(y==N-1) u1_d=u1[id-N*(N-1)];
    else       u1_d=u1[id+N];
    lap_Du1=u1_l+u1_r+u1_u+u1_d-u1_c*4.0;

    //lap_Du1I
    double v1_l,v1_r,v1_u,v1_d,lap_Dv1;
    if(x==0)   v1_l=v1[id+(N-1)];
    else       v1_l=v1[id-1]; 
    if(x==N-1) v1_r=v1[id-(N-1)];
    else       v1_r=v1[id+1];
    if(y==0)   v1_u=v1[id+N*(N-1)];
    else       v1_u=v1[id-N]; 
    if(y==N-1) v1_d=v1[id-N*(N-1)];
    else       v1_d=v1[id+N];
    lap_Dv1=v1_l+v1_r+v1_u+v1_d-v1_c*4.0;


    //reaction
    double react_u1,react_v1;
    react_u1=eta*( a-(b+1.0)*u1_c + u1_c*u1_c*v1_c );
    react_v1=eta*( b*u1_c - u1_c*u1_c*v1_c );

    //main
    u1[id] = u1_c+dt*react_u1+d_u1*D*lap_Du1;
    v1[id] = v1_c+dt*react_v1+d_v1*D*lap_Dv1;
  

}

	.text
	.file	"Brusselator_2D.hip"
	.globl	_Z21__device_stub__KernelPdS_dddddddi # -- Begin function _Z21__device_stub__KernelPdS_dddddddi
	.type	_Z21__device_stub__KernelPdS_dddddddi,@function
_Z21__device_stub__KernelPdS_dddddddi:  # @_Z21__device_stub__KernelPdS_dddddddi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	72(%rsp), %rsi
	movsd	%xmm0, (%rsi)
	leaq	64(%rsp), %rdi
	movsd	%xmm1, (%rdi)
	leaq	56(%rsp), %r8
	movsd	%xmm2, (%r8)
	leaq	48(%rsp), %r9
	movsd	%xmm3, (%r9)
	leaq	40(%rsp), %r10
	movsd	%xmm4, (%r10)
	leaq	32(%rsp), %r11
	movsd	%xmm5, (%r11)
	leaq	24(%rsp), %r14
	movsd	%xmm6, (%r14)
	leaq	4(%rsp), %r15
	movl	%edx, (%r15)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%r9, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%r15, 72(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6KernelPdS_dddddddi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__KernelPdS_dddddddi, .Lfunc_end0-_Z21__device_stub__KernelPdS_dddddddi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6KernelPdS_dddddddi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6KernelPdS_dddddddi,@object   # @_Z6KernelPdS_dddddddi
	.section	.rodata,"a",@progbits
	.globl	_Z6KernelPdS_dddddddi
	.p2align	3, 0x0
_Z6KernelPdS_dddddddi:
	.quad	_Z21__device_stub__KernelPdS_dddddddi
	.size	_Z6KernelPdS_dddddddi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6KernelPdS_dddddddi"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__KernelPdS_dddddddi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6KernelPdS_dddddddi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6KernelPdS_dddddddi   ; -- Begin function _Z6KernelPdS_dddddddi
	.globl	_Z6KernelPdS_dddddddi
	.p2align	8
	.type	_Z6KernelPdS_dddddddi,@function
_Z6KernelPdS_dddddddi:                  ; @_Z6KernelPdS_dddddddi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b32 s6, s[0:1], 0x48
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s7, s6, 31
	v_mad_u64_u32 v[15:16], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[16:17], null, s15, s3, v[0:1]
	s_load_b512 s[8:23], s[0:1], 0x0
	s_add_i32 s5, s6, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v16, s6, v[15:16]
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v21, s6, v8
	v_sub_co_u32 v0, vcc_lo, v8, s6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 3, v[8:9]
	v_subrev_co_ci_u32_e32 v1, vcc_lo, s7, v9, vcc_lo
	v_add_nc_u32_e32 v2, -1, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[17:18], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v0, -8
	v_add_co_ci_u32_e32 v7, vcc_lo, -1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v9, vcc_lo, s8, v17
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v18, vcc_lo
	v_add_co_u32 v11, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v2
	v_add_co_u32 v19, s2, v9, 8
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_add_co_ci_u32_e64 v20, s2, 0, v10, s2
	v_cmp_eq_u32_e64 s2, s5, v15
	v_add_co_u32 v2, s3, s10, v4
	v_cndmask_b32_e32 v10, v7, v14, vcc_lo
	v_add_co_ci_u32_e64 v3, s3, s11, v5, s3
	v_cndmask_b32_e32 v9, v6, v13, vcc_lo
	v_cndmask_b32_e64 v13, v12, v20, s2
	v_cndmask_b32_e64 v12, v11, v19, s2
	global_load_b64 v[6:7], v[0:1], off
	global_load_b64 v[4:5], v[2:3], off
	global_load_b64 v[10:11], v[9:10], off
	global_load_b64 v[12:13], v[12:13], off
	v_cmp_ne_u32_e64 s3, 0, v16
	v_subrev_nc_u32_e32 v14, s6, v8
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s3
	s_xor_b32 s4, exec_lo, s4
; %bb.1:
	v_subrev_nc_u32_e32 v19, s6, v8
; %bb.2:                                ; %Flow155
	s_and_not1_saveexec_b32 s4, s4
; %bb.3:
	v_mad_u64_u32 v[19:20], null, s5, s6, v[8:9]
; %bb.4:
	s_or_b32 exec_lo, exec_lo, s4
	v_cmp_eq_u32_e64 s4, s5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v20, 31, v19
	s_lshl_b64 s[24:25], s[6:7], 3
	v_cndmask_b32_e64 v15, v21, v15, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[22:23], 3, v[19:20]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[20:21], 3, v[15:16]
	v_add_co_u32 v15, s4, s8, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s4, s9, v23, s4
	v_add_co_u32 v9, s4, v2, s24
	v_add_co_ci_u32_e64 v19, s4, s25, v3, s4
	v_add_co_u32 v17, s4, s10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s4, s11, v18, s4
	v_add_co_u32 v22, s4, s8, v20
	v_add_co_ci_u32_e64 v23, s4, s9, v21, s4
	v_dual_cndmask_b32 v25, v3, v19 :: v_dual_cndmask_b32 v24, v2, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v27, v3, v18, s2
	v_cndmask_b32_e64 v26, v2, v17, s2
	s_clause 0x1
	global_load_b64 v[18:19], v[15:16], off
	global_load_b64 v[16:17], v[22:23], off
	global_load_b64 v[22:23], v[24:25], off offset:-8
	global_load_b64 v[24:25], v[26:27], off offset:8
	s_and_saveexec_b32 s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
; %bb.5:
                                        ; implicit-def: $vgpr8_vgpr9
; %bb.6:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_saveexec_b32 s2, s2
; %bb.7:
	v_mad_u64_u32 v[14:15], null, s5, s6, v[8:9]
; %bb.8:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	s_waitcnt vmcnt(7)
	v_mul_f64 v[26:27], v[6:7], v[6:7]
	s_waitcnt vmcnt(4)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	s_load_b64 s[0:1], s[0:1], 0x40
	v_lshlrev_b64 v[8:9], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v14, vcc_lo, s10, v20
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v21, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	v_add_f64 v[20:21], s[14:15], 1.0
	global_load_b64 v[14:15], v[14:15], off
	v_add_f64 v[10:11], v[10:11], v[18:19]
	v_fma_f64 v[12:13], -v[20:21], v[6:7], s[12:13]
	v_mul_f64 v[20:21], v[26:27], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[16:17]
	v_fma_f64 v[12:13], v[26:27], v[4:5], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[6:7], s[14:15], -v[20:21]
	v_fma_f64 v[10:11], v[6:7], -4.0, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[12:13], v[12:13], s[16:17]
	v_mul_f64 v[16:17], v[18:19], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[12:13], s[22:23], v[6:7]
	v_fma_f64 v[12:13], v[16:17], s[22:23], v[4:5]
	s_waitcnt vmcnt(1)
	v_add_f64 v[8:9], v[22:23], v[8:9]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[14:15]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[14:15], s[18:19], s[0:1]
	v_fma_f64 v[4:5], v[4:5], -4.0, v[8:9]
	v_mul_f64 v[8:9], s[20:21], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[14:15], v[10:11], v[6:7]
	v_fma_f64 v[4:5], v[8:9], v[4:5], v[12:13]
	global_store_b64 v[0:1], v[6:7], off
	global_store_b64 v[2:3], v[4:5], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6KernelPdS_dddddddi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6KernelPdS_dddddddi, .Lfunc_end0-_Z6KernelPdS_dddddddi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 916
; NumSgprs: 28
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6KernelPdS_dddddddi
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z6KernelPdS_dddddddi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
