#include <cuda.h>
#include <cuda_runtime.h>

/* initialize grid
 * we'll distribute all particles evenly on the screen
 */
__global__ void d_reset( float4* verts, float4* states,
                         float ww, float wh,
                         int mesh_width, int mesh_height
  )
{
  int x, y;
  for (y = blockIdx.y * blockDim.y + threadIdx.y;
       y < mesh_height;
       y += blockDim.y * gridDim.y)
  {
    for (x = blockIdx.x * blockDim.x + threadIdx.x;
         x < mesh_width;
         x += blockDim.x * gridDim.x)
    {
      int vi = y*mesh_width + x;
      float u, v, w;
      u = ww * (-0.5f + x*1.f/mesh_width);
      v = wh * (-0.5f + y*1.f/mesh_height);
      w = 0.0f;
      verts[vi].x = u;
      verts[vi].y = v;
      verts[vi].z = w;
      states[vi].x = 0.0f;
      states[vi].y = 0.0f;
      states[vi].z = 0.0f;
      /* color information is uploaded by host, no init here */
    }
  }
}

/*
 * calculate particle forces & new positions & colors
 */
__global__ void d_advance( float4* verts, float4* states,
                           float mx, float my,
                           int mesh_count,
                           float speed,
                           float delta)
{
  int vi;
  for (vi = blockIdx.x * blockDim.x + threadIdx.x;
       vi < mesh_count;
       vi += blockDim.x * gridDim.x)
  {
    // colors are stored after all vertices
    unsigned int ci = mesh_count + vi;

    float3 state  = {states[vi].x, states[vi].y, 0.f/*states[vi].z*/};
    // calculate vector between mouse and particle
    float3 dir_force = {verts[vi].x-mx, verts[vi].y-my, 0.f};
    /* steering:
     * the new particle state vector is given by current directional force
     * and the old state scaled by the particle mass
     */
    float flen = rsqrtf( dir_force.x*dir_force.x
                         +dir_force.y*dir_force.y
                         /*+dir_force.z*dir_force.z*/);
    dir_force.x *= flen;
    dir_force.y *= flen;
    /*dir_force.z *= flen;*/
    state.x += delta * dir_force.x;
    state.y += delta * dir_force.y;
    /*state.z += dir_force.z;*/

    // speed: base speed scale by particle mass
    float v = speed / states[vi].w;
    /* update particle position:
     * new_position = old_position - state_vector*speed;
     */
    float3 dv = {state.x * v, state.y * v, 0.f/*state.z * v*/};

    verts[vi].x -= delta * dv.x;
    verts[vi].y -= delta * dv.y;
    /*verts[vi].z -= delta * dv.z;*/
    // update colors depending on particles force
    float dx = 0.5f*dv.x;
    float dy = 0.5f*dv.y;
    verts[ci].x = 0.1f+fabs(dx);
    verts[ci].y = 0.1f+fabs(dy);
    verts[ci].z = 0.1f+fabs(dx+dy);
    states[vi].x = state.x;
    states[vi].y = state.y;
    /*states[vi].z = state.z;*/
  }
}

void kernel_reset(float4* verts, float4* states,
                  int ww, int wh,
                  int mesh_width, int mesh_height,
                  int numSMs)
{
  dim3 threads(16,16);
  dim3 blocks(16*numSMs);

  d_reset<<<blocks, threads>>>( verts, states,
                                ww, wh,
                                mesh_width, mesh_height );
}

void kernel_advance(float4* verts, float4* states,
                    float mx, float my,
                    int mesh_count,
                    float speed,
                    int numSMs,
                    double delta)
{
  dim3 threads(128);
  dim3 blocks( 16*numSMs );
    
  d_advance<<<blocks, threads>>>( verts, states,
                                  mx, my,
                                  mesh_count,
                                  speed,
                                  static_cast<float>(delta));
}

	.file	"tmpxft_0020c05b_00000000-6_lab03-flake_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii
	.type	_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii, @function
_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 4(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, (%rsp)
	leaq	48(%rsp), %rcx
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7d_resetP6float4S0_ffii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii, .-_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii
	.globl	_Z7d_resetP6float4S0_ffii
	.type	_Z7d_resetP6float4S0_ffii, @function
_Z7d_resetP6float4S0_ffii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii
	.cfi_endproc
.LFE2035:
	.size	_Z7d_resetP6float4S0_ffii, .-_Z7d_resetP6float4S0_ffii
	.globl	_Z12kernel_resetP6float4S0_iiiii
	.type	_Z12kernel_resetP6float4S0_iiiii, @function
_Z12kernel_resetP6float4S0_iiiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	movabsq	$68719476752, %rdx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r9d, %r14d
	xorl	%r9d, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	96(%rsp), %eax
	sall	$4, %eax
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	cvtsi2ssl	%r15d, %xmm0
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r14d, %ecx
	movl	%r13d, %edx
	cvtsi2ssl	%r12d, %xmm1
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__Z7d_resetP6float4S0_ffiiP6float4S0_ffii
.L8:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z12kernel_resetP6float4S0_iiiii, .-_Z12kernel_resetP6float4S0_iiiii
	.globl	_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff
	.type	_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff, @function
_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	56(%rsp), %rcx
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	48(%rsp), %rdx
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 16(%rsp)
	movss	%xmm3, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9d_advanceP6float4S0_ffiff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff, .-_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff
	.globl	_Z9d_advanceP6float4S0_ffiff
	.type	_Z9d_advanceP6float4S0_ffiff, @function
_Z9d_advanceP6float4S0_ffiff:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff
	.cfi_endproc
.LFE2037:
	.size	_Z9d_advanceP6float4S0_ffiff, .-_Z9d_advanceP6float4S0_ffiff
	.globl	_Z14kernel_advanceP6float4S0_ffifid
	.type	_Z14kernel_advanceP6float4S0_ffifid, @function
_Z14kernel_advanceP6float4S0_ffifid:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	sall	$4, %ecx
	movl	%edx, %r12d
	movl	$33554433, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	salq	$7, %rdx
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movl	%ecx, 52(%rsp)
	movl	$1, %ecx
	movq	%rax, 56(%rsp)
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 20(%rsp)
	movsd	%xmm3, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movsd	8(%rsp), %xmm3
	movss	20(%rsp), %xmm2
	testl	%eax, %eax
	movss	24(%rsp), %xmm1
	movss	28(%rsp), %xmm0
	jne	.L16
	addq	$64, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	cvtsd2ss	%xmm3, %xmm3
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z42__device_stub__Z9d_advanceP6float4S0_ffiffP6float4S0_ffiff
.L16:
	.cfi_restore_state
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z14kernel_advanceP6float4S0_ffifid, .-_Z14kernel_advanceP6float4S0_ffifid
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9d_advanceP6float4S0_ffiff"
.LC1:
	.string	"_Z7d_resetP6float4S0_ffii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9d_advanceP6float4S0_ffiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7d_resetP6float4S0_ffii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>


/* initialize grid
 * we'll distribute all particles evenly on the screen
 */
__global__ void d_reset( float4* verts, float4* states,
                         float ww, float wh,
                         int mesh_width, int mesh_height
  )
{
  int x, y;
  for (y = blockIdx.y * blockDim.y + threadIdx.y;
       y < mesh_height;
       y += blockDim.y * gridDim.y)
  {
    for (x = blockIdx.x * blockDim.x + threadIdx.x;
         x < mesh_width;
         x += blockDim.x * gridDim.x)
    {
      int vi = y*mesh_width + x;
      float u, v, w;
      u = ww * (-0.5f + x*1.f/mesh_width);
      v = wh * (-0.5f + y*1.f/mesh_height);
      w = 0.0f;
      verts[vi].x = u;
      verts[vi].y = v;
      verts[vi].z = w;
      states[vi].x = 0.0f;
      states[vi].y = 0.0f;
      states[vi].z = 0.0f;
      /* color information is uploaded by host, no init here */
    }
  }
}

/*
 * calculate particle forces & new positions & colors
 */
__global__ void d_advance( float4* verts, float4* states,
                           float mx, float my,
                           int mesh_count,
                           float speed,
                           float delta)
{
  int vi;
  for (vi = blockIdx.x * blockDim.x + threadIdx.x;
       vi < mesh_count;
       vi += blockDim.x * gridDim.x)
  {
    // colors are stored after all vertices
    unsigned int ci = mesh_count + vi;

    float3 state  = {states[vi].x, states[vi].y, 0.f/*states[vi].z*/};
    // calculate vector between mouse and particle
    float3 dir_force = {verts[vi].x-mx, verts[vi].y-my, 0.f};
    /* steering:
     * the new particle state vector is given by current directional force
     * and the old state scaled by the particle mass
     */
    float flen = rsqrtf( dir_force.x*dir_force.x
                         +dir_force.y*dir_force.y
                         /*+dir_force.z*dir_force.z*/);
    dir_force.x *= flen;
    dir_force.y *= flen;
    /*dir_force.z *= flen;*/
    state.x += delta * dir_force.x;
    state.y += delta * dir_force.y;
    /*state.z += dir_force.z;*/

    // speed: base speed scale by particle mass
    float v = speed / states[vi].w;
    /* update particle position:
     * new_position = old_position - state_vector*speed;
     */
    float3 dv = {state.x * v, state.y * v, 0.f/*state.z * v*/};

    verts[vi].x -= delta * dv.x;
    verts[vi].y -= delta * dv.y;
    /*verts[vi].z -= delta * dv.z;*/
    // update colors depending on particles force
    float dx = 0.5f*dv.x;
    float dy = 0.5f*dv.y;
    verts[ci].x = 0.1f+fabs(dx);
    verts[ci].y = 0.1f+fabs(dy);
    verts[ci].z = 0.1f+fabs(dx+dy);
    states[vi].x = state.x;
    states[vi].y = state.y;
    /*states[vi].z = state.z;*/
  }
}

void kernel_reset(float4* verts, float4* states,
                  int ww, int wh,
                  int mesh_width, int mesh_height,
                  int numSMs)
{
  dim3 threads(16,16);
  dim3 blocks(16*numSMs);

  d_reset<<<blocks, threads>>>( verts, states,
                                ww, wh,
                                mesh_width, mesh_height );
}

void kernel_advance(float4* verts, float4* states,
                    float mx, float my,
                    int mesh_count,
                    float speed,
                    int numSMs,
                    double delta)
{
  dim3 threads(128);
  dim3 blocks( 16*numSMs );
    
  d_advance<<<blocks, threads>>>( verts, states,
                                  mx, my,
                                  mesh_count,
                                  speed,
                                  static_cast<float>(delta));
}

	.text
	.file	"lab03-flake_kernel.hip"
	.globl	_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii # -- Begin function _Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.type	_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii,@function
_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii: # @_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	8(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	4(%rsp), %r9
	movl	%edx, (%r9)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%rdx, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii, .Lfunc_end0-_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff # -- Begin function _Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.type	_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff,@function
_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff: # @_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	28(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	24(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	20(%rsp), %r8
	movl	%edx, (%r8)
	leaq	16(%rsp), %rdx
	movss	%xmm2, (%rdx)
	leaq	12(%rsp), %r9
	movss	%xmm3, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%rdx, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff, .Lfunc_end1-_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.cfi_endproc
                                        # -- End function
	.globl	_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii # -- Begin function _Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii
	.type	_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii,@function
_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii: # @_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movl	%edx, %r13d
	movq	%rsi, %r14
	movq	%rdi, %r12
	movl	64(%rsp), %edi
	shll	$4, %edi
	btsq	$32, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 64
	cvtsi2ss	%r13d, %xmm0
	cvtsi2ss	%r15d, %xmm1
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii # TAILCALL
.Lfunc_end2:
	.size	_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii, .Lfunc_end2-_Z12kernel_resetP15HIP_vector_typeIfLj4EES1_iiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid # -- Begin function _Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid
	.type	_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid,@function
_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid: # @_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movsd	%xmm3, 24(%rsp)                 # 8-byte Spill
                                        # kill: def $ecx killed $ecx def $rcx
	movss	%xmm2, 20(%rsp)                 # 4-byte Spill
	movl	%edx, %ebx
	movss	%xmm1, 16(%rsp)                 # 4-byte Spill
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r15
	shll	$4, %ecx
	btsq	$32, %rcx
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movq	%rcx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	xorps	%xmm3, %xmm3
	cvtsd2ss	24(%rsp), %xmm3                 # 8-byte Folded Reload
	movq	%r15, %rdi
	movq	%r14, %rsi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movl	%ebx, %edx
	movss	20(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff # TAILCALL
.Lfunc_end3:
	.size	_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid, .Lfunc_end3-_Z14kernel_advanceP15HIP_vector_typeIfLj4EES1_ffifid
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii,@object # @_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.section	.rodata,"a",@progbits
	.globl	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.p2align	3, 0x0
_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii:
	.quad	_Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.size	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii, 8

	.type	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff,@object # @_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.globl	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.p2align	3, 0x0
_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff:
	.quad	_Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.size	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii"
	.size	.L__unnamed_1, 43

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff"
	.size	.L__unnamed_2, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.addrsig_sym _Z24__device_stub__d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.addrsig_sym _Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii ; -- Begin function _Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.globl	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
	.p2align	8
	.type	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii,@function
_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii: ; @_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s8, 16
	s_mov_b32 s8, exec_lo
	v_mad_u64_u32 v[3:4], null, s15, s12, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s7, v3
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph42
	s_clause 0x1
	s_load_b32 s13, s[2:3], 0xc
	s_load_b64 s[16:17], s[2:3], 0x0
	s_load_b128 s[8:11], s[0:1], 0x0
	v_and_b32_e32 v0, 0x3ff, v0
	v_mul_lo_u32 v7, s6, v3
	v_cvt_f32_i32_e32 v6, s7
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s13, 0xffff
	s_mul_i32 s2, s17, s12
	v_mad_u64_u32 v[4:5], null, s14, s1, v[0:1]
	v_cvt_f32_i32_e32 v5, s6
	s_mul_i32 s3, s16, s1
	s_mul_i32 s12, s2, s6
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s6, v4
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f32_i32_e32 v0, v3
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v6, v6, v0
	v_div_scale_f32 v10, vcc_lo, v0, v6, v0
	v_rcp_f32_e32 v8, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v1, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v9, v8
	v_mul_f32_e32 v9, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v1, v9, v10
	v_fmac_f32_e32 v9, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v9, v10
	v_div_fmas_f32 v1, v1, v8, v9
	v_mov_b32_e32 v8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v6, v0
	v_add_f32_e32 v0, -0.5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s5, v0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v0, v8
	v_add_nc_u32_e32 v12, v7, v8
	v_add_nc_u32_e32 v8, s3, v8
	v_mov_b32_e32 v10, v2
	v_div_scale_f32 v14, null, v5, v5, v0
	v_div_scale_f32 v16, vcc_lo, v0, v5, v0
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v15, v14
	v_cmp_le_i32_e64 s1, s6, v8
	v_lshlrev_b64 v[12:13], 4, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 s15, s1, s15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v9, v15
	v_mov_b32_e32 v9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v15
	v_fma_f32 v11, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v11, v15
	v_fma_f32 v14, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v14, v14, v15, v17
	v_div_fixup_f32 v0, v14, v5, v0
	v_add_co_u32 v14, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, -0.5, v0
	v_add_co_u32 v12, vcc_lo, s10, v12
	v_mov_b32_e32 v11, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
	v_mul_f32_e32 v0, s4, v0
	global_store_b96 v[14:15], v[0:2], off
	global_store_b96 v[12:13], v[9:11], off
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow61
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v3, s2, v3
	v_add_nc_u32_e32 v7, s12, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s7, v3
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
.LBB0_6:                                ; %._crit_edge43
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii, .Lfunc_end0-_Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 20
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff ; -- Begin function _Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.globl	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
	.p2align	8
	.type	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff,@function
_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff: ; @_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x10
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s8, 0xffff
	s_mov_b32 s8, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s3, s[2:3], 0x0
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x20
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s3, s12
	s_mov_b32 s3, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 4, v[1:2]
	v_add_co_u32 v7, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v5, vcc_lo
	global_load_b64 v[11:12], v[7:8], off
	s_clause 0x1
	global_load_b32 v0, v[9:10], off offset:12
	global_load_b64 v[13:14], v[9:10], off
	v_add_nc_u32_e32 v2, s6, v1
	v_add_nc_u32_e32 v1, s1, v1
	s_waitcnt vmcnt(2)
	v_subrev_f32_e32 v15, s5, v12
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v16, null, v0, v0, s7
	v_subrev_f32_e32 v6, s4, v11
	v_div_scale_f32 v17, vcc_lo, s7, v0, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v16
	v_mul_f32_e32 v4, v15, v15
	v_fmac_f32_e32 v4, v6, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v16, v18, 1.0
	v_mul_f32_e32 v5, 0x4b800000, v4
	v_cmp_gt_f32_e64 s0, 0x800000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v19, v18
	v_cndmask_b32_e64 v4, v4, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, v17, v18
	v_rsq_f32_e32 v19, v4
	v_lshlrev_b64 v[4:5], 4, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v16, v20, v17
	s_waitcnt_depctr 0xfff
	v_dual_fmac_f32 v20, v2, v18 :: v_dual_mul_f32 v21, 0x45800000, v19
	v_fma_f32 v16, -v16, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v19, v21, s0
	v_div_fmas_f32 v16, v16, v18, v20
	v_cmp_le_i32_e32 vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v0, v16, v0, s7
	v_mul_f32_e32 v15, v15, v2
	v_mul_f32_e32 v2, v6, v2
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, s2, v15
	v_fma_f32 v13, s2, v2, v13
	v_add_co_u32 v15, s0, s8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v16, s0, s9, v5, s0
	v_mul_f32_e32 v2, v0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, v0, v13
	v_mul_f32_e32 v6, 0.5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v4, 0.5, v0
	v_fma_f32 v11, -v0, s2, v11
	v_fma_f32 v12, -v2, s2, v12
	v_add_f32_e64 v5, 0x3dcccccd, |v6|
	v_fmac_f32_e32 v6, 0.5, v0
	v_add_f32_e64 v4, 0x3dcccccd, |v4|
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e64 v6, 0x3dcccccd, |v6|
	s_clause 0x1
	global_store_b64 v[7:8], v[11:12], off
	global_store_b96 v[15:16], v[4:6], off
	global_store_b64 v[9:10], v[13:14], off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff, .Lfunc_end1-_Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 564
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7d_resetP15HIP_vector_typeIfLj4EES1_ffii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9d_advanceP15HIP_vector_typeIfLj4EES1_ffiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
