// input: in_data (b,g,c), in_grid (b,n)
// output: out_data (b,n,c)
__global__ void grid_upsampling_gpu(int b,int n,int c,int g,const float * in_data,const int * in_grid,float * out_data){
    
    //int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    for (int index = blockIdx.x * blockDim.x + threadIdx.x; index < c*n; index += stride)
    {

        int index_channel = index / n;
        int index_point = index % n;

        for (int index_batch = 0; index_batch < b; index_batch++)
        {
            int index_grid = in_grid[index_batch*n + index_point]; // in_grid[b, n]
            int index_in_data = index_batch*g*c + index_grid*c + index_channel; // in_data[b,g,c]
            int index_out_data = index_batch*n*c + index_point*c + index_channel; // out_data[b,n,c]

            out_data[index_out_data] = in_data[index_in_data];
        }

    }
}

__global__ void grid_upsampling_grad_gpu(int b,int n,int c,int g,const int * in_grid,const float * grad_out,float * grad_in){
    
    //int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    for (int index = blockIdx.x * blockDim.x + threadIdx.x; index < b*c; index += stride)
    {
        int index_batch = index / c;
        int index_channel = index % c;

        /*for (int index_grid = 0; index_grid < g; index_grid++)
        {
            int index_grad_in = index_batch*g*c + index_grid*c + index_channel;
            grad_in[index_grad_in] = .0;
        }*/

        for (int index_point = 0; index_point < n; index_point++)
        {
            int index_grid = in_grid[index_batch*n + index_point]; // in_grid[b, n]
            int index_grad_out = index_batch*n*c + index_point*c + index_channel; // grad_out[b,n,c]
            int index_grad_in = index_batch*g*c + index_grid*c + index_channel; // grad_in[b,g,c]

            grad_in[index_grad_in] += 1 * grad_out[index_grad_out];
        }
    }
}

void gridupsamplingLauncher(int b,int n,int c,int g,const float * in_data,const int * in_grid,float * out_data){
    const int threads_per_block = 128;
    //const int number_of_blocks = (c*n + threads_per_block - 1)/threads_per_block;
    const int number_of_blocks = 8;

    cudaMemset(out_data,0,b*n*c*4);

    grid_upsampling_gpu<<<number_of_blocks, threads_per_block>>>(b,n,c,g,in_data,in_grid,out_data);
    //grid_upsampling_gpu<<<1, 1>>>(b,n,c,g,inp_data,grid_index,out);
    //cudaDeviceSynchronize();
}

void gridupsamplinggradLauncher(int b,int n,int c,int g,const int * in_grid,const float * grad_out,float * grad_in){
    const int threads_per_block = 128;
    //const int number_of_blocks = (b*c + threads_per_block - 1)/threads_per_block;
    const int number_of_blocks = 8;

    cudaMemset(grad_in,0,b*g*c*4);

    grid_upsampling_grad_gpu<<<number_of_blocks, threads_per_block>>>(b,n,c,g,in_grid,grad_out,grad_in);
    //grid_upsampling_grad_gpu<<<1, 1>>>(b,n,c,g,in_grid,grad_out,grad_in);
    //cudaDeviceSynchronize();
}

	.file	"tmpxft_002386e2_00000000-6_tf_grid_upsampling.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf
	.type	_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf, @function
_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19grid_upsampling_gpuiiiiPKfPKiPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf, .-_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf
	.globl	_Z19grid_upsampling_gpuiiiiPKfPKiPf
	.type	_Z19grid_upsampling_gpuiiiiPKfPKiPf, @function
_Z19grid_upsampling_gpuiiiiPKfPKiPf:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf
	.cfi_endproc
.LFE2035:
	.size	_Z19grid_upsampling_gpuiiiiPKfPKiPf, .-_Z19grid_upsampling_gpuiiiiPKfPKiPf
	.globl	_Z22gridupsamplingLauncheriiiiPKfPKiPf
	.type	_Z22gridupsamplingLauncheriiiiPKfPKiPf, @function
_Z22gridupsamplingLauncheriiiiPKfPKiPf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	movl	%edi, %edx
	imull	%esi, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	imull	%r15d, %edx
	movl	%esi, %ebp
	xorl	%esi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	sall	$2, %edx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movslq	%edx, %rdx
	movq	112(%rsp), %r12
	movl	%ecx, 12(%rsp)
	movq	%r12, %rdi
	call	cudaMemset@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870913, %edi
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	movq	%r12, 112(%rsp)
	movl	12(%rsp), %ecx
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r14, %r9
	movq	%r13, %r8
	movl	%r15d, %edx
	movl	%ebp, %esi
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z49__device_stub__Z19grid_upsampling_gpuiiiiPKfPKiPfiiiiPKfPKiPf
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z22gridupsamplingLauncheriiiiPKfPKiPf, .-_Z22gridupsamplingLauncheriiiiPKfPKiPf
	.globl	_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf
	.type	_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf, @function
_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf, .-_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf
	.globl	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.type	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, @function
_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf
	.cfi_endproc
.LFE2037:
	.size	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, .-_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.globl	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf
	.type	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf, @function
_Z26gridupsamplinggradLauncheriiiiPKiPKfPf:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	movl	%edi, %edx
	imull	%ecx, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	imull	%ebp, %edx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	112(%rsp), %r12
	movl	%esi, 12(%rsp)
	xorl	%esi, %esi
	sall	$2, %edx
	movq	%r12, %rdi
	movslq	%edx, %rdx
	call	cudaMemset@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870913, %edi
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	%r12, 112(%rsp)
	movl	12(%rsp), %esi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r14, %r9
	movq	%r13, %r8
	movl	%r15d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z54__device_stub__Z24grid_upsampling_grad_gpuiiiiPKiPKfPfiiiiPKiPKfPf
.L16:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf, .-_Z26gridupsamplinggradLauncheriiiiPKiPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf"
.LC1:
	.string	"_Z19grid_upsampling_gpuiiiiPKfPKiPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19grid_upsampling_gpuiiiiPKfPKiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// input: in_data (b,g,c), in_grid (b,n)
// output: out_data (b,n,c)
__global__ void grid_upsampling_gpu(int b,int n,int c,int g,const float * in_data,const int * in_grid,float * out_data){
    
    //int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    for (int index = blockIdx.x * blockDim.x + threadIdx.x; index < c*n; index += stride)
    {

        int index_channel = index / n;
        int index_point = index % n;

        for (int index_batch = 0; index_batch < b; index_batch++)
        {
            int index_grid = in_grid[index_batch*n + index_point]; // in_grid[b, n]
            int index_in_data = index_batch*g*c + index_grid*c + index_channel; // in_data[b,g,c]
            int index_out_data = index_batch*n*c + index_point*c + index_channel; // out_data[b,n,c]

            out_data[index_out_data] = in_data[index_in_data];
        }

    }
}

__global__ void grid_upsampling_grad_gpu(int b,int n,int c,int g,const int * in_grid,const float * grad_out,float * grad_in){
    
    //int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    for (int index = blockIdx.x * blockDim.x + threadIdx.x; index < b*c; index += stride)
    {
        int index_batch = index / c;
        int index_channel = index % c;

        /*for (int index_grid = 0; index_grid < g; index_grid++)
        {
            int index_grad_in = index_batch*g*c + index_grid*c + index_channel;
            grad_in[index_grad_in] = .0;
        }*/

        for (int index_point = 0; index_point < n; index_point++)
        {
            int index_grid = in_grid[index_batch*n + index_point]; // in_grid[b, n]
            int index_grad_out = index_batch*n*c + index_point*c + index_channel; // grad_out[b,n,c]
            int index_grad_in = index_batch*g*c + index_grid*c + index_channel; // grad_in[b,g,c]

            grad_in[index_grad_in] += 1 * grad_out[index_grad_out];
        }
    }
}

void gridupsamplingLauncher(int b,int n,int c,int g,const float * in_data,const int * in_grid,float * out_data){
    const int threads_per_block = 128;
    //const int number_of_blocks = (c*n + threads_per_block - 1)/threads_per_block;
    const int number_of_blocks = 8;

    hipMemset(out_data,0,b*n*c*4);

    grid_upsampling_gpu<<<number_of_blocks, threads_per_block>>>(b,n,c,g,in_data,in_grid,out_data);
    //grid_upsampling_gpu<<<1, 1>>>(b,n,c,g,inp_data,grid_index,out);
    //cudaDeviceSynchronize();
}

void gridupsamplinggradLauncher(int b,int n,int c,int g,const int * in_grid,const float * grad_out,float * grad_in){
    const int threads_per_block = 128;
    //const int number_of_blocks = (b*c + threads_per_block - 1)/threads_per_block;
    const int number_of_blocks = 8;

    hipMemset(grad_in,0,b*g*c*4);

    grid_upsampling_grad_gpu<<<number_of_blocks, threads_per_block>>>(b,n,c,g,in_grid,grad_out,grad_in);
    //grid_upsampling_grad_gpu<<<1, 1>>>(b,n,c,g,in_grid,grad_out,grad_in);
    //cudaDeviceSynchronize();
}

	.text
	.file	"tf_grid_upsampling.hip"
	.globl	_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf # -- Begin function _Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf
	.type	_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf,@function
_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf: # @_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19grid_upsampling_gpuiiiiPKfPKiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf, .Lfunc_end0-_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf # -- Begin function _Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf
	.type	_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf,@function
_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf: # @_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf, .Lfunc_end1-_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z22gridupsamplingLauncheriiiiPKfPKiPf # -- Begin function _Z22gridupsamplingLauncheriiiiPKfPKiPf
	.type	_Z22gridupsamplingLauncheriiiiPKfPKiPf,@function
_Z22gridupsamplingLauncheriiiiPKfPKiPf: # @_Z22gridupsamplingLauncheriiiiPKfPKiPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movq	64(%rsp), %rdi
	movl	%r13d, %eax
	imull	%esi, %eax
	imull	%edx, %eax
	shll	$2, %eax
	movslq	%eax, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movabsq	$4294967304, %rdi               # imm = 0x100000008
	leaq	120(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf # TAILCALL
.Lfunc_end2:
	.size	_Z22gridupsamplingLauncheriiiiPKfPKiPf, .Lfunc_end2-_Z22gridupsamplingLauncheriiiiPKfPKiPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf # -- Begin function _Z26gridupsamplinggradLauncheriiiiPKiPKfPf
	.type	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf,@function
_Z26gridupsamplinggradLauncheriiiiPKiPKfPf: # @_Z26gridupsamplinggradLauncheriiiiPKiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movq	64(%rsp), %rdi
	movl	%r13d, %eax
	imull	%edx, %eax
	imull	%ecx, %eax
	shll	$2, %eax
	movslq	%eax, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movabsq	$4294967304, %rdi               # imm = 0x100000008
	leaq	120(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf # TAILCALL
.Lfunc_end3:
	.size	_Z26gridupsamplinggradLauncheriiiiPKiPKfPf, .Lfunc_end3-_Z26gridupsamplinggradLauncheriiiiPKiPKfPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19grid_upsampling_gpuiiiiPKfPKiPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19grid_upsampling_gpuiiiiPKfPKiPf,@object # @_Z19grid_upsampling_gpuiiiiPKfPKiPf
	.section	.rodata,"a",@progbits
	.globl	_Z19grid_upsampling_gpuiiiiPKfPKiPf
	.p2align	3, 0x0
_Z19grid_upsampling_gpuiiiiPKfPKiPf:
	.quad	_Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf
	.size	_Z19grid_upsampling_gpuiiiiPKfPKiPf, 8

	.type	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf,@object # @_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.globl	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.p2align	3, 0x0
_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf:
	.quad	_Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf
	.size	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19grid_upsampling_gpuiiiiPKfPKiPf"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf"
	.size	.L__unnamed_2, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__grid_upsampling_gpuiiiiPKfPKiPf
	.addrsig_sym _Z39__device_stub__grid_upsampling_grad_gpuiiiiPKiPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19grid_upsampling_gpuiiiiPKfPKiPf
	.addrsig_sym _Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19grid_upsampling_gpuiiiiPKfPKiPf ; -- Begin function _Z19grid_upsampling_gpuiiiiPKfPKiPf
	.globl	_Z19grid_upsampling_gpuiiiiPKfPKiPf
	.p2align	8
	.type	_Z19grid_upsampling_gpuiiiiPKfPKiPf,@function
_Z19grid_upsampling_gpuiiiiPKfPKiPf:    ; @_Z19grid_upsampling_gpuiiiiPKfPKiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s8, 0xffff
	s_mul_i32 s12, s6, s5
	v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph38
	s_cmp_gt_i32 s4, 0
	s_load_b32 s2, s[2:3], 0x0
	s_cselect_b32 s13, -1, 0
	s_ashr_i32 s14, s5, 31
	s_mov_b32 s3, 0
	s_add_i32 s8, s5, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s15, s8, s14
	v_cvt_f32_u32_e32 v0, s15
	s_sub_i32 s8, 0, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s8, v0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v0, v2
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB0_5
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v0, 31, v1
	s_mov_b32 s16, 0
	s_mov_b32 s17, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v1, v0
	v_xor_b32_e32 v7, s14, v0
	v_xor_b32_e32 v2, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v6
	v_mul_lo_u32 v4, v3, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s15, v2
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v0, v7
	v_sub_nc_u32_e32 v0, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v0, s5
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s6, v2, v[3:4]
	v_sub_nc_u32_e32 v4, v4, v7
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s17, s17, -1
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s5, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, s16, v3
	s_add_i32 s16, s16, s7
	s_cmp_eq_u32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, s6, v[0:1]
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s12, v4
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v3, off
	s_cbranch_scc0 .LBB0_4
.LBB0_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s12, v1
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_6:                                ; %Flow69
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19grid_upsampling_gpuiiiiPKfPKiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19grid_upsampling_gpuiiiiPKfPKiPf, .Lfunc_end0-_Z19grid_upsampling_gpuiiiiPKfPKiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 548
; NumSgprs: 20
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf ; -- Begin function _Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.globl	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
	.p2align	8
	.type	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf,@function
_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf: ; @_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s8, 0xffff
	s_mul_i32 s4, s6, s4
	v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.lr.ph39
	s_cmp_gt_i32 s5, 0
	s_load_b32 s2, s[2:3], 0x0
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s13, s6, 31
	s_add_i32 s15, s5, -1
	s_add_i32 s8, s6, s13
	s_mul_i32 s15, s6, s15
	s_xor_b32 s14, s8, s13
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	v_cvt_f32_u32_e32 v0, s14
	s_sub_i32 s3, 0, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s3, v0
	s_mov_b32 s3, 0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v0, v2
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v0, 31, v1
	s_mov_b32 s16, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v0
	v_xor_b32_e32 v2, v2, v0
	v_xor_b32_e32 v0, s13, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v6
	v_mul_lo_u32 v4, v3, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s14, v2
	v_cmp_le_u32_e32 vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s14, v2
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v0
	v_sub_nc_u32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v2, v0, s5
	v_mul_lo_u32 v8, v0, s6
	v_mul_lo_u32 v7, v0, s7
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, v0, v[1:2]
	v_sub_nc_u32_e32 v0, v1, v8
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v3, v[4:5], off
	s_add_i32 s16, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s16, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v3, v7
	v_mad_u64_u32 v[8:9], null, v3, s6, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v3, v[10:11], off
	global_load_b32 v10, v[8:9], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v10
	global_store_b32 v[8:9], v3, off
	s_cbranch_scc0 .LBB1_4
.LBB1_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_6:                                ; %Flow68
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf, .Lfunc_end1-_Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 19
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19grid_upsampling_gpuiiiiPKfPKiPf
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z19grid_upsampling_gpuiiiiPKfPKiPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
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        .value_kind:     by_value
      - .offset:         12
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        .value_kind:     by_value
      - .address_space:  global
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        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
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        .value_kind:     hidden_block_count_x
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        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_remainder_y
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    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
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    .name:           _Z24grid_upsampling_grad_gpuiiiiPKiPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z24grid_upsampling_grad_gpuiiiiPKiPKfPf.kd
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    .vgpr_spill_count: 0
    .wavefront_size: 32
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
