
/* This is a automatically generated test. Do not modify */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.1195E-36f - +1.9660E-43f * fmodf((+1.8591E-42f / var_4), +1.6926E36f))) {
  for (int i=0; i < var_1; ++i) {
    float tmp_1 = +1.5888E-16f;
float tmp_2 = -1.4103E-42f / log10f(ceilf(var_5 + var_6));
comp = tmp_2 - tmp_1 / var_7 * +1.8376E35f;
for (int i=0; i < var_2; ++i) {
  var_8[i] = +0.0f;
comp = var_8[i] * (+1.0901E-35f + var_9);
}
for (int i=0; i < var_3; ++i) {
  float tmp_3 = (var_10 * +1.8910E-43f * (var_11 - var_12));
comp += tmp_3 - -1.0091E-37f / var_13;
}
}
}
   printf("%.17g\n", comp);

}

float* initPointer(float v) {
  float *ret = (float*) malloc(sizeof(float)*10);
  for(int i=0; i < 10; ++i)
    ret[i] = v;
  return ret;
}

int main(int argc, char** argv) {
/* Program variables */

  float tmp_1 = atof(argv[1]);
  int tmp_2 = atoi(argv[2]);
  int tmp_3 = atoi(argv[3]);
  int tmp_4 = atoi(argv[4]);
  float tmp_5 = atof(argv[5]);
  float tmp_6 = atof(argv[6]);
  float tmp_7 = atof(argv[7]);
  float tmp_8 = atof(argv[8]);
  float* tmp_9 = initPointer( atof(argv[9]) );
  float tmp_10 = atof(argv[10]);
  float tmp_11 = atof(argv[11]);
  float tmp_12 = atof(argv[12]);
  float tmp_13 = atof(argv[13]);
  float tmp_14 = atof(argv[14]);

  compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
  cudaDeviceSynchronize();

  return 0;
}

	.file	"tmpxft_003ae344_00000000-6_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11initPointerf
	.type	_Z11initPointerf, @function
_Z11initPointerf:
.LFB2027:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$40, %edi
	movss	%xmm0, 12(%rsp)
	call	malloc@PLT
	movss	12(%rsp), %xmm0
	xorl	%edx, %edx
.L3:
	movss	%xmm0, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.L3
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11initPointerf, .-_Z11initPointerf
	.globl	_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff
	.type	_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff, @function
_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movl	%edi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movss	%xmm0, 60(%rsp)
	movss	%xmm1, 44(%rsp)
	movss	%xmm2, 40(%rsp)
	movss	%xmm3, 36(%rsp)
	movss	%xmm4, 32(%rsp)
	movss	%xmm5, 20(%rsp)
	movss	%xmm6, 16(%rsp)
	movss	%xmm7, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z7computefiiiffffPffffff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L7:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff, .-_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff
	.globl	_Z7computefiiiffffPffffff
	.type	_Z7computefiiiffffPffffff, @function
_Z7computefiiiffffPffffff:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff
	.cfi_endproc
.LFE2054:
	.size	_Z7computefiiiffffPffffff, .-_Z7computefiiiffffPffffff
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rsi, %rbx
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	movq	8(%rsi), %rdi
	call	atof@PLT
	movq	16(%rbx), %rdi
	movsd	%xmm0, 72(%rsp)
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	32(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movq	40(%rbx), %rdi
	movl	%eax, %r13d
	call	atof@PLT
	movq	48(%rbx), %rdi
	movsd	%xmm0, 64(%rsp)
	call	atof@PLT
	movq	56(%rbx), %rdi
	movsd	%xmm0, 56(%rsp)
	call	atof@PLT
	movq	64(%rbx), %rdi
	movsd	%xmm0, 48(%rsp)
	call	atof@PLT
	movq	72(%rbx), %rdi
	movsd	%xmm0, 40(%rsp)
	call	atof@PLT
	cvtsd2ss	%xmm0, %xmm0
	call	_Z11initPointerf
	movq	80(%rbx), %rdi
	movq	%rax, %r14
	call	atof@PLT
	movq	88(%rbx), %rdi
	movsd	%xmm0, 32(%rsp)
	call	atof@PLT
	movq	96(%rbx), %rdi
	movsd	%xmm0, 24(%rsp)
	call	atof@PLT
	movq	104(%rbx), %rdi
	movsd	%xmm0, 16(%rsp)
	call	atof@PLT
	movq	112(%rbx), %rdi
	movsd	%xmm0, 8(%rsp)
	call	atof@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movsd	%xmm0, (%rsp)
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	movsd	(%rsp), %xmm0
	movsd	8(%rsp), %xmm8
	testl	%eax, %eax
	movsd	16(%rsp), %xmm7
	movsd	24(%rsp), %xmm6
	movsd	32(%rsp), %xmm5
	movsd	40(%rsp), %xmm4
	movsd	48(%rsp), %xmm3
	movsd	56(%rsp), %xmm2
	movsd	64(%rsp), %xmm1
	movsd	72(%rsp), %xmm9
	jne	.L13
	pushq	%rax
	.cfi_def_cfa_offset 168
	movq	%r14, %rcx
	movl	%r13d, %edx
	cvtsd2ss	%xmm0, %xmm0
	pushq	%rax
	.cfi_def_cfa_offset 176
	cvtsd2ss	%xmm9, %xmm9
	movl	%r12d, %esi
	movl	%ebp, %edi
	cvtsd2ss	%xmm7, %xmm7
	cvtsd2ss	%xmm6, %xmm6
	cvtsd2ss	%xmm5, %xmm5
	cvtsd2ss	%xmm4, %xmm4
	cvtsd2ss	%xmm8, %xmm8
	cvtsd2ss	%xmm3, %xmm3
	cvtsd2ss	%xmm2, %xmm2
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm0, 8(%rsp)
	movaps	%xmm9, %xmm0
	movss	%xmm8, (%rsp)
	call	_Z39__device_stub__Z7computefiiiffffPfffffffiiiffffPffffff
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
.L13:
	call	cudaDeviceSynchronize@PLT
	addq	$112, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7computefiiiffffPffffff"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7computefiiiffffPffffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


/* This is a automatically generated test. Do not modify */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.1195E-36f - +1.9660E-43f * fmodf((+1.8591E-42f / var_4), +1.6926E36f))) {
  for (int i=0; i < var_1; ++i) {
    float tmp_1 = +1.5888E-16f;
float tmp_2 = -1.4103E-42f / log10f(ceilf(var_5 + var_6));
comp = tmp_2 - tmp_1 / var_7 * +1.8376E35f;
for (int i=0; i < var_2; ++i) {
  var_8[i] = +0.0f;
comp = var_8[i] * (+1.0901E-35f + var_9);
}
for (int i=0; i < var_3; ++i) {
  float tmp_3 = (var_10 * +1.8910E-43f * (var_11 - var_12));
comp += tmp_3 - -1.0091E-37f / var_13;
}
}
}
   printf("%.17g\n", comp);

}

float* initPointer(float v) {
  float *ret = (float*) malloc(sizeof(float)*10);
  for(int i=0; i < 10; ++i)
    ret[i] = v;
  return ret;
}

int main(int argc, char** argv) {
/* Program variables */

  float tmp_1 = atof(argv[1]);
  int tmp_2 = atoi(argv[2]);
  int tmp_3 = atoi(argv[3]);
  int tmp_4 = atoi(argv[4]);
  float tmp_5 = atof(argv[5]);
  float tmp_6 = atof(argv[6]);
  float tmp_7 = atof(argv[7]);
  float tmp_8 = atof(argv[8]);
  float* tmp_9 = initPointer( atof(argv[9]) );
  float tmp_10 = atof(argv[10]);
  float tmp_11 = atof(argv[11]);
  float tmp_12 = atof(argv[12]);
  float tmp_13 = atof(argv[13]);
  float tmp_14 = atof(argv[14]);

  compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
  hipDeviceSynchronize();

  return 0;
}

	.text
	.file	"test.hip"
	.globl	_Z22__device_stub__computefiiiffffPffffff # -- Begin function _Z22__device_stub__computefiiiffffPffffff
	.type	_Z22__device_stub__computefiiiffffPffffff,@function
_Z22__device_stub__computefiiiffffPffffff: # @_Z22__device_stub__computefiiiffffPffffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	52(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	48(%rsp), %r8
	movl	%edi, (%r8)
	leaq	44(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	36(%rsp), %rdx
	movss	%xmm1, (%rdx)
	leaq	32(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	28(%rsp), %r10
	movss	%xmm3, (%r10)
	leaq	24(%rsp), %r11
	movss	%xmm4, (%r11)
	leaq	72(%rsp), %r14
	movq	%rcx, (%r14)
	leaq	20(%rsp), %rcx
	movss	%xmm5, (%rcx)
	leaq	16(%rsp), %r15
	movss	%xmm6, (%r15)
	leaq	12(%rsp), %r12
	movss	%xmm7, (%r12)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%r9, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%rcx, 72(%rbx)
	movq	%r15, 80(%rbx)
	movq	%r12, 88(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	64(%rsp), %r12
	leaq	56(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7computefiiiffffPffffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__computefiiiffffPffffff, .Lfunc_end0-_Z22__device_stub__computefiiiffffPffffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z11initPointerf                # -- Begin function _Z11initPointerf
	.type	_Z11initPointerf,@function
_Z11initPointerf:                       # @_Z11initPointerf
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	xorl	%ecx, %ecx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%rax,%rcx,4)
	incq	%rcx
	cmpq	$10, %rcx
	jne	.LBB1_1
# %bb.2:
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z11initPointerf, .Lfunc_end1-_Z11initPointerf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r15
	movq	8(%rsi), %rdi
	callq	atof
	movsd	%xmm0, 88(%rsp)                 # 8-byte Spill
	movq	16(%r15), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	24(%r15), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	32(%r15), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	40(%r15), %rdi
	callq	atof
	movsd	%xmm0, 80(%rsp)                 # 8-byte Spill
	movq	48(%r15), %rdi
	callq	atof
	movsd	%xmm0, 72(%rsp)                 # 8-byte Spill
	movq	56(%r15), %rdi
	callq	atof
	movsd	%xmm0, 64(%rsp)                 # 8-byte Spill
	movq	64(%r15), %rdi
	callq	atof
	movsd	%xmm0, 56(%rsp)                 # 8-byte Spill
	movq	72(%r15), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 16(%rsp)                 # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %r12
	xorl	%eax, %eax
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_1
# %bb.2:                                # %_Z11initPointerf.exit
	movq	80(%r15), %rdi
	callq	atof
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movq	88(%r15), %rdi
	callq	atof
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movq	96(%r15), %rdi
	callq	atof
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	movq	104(%r15), %rdi
	callq	atof
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	movq	112(%r15), %rdi
	callq	atof
	movsd	%xmm0, 24(%rsp)                 # 8-byte Spill
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	cvtsd2ss	24(%rsp), %xmm8                 # 8-byte Folded Reload
	cvtsd2ss	32(%rsp), %xmm9                 # 8-byte Folded Reload
	cvtsd2ss	40(%rsp), %xmm7                 # 8-byte Folded Reload
	cvtsd2ss	48(%rsp), %xmm6                 # 8-byte Folded Reload
	cvtsd2ss	16(%rsp), %xmm5                 # 8-byte Folded Reload
	cvtsd2ss	56(%rsp), %xmm4                 # 8-byte Folded Reload
	cvtsd2ss	64(%rsp), %xmm3                 # 8-byte Folded Reload
	cvtsd2ss	72(%rsp), %xmm2                 # 8-byte Folded Reload
	cvtsd2ss	80(%rsp), %xmm1                 # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsd2ss	88(%rsp), %xmm0                 # 8-byte Folded Reload
	movss	%xmm8, 8(%rsp)
	movss	%xmm9, (%rsp)
	movl	%ebx, %edi
	movl	%ebp, %esi
	movl	%r14d, %edx
	movq	%r12, %rcx
	callq	_Z22__device_stub__computefiiiffffPffffff
.LBB2_4:
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	addq	$96, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7computefiiiffffPffffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7computefiiiffffPffffff,@object # @_Z7computefiiiffffPffffff
	.section	.rodata,"a",@progbits
	.globl	_Z7computefiiiffffPffffff
	.p2align	3, 0x0
_Z7computefiiiffffPffffff:
	.quad	_Z22__device_stub__computefiiiffffPffffff
	.size	_Z7computefiiiffffPffffff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7computefiiiffffPffffff"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__computefiiiffffPffffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7computefiiiffffPffffff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7computefiiiffffPffffff ; -- Begin function _Z7computefiiiffffPffffff
	.globl	_Z7computefiiiffffPffffff
	.p2align	8
	.type	_Z7computefiiiffffPffffff,@function
_Z7computefiiiffffPffffff:              ; @_Z7computefiiiffffPffffff
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_movk_i32 s2, 0x52f
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v0, null, s8, s8, 0x52f
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v0, v1, 1.0
	v_fmac_f32_e32 v1, v2, v1
	v_div_scale_f32 v2, vcc_lo, s2, s8, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v2, v1
	v_fma_f32 v4, -v0, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v1
	v_fma_f32 v0, -v0, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v0, v0, v1, v3
	v_div_fixup_f32 v0, v0, s8, 0x52f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e64 s2, 0x7ba2fdd0, |v0|
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_2
; %bb.1:
	v_bfi_b32 v1, 0x7fffffff, 0, v0
	v_cmp_eq_f32_e64 vcc_lo, 0x7ba2fdd0, |v0|
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v0, v1, vcc_lo
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr1
.LBB0_3:                                ; %Flow438
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_8
; %bb.4:
	v_frexp_exp_i32_f32_e32 v1, v0
	v_frexp_mant_f32_e64 v2, |v0|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v1
	v_ldexp_f32 v1, v2, 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_addk_i32 s2, 0xff87
	s_cmp_lt_i32 s2, 13
	s_cbranch_scc1 .LBB0_7
; %bb.5:
	v_mov_b32_e32 v2, 0x3fa2fdd0
.LBB0_6:                                ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x3f490a8d, v1
	s_mov_b32 s3, s2
	s_add_i32 s2, s2, -12
	s_cmp_gt_u32 s3, 24
	v_rndne_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0xbfa2fdd0, v3
	v_cmp_gt_f32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e32 v3, 0x80000000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v3
	v_ldexp_f32 v1, v1, 12
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %.loopexit.i.i
	s_add_i32 s2, s2, -11
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v1, v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3f490a8d, v1
	v_rndne_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v1, v2, 0xbfa2fdd0, v1
	v_mov_b32_e32 v2, 0x3fa2fdd0
	v_cmp_gt_f32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0x80000000, v2, vcc_lo
	v_dual_add_f32 v1, v1, v2 :: v_dual_and_b32 v2, 0x80000000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v1, v1, 0x78
	v_xor_b32_e32 v1, v2, v1
.LBB0_8:                                ; %_ZL5fmodfff.exit
	s_mov_b32 s2, 0x8000008c
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmaak_f32 v1, s2, v1, 0x3be791a
	s_cmp_lt_i32 s5, 1
	v_mov_b32_e32 v31, s4
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_neq_f32_e32 vcc_lo, s4, v0
	s_or_b32 s2, vcc_lo, s2
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_16
; %bb.9:                                ; %.lr.ph68
	v_add_f32_e64 v0, s9, s10
	s_mov_b32 s2, 0xa5372d19
	s_load_b32 s4, s[0:1], 0x38
	v_div_scale_f32 v8, s2, s2, s11, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_ceil_f32_e32 v0, v0
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x20
	s_mov_b32 s3, 0x2095a01
	s_cmp_gt_i32 s6, 0
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v2, 0, 0x411a209b, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, v0, v1
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v5, null, s4, s4, 0x2095a01
	v_log_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v7, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x3e9a209a, v0
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_fma_f32 v1, 0x3e9a209a, v0, -v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v0, 0x3284fbcf, v1
	v_fmac_f32_e32 v1, 0x3e9a209a, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_div_scale_f32 v1, null, s11, s11, 0xa5372d19
	v_sub_f32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v1
	v_div_scale_f32 v4, null, v2, v2, 0x800003ee
	v_div_scale_f32 v10, vcc_lo, 0x800003ee, v2, 0x800003ee
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v0, -v1, v3, 1.0
	v_fmac_f32_e32 v3, v0, v3
	v_fma_f32 v0, -v5, v7, 1.0
	v_fma_f32 v9, -v4, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v7, v0, v7 :: v_dual_fmac_f32 v6, v9, v6
	v_div_scale_f32 v9, s3, s3, s4, s3
	v_mul_f32_e32 v11, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v4, v11, v10
	v_dual_fmac_f32 v11, v0, v6 :: v_dual_mov_b32 v0, 0
	v_mul_f32_e32 v12, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v1, v12, v8
	v_fmac_f32_e32 v12, v14, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v4, -v4, v11, v10
	v_add_f32_e64 v14, 0x567d6b0, s12
	v_fma_f32 v1, -v1, v12, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v4, v4, v6, v11
	s_mov_b32 vcc_lo, s2
	v_sub_f32_e64 v6, s14, s15
	v_div_fmas_f32 v1, v1, v3, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v4, v2, 0x800003ee
	v_dual_mul_f32 v2, 0, v14 :: v_dual_mul_f32 v13, v9, v7
	s_mov_b32 vcc_lo, s3
	v_fma_f32 v15, -v5, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v7
	v_fma_f32 v5, -v5, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v5, v7, v13
	v_mul_f32_e64 v5, 0x87, s13
	v_div_fixup_f32 v7, v1, s11, 0xa5372d19
	s_mov_b32 s11, 0
	v_div_fixup_f32 v1, v3, s4, 0x2095a01
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v3, v7, 0x7a0d9045, v4
	s_cmp_gt_i32 s7, 0
	v_fmac_f32_e32 v1, v5, v6
	s_cselect_b32 s10, -1, 0
.LBB0_10:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v31, v3
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_mov_b64 s[2:3], s[8:9]
	s_mov_b32 s12, s6
	s_cbranch_vccnz .LBB0_12
.LBB0_11:                               ; %.lr.ph
                                        ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s12, s12, -1
	v_mov_b32_e32 v31, v2
	global_store_b32 v0, v0, s[2:3]
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc0 .LBB0_11
.LBB0_12:                               ; %.preheader46
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_15
; %bb.13:                               ; %.lr.ph66.preheader
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_mov_b32 s2, s7
.LBB0_14:                               ; %.lr.ph66
                                        ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v31, v1, v31
	s_add_i32 s2, s2, -1
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc0 .LBB0_14
.LBB0_15:                               ; %Flow429
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, s5
	s_cbranch_scc0 .LBB0_10
.LBB0_16:                               ; %.loopexit
	s_load_b64 s[2:3], s[0:1], 0x90
	v_mbcnt_lo_u32_b32 v28, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v28
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_22
; %bb.17:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB0_21
; %bb.18:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_19:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_19
; %bb.20:                               ; %Flow425
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_21:                               ; %Flow427
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_22:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_32
; %bb.25:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB0_28
; %bb.26:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_27:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_27
.LBB0_28:                               ; %Flow423
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_30
; %bb.29:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_30:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_32
; %bb.31:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_32:                               ; %Flow424
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_33:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_35:                               ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_37
; %bb.36:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_38
.LBB0_37:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s1, -1
.LBB0_38:                               ; %Flow418
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_33
; %bb.39:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_43
; %bb.40:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_43
; %bb.41:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_42:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_42
.LBB0_43:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_129
; %bb.44:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v32, 2, v0
	v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v7, 1
	v_and_b32_e32 v2, -3, v0
	v_mov_b32_e32 v6, 2
	s_mov_b64 s[6:7], 7
.LBB0_45:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_48 Depth 2
                                        ;     Child Loop BB0_55 Depth 2
                                        ;     Child Loop BB0_63 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
                                        ;     Child Loop BB0_79 Depth 2
                                        ;     Child Loop BB0_87 Depth 2
                                        ;     Child Loop BB0_95 Depth 2
                                        ;     Child Loop BB0_103 Depth 2
                                        ;     Child Loop BB0_111 Depth 2
                                        ;     Child Loop BB0_117 Depth 2
                                        ;     Child Loop BB0_126 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_50
; %bb.46:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_49
; %bb.47:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB0_48:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB0_48
.LBB0_49:                               ; %Flow394
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB0_50:                               ; %Flow396
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[10:11], v30, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_52:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_55:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow389
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr14
.LBB0_58:                               ; %Flow391
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[12:13], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_60:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_63:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow384
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_66:                               ; %Flow386
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[14:15], v30, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_68:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_71:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow379
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr14
.LBB0_74:                               ; %Flow381
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[16:17], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_76:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_79:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow374
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_82:                               ; %Flow376
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[18:19], v30, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_84:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_89
; %bb.85:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_88
; %bb.86:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_87:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB0_87
.LBB0_88:                               ; %Flow369
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_90
.LBB0_89:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr14
.LBB0_90:                               ; %Flow371
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[20:21], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_92:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_97
; %bb.93:                               ;   in Loop: Header=BB0_45 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_96
; %bb.94:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB0_95:                               ; %.preheader.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB0_95
.LBB0_96:                               ; %Flow364
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB0_98
.LBB0_97:                               ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s10, -1
.LBB0_98:                               ; %Flow366
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[22:23], v30, s[0:1]
.LBB0_100:                              ; %.loopexit.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v29, v28 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v29
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_106
; %bb.101:                              ;   in Loop: Header=BB0_45 Depth=1
	global_load_b64 v[26:27], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	global_load_b64 v[8:9], v30, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB0_105
; %bb.102:                              ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s11, 0
.LBB0_103:                              ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[2:3] offset:40
	global_load_b64 v[24:25], v30, s[2:3]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_103
; %bb.104:                              ; %Flow359
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_105:                              ; %Flow361
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_106:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[2:3] offset:40
	global_load_b128 v[24:27], v30, s[2:3]
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_45 Depth=1
	v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, v30
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s16, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_108:                              ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v32
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s12
	v_add_co_ci_u32_e32 v27, vcc_lo, s13, v27, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_116
; %bb.109:                              ;   in Loop: Header=BB0_45 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v30, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v2
	v_readfirstlane_b32 s17, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v8, vcc_lo, v24, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v25, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v30, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB0_112
; %bb.110:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s16, 0
.LBB0_111:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_111
.LBB0_112:                              ; %Flow357
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[2:3], v30, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v4, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_45 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[29:30], off offset:8
.LBB0_114:                              ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_116
; %bb.115:                              ;   in Loop: Header=BB0_45 Depth=1
	global_load_b32 v29, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[29:30], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_116:                              ; %Flow358
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v24, s15
	v_add_co_ci_u32_e32 v3, vcc_lo, s14, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_117:                              ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_119
; %bb.118:                              ;   in Loop: Header=BB0_117 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB0_119:                              ;   in Loop: Header=BB0_117 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_121
; %bb.120:                              ;   in Loop: Header=BB0_117 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_122
.LBB0_121:                              ;   in Loop: Header=BB0_117 Depth=2
	s_mov_b32 s1, -1
.LBB0_122:                              ; %Flow352
                                        ;   in Loop: Header=BB0_117 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_117
; %bb.123:                              ;   in Loop: Header=BB0_45 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_127
; %bb.124:                              ;   in Loop: Header=BB0_45 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	global_load_b64 v[12:13], v30, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v30, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_mov_b32 s0, 0
.LBB0_126:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_45 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v30, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_45 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB0_45
; %bb.128:                              ; %Flow397
	s_mov_b32 s0, 0
	s_branch .LBB0_130
.LBB0_129:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_130:                              ; %Flow412
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_159
; %bb.131:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v28
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_137
; %bb.132:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_136
; %bb.133:                              ; %.preheader3.i.i.i38.preheader
	s_mov_b32 s5, 0
.LBB0_134:                              ; %.preheader3.i.i.i38
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_134
; %bb.135:                              ; %Flow409
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_136:                              ; %Flow411
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_137:                              ; %.loopexit4.i.i.i33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_139
; %bb.138:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_139:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_147
; %bb.140:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_143
; %bb.141:                              ; %.preheader1.i.i.i36.preheader
	s_mov_b32 s10, 0
.LBB0_142:                              ; %.preheader1.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_142
.LBB0_143:                              ; %Flow407
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_145
; %bb.144:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_145:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_147
; %bb.146:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_147:                              ; %Flow408
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_148:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_150
; %bb.149:                              ;   in Loop: Header=BB0_148 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_150:                              ;   in Loop: Header=BB0_148 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_152
; %bb.151:                              ;   in Loop: Header=BB0_148 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_153
.LBB0_152:                              ;   in Loop: Header=BB0_148 Depth=1
	s_mov_b32 s1, -1
.LBB0_153:                              ; %Flow402
                                        ;   in Loop: Header=BB0_148 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_148
; %bb.154:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_158
; %bb.155:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_158
; %bb.156:                              ; %.preheader.i.i.i35.preheader
	s_mov_b32 s0, 0
.LBB0_157:                              ; %.preheader.i.i.i35
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_157
.LBB0_158:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_159:                              ; %__ockl_printf_append_string_n.exit
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v28
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v28
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_165
; %bb.160:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[7:8], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[2:3] offset:40
	global_load_b64 v[5:6], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v9, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v9, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[7:8]
	s_cbranch_execz .LBB0_164
; %bb.161:                              ; %.preheader3.i.i.i45.preheader
	s_mov_b32 s5, 0
.LBB0_162:                              ; %.preheader3.i.i.i45
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[9:10], v4, s[2:3]
	v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[1:2]
	v_mov_b32_e32 v1, v5
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[7:8]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_162
; %bb.163:                              ; %Flow345
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_164:                              ; %Flow347
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_165:                              ; %.loopexit4.i.i.i39
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v29, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[4:5], v29, s[2:3] offset:40
	global_load_b128 v[6:9], v29, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v4
	v_readfirstlane_b32 s7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_167
; %bb.166:
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, v29
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB0_167:
	s_or_b32 exec_lo, exec_lo, s11
	v_cvt_f64_f32_e32 v[4:5], v31
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v2, 0xffffff1d, v2, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[2:5], off
	global_store_b128 v[0:1], v[8:11], off offset:16
	global_store_b128 v[0:1], v[8:11], off offset:32
	global_store_b128 v[0:1], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_175
; %bb.168:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v4, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_171
; %bb.169:                              ; %.preheader1.i.i.i43.preheader
	s_mov_b32 s10, 0
.LBB0_170:                              ; %.preheader1.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_170
.LBB0_171:                              ; %Flow343
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_173
; %bb.172:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_173:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_175
; %bb.174:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_175:                              ; %Flow344
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_176:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_178
; %bb.177:                              ;   in Loop: Header=BB0_176 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_178:                              ;   in Loop: Header=BB0_176 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_180
; %bb.179:                              ;   in Loop: Header=BB0_176 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_181
.LBB0_180:                              ;   in Loop: Header=BB0_176 Depth=1
	s_mov_b32 s1, -1
.LBB0_181:                              ; %Flow338
                                        ;   in Loop: Header=BB0_176 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_176
; %bb.182:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_186
; %bb.183:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_186
; %bb.184:                              ; %.preheader.i.i.i42.preheader
	s_mov_b32 s0, 0
.LBB0_185:                              ; %.preheader.i.i.i42
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_185
.LBB0_186:                              ; %__ockl_printf_append_args.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7computefiiiffffPffffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7computefiiiffffPffffff, .Lfunc_end0-_Z7computefiiiffffPffffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7816
; NumSgprs: 20
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%.17g\n"
	.size	.str, 7

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7computefiiiffffPffffff
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7computefiiiffffPffffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
