#include <iostream>
#include <sys/time.h>
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#define t1 4096
#define t2 4096
#define N 1
#define ITERATIONS 10
#define BLOCK_SIZE 32
using namespace std;
float A[N * N], B[N * N], C[N * N], C_cmp[N * N];

__global__ void split(float *C11, float *C12, float *C21, float *C22, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C11[i * n + j] = C[i * 2 * n + j];
		C12[i * n + j] = C[i * 2 * n + j + n];
		C21[i * n + j] = C[(i + n) * 2 * n + j];
		C22[i * n + j] = C[(i + n) * 2 * n + j + n];
	}
}

__global__ void merge(float *C11, float *C12, float *C21, float *C22, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * 2 * n + j] = C11[i * n + j];
		C[i * 2 * n + j + n] = C12[i * n + j];
		C[(i + n) *2 * n + j] = C21[i * n + j];
		C[(i + n) * 2 * n + j + n] = C22[i * n + j];
	}
}

__global__ void add(float *A, float *B, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = A[i * n + j] + B[i * n + j];
	}
}

__global__ void sub(float *A, float *B, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = A[i * n + j] - B[i * n + j];
	}
}

__global__ void mul(float *A, float *B, float *C, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
	}
}

__global__ void mul_add(float *A, float *B, float *T, float *C, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = T[i * n + j];
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
	}
}

__global__ void mul_sub_inc(float *A, float *B, float *T, float *C1, float *C2, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C1[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C1[i * n + j] += A[i * n + k] * B[k * n + j];
		}
		C1[i * n + j] = T[i * n + j] - C1[i * n + j];
		C2[i * n + j] += T[i * n + j];
	}
}

__global__ void mul_inc_inc_inc(float *A, float *B, float *C, float *T, float *C1, float *C2, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
		C1[i * n + j] += C[i * n + j];
		C2[i * n + j] += C1[i * n + j];
		C1[i * n + j] += T[i * n + j];
	}
}

void strassen(float *A, float *B, float *C, int n) {
	float *A_gpu, *B_gpu, *C_gpu;
	dim3 block(BLOCK_SIZE, BLOCK_SIZE);
	cudaMalloc((void **)&A_gpu, sizeof(float) * n * n);
	cudaMalloc((void **)&B_gpu, sizeof(float) * n * n);
	cudaMalloc((void **)&C_gpu, sizeof(float) * n * n);
	cudaMemcpy(A_gpu, A, sizeof(float) * n * n, cudaMemcpyHostToDevice);
	cudaMemcpy(B_gpu, B, sizeof(float) * n * n, cudaMemcpyHostToDevice);
	if(n <= t1) {
		dim3 grid((size_t)ceil((float)n / (float)block.x), (size_t)ceil((float)n / (float)block.y));
		mul<<<grid, block>>>(A_gpu, B_gpu, C_gpu, n);
		cudaThreadSynchronize();
	}
	else{
		int m = n >> 1;
		dim3 grid((size_t)ceil((float)m / (float)block.x), (size_t)ceil((float)m / (float)block.y));
		float *A11, *A12, *A21, *A22, *B11, *B12, *B21, *B22, *C11, *C12, *C21, *C22, *T1, *T2;
		cudaMalloc((void **)&A11, sizeof(float) * m * m);
		cudaMalloc((void **)&A12, sizeof(float) * m * m);
		cudaMalloc((void **)&A21, sizeof(float) * m * m);
		cudaMalloc((void **)&A22, sizeof(float) * m * m);
		cudaMalloc((void **)&B11, sizeof(float) * m * m);
		cudaMalloc((void **)&B12, sizeof(float) * m * m);
		cudaMalloc((void **)&B21, sizeof(float) * m * m);
		cudaMalloc((void **)&B22, sizeof(float) * m * m);
		cudaMalloc((void **)&C11, sizeof(float) * m * m);
		cudaMalloc((void **)&C12, sizeof(float) * m * m);
		cudaMalloc((void **)&C21, sizeof(float) * m * m);
		cudaMalloc((void **)&C22, sizeof(float) * m * m);
		cudaMalloc((void **)&T1, sizeof(float) * m * m);
		cudaMalloc((void **)&T2, sizeof(float) * m * m);
		if(n <= t2) {
			split<<<grid, block>>>(A11, A12, A21, A22, A_gpu, m);
			cudaThreadSynchronize();
			split<<<grid, block>>>(B11, B12, B21, B22, B_gpu, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(A11, A21, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B22, B12, T2, m);
			cudaThreadSynchronize();
			mul<<<grid, block>>>(T1, T2, C21, m);
			cudaThreadSynchronize();
			add<<<grid, block>>>(A21, A22, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B12, B11, T2, m);
			cudaThreadSynchronize();
			mul<<<grid, block>>>(T1, T2, C22, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(T1, A11, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B22, T2, T2, m);
			cudaThreadSynchronize();
			mul<<<grid, block>>>(T1, T2, C11, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(A12, T1, T1, m);
			cudaThreadSynchronize();
			mul_add<<<grid, block>>>(T1, B22, C22, C12, m);
			cudaThreadSynchronize();
			mul_inc_inc_inc<<<grid, block>>>(A11, B11, T1, C21, C11, C12, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(T2, B21, T2, m);
			cudaThreadSynchronize();
			mul_sub_inc<<<grid, block>>>(A22, T2, C11, C21, C22, m);
			cudaThreadSynchronize();
			mul_add<<<grid, block>>>(A12, B21, T1, C11, m);
			cudaThreadSynchronize();
			merge<<<grid, block>>>(C11, C12, C21, C22, C_gpu, m);	
			cudaThreadSynchronize();
		}
		else{
			split<<<grid, block>>>(A11, A12, A21, A22, A_gpu, m);
			cudaThreadSynchronize();
			split<<<grid, block>>>(B11, B12, B21, B22, B_gpu, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(A11, A21, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B22, B12, T2, m);
			cudaThreadSynchronize();
			strassen(T1, T2, C21, m);
			add<<<grid, block>>>(A21, A22, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B12, B11, T2, m);
			cudaThreadSynchronize();
			strassen(T1, T2, C22, m);
			sub<<<grid, block>>>(T1, A11, T1, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(B22, T2, T2, m);
			cudaThreadSynchronize();
			strassen(T1, T2, C11, m);
			sub<<<grid, block>>>(A12, T1, T1, m);
			cudaThreadSynchronize();
			strassen(T1, B22, C12, m);
			add<<<grid, block>>>(C12, C22, C12, m);
			cudaThreadSynchronize();
			strassen(A11, B11, T1, m);
			add<<<grid, block>>>(C11, C12, C12, m);
			cudaThreadSynchronize();
			add<<<grid, block>>>(C12, T1, C12, m);
			cudaThreadSynchronize();
			add<<<grid, block>>>(C11, C21, C11, m);
			cudaThreadSynchronize();
			add<<<grid, block>>>(C11, T1, C11, m);
			cudaThreadSynchronize();
			sub<<<grid, block>>>(T2, B21, T2, m);
			cudaThreadSynchronize();
			strassen(A22, T2, C21, m);
			sub<<<grid, block>>>(C11, C21, C21, m);
			cudaThreadSynchronize();
			add<<<grid, block>>>(C11, C22, C22, m);
			cudaThreadSynchronize();
			strassen(A12, B21, C11, m);
			add<<<grid, block>>>(C11, T1, C11, m);
			cudaThreadSynchronize();
			merge<<<grid, block>>>(C11, C12, C21, C22, C_gpu, m);	
			cudaThreadSynchronize();
		}
		cudaFree(A11); 
		cudaFree(A12); 
		cudaFree(A21); 
		cudaFree(A22); 
		cudaFree(B11); 
		cudaFree(B12); 
		cudaFree(B21); 
		cudaFree(B22); 
		cudaFree(T1);
		cudaFree(T2);	
	} 
	cudaMemcpy(C, C_gpu, sizeof(float) * n * n, cudaMemcpyDeviceToHost);
	cudaFree(A_gpu);
	cudaFree(B_gpu);
	cudaFree(C_gpu);
}

void compare(float *res1, float *res2, int n) {
	int fail = 0;
	for(int i = 0; i < n; i++) {
		float a, b;
		a = res1[i] < 0 ? -res1[i] : res1[i];
		b = res2[i] < 0 ? -res2[i] : res2[i];
		if(a < 0.01 && b < 0.01) {
			continue;
		}
		if(i<10) {
			printf("i = %d\t%lf\t%lf\n", i, a, b);
		}
		float diff = (a - b) / (a + 0.000001);
		if(diff < 0) {
			diff= -diff;
		}
		if(diff>0.0005) {
			fail++;
		}
	}
	printf("Number of errors: %d\n", fail);
}

double timestamp(){
	struct timeval tv;
	gettimeofday(&tv, 0);
	return tv.tv_sec + 1e-6 * tv.tv_usec;
}

int main() {
	for(int i = 0; i < N; i++) {
		for(int j = 0; j < N; j++) {
			A[i * N + j] = (float)rand() / (float)RAND_MAX;
			B[i * N + j] = (float)rand() / (float)RAND_MAX;
			C[i * N + j] = 0;
			C_cmp[i * N + j] = 0;
		}
	}

	for(int j = 0; j < N; j++) {
		for(int i = 0; i < N; i++) {
			for(int k = 0; k < N; k++) {
				C_cmp[i * N + j] += A[i * N + k] * B[k * N + j];
			}
		}
	}
	strassen(A, B, C, N);
	compare(C, C_cmp, N * N);

	double time1 = timestamp();
	for(int numOfTimes = 0; numOfTimes < ITERATIONS; numOfTimes++) {
		strassen(A, B, C, N);
	}
	double time2 = timestamp();

	double time = (time2 - time1) / ITERATIONS;
	double flops = 2.0 * N * N * N;
	double gflopsPerSecond = flops / 1000000000 /time;
	double GB = 4.0 * N * N / 1000000000;
	double GBpS = 4.0 * N * N / 1000000000 / time;
	printf("GFLOPS/s = %lf\n", gflopsPerSecond);
	printf("GB/s = %lf\n", GBpS);
	printf("GFLOPS = %lf\n", flops / 1000000000);
	printf("GB = %lf\n", GB);
	printf("time(s) = %lf\n", time);
	return 0;
}

	.file	"tmpxft_00203686_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"i = %d\t%lf\t%lf\n"
.LC6:
	.string	"Number of errors: %d\n"
	.text
	.globl	_Z7comparePfS_i
	.type	_Z7comparePfS_i, @function
_Z7comparePfS_i:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	movss	.LC1(%rip), %xmm4
.L3:
	cmpl	%ebx, %ebp
	jle	.L23
	movss	0(%r13,%rbx,4), %xmm2
	xorps	%xmm0, %xmm0
	comiss	%xmm2, %xmm0
	jbe	.L4
	xorps	%xmm4, %xmm2
.L4:
	movss	(%r14,%rbx,4), %xmm3
	xorps	%xmm0, %xmm0
	comiss	%xmm3, %xmm0
	jbe	.L6
	xorps	.LC1(%rip), %xmm3
.L6:
	movsd	.LC2(%rip), %xmm5
	cvtss2sd	%xmm2, %xmm0
	comisd	%xmm0, %xmm5
	jbe	.L8
	cvtss2sd	%xmm3, %xmm1
	comisd	%xmm1, %xmm5
	ja	.L15
.L8:
	cmpq	$9, %rbx
	ja	.L11
	movl	%ebx, %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$2, %al
	movss	%xmm2, 12(%rsp)
	cvtss2sd	%xmm3, %xmm1
	movss	%xmm3, 8(%rsp)
	movsd	%xmm0, (%rsp)
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm2
	movss	8(%rsp), %xmm3
	movss	.LC1(%rip), %xmm4
	movsd	(%rsp), %xmm0
.L11:
	addsd	.LC4(%rip), %xmm0
	subss	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	divsd	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm2, %xmm2
	comiss	%xmm2, %xmm0
	jbe	.L12
	xorps	.LC1(%rip), %xmm2
.L12:
	cvtss2sd	%xmm2, %xmm2
	comisd	.LC5(%rip), %xmm2
	jbe	.L15
	incl	%r12d
.L15:
	incq	%rbx
	jmp	.L3
.L23:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	movl	%r12d, %edx
	leaq	.LC6(%rip), %rsi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z7comparePfS_i, .-_Z7comparePfS_i
	.globl	_Z9timestampv
	.type	_Z9timestampv, @function
_Z9timestampv:
.LFB3637:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	xorl	%esi, %esi
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	cvtsi2sdq	16(%rsp), %xmm0
	mulsd	.LC4(%rip), %xmm0
	cvtsi2sdq	8(%rsp), %xmm1
	addsd	%xmm1, %xmm0
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z9timestampv, .-_Z9timestampv
	.globl	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i
	.type	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i, @function
_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z5splitPfS_S_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L27:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i, .-_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i
	.globl	_Z5splitPfS_S_S_S_i
	.type	_Z5splitPfS_S_S_S_i, @function
_Z5splitPfS_S_S_S_i:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i
	.cfi_endproc
.LFE3664:
	.size	_Z5splitPfS_S_S_S_i, .-_Z5splitPfS_S_S_S_i
	.globl	_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i
	.type	_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i, @function
_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z5mergePfS_S_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L32:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i, .-_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i
	.globl	_Z5mergePfS_S_S_S_i
	.type	_Z5mergePfS_S_S_S_i, @function
_Z5mergePfS_S_S_S_i:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i
	.cfi_endproc
.LFE3666:
	.size	_Z5mergePfS_S_S_S_i, .-_Z5mergePfS_S_S_S_i
	.globl	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
	.type	_Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3addPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L37:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
	.globl	_Z3addPfS_S_i
	.type	_Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3668:
	.size	_Z3addPfS_S_i, .-_Z3addPfS_S_i
	.globl	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
	.type	_Z27__device_stub__Z3subPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3subPfS_S_iPfS_S_i:
.LFB3669:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3subPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L42:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3669:
	.size	_Z27__device_stub__Z3subPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3subPfS_S_iPfS_S_i
	.globl	_Z3subPfS_S_i
	.type	_Z3subPfS_S_i, @function
_Z3subPfS_S_i:
.LFB3670:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3670:
	.size	_Z3subPfS_S_i, .-_Z3subPfS_S_i
	.globl	_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
	.type	_Z27__device_stub__Z3mulPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3mulPfS_S_iPfS_S_i:
.LFB3671:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3mulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L47:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3671:
	.size	_Z27__device_stub__Z3mulPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
	.globl	_Z3mulPfS_S_i
	.type	_Z3mulPfS_S_i, @function
_Z3mulPfS_S_i:
.LFB3672:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3672:
	.size	_Z3mulPfS_S_i, .-_Z3mulPfS_S_i
	.globl	_Z8strassenPfS_S_i
	.type	_Z8strassenPfS_S_i, @function
_Z8strassenPfS_S_i:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movslq	%ecx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%r12, %rbx
	imulq	%r12, %r12
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	salq	$2, %r12
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, 152(%rsp)
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cmpl	$4096, %ebx
	movss	.LC7(%rip), %xmm1
	jg	.L53
	cvtsi2ssl	%ebx, %xmm0
	mulss	%xmm1, %xmm0
	call	ceilf@PLT
	comiss	.LC8(%rip), %xmm0
	jnb	.L54
	cvttss2siq	%xmm0, %rax
	jmp	.L55
.L54:
	subss	.LC8(%rip), %xmm0
	cvttss2siq	%xmm0, %rax
	btcq	$63, %rax
.L55:
	movl	%eax, 156(%rsp)
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 160(%rsp)
	movl	$1, %esi
	movq	156(%rsp), %rdi
	movabsq	$137438953504, %rdx
	movl	$1, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebx, %ecx
	movq	8(%rsp), %rdi
	call	_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
.L56:
	call	cudaThreadSynchronize@PLT
	jmp	.L57
.L53:
	sarl	%ebx
	cvtsi2ssl	%ebx, %xmm0
	mulss	%xmm1, %xmm0
	call	ceilf@PLT
	comiss	.LC8(%rip), %xmm0
	jnb	.L58
	cvttss2siq	%xmm0, %rax
	jmp	.L59
.L58:
	subss	.LC8(%rip), %xmm0
	cvttss2siq	%xmm0, %rax
	btcq	$63, %rax
.L59:
	movslq	%ebx, %rbp
	leaq	32(%rsp), %rdi
	movl	%eax, 156(%rsp)
	imulq	%rbp, %rbp
	movl	%eax, 160(%rsp)
	movl	$1, 164(%rsp)
	salq	$2, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	96(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	112(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	120(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	136(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	movabsq	$137438953504, %rdx
	movq	%rdx, 144(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	movq	8(%rsp), %r8
	movq	56(%rsp), %rcx
	movl	%ebx, %r9d
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i
.L60:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	movq	16(%rsp), %r8
	movq	88(%rsp), %rcx
	movl	%ebx, %r9d
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z33__device_stub__Z5splitPfS_S_S_S_iPfS_S_S_S_i
.L61:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	128(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebx, %ecx
	movq	32(%rsp), %rdi
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L62:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	movq	136(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	%ebx, %ecx
	movq	88(%rsp), %rdi
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L63:
	call	cudaThreadSynchronize@PLT
	movq	112(%rsp), %rdx
	movq	136(%rsp), %rsi
	movl	%ebx, %ecx
	movq	128(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	movq	128(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	%ebx, %ecx
	movq	48(%rsp), %rdi
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L64:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	movq	136(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %ecx
	movq	72(%rsp), %rdi
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L65:
	call	cudaThreadSynchronize@PLT
	movq	120(%rsp), %rdx
	movq	136(%rsp), %rsi
	movl	%ebx, %ecx
	movq	128(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	movq	128(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L66:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movq	136(%rsp), %rsi
	movq	88(%rsp), %rdi
	movl	%ebx, %ecx
	movq	%rsi, %rdx
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L67:
	call	cudaThreadSynchronize@PLT
	movq	96(%rsp), %rdx
	movq	136(%rsp), %rsi
	movl	%ebx, %ecx
	movq	128(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movq	128(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	%ebx, %ecx
	movq	%rsi, %rdx
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L68:
	call	cudaThreadSynchronize@PLT
	movq	104(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	%ebx, %ecx
	movq	128(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	movq	104(%rsp), %rdi
	movq	120(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L69:
	call	cudaThreadSynchronize@PLT
	movq	128(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %ecx
	movq	32(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdi
	movl	%ebx, %ecx
	movq	%rsi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L70:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	movq	104(%rsp), %rdi
	movq	128(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L71:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	movq	96(%rsp), %rdi
	movq	112(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L72:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movq	96(%rsp), %rdi
	movq	128(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L73:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	movq	136(%rsp), %rdi
	movq	80(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L74:
	call	cudaThreadSynchronize@PLT
	movq	112(%rsp), %rdx
	movq	56(%rsp), %rdi
	movl	%ebx, %ecx
	movq	136(%rsp), %rsi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L75
	movq	112(%rsp), %rsi
	movq	96(%rsp), %rdi
	movl	%ebx, %ecx
	movq	%rsi, %rdx
	call	_Z27__device_stub__Z3subPfS_S_iPfS_S_i
.L75:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movq	120(%rsp), %rsi
	movq	96(%rsp), %rdi
	movl	%ebx, %ecx
	movq	%rsi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L76:
	call	cudaThreadSynchronize@PLT
	movq	96(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	%ebx, %ecx
	movq	40(%rsp), %rdi
	call	_Z8strassenPfS_S_i
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L77
	movq	96(%rsp), %rdi
	movq	128(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rdi, %rdx
	call	_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.L77:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movq	24(%rsp), %r8
	movq	120(%rsp), %rcx
	movl	%ebx, %r9d
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdi
	call	_Z33__device_stub__Z5mergePfS_S_S_S_iPfS_S_S_S_i
.L78:
	call	cudaThreadSynchronize@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
.L57:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L79
	call	__stack_chk_fail@PLT
.L79:
	addq	$176, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z8strassenPfS_S_i, .-_Z8strassenPfS_S_i
	.section	.rodata.str1.1
.LC13:
	.string	"GFLOPS/s = %lf\n"
.LC14:
	.string	"GB/s = %lf\n"
.LC15:
	.string	"GFLOPS = %lf\n"
.LC16:
	.string	"GB = %lf\n"
.LC17:
	.string	"time(s) = %lf\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	B(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	A(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	leaq	C(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	$10, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC9(%rip), %xmm0
	movss	%xmm0, A(%rip)
	call	rand@PLT
	xorps	%xmm1, %xmm1
	movl	$1, %ecx
	movq	%rbp, %rdx
	cvtsi2ssl	%eax, %xmm0
	movq	%r13, %rsi
	movq	%r12, %rdi
	movl	$0x00000000, C(%rip)
	mulss	.LC9(%rip), %xmm0
	movss	%xmm0, B(%rip)
	mulss	A(%rip), %xmm0
	addss	%xmm1, %xmm0
	movss	%xmm0, C_cmp(%rip)
	call	_Z8strassenPfS_S_i
	movl	$1, %edx
	leaq	C_cmp(%rip), %rsi
	movq	%rbp, %rdi
	call	_Z7comparePfS_i
	call	_Z9timestampv
	movsd	%xmm0, 8(%rsp)
.L82:
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_Z8strassenPfS_S_i
	decl	%ebx
	jne	.L82
	call	_Z9timestampv
	movsd	.LC11(%rip), %xmm2
	leaq	.LC13(%rip), %rsi
	movb	$1, %al
	movaps	%xmm0, %xmm1
	movsd	.LC12(%rip), %xmm0
	subsd	8(%rsp), %xmm1
	divsd	.LC10(%rip), %xmm1
	divsd	%xmm1, %xmm2
	movl	$2, %edi
	movsd	%xmm1, 8(%rsp)
	divsd	%xmm1, %xmm0
	movq	%xmm2, %rbx
	call	__printf_chk@PLT
	movq	%rbx, %xmm0
	leaq	.LC14(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC12(%rip), %xmm0
	leaq	.LC15(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC11(%rip), %xmm0
	leaq	.LC16(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	8(%rsp), %xmm1
	leaq	.LC17(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	movaps	%xmm1, %xmm0
	call	__printf_chk@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.text
	.globl	_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i
	.type	_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i, @function
_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i:
.LFB3673:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7mul_addPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L85:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L87
	call	__stack_chk_fail@PLT
.L87:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3673:
	.size	_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i, .-_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i
	.globl	_Z7mul_addPfS_S_S_i
	.type	_Z7mul_addPfS_S_S_i, @function
_Z7mul_addPfS_S_S_i:
.LFB3674:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7mul_addPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE3674:
	.size	_Z7mul_addPfS_S_S_i, .-_Z7mul_addPfS_S_S_i
	.globl	_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i
	.type	_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i, @function
_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i:
.LFB3675:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11mul_sub_incPfS_S_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L90:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i, .-_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i
	.globl	_Z11mul_sub_incPfS_S_S_S_i
	.type	_Z11mul_sub_incPfS_S_S_S_i, @function
_Z11mul_sub_incPfS_S_S_S_i:
.LFB3676:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11mul_sub_incPfS_S_S_S_iPfS_S_S_S_i
	.cfi_endproc
.LFE3676:
	.size	_Z11mul_sub_incPfS_S_S_S_i, .-_Z11mul_sub_incPfS_S_S_S_i
	.globl	_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i
	.type	_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i, @function
_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i:
.LFB3677:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L95
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15mul_inc_inc_incPfS_S_S_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L95:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L97
	call	__stack_chk_fail@PLT
.L97:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i, .-_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i
	.globl	_Z15mul_inc_inc_incPfS_S_S_S_S_i
	.type	_Z15mul_inc_inc_incPfS_S_S_S_S_i, @function
_Z15mul_inc_inc_incPfS_S_S_S_S_i:
.LFB3678:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15mul_inc_inc_incPfS_S_S_S_S_iPfS_S_S_S_S_i
	.cfi_endproc
.LFE3678:
	.size	_Z15mul_inc_inc_incPfS_S_S_S_S_i, .-_Z15mul_inc_inc_incPfS_S_S_S_S_i
	.section	.rodata.str1.1
.LC18:
	.string	"_Z15mul_inc_inc_incPfS_S_S_S_S_i"
.LC19:
	.string	"_Z11mul_sub_incPfS_S_S_S_i"
.LC20:
	.string	"_Z7mul_addPfS_S_S_i"
.LC21:
	.string	"_Z3mulPfS_S_i"
.LC22:
	.string	"_Z3subPfS_S_i"
.LC23:
	.string	"_Z3addPfS_S_i"
.LC24:
	.string	"_Z5mergePfS_S_S_S_i"
.LC25:
	.string	"_Z5splitPfS_S_S_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3680:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15mul_inc_inc_incPfS_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11mul_sub_incPfS_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7mul_addPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3mulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3subPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z3addPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5mergePfS_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5splitPfS_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3680:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	C_cmp
	.bss
	.align 4
	.type	C_cmp, @object
	.size	C_cmp, 4
C_cmp:
	.zero	4
	.globl	C
	.align 4
	.type	C, @object
	.size	C, 4
C:
	.zero	4
	.globl	B
	.align 4
	.type	B, @object
	.size	B, 4
B:
	.zero	4
	.globl	A
	.align 4
	.type	A, @object
	.size	A, 4
A:
	.zero	4
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	1202590843
	.long	1065646817
	.align 8
.LC4:
	.long	-1598689907
	.long	1051772663
	.align 8
.LC5:
	.long	-755914244
	.long	1061184077
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC7:
	.long	1023410176
	.align 4
.LC8:
	.long	1593835520
	.align 4
.LC9:
	.long	805306368
	.section	.rodata.cst8
	.align 8
.LC10:
	.long	0
	.long	1076101120
	.align 8
.LC11:
	.long	-400107883
	.long	1043410443
	.align 8
.LC12:
	.long	-400107883
	.long	1042361867
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <sys/time.h>
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define t1 4096
#define t2 4096
#define N 1
#define ITERATIONS 10
#define BLOCK_SIZE 32
using namespace std;
float A[N * N], B[N * N], C[N * N], C_cmp[N * N];

__global__ void split(float *C11, float *C12, float *C21, float *C22, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C11[i * n + j] = C[i * 2 * n + j];
		C12[i * n + j] = C[i * 2 * n + j + n];
		C21[i * n + j] = C[(i + n) * 2 * n + j];
		C22[i * n + j] = C[(i + n) * 2 * n + j + n];
	}
}

__global__ void merge(float *C11, float *C12, float *C21, float *C22, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * 2 * n + j] = C11[i * n + j];
		C[i * 2 * n + j + n] = C12[i * n + j];
		C[(i + n) *2 * n + j] = C21[i * n + j];
		C[(i + n) * 2 * n + j + n] = C22[i * n + j];
	}
}

__global__ void add(float *A, float *B, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = A[i * n + j] + B[i * n + j];
	}
}

__global__ void sub(float *A, float *B, float *C, int n) {
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = A[i * n + j] - B[i * n + j];
	}
}

__global__ void mul(float *A, float *B, float *C, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
	}
}

__global__ void mul_add(float *A, float *B, float *T, float *C, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = T[i * n + j];
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
	}
}

__global__ void mul_sub_inc(float *A, float *B, float *T, float *C1, float *C2, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C1[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C1[i * n + j] += A[i * n + k] * B[k * n + j];
		}
		C1[i * n + j] = T[i * n + j] - C1[i * n + j];
		C2[i * n + j] += T[i * n + j];
	}
}

__global__ void mul_inc_inc_inc(float *A, float *B, float *C, float *T, float *C1, float *C2, int n) {
	int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
	if(i < n && j < n) {
		C[i * n + j] = 0;
		for(int k = 0; k < n; k++) {
			C[i * n + j] += A[i * n + k] * B[k * n + j];
		}
		C1[i * n + j] += C[i * n + j];
		C2[i * n + j] += C1[i * n + j];
		C1[i * n + j] += T[i * n + j];
	}
}

void strassen(float *A, float *B, float *C, int n) {
	float *A_gpu, *B_gpu, *C_gpu;
	dim3 block(BLOCK_SIZE, BLOCK_SIZE);
	hipMalloc((void **)&A_gpu, sizeof(float) * n * n);
	hipMalloc((void **)&B_gpu, sizeof(float) * n * n);
	hipMalloc((void **)&C_gpu, sizeof(float) * n * n);
	hipMemcpy(A_gpu, A, sizeof(float) * n * n, hipMemcpyHostToDevice);
	hipMemcpy(B_gpu, B, sizeof(float) * n * n, hipMemcpyHostToDevice);
	if(n <= t1) {
		dim3 grid((size_t)ceil((float)n / (float)block.x), (size_t)ceil((float)n / (float)block.y));
		mul<<<grid, block>>>(A_gpu, B_gpu, C_gpu, n);
		hipDeviceSynchronize();
	}
	else{
		int m = n >> 1;
		dim3 grid((size_t)ceil((float)m / (float)block.x), (size_t)ceil((float)m / (float)block.y));
		float *A11, *A12, *A21, *A22, *B11, *B12, *B21, *B22, *C11, *C12, *C21, *C22, *T1, *T2;
		hipMalloc((void **)&A11, sizeof(float) * m * m);
		hipMalloc((void **)&A12, sizeof(float) * m * m);
		hipMalloc((void **)&A21, sizeof(float) * m * m);
		hipMalloc((void **)&A22, sizeof(float) * m * m);
		hipMalloc((void **)&B11, sizeof(float) * m * m);
		hipMalloc((void **)&B12, sizeof(float) * m * m);
		hipMalloc((void **)&B21, sizeof(float) * m * m);
		hipMalloc((void **)&B22, sizeof(float) * m * m);
		hipMalloc((void **)&C11, sizeof(float) * m * m);
		hipMalloc((void **)&C12, sizeof(float) * m * m);
		hipMalloc((void **)&C21, sizeof(float) * m * m);
		hipMalloc((void **)&C22, sizeof(float) * m * m);
		hipMalloc((void **)&T1, sizeof(float) * m * m);
		hipMalloc((void **)&T2, sizeof(float) * m * m);
		if(n <= t2) {
			split<<<grid, block>>>(A11, A12, A21, A22, A_gpu, m);
			hipDeviceSynchronize();
			split<<<grid, block>>>(B11, B12, B21, B22, B_gpu, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(A11, A21, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B22, B12, T2, m);
			hipDeviceSynchronize();
			mul<<<grid, block>>>(T1, T2, C21, m);
			hipDeviceSynchronize();
			add<<<grid, block>>>(A21, A22, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B12, B11, T2, m);
			hipDeviceSynchronize();
			mul<<<grid, block>>>(T1, T2, C22, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(T1, A11, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B22, T2, T2, m);
			hipDeviceSynchronize();
			mul<<<grid, block>>>(T1, T2, C11, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(A12, T1, T1, m);
			hipDeviceSynchronize();
			mul_add<<<grid, block>>>(T1, B22, C22, C12, m);
			hipDeviceSynchronize();
			mul_inc_inc_inc<<<grid, block>>>(A11, B11, T1, C21, C11, C12, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(T2, B21, T2, m);
			hipDeviceSynchronize();
			mul_sub_inc<<<grid, block>>>(A22, T2, C11, C21, C22, m);
			hipDeviceSynchronize();
			mul_add<<<grid, block>>>(A12, B21, T1, C11, m);
			hipDeviceSynchronize();
			merge<<<grid, block>>>(C11, C12, C21, C22, C_gpu, m);	
			hipDeviceSynchronize();
		}
		else{
			split<<<grid, block>>>(A11, A12, A21, A22, A_gpu, m);
			hipDeviceSynchronize();
			split<<<grid, block>>>(B11, B12, B21, B22, B_gpu, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(A11, A21, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B22, B12, T2, m);
			hipDeviceSynchronize();
			strassen(T1, T2, C21, m);
			add<<<grid, block>>>(A21, A22, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B12, B11, T2, m);
			hipDeviceSynchronize();
			strassen(T1, T2, C22, m);
			sub<<<grid, block>>>(T1, A11, T1, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(B22, T2, T2, m);
			hipDeviceSynchronize();
			strassen(T1, T2, C11, m);
			sub<<<grid, block>>>(A12, T1, T1, m);
			hipDeviceSynchronize();
			strassen(T1, B22, C12, m);
			add<<<grid, block>>>(C12, C22, C12, m);
			hipDeviceSynchronize();
			strassen(A11, B11, T1, m);
			add<<<grid, block>>>(C11, C12, C12, m);
			hipDeviceSynchronize();
			add<<<grid, block>>>(C12, T1, C12, m);
			hipDeviceSynchronize();
			add<<<grid, block>>>(C11, C21, C11, m);
			hipDeviceSynchronize();
			add<<<grid, block>>>(C11, T1, C11, m);
			hipDeviceSynchronize();
			sub<<<grid, block>>>(T2, B21, T2, m);
			hipDeviceSynchronize();
			strassen(A22, T2, C21, m);
			sub<<<grid, block>>>(C11, C21, C21, m);
			hipDeviceSynchronize();
			add<<<grid, block>>>(C11, C22, C22, m);
			hipDeviceSynchronize();
			strassen(A12, B21, C11, m);
			add<<<grid, block>>>(C11, T1, C11, m);
			hipDeviceSynchronize();
			merge<<<grid, block>>>(C11, C12, C21, C22, C_gpu, m);	
			hipDeviceSynchronize();
		}
		hipFree(A11); 
		hipFree(A12); 
		hipFree(A21); 
		hipFree(A22); 
		hipFree(B11); 
		hipFree(B12); 
		hipFree(B21); 
		hipFree(B22); 
		hipFree(T1);
		hipFree(T2);	
	} 
	hipMemcpy(C, C_gpu, sizeof(float) * n * n, hipMemcpyDeviceToHost);
	hipFree(A_gpu);
	hipFree(B_gpu);
	hipFree(C_gpu);
}

void compare(float *res1, float *res2, int n) {
	int fail = 0;
	for(int i = 0; i < n; i++) {
		float a, b;
		a = res1[i] < 0 ? -res1[i] : res1[i];
		b = res2[i] < 0 ? -res2[i] : res2[i];
		if(a < 0.01 && b < 0.01) {
			continue;
		}
		if(i<10) {
			printf("i = %d\t%lf\t%lf\n", i, a, b);
		}
		float diff = (a - b) / (a + 0.000001);
		if(diff < 0) {
			diff= -diff;
		}
		if(diff>0.0005) {
			fail++;
		}
	}
	printf("Number of errors: %d\n", fail);
}

double timestamp(){
	struct timeval tv;
	gettimeofday(&tv, 0);
	return tv.tv_sec + 1e-6 * tv.tv_usec;
}

int main() {
	for(int i = 0; i < N; i++) {
		for(int j = 0; j < N; j++) {
			A[i * N + j] = (float)rand() / (float)RAND_MAX;
			B[i * N + j] = (float)rand() / (float)RAND_MAX;
			C[i * N + j] = 0;
			C_cmp[i * N + j] = 0;
		}
	}

	for(int j = 0; j < N; j++) {
		for(int i = 0; i < N; i++) {
			for(int k = 0; k < N; k++) {
				C_cmp[i * N + j] += A[i * N + k] * B[k * N + j];
			}
		}
	}
	strassen(A, B, C, N);
	compare(C, C_cmp, N * N);

	double time1 = timestamp();
	for(int numOfTimes = 0; numOfTimes < ITERATIONS; numOfTimes++) {
		strassen(A, B, C, N);
	}
	double time2 = timestamp();

	double time = (time2 - time1) / ITERATIONS;
	double flops = 2.0 * N * N * N;
	double gflopsPerSecond = flops / 1000000000 /time;
	double GB = 4.0 * N * N / 1000000000;
	double GBpS = 4.0 * N * N / 1000000000 / time;
	printf("GFLOPS/s = %lf\n", gflopsPerSecond);
	printf("GB/s = %lf\n", GBpS);
	printf("GFLOPS = %lf\n", flops / 1000000000);
	printf("GB = %lf\n", GB);
	printf("time(s) = %lf\n", time);
	return 0;
}

	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z20__device_stub__splitPfS_S_S_S_i # -- Begin function _Z20__device_stub__splitPfS_S_S_S_i
	.type	_Z20__device_stub__splitPfS_S_S_S_i,@function
_Z20__device_stub__splitPfS_S_S_S_i:    # @_Z20__device_stub__splitPfS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5splitPfS_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__splitPfS_S_S_S_i, .Lfunc_end0-_Z20__device_stub__splitPfS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__mergePfS_S_S_S_i # -- Begin function _Z20__device_stub__mergePfS_S_S_S_i
	.type	_Z20__device_stub__mergePfS_S_S_S_i,@function
_Z20__device_stub__mergePfS_S_S_S_i:    # @_Z20__device_stub__mergePfS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5mergePfS_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__mergePfS_S_S_S_i, .Lfunc_end1-_Z20__device_stub__mergePfS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__addPfS_S_i   # -- Begin function _Z18__device_stub__addPfS_S_i
	.type	_Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i:          # @_Z18__device_stub__addPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z18__device_stub__addPfS_S_i, .Lfunc_end2-_Z18__device_stub__addPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__subPfS_S_i   # -- Begin function _Z18__device_stub__subPfS_S_i
	.type	_Z18__device_stub__subPfS_S_i,@function
_Z18__device_stub__subPfS_S_i:          # @_Z18__device_stub__subPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3subPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z18__device_stub__subPfS_S_i, .Lfunc_end3-_Z18__device_stub__subPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__mulPfS_S_i   # -- Begin function _Z18__device_stub__mulPfS_S_i
	.type	_Z18__device_stub__mulPfS_S_i,@function
_Z18__device_stub__mulPfS_S_i:          # @_Z18__device_stub__mulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3mulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z18__device_stub__mulPfS_S_i, .Lfunc_end4-_Z18__device_stub__mulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__mul_addPfS_S_S_i # -- Begin function _Z22__device_stub__mul_addPfS_S_S_i
	.type	_Z22__device_stub__mul_addPfS_S_S_i,@function
_Z22__device_stub__mul_addPfS_S_S_i:    # @_Z22__device_stub__mul_addPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7mul_addPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__mul_addPfS_S_S_i, .Lfunc_end5-_Z22__device_stub__mul_addPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mul_sub_incPfS_S_S_S_i # -- Begin function _Z26__device_stub__mul_sub_incPfS_S_S_S_i
	.type	_Z26__device_stub__mul_sub_incPfS_S_S_S_i,@function
_Z26__device_stub__mul_sub_incPfS_S_S_S_i: # @_Z26__device_stub__mul_sub_incPfS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mul_sub_incPfS_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z26__device_stub__mul_sub_incPfS_S_S_S_i, .Lfunc_end6-_Z26__device_stub__mul_sub_incPfS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i # -- Begin function _Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i
	.type	_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i,@function
_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i: # @_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15mul_inc_inc_incPfS_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i, .Lfunc_end7-_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8strassenPfS_S_i
.LCPI8_0:
	.long	0x3d000000                      # float 0.03125
.LCPI8_1:
	.long	0x5f000000                      # float 9.22337203E+18
	.text
	.globl	_Z8strassenPfS_S_i
	.type	_Z8strassenPfS_S_i,@function
_Z8strassenPfS_S_i:                     # @_Z8strassenPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rdx, 144(%rsp)                 # 8-byte Spill
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	%rcx, 136(%rsp)                 # 8-byte Spill
	movslq	%ecx, %r15
	movq	%r15, %r14
	imulq	%r15, %r14
	shlq	$2, %r14
	leaq	128(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	120(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	112(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r14, %rbx
	movq	%rbp, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$4096, %r15d                    # imm = 0x1000
	jg	.LBB8_4
# %bb.1:
	movq	136(%rsp), %r14                 # 8-byte Reload
	cvtsi2ss	%r14d, %xmm0
	mulss	.LCPI8_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rdi
	movq	%rdi, %rax
	subss	.LCPI8_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	sarq	$63, %rax
	andl	%eax, %ecx
	orl	%ecx, %edi
	movabsq	$4294967297, %rax               # imm = 0x100000001
	imulq	%rax, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_3
# %bb.2:
	movq	%r14, %rcx
	movq	128(%rsp), %rdi
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdx
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z18__device_stub__mulPfS_S_i
.LBB8_3:
	callq	hipDeviceSynchronize
	jmp	.LBB8_43
.LBB8_4:
	movq	136(%rsp), %r14                 # 8-byte Reload
	shrl	%r14d
	cvtsi2ss	%r14d, %xmm0
	mulss	.LCPI8_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r13
	movq	%r13, %rax
	sarq	$63, %rax
	subss	.LCPI8_1(%rip), %xmm0
	cvttss2si	%xmm0, %rcx
	andl	%eax, %ecx
	orl	%ecx, %r13d
	movabsq	$4294967297, %rax               # imm = 0x100000001
	imulq	%rax, %r13
	movq	%r14, %rbp
	imulq	%r14, %rbp
	shlq	$2, %rbp
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	104(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	96(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %r15             # imm = 0x2000000020
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_6
# %bb.5:
	movq	48(%rsp), %rdi
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rcx
	movq	128(%rsp), %r8
	movl	%r14d, %r9d
	callq	_Z20__device_stub__splitPfS_S_S_S_i
.LBB8_6:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_8
# %bb.7:
	movq	80(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	120(%rsp), %r8
	movl	%r14d, %r9d
	callq	_Z20__device_stub__splitPfS_S_S_S_i
.LBB8_8:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_10
# %bb.9:
	movq	48(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_10:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_12
# %bb.11:
	movq	40(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_12:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_14
# %bb.13:
	movq	96(%rsp), %rdi
	movq	88(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_14:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_16
# %bb.15:
	movq	72(%rsp), %rdi
	movq	80(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_16:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_18
# %bb.17:
	movq	(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_18:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_20
# %bb.19:
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rdx
	movq	%rdx, %rsi
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_20:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_22
# %bb.21:
	movq	104(%rsp), %rdi
	movq	(%rsp), %rdx
	movq	%rdx, %rsi
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_22:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_24
# %bb.23:
	movq	32(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_24:
	callq	hipDeviceSynchronize
	movq	48(%rsp), %rdi
	movq	80(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_26
# %bb.25:
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rdx
	movq	%rdx, %rsi
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_26:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_28
# %bb.27:
	movq	32(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_28:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_30
# %bb.29:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_30:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_32
# %bb.31:
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_32:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_34
# %bb.33:
	movq	8(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_34:
	callq	hipDeviceSynchronize
	movq	88(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_36
# %bb.35:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rdx
	movq	%rdx, %rsi
	movl	%r14d, %ecx
	callq	_Z18__device_stub__subPfS_S_i
.LBB8_36:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_38
# %bb.37:
	movq	16(%rsp), %rdi
	movq	56(%rsp), %rdx
	movq	%rdx, %rsi
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_38:
	callq	hipDeviceSynchronize
	movq	104(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z8strassenPfS_S_i
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_40
# %bb.39:
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%r14d, %ecx
	callq	_Z18__device_stub__addPfS_S_i
.LBB8_40:
	callq	hipDeviceSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_42
# %bb.41:
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	112(%rsp), %r8
	movl	%r14d, %r9d
	callq	_Z20__device_stub__mergePfS_S_S_S_i
.LBB8_42:
	callq	hipDeviceSynchronize
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
.LBB8_43:
	movq	112(%rsp), %rsi
	movq	144(%rsp), %rdi                 # 8-byte Reload
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z8strassenPfS_S_i, .Lfunc_end8-_Z8strassenPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z7comparePfS_i
.LCPI9_0:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI9_1:
	.quad	0x3f847ae147ae147b              # double 0.01
.LCPI9_2:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
.LCPI9_3:
	.quad	0x3f40624dd2f1a9fc              # double 5.0000000000000001E-4
	.text
	.globl	_Z7comparePfS_i
	.type	_Z7comparePfS_i,@function
_Z7comparePfS_i:                        # @_Z7comparePfS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%edx, %edx
	jle	.LBB9_1
# %bb.3:                                # %.lr.ph.preheader
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	%edx, %r12d
	xorl	%r15d, %r15d
	movaps	.LCPI9_0(%rip), %xmm2           # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
	movsd	.LCPI9_1(%rip), %xmm3           # xmm3 = mem[0],zero
	movsd	.LCPI9_2(%rip), %xmm4           # xmm4 = mem[0],zero
	movsd	.LCPI9_3(%rip), %xmm5           # xmm5 = mem[0],zero
	xorl	%ebp, %ebp
.LBB9_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r14,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm6
	xorps	%xmm2, %xmm6
	maxss	%xmm0, %xmm6
	movss	(%rbx,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm7
	xorps	%xmm2, %xmm7
	maxss	%xmm0, %xmm7
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm6, %xmm0
	ucomisd	%xmm0, %xmm3
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm7, %xmm1
	jbe	.LBB9_6
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB9_4 Depth=1
	ucomisd	%xmm1, %xmm3
	ja	.LBB9_9
.LBB9_6:                                #   in Loop: Header=BB9_4 Depth=1
	cmpq	$9, %r15
	ja	.LBB9_8
# %bb.7:                                #   in Loop: Header=BB9_4 Depth=1
	movl	$.L.str, %edi
	movl	%r15d, %esi
	movb	$2, %al
	movaps	%xmm6, 32(%rsp)                 # 16-byte Spill
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movaps	%xmm7, 16(%rsp)                 # 16-byte Spill
	callq	printf
	movaps	16(%rsp), %xmm7                 # 16-byte Reload
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movaps	32(%rsp), %xmm6                 # 16-byte Reload
	movsd	.LCPI9_3(%rip), %xmm5           # xmm5 = mem[0],zero
	movsd	.LCPI9_2(%rip), %xmm4           # xmm4 = mem[0],zero
	movsd	.LCPI9_1(%rip), %xmm3           # xmm3 = mem[0],zero
	movaps	.LCPI9_0(%rip), %xmm2           # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
.LBB9_8:                                #   in Loop: Header=BB9_4 Depth=1
	subss	%xmm7, %xmm6
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm6, %xmm1
	addsd	%xmm4, %xmm0
	divsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm1, %xmm0
	movaps	%xmm0, %xmm1
	xorps	%xmm2, %xmm1
	maxss	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	xorl	%eax, %eax
	ucomisd	%xmm5, %xmm0
	seta	%al
	addl	%eax, %ebp
.LBB9_9:                                #   in Loop: Header=BB9_4 Depth=1
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB9_4
	jmp	.LBB9_2
.LBB9_1:
	xorl	%ebp, %ebp
.LBB9_2:                                # %._crit_edge
	movl	$.L.str.1, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end9:
	.size	_Z7comparePfS_i, .Lfunc_end9-_Z7comparePfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9timestampv
.LCPI10_0:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	_Z9timestampv
	.type	_Z9timestampv,@function
_Z9timestampv:                          # @_Z9timestampv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cvtsi2sdq	(%rbx), %xmm1
	cvtsi2sdq	8(%rbx), %xmm0
	mulsd	.LCPI10_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z9timestampv, .Lfunc_end10-_Z9timestampv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI11_0:
	.long	0x30000000                      # float 4.65661287E-10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI11_1:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
.LCPI11_2:
	.quad	0x4024000000000000              # double 10
.LCPI11_3:
	.quad	0x3e212e0be826d695              # double 2.0000000000000001E-9
.LCPI11_4:
	.quad	0x3e312e0be826d695              # double 4.0000000000000002E-9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.critedge
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	callq	rand
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI11_0(%rip), %xmm0
	movss	%xmm0, A(%rip)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI11_0(%rip), %xmm0
	movss	%xmm0, B(%rip)
	mulss	A(%rip), %xmm0
	movl	$0, C(%rip)
	xorps	%xmm1, %xmm1
	addss	%xmm0, %xmm1
	movss	%xmm1, C_cmp(%rip)
	movl	$A, %edi
	movl	$B, %esi
	movl	$C, %edx
	movl	$1, %ecx
	callq	_Z8strassenPfS_S_i
	movl	$C, %edi
	movl	$C_cmp, %esi
	movl	$1, %edx
	callq	_Z7comparePfS_i
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbx), %r14
	movq	8(%rbx), %rbx
	movl	$10, %ebp
.LBB11_1:                               # =>This Inner Loop Header: Depth=1
	movl	$A, %edi
	movl	$B, %esi
	movl	$C, %edx
	movl	$1, %ecx
	callq	_Z8strassenPfS_S_i
	decl	%ebp
	jne	.LBB11_1
# %bb.2:
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rbx, %xmm0
	mulsd	.LCPI11_1(%rip), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sd	%r14, %xmm1
	addsd	%xmm0, %xmm1
	movsd	%xmm1, (%rsp)                   # 8-byte Spill
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm0, %xmm0
	cvtsi2sdq	(%rbx), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sdq	8(%rbx), %xmm1
	mulsd	.LCPI11_1(%rip), %xmm1
	addsd	%xmm0, %xmm1
	subsd	(%rsp), %xmm1                   # 8-byte Folded Reload
	divsd	.LCPI11_2(%rip), %xmm1
	movsd	%xmm1, (%rsp)                   # 8-byte Spill
	movsd	.LCPI11_3(%rip), %xmm0          # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movsd	.LCPI11_4(%rip), %xmm2          # xmm2 = mem[0],zero
	divsd	%xmm1, %xmm2
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.3, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.4, %edi
	movsd	.LCPI11_3(%rip), %xmm0          # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.5, %edi
	movsd	.LCPI11_4(%rip), %xmm0          # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.6, %edi
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	main, .Lfunc_end11-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB12_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB12_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5splitPfS_S_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5mergePfS_S_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3subPfS_S_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3mulPfS_S_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7mul_addPfS_S_S_i, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mul_sub_incPfS_S_S_S_i, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15mul_inc_inc_incPfS_S_S_S_S_i, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end12:
	.size	__hip_module_ctor, .Lfunc_end12-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB13_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB13_2:
	retq
.Lfunc_end13:
	.size	__hip_module_dtor, .Lfunc_end13-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	A,@object                       # @A
	.bss
	.globl	A
	.p2align	2, 0x0
A:
	.zero	4
	.size	A, 4

	.type	B,@object                       # @B
	.globl	B
	.p2align	2, 0x0
B:
	.zero	4
	.size	B, 4

	.type	C,@object                       # @C
	.globl	C
	.p2align	2, 0x0
C:
	.zero	4
	.size	C, 4

	.type	C_cmp,@object                   # @C_cmp
	.globl	C_cmp
	.p2align	2, 0x0
C_cmp:
	.zero	4
	.size	C_cmp, 4

	.type	_Z5splitPfS_S_S_S_i,@object     # @_Z5splitPfS_S_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z5splitPfS_S_S_S_i
	.p2align	3, 0x0
_Z5splitPfS_S_S_S_i:
	.quad	_Z20__device_stub__splitPfS_S_S_S_i
	.size	_Z5splitPfS_S_S_S_i, 8

	.type	_Z5mergePfS_S_S_S_i,@object     # @_Z5mergePfS_S_S_S_i
	.globl	_Z5mergePfS_S_S_S_i
	.p2align	3, 0x0
_Z5mergePfS_S_S_S_i:
	.quad	_Z20__device_stub__mergePfS_S_S_S_i
	.size	_Z5mergePfS_S_S_S_i, 8

	.type	_Z3addPfS_S_i,@object           # @_Z3addPfS_S_i
	.globl	_Z3addPfS_S_i
	.p2align	3, 0x0
_Z3addPfS_S_i:
	.quad	_Z18__device_stub__addPfS_S_i
	.size	_Z3addPfS_S_i, 8

	.type	_Z3subPfS_S_i,@object           # @_Z3subPfS_S_i
	.globl	_Z3subPfS_S_i
	.p2align	3, 0x0
_Z3subPfS_S_i:
	.quad	_Z18__device_stub__subPfS_S_i
	.size	_Z3subPfS_S_i, 8

	.type	_Z3mulPfS_S_i,@object           # @_Z3mulPfS_S_i
	.globl	_Z3mulPfS_S_i
	.p2align	3, 0x0
_Z3mulPfS_S_i:
	.quad	_Z18__device_stub__mulPfS_S_i
	.size	_Z3mulPfS_S_i, 8

	.type	_Z7mul_addPfS_S_S_i,@object     # @_Z7mul_addPfS_S_S_i
	.globl	_Z7mul_addPfS_S_S_i
	.p2align	3, 0x0
_Z7mul_addPfS_S_S_i:
	.quad	_Z22__device_stub__mul_addPfS_S_S_i
	.size	_Z7mul_addPfS_S_S_i, 8

	.type	_Z11mul_sub_incPfS_S_S_S_i,@object # @_Z11mul_sub_incPfS_S_S_S_i
	.globl	_Z11mul_sub_incPfS_S_S_S_i
	.p2align	3, 0x0
_Z11mul_sub_incPfS_S_S_S_i:
	.quad	_Z26__device_stub__mul_sub_incPfS_S_S_S_i
	.size	_Z11mul_sub_incPfS_S_S_S_i, 8

	.type	_Z15mul_inc_inc_incPfS_S_S_S_S_i,@object # @_Z15mul_inc_inc_incPfS_S_S_S_S_i
	.globl	_Z15mul_inc_inc_incPfS_S_S_S_S_i
	.p2align	3, 0x0
_Z15mul_inc_inc_incPfS_S_S_S_S_i:
	.quad	_Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i
	.size	_Z15mul_inc_inc_incPfS_S_S_S_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"i = %d\t%lf\t%lf\n"
	.size	.L.str, 16

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Number of errors: %d\n"
	.size	.L.str.1, 22

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"GFLOPS/s = %lf\n"
	.size	.L.str.2, 16

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"GB/s = %lf\n"
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GFLOPS = %lf\n"
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"GB = %lf\n"
	.size	.L.str.5, 10

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"time(s) = %lf\n"
	.size	.L.str.6, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5splitPfS_S_S_S_i"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5mergePfS_S_S_S_i"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z3addPfS_S_i"
	.size	.L__unnamed_3, 14

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z3subPfS_S_i"
	.size	.L__unnamed_4, 14

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z3mulPfS_S_i"
	.size	.L__unnamed_5, 14

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7mul_addPfS_S_S_i"
	.size	.L__unnamed_6, 20

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z11mul_sub_incPfS_S_S_S_i"
	.size	.L__unnamed_7, 27

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z15mul_inc_inc_incPfS_S_S_S_S_i"
	.size	.L__unnamed_8, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__splitPfS_S_S_S_i
	.addrsig_sym _Z20__device_stub__mergePfS_S_S_S_i
	.addrsig_sym _Z18__device_stub__addPfS_S_i
	.addrsig_sym _Z18__device_stub__subPfS_S_i
	.addrsig_sym _Z18__device_stub__mulPfS_S_i
	.addrsig_sym _Z22__device_stub__mul_addPfS_S_S_i
	.addrsig_sym _Z26__device_stub__mul_sub_incPfS_S_S_S_i
	.addrsig_sym _Z30__device_stub__mul_inc_inc_incPfS_S_S_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym A
	.addrsig_sym B
	.addrsig_sym C
	.addrsig_sym C_cmp
	.addrsig_sym _Z5splitPfS_S_S_S_i
	.addrsig_sym _Z5mergePfS_S_S_S_i
	.addrsig_sym _Z3addPfS_S_i
	.addrsig_sym _Z3subPfS_S_i
	.addrsig_sym _Z3mulPfS_S_i
	.addrsig_sym _Z7mul_addPfS_S_S_i
	.addrsig_sym _Z11mul_sub_incPfS_S_S_S_i
	.addrsig_sym _Z15mul_inc_inc_incPfS_S_S_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5splitPfS_S_S_S_i     ; -- Begin function _Z5splitPfS_S_S_S_i
	.globl	_Z5splitPfS_S_S_S_i
	.p2align	8
	.type	_Z5splitPfS_S_S_S_i,@function
_Z5splitPfS_S_S_S_i:                    ; @_Z5splitPfS_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s8, s[0:1], 0x28
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s8, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_lshl_b32 s12, s8, 1
	s_load_b64 s[10:11], s[0:1], 0x20
	v_mad_u64_u32 v[2:3], null, s12, v0, v[1:2]
	s_load_b256 s[0:7], s[0:1], 0x0
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, s8, v[1:2]
	global_load_b32 v8, v[2:3], off
	v_add_nc_u32_e32 v0, s8, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	s_lshl_b64 s[0:1], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v8, off
	global_load_b32 v6, v[2:3], off
	v_mad_u64_u32 v[2:3], null, s12, v0, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v6, v[0:1], off
	v_add_co_u32 v2, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v2, v[0:1], off
	v_add_co_u32 v0, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5splitPfS_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5splitPfS_S_S_S_i, .Lfunc_end0-_Z5splitPfS_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z5mergePfS_S_S_S_i     ; -- Begin function _Z5mergePfS_S_S_S_i
	.globl	_Z5mergePfS_S_S_S_i
	.p2align	8
	.type	_Z5mergePfS_S_S_S_i,@function
_Z5mergePfS_S_S_S_i:                    ; @_Z5mergePfS_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x3c
	s_load_b32 s2, s[0:1], 0x28
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	s_lshl_b32 s12, s2, 1
	s_load_b64 s[0:1], s[0:1], 0x20
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_lshl_b64 s[4:5], s[2:3], 2
	global_load_b32 v8, v[4:5], off
	v_mad_u64_u32 v[4:5], null, s12, v0, v[1:2]
	v_add_nc_u32_e32 v0, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v8, off
	global_load_b32 v8, v[6:7], off
	v_add_co_u32 v4, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v8, off
	global_load_b32 v6, v[6:7], off
	v_mad_u64_u32 v[4:5], null, s12, v0, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v6, off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5mergePfS_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5mergePfS_S_S_S_i, .Lfunc_end1-_Z5mergePfS_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3addPfS_S_i           ; -- Begin function _Z3addPfS_S_i
	.globl	_Z3addPfS_S_i
	.p2align	8
	.type	_Z3addPfS_S_i,@function
_Z3addPfS_S_i:                          ; @_Z3addPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z3addPfS_S_i, .Lfunc_end2-_Z3addPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3subPfS_S_i           ; -- Begin function _Z3subPfS_S_i
	.globl	_Z3subPfS_S_i
	.p2align	8
	.type	_Z3subPfS_S_i,@function
_Z3subPfS_S_i:                          ; @_Z3subPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3subPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z3subPfS_S_i, .Lfunc_end3-_Z3subPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3mulPfS_S_i           ; -- Begin function _Z3mulPfS_S_i
	.globl	_Z3mulPfS_S_i
	.p2align	8
	.type	_Z3mulPfS_S_i,@function
_Z3mulPfS_S_i:                          ; @_Z3mulPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB4_4
; %bb.1:
	v_mul_lo_u32 v4, v1, s4
	s_load_b64 s[2:3], s[0:1], 0x10
	s_cmp_lt_i32 s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v1, v4, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB4_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_mov_b32 s0, s4
.LBB4_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v1, v7
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB4_3
.LBB4_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3mulPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z3mulPfS_S_i, .Lfunc_end4-_Z3mulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7mul_addPfS_S_S_i     ; -- Begin function _Z7mul_addPfS_S_S_i
	.globl	_Z7mul_addPfS_S_S_i
	.p2align	8
	.type	_Z7mul_addPfS_S_S_i,@function
_Z7mul_addPfS_S_S_i:                    ; @_Z7mul_addPfS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s8, s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s8, v2
	s_cbranch_execz .LBB5_4
; %bb.1:
	v_mul_lo_u32 v4, v1, s8
	s_load_b256 s[0:7], s[0:1], 0x0
	s_cmp_lt_i32 s8, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v4, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v6, v[5:6], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB5_4
; %bb.2:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_mov_b32 s0, s8
.LBB5_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 0
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v1, v[4:5], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v1, v7
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB5_3
.LBB5_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7mul_addPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z7mul_addPfS_S_S_i, .Lfunc_end5-_Z7mul_addPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11mul_sub_incPfS_S_S_S_i ; -- Begin function _Z11mul_sub_incPfS_S_S_S_i
	.globl	_Z11mul_sub_incPfS_S_S_S_i
	.p2align	8
	.type	_Z11mul_sub_incPfS_S_S_S_i,@function
_Z11mul_sub_incPfS_S_S_S_i:             ; @_Z11mul_sub_incPfS_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x3c
	s_load_b32 s2, s[0:1], 0x28
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB6_5
; %bb.1:
	v_mul_lo_u32 v6, v1, s2
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_cmp_lt_i32 s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v1, v6, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc1 .LBB6_4
; %bb.2:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v8, 0
	s_mov_b32 s3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.LBB6_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	v_lshlrev_b64 v[9:10], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v1, v[6:7], off
	global_load_b32 v9, v[9:10], off
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v1, v9
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc0 .LBB6_3
.LBB6_4:                                ; %Flow74
	v_add_co_u32 v0, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v6, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, v6, v8
	global_store_b32 v[2:3], v6, off
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v[4:5], v0, off
.LBB6_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mul_sub_incPfS_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z11mul_sub_incPfS_S_S_S_i, .Lfunc_end6-_Z11mul_sub_incPfS_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15mul_inc_inc_incPfS_S_S_S_S_i ; -- Begin function _Z15mul_inc_inc_incPfS_S_S_S_S_i
	.globl	_Z15mul_inc_inc_incPfS_S_S_S_S_i
	.p2align	8
	.type	_Z15mul_inc_inc_incPfS_S_S_S_S_i,@function
_Z15mul_inc_inc_incPfS_S_S_S_S_i:       ; @_Z15mul_inc_inc_incPfS_S_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b32 s12, s[0:1], 0x30
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v1, v2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB7_5
; %bb.1:
	v_mul_lo_u32 v6, v0, s12
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x20
	v_mov_b32_e32 v8, 0
	s_cmp_lt_i32 s12, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v6, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[4:5], v8, off
	s_cbranch_scc1 .LBB7_4
; %bb.2:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s4, s12
.LBB7_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s4, 0
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	v_add_nc_u32_e32 v2, s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v3, v[6:7], off
	global_load_b32 v9, v[9:10], off
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v3, v9
	global_store_b32 v[4:5], v8, off
	s_cbranch_scc0 .LBB7_3
.LBB7_4:                                ; %Flow82
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v8, v4
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[2:3], v6, off
	v_add_co_u32 v0, vcc_lo, s10, v0
	global_load_b32 v7, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	global_store_b32 v[4:5], v6, off
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v[2:3], v0, off
.LBB7_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15mul_inc_inc_incPfS_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z15mul_inc_inc_incPfS_S_S_S_S_i, .Lfunc_end7-_Z15mul_inc_inc_incPfS_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 448
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5splitPfS_S_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5splitPfS_S_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
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...

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