/*__global__ void Rotate3D(float* Destination,  float* Source, int sizeX, int sizeY, float deg)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
    int j = blockIdx.y * blockDim.y + threadIdx.y;
    int k = blockIdx.z * blockDim.z + threadIdx.z;
    int xc = sizeX - sizeX/2;
    int yc = sizeY - sizeY/2;
    int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
    int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
    if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
    {
        // putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
	Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
    }
} */

// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination,  float* Source, int sizeX, int sizeY, float deg)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
    int j = blockIdx.y * blockDim.y + threadIdx.y;
    int k = blockIdx.z * blockDim.z + threadIdx.z;
    int z_offset = k*sizeX*sizeY;
    int xc = sizeX - sizeX/2;
    int yc = sizeY - sizeY/2;
    float cos_rad = cosf(deg/180*pi);
    float sin_rad = sinf(deg/180*pi);
    float newx = +((float)i-xc)*cos_rad  + ((float)j-yc)*sin_rad + xc ;
    float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad  + yc ;
    int newx_0 = floorf(newx);
    int newy_0 = floorf(newy);
    int newx_1 = newx_0 + 1;
    int newy_1 = newy_0 + 1;
    // put the pixel coo. in unit square
    float x = newx - float(newx_0);
    float y = newy - float(newy_0);
    float val_00 = 0.0, val_01 = 0.0,  val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
    if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
    {
        // perform bilinear interpolation
	val_00 = Source[z_offset + newy_0*sizeX + newx_0];
	val_01 = Source[z_offset + newy_1*sizeX + newx_0];
	val_10 = Source[z_offset + newy_0*sizeX + newx_1];
	val_11 = Source[z_offset + newy_1*sizeX + newx_1];
	val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
	Destination[z_offset + j*sizeX+i] = val_intp;
    }
}
	.file	"tmpxft_002f2b1f_00000000-6_imrotate.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
	.type	_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, @function
_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17Rotate3D_bilinearPfS_iif(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, .-_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
	.globl	_Z17Rotate3D_bilinearPfS_iif
	.type	_Z17Rotate3D_bilinearPfS_iif, @function
_Z17Rotate3D_bilinearPfS_iif:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
	.cfi_endproc
.LFE2033:
	.size	_Z17Rotate3D_bilinearPfS_iif, .-_Z17Rotate3D_bilinearPfS_iif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17Rotate3D_bilinearPfS_iif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17Rotate3D_bilinearPfS_iif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*__global__ void Rotate3D(float* Destination,  float* Source, int sizeX, int sizeY, float deg)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
    int j = blockIdx.y * blockDim.y + threadIdx.y;
    int k = blockIdx.z * blockDim.z + threadIdx.z;
    int xc = sizeX - sizeX/2;
    int yc = sizeY - sizeY/2;
    int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
    int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
    if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
    {
        // putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
	Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
    }
} */

// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination,  float* Source, int sizeX, int sizeY, float deg)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
    int j = blockIdx.y * blockDim.y + threadIdx.y;
    int k = blockIdx.z * blockDim.z + threadIdx.z;
    int z_offset = k*sizeX*sizeY;
    int xc = sizeX - sizeX/2;
    int yc = sizeY - sizeY/2;
    float cos_rad = cosf(deg/180*pi);
    float sin_rad = sinf(deg/180*pi);
    float newx = +((float)i-xc)*cos_rad  + ((float)j-yc)*sin_rad + xc ;
    float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad  + yc ;
    int newx_0 = floorf(newx);
    int newy_0 = floorf(newy);
    int newx_1 = newx_0 + 1;
    int newy_1 = newy_0 + 1;
    // put the pixel coo. in unit square
    float x = newx - float(newx_0);
    float y = newy - float(newy_0);
    float val_00 = 0.0, val_01 = 0.0,  val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
    if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
    {
        // perform bilinear interpolation
	val_00 = Source[z_offset + newy_0*sizeX + newx_0];
	val_01 = Source[z_offset + newy_1*sizeX + newx_0];
	val_10 = Source[z_offset + newy_0*sizeX + newx_1];
	val_11 = Source[z_offset + newy_1*sizeX + newx_1];
	val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
	Destination[z_offset + j*sizeX+i] = val_intp;
    }
}
	.text
	.file	"imrotate.hip"
	.globl	_Z32__device_stub__Rotate3D_bilinearPfS_iif # -- Begin function _Z32__device_stub__Rotate3D_bilinearPfS_iif
	.type	_Z32__device_stub__Rotate3D_bilinearPfS_iif,@function
_Z32__device_stub__Rotate3D_bilinearPfS_iif: # @_Z32__device_stub__Rotate3D_bilinearPfS_iif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17Rotate3D_bilinearPfS_iif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__Rotate3D_bilinearPfS_iif, .Lfunc_end0-_Z32__device_stub__Rotate3D_bilinearPfS_iif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17Rotate3D_bilinearPfS_iif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17Rotate3D_bilinearPfS_iif,@object # @_Z17Rotate3D_bilinearPfS_iif
	.section	.rodata,"a",@progbits
	.globl	_Z17Rotate3D_bilinearPfS_iif
	.p2align	3, 0x0
_Z17Rotate3D_bilinearPfS_iif:
	.quad	_Z32__device_stub__Rotate3D_bilinearPfS_iif
	.size	_Z17Rotate3D_bilinearPfS_iif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17Rotate3D_bilinearPfS_iif"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__Rotate3D_bilinearPfS_iif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17Rotate3D_bilinearPfS_iif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17Rotate3D_bilinearPfS_iif ; -- Begin function _Z17Rotate3D_bilinearPfS_iif
	.globl	_Z17Rotate3D_bilinearPfS_iif
	.p2align	8
	.type	_Z17Rotate3D_bilinearPfS_iif,@function
_Z17Rotate3D_bilinearPfS_iif:           ; @_Z17Rotate3D_bilinearPfS_iif
; %bb.0:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x30
	s_mov_b32 s2, 0x43340000
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v1, null, s2, s2, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v3, v2
	v_div_scale_f32 v3, vcc_lo, s10, 0x43340000, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v3, v2
	v_fma_f32 v5, -v1, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v2
	v_fma_f32 v1, -v1, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v4
	v_div_fixup_f32 v1, v1, 0x43340000, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x40490fdb, v1
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v4|
	v_readfirstlane_b32 s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_bitset0_b32 s2, 31
	s_cbranch_vccz .LBB0_2
; %bb.1:
	s_and_b32 s3, s2, 0x7fffff
	s_lshr_b32 s6, s2, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s6, 0xff88
	s_mul_hi_u32 s7, s3, 0xfe5163ab
	s_mul_i32 s10, s3, 0x3c439041
	s_mul_hi_u32 s11, s3, 0x3c439041
	s_add_u32 s7, s7, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0xdb629599
	s_mul_hi_u32 s12, s3, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s3, 0xf534ddc0
	s_mul_hi_u32 s16, s3, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s16
	s_mul_i32 s16, s3, 0xfc2757d1
	s_mul_hi_u32 s17, s3, 0xfc2757d1
	s_add_u32 s12, s12, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s3, 0x4e441529
	s_mul_hi_u32 s18, s3, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s6, 63
	s_mul_i32 s18, s3, 0xfe5163ab
	s_mul_hi_u32 s19, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s20, s10, s12
	s_cselect_b32 s7, s7, s11
	s_cselect_b32 s10, s18, s10
	s_add_u32 s3, s17, s3
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s6, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s16
	s_cselect_b32 s3, s12, s3
	s_cselect_b32 s12, s16, s17
	s_add_i32 s18, s18, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s16, s11, s3
	s_cselect_b32 s3, s3, s12
	s_cselect_b32 s11, s20, s11
	s_cselect_b32 s12, s7, s20
	s_cselect_b32 s7, s10, s7
	s_add_i32 s6, s6, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s6, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s3, s16, s3
	s_cselect_b32 s16, s11, s16
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s7, s7, s12
	s_add_i32 s10, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s6, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v1, s6
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v2, s3, s16, v1
	v_alignbit_b32 v3, s16, s11, v1
	v_alignbit_b32 v1, s11, s7, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s6, v2
	v_cndmask_b32_e64 v2, v3, s16, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, s11, s10
	s_cselect_b32 s3, s3, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, s3, v2, 30
	s_bfe_u32 s12, s3, 0x1001d
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v2, v2, v1, 30
	s_sub_i32 s6, 0, s12
	v_alignbit_b32 v1, v1, s7, 30
	v_xor_b32_e32 v3, s6, v3
	v_xor_b32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v1, s6, v1
	v_clz_i32_u32_e32 v5, v3
	s_lshr_b32 s6, s3, 29
	s_lshr_b32 s3, s3, 30
	s_lshl_b32 s6, s6, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min_u32_e32 v5, 32, v5
	s_or_b32 s7, s6, 0.5
	v_sub_nc_u32_e32 v6, 31, v5
	v_lshlrev_b32_e32 v7, 23, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v3, v2, v6
	v_alignbit_b32 v1, v2, v1, v6
	v_sub_nc_u32_e32 v7, s7, v7
	s_add_i32 s7, s12, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v2, v3, v1, 9
	v_clz_i32_u32_e32 v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v6, 32, v6
	v_sub_nc_u32_e32 v8, 31, v6
	v_add_nc_u32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v1, v2, v1, v8
	v_lshrrev_b32_e32 v2, 9, v3
	v_lshlrev_b32_e32 v3, 23, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v1, 9, v1
	v_or_b32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v3
	v_add_nc_u32_e32 v1, 0x33000000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or_b32_e32 v1, s6, v1
	v_mul_f32_e32 v3, 0x3fc90fda, v2
	s_mov_b32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3fc90fda, v2, -v3
	v_fmamk_f32 v2, v2, 0x33a22168, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3fc90fda, v1
	v_add_f32_e32 v3, v3, v2
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s6, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr3
.LBB0_3:                                ; %Flow117
	s_load_b32 s3, s[0:1], 0x2c
	v_mov_b32_e32 v1, s7
	v_mul_f32_e64 v2, 0x3f22f983, |v4|
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_and_b32 s5, s5, 0xffff
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v1, v2
	v_fma_f32 v3, 0xbfc90fda, v1, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v1, 0xb3a22168, v3
	v_fmamk_f32 v3, v1, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v1, v1
.LBB0_5:                                ; %_ZL4cosff.exit
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_7
; %bb.6:
	s_and_b32 s4, s2, 0x7fffff
	s_lshr_b32 s6, s2, 23
	s_bitset1_b32 s4, 23
	s_addk_i32 s6, 0xff88
	s_mul_hi_u32 s7, s4, 0xfe5163ab
	s_mul_i32 s10, s4, 0x3c439041
	s_mul_hi_u32 s11, s4, 0x3c439041
	s_add_u32 s7, s7, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s4, 0xdb629599
	s_mul_hi_u32 s12, s4, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s4, 0xf534ddc0
	s_mul_hi_u32 s16, s4, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s16
	s_mul_i32 s16, s4, 0xfc2757d1
	s_mul_hi_u32 s17, s4, 0xfc2757d1
	s_add_u32 s12, s12, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s4, 0x4e441529
	s_mul_hi_u32 s18, s4, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s6, 63
	s_mul_i32 s18, s4, 0xfe5163ab
	s_mul_hi_u32 s19, s4, 0xa2f9836e
	s_mul_i32 s4, s4, 0xa2f9836e
	s_cselect_b32 s20, s10, s12
	s_cselect_b32 s7, s7, s11
	s_cselect_b32 s10, s18, s10
	s_add_u32 s4, s17, s4
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s6, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s16
	s_cselect_b32 s4, s12, s4
	s_cselect_b32 s12, s16, s17
	s_add_i32 s18, s18, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s16, s11, s4
	s_cselect_b32 s4, s4, s12
	s_cselect_b32 s11, s20, s11
	s_cselect_b32 s12, s7, s20
	s_cselect_b32 s7, s10, s7
	s_add_i32 s6, s6, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s6, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s4, s16, s4
	s_cselect_b32 s16, s11, s16
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s7, s7, s12
	s_add_i32 s10, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s6, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v5, s6
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v6, s4, s16, v5
	v_alignbit_b32 v7, s16, s11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v6
	v_cndmask_b32_e64 v6, v7, s16, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s4, s4, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v7, s4, v6, 30
	s_bfe_u32 s6, s4, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v7, s12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v7
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v10, 23, v8
	v_alignbit_b32 v5, s11, s7, v5
	v_sub_nc_u32_e32 v9, 31, v8
	v_cndmask_b32_e64 v5, v5, s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v5, v5, s7, 30
	s_lshr_b32 s7, s4, 29
	s_lshl_b32 s7, s7, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, s12, v6
	v_xor_b32_e32 v5, s12, v5
	s_or_b32 s10, s7, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, s10, v10
	v_alignbit_b32 v7, v7, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v6, v5, v9
	v_alignbit_b32 v6, v7, v5, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v6
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, 31, v9
	v_alignbit_b32 v5, v6, v5, v11
	v_lshrrev_b32_e32 v6, 9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v5, 9, v5
	v_or_b32_e32 v6, v6, v10
	v_add_nc_u32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v7, 23, v8
	v_sub_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, 0x3fc90fda, v6
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v7
	v_or_b32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v6, 0x33a22168, v8
	s_lshr_b32 s7, s4, 30
	s_mov_b32 s4, 0
	s_add_i32 s6, s6, s7
	v_fmac_f32_e32 v6, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v6
	s_branch .LBB0_8
.LBB0_7:
	s_mov_b32 s4, -1
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $vgpr5
.LBB0_8:                                ; %Flow
	v_mov_b32_e32 v6, s6
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_10
; %bb.9:
	v_rndne_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0xbfc90fda, v2, |v4|
	v_cvt_i32_f32_e32 v6, v2
	v_fmamk_f32 v5, v2, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v5, v2, 0xa7c234c4, v5
.LBB0_10:                               ; %_ZL4sinff.exit
	v_dual_mul_f32 v2, v3, v3 :: v_dual_and_b32 v9, 1, v1
	s_mov_b32 s4, 0xb94c1982
	s_mov_b32 s6, 0x37d75334
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s3, 16
	v_dual_fmaak_f32 v7, s4, v2, 0x3c0881c4 :: v_dual_mul_f32 v12, v5, v5
	v_dual_fmaak_f32 v8, s6, v2, 0xbab64f3b :: v_dual_lshlrev_b32 v1, 30, v1
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_3)
	v_fmaak_f32 v14, s4, v12, 0x3c0881c4
	v_fmaak_f32 v10, v2, v7, 0xbe2aaa9d
	v_fmaak_f32 v15, s6, v12, 0xbab64f3b
	v_fmaak_f32 v11, v2, v8, 0x3d2aabf7
	v_and_b32_e32 v7, 0x3ff, v0
	v_bfe_u32 v8, v0, 10, 10
	v_dual_mul_f32 v10, v2, v10 :: v_dual_and_b32 v13, 0x80000000, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v11, v2, v11, 0xbf000004
	s_lshr_b32 s4, s9, 31
	v_fmac_f32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v2, v11, 1.0
	v_mad_u64_u32 v[1:2], null, s13, s3, v[7:8]
	v_fmaak_f32 v7, v12, v14, 0xbe2aaa9d
	s_lshr_b32 s3, s8, 31
	v_cndmask_b32_e64 v9, -v3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, s14, s7, v[8:9]
	v_mul_f32_e32 v3, v12, v7
	v_xor_b32_e32 v7, v13, v9
	v_lshlrev_b32_e32 v9, 30, v6
	v_and_b32_e32 v6, 1, v6
	v_fmaak_f32 v10, v12, v15, 0x3d2aabf7
	v_fmac_f32_e32 v5, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	v_fmaak_f32 v8, v12, v10, 0xbf000004
	v_cvt_f32_i32_e32 v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v3, v12, v8, 1.0
	v_and_b32_e32 v8, 0x80000000, v9
	v_xor_b32_e32 v9, s2, v4
	s_add_i32 s2, s8, s3
	s_add_i32 s3, s9, s4
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_ashr_i32 s2, s2, 1
	v_xor_b32_e32 v5, v9, v8
	s_ashr_i32 s3, s3, 1
	s_sub_i32 s2, s8, s2
	s_sub_i32 s3, s9, s3
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	v_xor_b32_e32 v3, v5, v3
	v_cvt_f32_i32_e32 v5, v1
	v_cvt_f32_i32_e32 v4, s3
	v_cvt_f32_i32_e32 v8, s2
	v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v3, 0x7fc00000, v3 :: v_dual_sub_f32 v6, v6, v4
	v_sub_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, v6, v3
	v_mul_f32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v5, v7
	v_fma_f32 v5, v6, v7, -v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v9, v8
	v_add_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v5, v3
	v_floor_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v5
	v_add_nc_u32_e32 v8, 1, v6
	v_cmp_lt_i32_e64 s3, -1, v6
	v_cmp_lt_i32_e64 s4, -1, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s8, v7
	v_cmp_gt_i32_e64 s2, s9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_bfe_u32 v0, v0, 20, 10
	s_and_b32 s2, s5, 0xffff
	v_mul_lo_u32 v2, v2, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, s15, s2, v[0:1]
	s_mul_i32 s2, s9, s8
	v_mul_lo_u32 v0, v6, s8
	v_mul_lo_u32 v11, s2, v7
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v0, v11, v5
	v_cvt_f32_i32_e32 v0, v6
	v_cvt_f32_i32_e32 v5, v5
	v_add_nc_u32_e32 v9, s8, v7
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v4, v0
	v_add3_u32 v0, v2, v1, v11
	v_sub_f32_e32 v2, v3, v5
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[9:10], v[9:10], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v3, v8, v7 :: v_dual_add_f32 v6, v7, v10
	v_sub_f32_e32 v10, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_fma_f32 v5, v4, v10, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v9
	v_fmac_f32_e32 v5, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v6
	v_fmac_f32_e32 v5, v4, v2
	global_store_b32 v[0:1], v5, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17Rotate3D_bilinearPfS_iif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17Rotate3D_bilinearPfS_iif, .Lfunc_end0-_Z17Rotate3D_bilinearPfS_iif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2428
; NumSgprs: 23
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17Rotate3D_bilinearPfS_iif
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z17Rotate3D_bilinearPfS_iif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
