#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>

#include <iostream>
#include <fstream>
#include <chrono>

#define TILE_DIM 64

void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);

// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
//     // Row i of matrix C
//     int row = blockIdx.y * blockDim.y + threadIdx.y;
//     // Column j of matrix C
//     int col = blockIdx.x * blockDim.x + threadIdx.x;

//     int accu = 0;
//     if(row<N && col<N) {
//         for(int k=0; k<N; k++) {
//             accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
//         }
//         C_gpu[row*N+col] = accu;
//     }
// }

__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
    int accu = 0;

    int row = blockIdx.y*TILE_DIM + threadIdx.y;
    int col = blockIdx.x*TILE_DIM + threadIdx.x;

    __shared__ int shd_A[TILE_DIM][TILE_DIM];
    __shared__ int shd_B[TILE_DIM][TILE_DIM];

    for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {

         if (k*TILE_DIM + threadIdx.x < N && row < N)
             shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
         else
             shd_A[threadIdx.y][threadIdx.x] = 0.0;

         if (k*TILE_DIM + threadIdx.y < N && col < N)
             shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
         else
             shd_B[threadIdx.y][threadIdx.x] = 0.0;

         __syncthreads();

         for (int k = 0; k<TILE_DIM; k++)
             accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];

         __syncthreads();
    }

    if (row < N && col < N)
        C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
           (blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}

// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
//     // Row i of matrix C
//     int row = blockIdx.y * blockDim.y + threadIdx.y;
//     // Column j of matrix C
//     int col = blockIdx.x * blockDim.x + threadIdx.x;
    
//     int accu = 0;
//     if(row<N && col<N) {
//         for(int k=0; k<N; k++) {
//             accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
//         }
//         C_gpu[row*N+col] = accu;
//     }
// }

__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
    int accu = 0;

    int row = blockIdx.y*TILE_DIM + threadIdx.y;
    int col = blockIdx.x*TILE_DIM + threadIdx.x;

    __shared__ int shd_A[TILE_DIM][TILE_DIM];
    __shared__ int shd_B[TILE_DIM][TILE_DIM];

    for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {

         if (k*TILE_DIM + threadIdx.x < N && row < N)
             shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
         else
             shd_A[threadIdx.y][threadIdx.x] = 0.0;

         if (k*TILE_DIM + threadIdx.y < N && col < N)
             shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
         else
             shd_B[threadIdx.y][threadIdx.x] = 0.0;

         __syncthreads();

         for (int k=0; k<TILE_DIM; k++)
             accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];

         __syncthreads();
    }

    if (row < N && col < N)
        C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
           (blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
    
void random_ints(int* x, int size)
    {
        srand(time(0)); 
        int i;
        for (i=0;i<size;i++) {
            x[i]=rand()%10;
            //std::cout << x[i] << " ";
        }
    }

void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
    for(int row=0; row<N; row++) {
        for(int col=0; col<N; col++){
            C_cpu[row*N+col] = 0;
            for(int elm=0; elm<N; elm++) {
                C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
            }
        }
    }
}


int main(int argc, char* argv[]){
    //int N = 3;
    int N = atoi(argv[1]);
    bool memCol = false;
    if (strcmp(argv[4],"MC")==0) {
        memCol=true;
    }
    int NN = N*N;
    //define A_cpu, B_cpu, C_cpu in the CPU memory
    int *A_cpu, *B_cpu, *C_cpu;

    int size = NN * sizeof(int);

    // Setup input values
    //std::cout << "A: ";
    A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
    //std::cout << "\nB: ";
    B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
    C_cpu = (int*)malloc(size);  
    if (strcmp(argv[2],"gpu")==0) {
        if(strcmp(argv[3],"MT")==0) {
            gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
        }
        else {
            gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
        }

    }
    else {
        auto t1 = std::chrono::high_resolution_clock::now();
        matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
        auto t2 = std::chrono::high_resolution_clock::now();
        auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
        std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
    }
    //std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
    free(A_cpu); free(B_cpu); free(C_cpu);
    return 0;
}
    

void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
    //define A_gpu, B_gpu, C_gpu in the GPU memory
    //std::cout << "\nMem Tr\n";
    int *A_gpu, *B_gpu, *C_gpu;

    cudaMalloc((void **)&A_gpu, size);
    cudaMalloc((void **)&B_gpu, size);
    cudaMalloc((void **)&C_gpu, size);

    dim3 dimBlock(16, 16);
    dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);

    float time = 0;
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    if (memCol==true) {
        //std::cout << "MC\n";
        cudaEventRecord( start, 0 );

        // Copy inputs to device
        cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
        cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);

        matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);

        //memcopy C_gpu to C_cpu
        cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
        //stop time
        cudaEventRecord( stop, 0 );
    }
    else {
        //std::cout << "nmc\n";
        cudaEventRecord( start, 0 );

        // Copy inputs to device
        cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
        cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);

        matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);

        //memcopy C_gpu to C_cpu
        cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
        //stop time
        cudaEventRecord( stop, 0 );
    }
    cudaEventSynchronize( stop );
    cudaEventElapsedTime( &time, start, stop );
    cudaEventDestroy( start );
    cudaEventDestroy( stop );
    cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
    float microsec = (time)*1000;
    std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}

void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
    //define A_gpu, B_gpu, C_gpu in the GPU memory
    //std::cout << "\nNoMem Tr\n";
    int *A_gpu, *B_gpu, *C_gpu;

    cudaMalloc((void **)&A_gpu, size);
    cudaMalloc((void **)&B_gpu, size);
    cudaMalloc((void **)&C_gpu, size);

    // Copy inputs to device
    cudaMemcpy(A_gpu, A_cpu, size, cudaMemcpyHostToDevice);
    cudaMemcpy(B_gpu, B_cpu, size, cudaMemcpyHostToDevice);

    dim3 dimBlock(16, 16);
    dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);

    float time = 0;
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    if (memCol==true) {
        //std::cout << "MC\n";
        cudaEventRecord( start, 0 );
        matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
        cudaEventRecord( stop, 0 );
    }
    else {
        //std::cout << "nmc\n";
        cudaEventRecord( start, 0 );
        matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
        cudaEventRecord( stop, 0 );
    }
    cudaEventSynchronize( stop );
    cudaEventElapsedTime( &time, start, stop );
    cudaEventDestroy( start );
    cudaEventDestroy( stop );
    //memcopy C_gpu to C_cpu
    cudaMemcpy(C_cpu, C_gpu, size, cudaMemcpyDeviceToHost);
    cudaFree(A_gpu); cudaFree(B_gpu); cudaFree(C_gpu);
    float microsec = (time)*1000;
    std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}

	.file	"tmpxft_00233de3_00000000-6_tile.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3874:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3874:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11random_intsPii
	.type	_Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3865:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$10, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L3:
	cmpl	%ebx, %ebp
	jle	.L7
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3865:
	.size	_Z11random_intsPii, .-_Z11random_intsPii
	.globl	_Z12matrixMulCPUPiS_S_i
	.type	_Z12matrixMulCPUPiS_S_i, @function
_Z12matrixMulCPUPiS_S_i:
.LFB3866:
	.cfi_startproc
	endbr64
	movq	%rsi, %r11
	movslq	%ecx, %rsi
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r10
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	salq	$2, %rsi
	xorl	%r9d, %r9d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdx, %rbx
	xorl	%edx, %edx
.L9:
	cmpl	%ecx, %r9d
	jge	.L16
	leaq	(%rbx,%rdx), %rax
	xorl	%edi, %edi
	leaq	(%r10,%rdx), %r13
.L11:
	xorl	%r8d, %r8d
	leaq	(%r11,%rdi,4), %rbp
	movl	%r8d, (%rax)
	xorl	%r8d, %r8d
.L10:
	movl	0(%r13,%r8,4), %r12d
	incq	%r8
	imull	0(%rbp), %r12d
	addq	%rsi, %rbp
	addl	%r12d, (%rax)
	cmpl	%r8d, %ecx
	jg	.L10
	incq	%rdi
	addq	$4, %rax
	cmpl	%edi, %ecx
	jg	.L11
	incl	%r9d
	addq	%rsi, %rdx
	jmp	.L9
.L16:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3866:
	.size	_Z12matrixMulCPUPiS_S_i, .-_Z12matrixMulCPUPiS_S_i
	.globl	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
	.type	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB3896:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9matrixMulPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L17:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3896:
	.size	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
	.globl	_Z9matrixMulPiS_S_i
	.type	_Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB3897:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3897:
	.size	_Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
	.globl	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
	.type	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i:
.LFB3898:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12matrixMulColPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L22:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3898:
	.size	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
	.globl	_Z12matrixMulColPiS_S_i
	.type	_Z12matrixMulColPiS_S_i, @function
_Z12matrixMulColPiS_S_i:
.LFB3899:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3899:
	.size	_Z12matrixMulColPiS_S_i, .-_Z12matrixMulColPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"N: "
.LC3:
	.string	"\tMT\t"
.LC4:
	.string	"\tGPU time: "
.LC5:
	.string	"us"
	.text
	.globl	_Z14gpuMemTransferPiS_S_iib
	.type	_Z14gpuMemTransferPiS_S_iib, @function
_Z14gpuMemTransferPiS_S_iib:
.LFB3870:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r8d, %rbx
	movq	%rbx, %rsi
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	leal	15(%r12), %eax
	leaq	48(%rsp), %rdi
	movl	$1, 72(%rsp)
	shrl	$4, %eax
	movl	$1, 84(%rsp)
	movl	%eax, 76(%rsp)
	movl	%eax, 80(%rsp)
	movl	$0x00000000, 20(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	xorl	%esi, %esi
	testb	%bpl, %bpl
	movq	48(%rsp), %rdi
	je	.L28
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r12d, %ecx
	movq	24(%rsp), %rdi
	call	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
	jmp	.L31
.L28:
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r12d, %ecx
	movq	24(%rsp), %rdi
	call	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.L31:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movss	.LC1(%rip), %xmm0
	mulss	20(%rsp), %xmm0
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movzbl	%bpl, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIbEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3870:
	.size	_Z14gpuMemTransferPiS_S_iib, .-_Z14gpuMemTransferPiS_S_iib
	.section	.rodata.str1.1
.LC6:
	.string	"\tnt\t"
	.text
	.globl	_Z16gpuNoMemTransferPiS_S_iib
	.type	_Z16gpuNoMemTransferPiS_S_iib, @function
_Z16gpuNoMemTransferPiS_S_iib:
.LFB3871:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r8d, %rbx
	movq	%rbx, %rsi
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%r12), %eax
	leaq	48(%rsp), %rdi
	movl	$1, 72(%rsp)
	shrl	$4, %eax
	movl	$1, 84(%rsp)
	movl	%eax, 76(%rsp)
	movl	%eax, 80(%rsp)
	movl	$0x00000000, 20(%rsp)
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	xorl	%esi, %esi
	testb	%bpl, %bpl
	movq	48(%rsp), %rdi
	je	.L35
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r12d, %ecx
	movq	24(%rsp), %rdi
	call	_Z37__device_stub__Z12matrixMulColPiS_S_iPiS_S_i
	jmp	.L38
.L35:
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r12d, %ecx
	movq	24(%rsp), %rdi
	call	_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.L38:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movss	.LC1(%rip), %xmm0
	mulss	20(%rsp), %xmm0
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movzbl	%bpl, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIbEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3871:
	.size	_Z16gpuNoMemTransferPiS_S_iib, .-_Z16gpuNoMemTransferPiS_S_iib
	.section	.rodata.str1.1
.LC7:
	.string	"MC"
.LC8:
	.string	"gpu"
.LC9:
	.string	"MT"
.LC10:
	.string	"\tCPU time: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3867:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movq	32(%rbp), %rdi
	leaq	.LC7(%rip), %rsi
	movl	%eax, %ebx
	call	strcmp@PLT
	movl	%ebx, %r15d
	imull	%ebx, %r15d
	movl	%eax, %r14d
	leal	0(,%r15,4), %r8d
	movslq	%r8d, %r13
	movl	%r8d, 12(%rsp)
	movq	%r13, %rdi
	call	malloc@PLT
	movl	%r15d, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	call	_Z11random_intsPii
	movq	%r13, %rdi
	call	malloc@PLT
	movl	%r15d, %esi
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	_Z11random_intsPii
	movq	%r13, %rdi
	call	malloc@PLT
	movq	16(%rbp), %rdi
	leaq	.LC8(%rip), %rsi
	movq	%rax, %r13
	call	strcmp@PLT
	testl	%eax, %eax
	jne	.L42
	movq	24(%rbp), %rdi
	leaq	.LC9(%rip), %rsi
	call	strcmp@PLT
	xorl	%r9d, %r9d
	testl	%r14d, %r14d
	movq	(%rsp), %rsi
	sete	%r9b
	testl	%eax, %eax
	movl	12(%rsp), %r8d
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%r12, %rdi
	jne	.L43
	call	_Z14gpuMemTransferPiS_S_iib
	jmp	.L44
.L43:
	call	_Z16gpuNoMemTransferPiS_S_iib
	jmp	.L44
.L42:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%r12, %rdi
	movq	%rax, %r14
	call	_Z12matrixMulCPUPiS_S_i
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	$1000, %ecx
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%r14, %rax
	cqto
	idivq	%rcx
	movq	%rax, %r14
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L44:
	movq	%r12, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3867:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z12matrixMulColPiS_S_i"
.LC12:
	.string	"_Z9matrixMulPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3901:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12matrixMulColPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9matrixMulPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3901:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>

#include <iostream>
#include <fstream>
#include <chrono>

#define TILE_DIM 64

void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);
void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol);

// __global__ void matrixMul(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
//     // Row i of matrix C
//     int row = blockIdx.y * blockDim.y + threadIdx.y;
//     // Column j of matrix C
//     int col = blockIdx.x * blockDim.x + threadIdx.x;

//     int accu = 0;
//     if(row<N && col<N) {
//         for(int k=0; k<N; k++) {
//             accu = accu + A_gpu[row*N+k] * B_gpu[k*N+col];
//         }
//         C_gpu[row*N+col] = accu;
//     }
// }

__global__ void matrixMul(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
    int accu = 0;

    int row = blockIdx.y*TILE_DIM + threadIdx.y;
    int col = blockIdx.x*TILE_DIM + threadIdx.x;

    __shared__ int shd_A[TILE_DIM][TILE_DIM];
    __shared__ int shd_B[TILE_DIM][TILE_DIM];

    for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {

         if (k*TILE_DIM + threadIdx.x < N && row < N)
             shd_A[threadIdx.y][threadIdx.x] = A_cpu[row*N + k*TILE_DIM + threadIdx.x];
         else
             shd_A[threadIdx.y][threadIdx.x] = 0.0;

         if (k*TILE_DIM + threadIdx.y < N && col < N)
             shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
         else
             shd_B[threadIdx.y][threadIdx.x] = 0.0;

         __syncthreads();

         for (int k = 0; k<TILE_DIM; k++)
             accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];

         __syncthreads();
    }

    if (row < N && col < N)
        C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
           (blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}

// __global__ void matrixMulCol(int* A_gpu, int* B_gpu, int* C_gpu, int N) {
//     // Row i of matrix C
//     int row = blockIdx.y * blockDim.y + threadIdx.y;
//     // Column j of matrix C
//     int col = blockIdx.x * blockDim.x + threadIdx.x;
    
//     int accu = 0;
//     if(row<N && col<N) {
//         for(int k=0; k<N; k++) {
//             accu = accu + A_gpu[k*N+row] * B_gpu[k*N+col];
//         }
//         C_gpu[row*N+col] = accu;
//     }
// }

__global__ void matrixMulCol(int* A_cpu, int* B_cpu, int* C_cpu, int N)
{
    int accu = 0;

    int row = blockIdx.y*TILE_DIM + threadIdx.y;
    int col = blockIdx.x*TILE_DIM + threadIdx.x;

    __shared__ int shd_A[TILE_DIM][TILE_DIM];
    __shared__ int shd_B[TILE_DIM][TILE_DIM];

    for (int k = 0; k < (TILE_DIM + N - 1)/TILE_DIM; k++) {

         if (k*TILE_DIM + threadIdx.x < N && row < N)
             shd_A[threadIdx.y][threadIdx.x] = A_cpu[(k*TILE_DIM + threadIdx.x)*N + row];
         else
             shd_A[threadIdx.y][threadIdx.x] = 0.0;

         if (k*TILE_DIM + threadIdx.y < N && col < N)
             shd_B[threadIdx.y][threadIdx.x] = B_cpu[(k*TILE_DIM + threadIdx.y)*N + col];
         else
             shd_B[threadIdx.y][threadIdx.x] = 0.0;

         __syncthreads();

         for (int k=0; k<TILE_DIM; k++)
             accu += shd_A[threadIdx.y][k] * shd_B[k][threadIdx.x];

         __syncthreads();
    }

    if (row < N && col < N)
        C_cpu[((blockIdx.y * blockDim.y + threadIdx.y)*N) +
           (blockIdx.x * blockDim.x)+ threadIdx.x] = accu;
}
    
void random_ints(int* x, int size)
    {
        srand(time(0)); 
        int i;
        for (i=0;i<size;i++) {
            x[i]=rand()%10;
            //std::cout << x[i] << " ";
        }
    }

void matrixMulCPU(int* A_cpu, int* B_cpu, int* C_cpu, int N) {
    for(int row=0; row<N; row++) {
        for(int col=0; col<N; col++){
            C_cpu[row*N+col] = 0;
            for(int elm=0; elm<N; elm++) {
                C_cpu[row*N+col] = C_cpu[row*N+col] + A_cpu[row*N+elm] * B_cpu[elm*N+col];
            }
        }
    }
}


int main(int argc, char* argv[]){
    //int N = 3;
    int N = atoi(argv[1]);
    bool memCol = false;
    if (strcmp(argv[4],"MC")==0) {
        memCol=true;
    }
    int NN = N*N;
    //define A_cpu, B_cpu, C_cpu in the CPU memory
    int *A_cpu, *B_cpu, *C_cpu;

    int size = NN * sizeof(int);

    // Setup input values
    //std::cout << "A: ";
    A_cpu = (int*)malloc(size); random_ints(A_cpu, NN);
    //std::cout << "\nB: ";
    B_cpu = (int*)malloc(size); random_ints(B_cpu, NN);
    C_cpu = (int*)malloc(size);  
    if (strcmp(argv[2],"gpu")==0) {
        if(strcmp(argv[3],"MT")==0) {
            gpuMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
        }
        else {
            gpuNoMemTransfer(A_cpu, B_cpu, C_cpu, N, size, memCol);
        }

    }
    else {
        auto t1 = std::chrono::high_resolution_clock::now();
        matrixMulCPU(A_cpu, B_cpu, C_cpu, N);
        auto t2 = std::chrono::high_resolution_clock::now();
        auto duration = std::chrono::duration_cast<std::chrono::microseconds>( t2 - t1 ).count();
        std::cout << "N: " << N << "\tCPU time: " << duration << "us" << std::endl;
    }
    //std::cout << "\nC: " << C_cpu[0] << " " << C_cpu[1] << " " <<C_cpu[2] << " " << C_cpu[3] << " " << C_cpu[4] <<" " << C_cpu[7] <<" " << C_cpu[8] <<"\n";
    free(A_cpu); free(B_cpu); free(C_cpu);
    return 0;
}
    

void gpuMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
    //define A_gpu, B_gpu, C_gpu in the GPU memory
    //std::cout << "\nMem Tr\n";
    int *A_gpu, *B_gpu, *C_gpu;

    hipMalloc((void **)&A_gpu, size);
    hipMalloc((void **)&B_gpu, size);
    hipMalloc((void **)&C_gpu, size);

    dim3 dimBlock(16, 16);
    dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);

    float time = 0;
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    if (memCol==true) {
        //std::cout << "MC\n";
        hipEventRecord( start, 0 );

        // Copy inputs to device
        hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
        hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);

        matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);

        //memcopy C_gpu to C_cpu
        hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
        //stop time
        hipEventRecord( stop, 0 );
    }
    else {
        //std::cout << "nmc\n";
        hipEventRecord( start, 0 );

        // Copy inputs to device
        hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
        hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);

        matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);

        //memcopy C_gpu to C_cpu
        hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
        //stop time
        hipEventRecord( stop, 0 );
    }
    hipEventSynchronize( stop );
    hipEventElapsedTime( &time, start, stop );
    hipEventDestroy( start );
    hipEventDestroy( stop );
    hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
    float microsec = (time)*1000;
    std::cout << "N: " << N << "\tMT\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}

void gpuNoMemTransfer(int* A_cpu, int* B_cpu, int* C_cpu, int N, int size, bool memCol) {
    //define A_gpu, B_gpu, C_gpu in the GPU memory
    //std::cout << "\nNoMem Tr\n";
    int *A_gpu, *B_gpu, *C_gpu;

    hipMalloc((void **)&A_gpu, size);
    hipMalloc((void **)&B_gpu, size);
    hipMalloc((void **)&C_gpu, size);

    // Copy inputs to device
    hipMemcpy(A_gpu, A_cpu, size, hipMemcpyHostToDevice);
    hipMemcpy(B_gpu, B_cpu, size, hipMemcpyHostToDevice);

    dim3 dimBlock(16, 16);
    dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x, (N+dimBlock.y-1)/dimBlock.y);

    float time = 0;
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
    if (memCol==true) {
        //std::cout << "MC\n";
        hipEventRecord( start, 0 );
        matrixMulCol<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
        hipEventRecord( stop, 0 );
    }
    else {
        //std::cout << "nmc\n";
        hipEventRecord( start, 0 );
        matrixMul<<<dimGrid, dimBlock>>>(A_gpu,B_gpu,C_gpu,N);
        hipEventRecord( stop, 0 );
    }
    hipEventSynchronize( stop );
    hipEventElapsedTime( &time, start, stop );
    hipEventDestroy( start );
    hipEventDestroy( stop );
    //memcopy C_gpu to C_cpu
    hipMemcpy(C_cpu, C_gpu, size, hipMemcpyDeviceToHost);
    hipFree(A_gpu); hipFree(B_gpu); hipFree(C_gpu);
    float microsec = (time)*1000;
    std::cout << "N: " << N << "\tnt\t" << memCol << "\tGPU time: " << microsec << "us" << std::endl;
}

	.text
	.file	"tile.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
	.type	_Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i:    # @_Z24__device_stub__matrixMulPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9matrixMulPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__matrixMulColPiS_S_i # -- Begin function _Z27__device_stub__matrixMulColPiS_S_i
	.type	_Z27__device_stub__matrixMulColPiS_S_i,@function
_Z27__device_stub__matrixMulColPiS_S_i: # @_Z27__device_stub__matrixMulColPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12matrixMulColPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__matrixMulColPiS_S_i, .Lfunc_end1-_Z27__device_stub__matrixMulColPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11random_intsPii              # -- Begin function _Z11random_intsPii
	.type	_Z11random_intsPii,@function
_Z11random_intsPii:                     # @_Z11random_intsPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	testl	%ebp, %ebp
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12matrixMulCPUPiS_S_i         # -- Begin function _Z12matrixMulCPUPiS_S_i
	.type	_Z12matrixMulCPUPiS_S_i,@function
_Z12matrixMulCPUPiS_S_i:                # @_Z12matrixMulCPUPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB3_7
# %bb.1:                                # %.preheader.lr.ph
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%edx, %edx
	xorl	%r10d, %r10d
.LBB3_2:                                # %.lr.ph33
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_3 Depth 2
                                        #       Child Loop BB3_4 Depth 3
	movl	%edx, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	movq	-8(%rsp), %r9                   # 8-byte Reload
	leaq	(%r9,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB3_3:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_4 Depth 3
	movl	$0, (%rbx,%r15,4)
	xorl	%r12d, %r12d
	movq	%r14, %r13
	xorl	%ebp, %ebp
.LBB3_4:                                #   Parent Loop BB3_2 Depth=1
                                        #     Parent Loop BB3_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%r13), %r9d
	imull	(%r11,%r12,4), %r9d
	addl	%r9d, %ebp
	movl	%ebp, (%rbx,%r15,4)
	incq	%r12
	addq	%r8, %r13
	cmpq	%r12, %rax
	jne	.LBB3_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB3_3 Depth=2
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB3_3
# %bb.6:                                # %._crit_edge34
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%r10
	addl	%ecx, %edx
	cmpq	%rax, %r10
	jne	.LBB3_2
.LBB3_7:                                # %._crit_edge36
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z12matrixMulCPUPiS_S_i, .Lfunc_end3-_Z12matrixMulCPUPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r13
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	32(%r13), %rdi
	movl	$.L.str, %esi
	callq	strcmp
	movl	%eax, 16(%rsp)                  # 4-byte Spill
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	movl	%ebx, %r15d
	imull	%r15d, %r15d
	leal	(,%r15,4), %r12d
	movslq	%r12d, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%rax, %rdi
	movl	%r15d, %esi
	callq	_Z11random_intsPii
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbp
	movq	%rax, %rdi
	movl	%r15d, %esi
	callq	_Z11random_intsPii
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	16(%r13), %rdi
	movl	$.L.str.1, %esi
	callq	strcmp
	testl	%eax, %eax
	je	.LBB4_1
# %bb.4:
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rbx
	movq	%r14, %rdi
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	movq	%rbp, %r15
	movq	%rbp, %rsi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	12(%rsp), %ebp                  # 4-byte Reload
	movl	%ebp, %ecx
	callq	_Z12matrixMulCPUPiS_S_i
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	%rbx, %rax
	movabsq	$2361183241434822607, %rcx      # imm = 0x20C49BA5E353F7CF
	imulq	%rcx
	movq	%rdx, %rbx
	shrq	$63, %rbx
	sarq	$7, %rdx
	addq	%rdx, %rbx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$3, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movl	$.L.str.4, %esi
	movl	$11, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%r15, %rbp
	movq	16(%rsp), %r15                  # 8-byte Reload
	jmp	.LBB4_5
.LBB4_1:
	movl	16(%rsp), %ebx                  # 4-byte Reload
	movq	24(%r13), %rdi
	movl	$.L.str.2, %esi
	callq	strcmp
	xorl	%r9d, %r9d
	testl	%eax, %eax
	je	.LBB4_2
# %bb.3:
	testl	%ebx, %ebx
	sete	%r9b
	movq	%r14, %rdi
	movq	%rbp, %rsi
	movq	%r15, %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	movl	%r12d, %r8d
	callq	_Z16gpuNoMemTransferPiS_S_iib
	jmp	.LBB4_5
.LBB4_2:
	testl	%ebx, %ebx
	sete	%r9b
	movq	%r14, %rdi
	movq	%rbp, %rsi
	movq	%r15, %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	movl	%r12d, %r8d
	callq	_Z14gpuMemTransferPiS_S_iib
.LBB4_5:
	movq	%r14, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z14gpuMemTransferPiS_S_iib
.LCPI5_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	_Z14gpuMemTransferPiS_S_iib
	.type	_Z14gpuMemTransferPiS_S_iib,@function
_Z14gpuMemTransferPiS_S_iib:            # @_Z14gpuMemTransferPiS_S_iib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r15d
	movl	%ecx, %ebx
	movq	%rdx, 64(%rsp)                  # 8-byte Spill
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movslq	%r8d, %r12
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%rbx, 8(%rsp)                   # 8-byte Spill
	leal	15(%rbx), %eax
	shrl	$4, %eax
	movq	%rax, %r14
	shlq	$32, %r14
	orq	%rax, %r14
	movl	$0, 52(%rsp)
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbp, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%r15d, %r15d
	je	.LBB5_3
# %bb.1:
	testl	%eax, %eax
	movq	8(%rsp), %r14                   # 8-byte Reload
	jne	.LBB5_5
# %bb.2:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z27__device_stub__matrixMulColPiS_S_i
	jmp	.LBB5_5
.LBB5_3:
	testl	%eax, %eax
	movq	8(%rsp), %r14                   # 8-byte Reload
	jne	.LBB5_5
# %bb.4:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z24__device_stub__matrixMulPiS_S_i
.LBB5_5:
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	56(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	mulss	.LCPI5_0(%rip), %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$3, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movzbl	%r15b, %esi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIbEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.7, %esi
	movl	$11, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z14gpuMemTransferPiS_S_iib, .Lfunc_end5-_Z14gpuMemTransferPiS_S_iib
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z16gpuNoMemTransferPiS_S_iib
.LCPI6_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	_Z16gpuNoMemTransferPiS_S_iib
	.type	_Z16gpuNoMemTransferPiS_S_iib,@function
_Z16gpuNoMemTransferPiS_S_iib:          # @_Z16gpuNoMemTransferPiS_S_iib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%ecx, %ebx
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movslq	%r8d, %r12
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbp, %rsi
	movq	%rbx, %rbp
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%rbx), %eax
	shrl	$4, %eax
	movq	%rax, %rbx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	$0, 44(%rsp)
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%r14d, %r14d
	je	.LBB6_3
# %bb.1:
	testl	%eax, %eax
	jne	.LBB6_5
# %bb.2:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z27__device_stub__matrixMulColPiS_S_i
	jmp	.LBB6_5
.LBB6_3:
	testl	%eax, %eax
	jne	.LBB6_5
# %bb.4:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z24__device_stub__matrixMulPiS_S_i
.LBB6_5:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	44(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	movq	48(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	mulss	.LCPI6_0(%rip), %xmm0
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$3, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.8, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movzbl	%r14b, %esi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIbEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.7, %esi
	movl	$11, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	24(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z16gpuNoMemTransferPiS_S_iib, .Lfunc_end6-_Z16gpuNoMemTransferPiS_S_iib
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9matrixMulPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12matrixMulColPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9matrixMulPiS_S_i,@object     # @_Z9matrixMulPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z9matrixMulPiS_S_i
	.p2align	3, 0x0
_Z9matrixMulPiS_S_i:
	.quad	_Z24__device_stub__matrixMulPiS_S_i
	.size	_Z9matrixMulPiS_S_i, 8

	.type	_Z12matrixMulColPiS_S_i,@object # @_Z12matrixMulColPiS_S_i
	.globl	_Z12matrixMulColPiS_S_i
	.p2align	3, 0x0
_Z12matrixMulColPiS_S_i:
	.quad	_Z27__device_stub__matrixMulColPiS_S_i
	.size	_Z12matrixMulColPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"MC"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"gpu"
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"MT"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"N: "
	.size	.L.str.3, 4

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\tCPU time: "
	.size	.L.str.4, 12

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"us"
	.size	.L.str.5, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\tMT\t"
	.size	.L.str.6, 5

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\tGPU time: "
	.size	.L.str.7, 12

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\tnt\t"
	.size	.L.str.8, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9matrixMulPiS_S_i"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12matrixMulColPiS_S_i"
	.size	.L__unnamed_2, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
	.addrsig_sym _Z27__device_stub__matrixMulColPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9matrixMulPiS_S_i
	.addrsig_sym _Z12matrixMulColPiS_S_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9matrixMulPiS_S_i     ; -- Begin function _Z9matrixMulPiS_S_i
	.globl	_Z9matrixMulPiS_S_i
	.p2align	8
	.type	_Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:                    ; @_Z9matrixMulPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s15, 6, v1
	v_lshl_add_u32 v0, s14, 6, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v5
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v7, 8, v1
	v_mul_lo_u32 v9, v6, s10
	s_delay_alu instid0(VALU_DEP_3)
	v_or_b32_e32 v8, 0x4000, v3
	v_cmp_gt_i32_e32 vcc_lo, s10, v6
	v_cmp_gt_i32_e64 s2, s10, v0
	v_add_nc_u32_e32 v10, v7, v3
	s_add_i32 s3, s10, 63
	v_add_nc_u32_e32 v11, v8, v7
	s_lshr_b32 s11, s3, 6
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s13, s12, 6
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v12, s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s3, s10, v12
	s_and_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v3, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_u32 v12, s3, s4, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s5, v13, s3
	global_load_b32 v3, v[12:13], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, s13, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v3
	v_cmp_gt_u32_e64 s3, s10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_and_saveexec_b32 s13, s3
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[13:14], null, v12, s10, v[0:1]
	v_mov_b32_e32 v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_add_co_u32 v12, s3, s6, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
	global_load_b32 v13, v[12:13], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v3, v8
	s_mov_b32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s3, v7
	s_add_i32 s3, s3, 4
	ds_load_b32 v14, v3
	ds_load_b32 v15, v12
	s_cmpk_eq_i32 s3, 0x100
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[12:13], null, v14, v15, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v12 :: v_dual_add_nc_u32 v3, 0x100, v3
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s11
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_10
.LBB0_9:
	v_mov_b32_e32 v2, 0
.LBB0_10:                               ; %Flow63
	v_max_i32_e32 v0, v6, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	s_load_b32 s0, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_mad_u64_u32 v[3:4], null, s15, s1, v[1:2]
	s_mul_i32 s14, s14, s0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v3, s10
	v_add3_u32 v0, s14, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9matrixMulPiS_S_i
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 19
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12matrixMulColPiS_S_i ; -- Begin function _Z12matrixMulColPiS_S_i
	.globl	_Z12matrixMulColPiS_S_i
	.p2align	8
	.type	_Z12matrixMulColPiS_S_i,@function
_Z12matrixMulColPiS_S_i:                ; @_Z12matrixMulColPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s15, 6, v1
	v_lshl_add_u32 v2, s14, 6, v4
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB1_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v7, 2, v4
	v_lshlrev_b32_e32 v5, 8, v1
	v_cmp_gt_i32_e32 vcc_lo, s10, v0
	v_cmp_gt_i32_e64 s2, s10, v2
	v_mov_b32_e32 v9, 0
	v_or_b32_e32 v6, 0x4000, v7
	v_mov_b32_e32 v3, 0
	v_add_nc_u32_e32 v7, v5, v7
	s_add_i32 s3, s10, 63
	s_mov_b32 s12, 0
	v_add_nc_u32_e32 v8, v6, v5
	s_lshr_b32 s11, s3, 6
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	s_lshl_b32 s13, s12, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s13, v4
	v_cmp_gt_u32_e64 s3, s10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s10, v[0:1]
	v_mov_b32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	v_add_co_u32 v10, s3, s4, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s5, v11, s3
	global_load_b32 v10, v[10:11], off
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s13, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v10
	v_cmp_gt_u32_e64 s3, s10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_and_saveexec_b32 s13, s3
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s10, v[2:3]
	v_mov_b32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	v_add_co_u32 v10, s3, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s7, v11, s3
	global_load_b32 v12, v[10:11], off
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v10, v6
	s_mov_b32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s3, v5
	s_add_i32 s3, s3, 4
	ds_load_b32 v13, v10
	ds_load_b32 v14, v11
	s_cmpk_eq_i32 s3, 0x100
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[11:12], null, v13, v14, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v11 :: v_dual_add_nc_u32 v10, 0x100, v10
	s_cbranch_scc0 .LBB1_7
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s11
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
	s_branch .LBB1_10
.LBB1_9:
	v_mov_b32_e32 v3, 0
.LBB1_10:                               ; %Flow63
	v_max_i32_e32 v0, v0, v2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB1_12
; %bb.11:
	s_load_b32 s0, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_mad_u64_u32 v[5:6], null, s15, s1, v[1:2]
	s_mul_i32 s14, s14, s0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v5, s10
	v_add3_u32 v0, s14, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB1_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12matrixMulColPiS_S_i
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12matrixMulColPiS_S_i, .Lfunc_end1-_Z12matrixMulColPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 592
; NumSgprs: 19
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9matrixMulPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z9matrixMulPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12matrixMulColPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z12matrixMulColPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
