#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#include <math.h>
#include "link.h"

using namespace std;

__global__ void link(int *bin, int *list, int *bnei, int *bnum,
	int *potCon, int *potConSize, int *npcnpt, 
	int *nsegpt, int *nxbinpt, int *nybinpt, int *nzbinpt){

	int npcn = *npcnpt;
	int nseg = *nsegpt;
	int nxbin = *nxbinpt;
	int nybin = *nybinpt;
	int nzbin = *nzbinpt;

	int mi = blockIdx.x; 
	int tid = threadIdx.x; 
	int miBin = bnum[mi]; 
	int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin]; 
	int nextTot = bin[nextBin]; 

	int nj, i, pos; 

	if (tid == 0){
		potConSize[mi] = 0; 
	}
	__syncthreads(); 

	for (i = 0; i < nextTot; i++){
		nj = list[nextBin + i*nxbin*nybin*nzbin];
		// skip when segments are connected
		if (mi >= nj){
			continue;
		}
		if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
			continue;
		}
		if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
			continue;
		}
		if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
			continue;
		}
		if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
			continue;
		}
		//printf("link mi nj %4d %4d\n", mi, nj); 
		pos = atomicAdd(potConSize + mi, 1); 
		if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos); 
		potCon[mi * npcn + pos] = nj; 
	}
}

	.file	"tmpxft_00275c25_00000000-6_link.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.type	_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_, @function
_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	288(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	104(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	104(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z4linkPiS_S_S_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 288
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_, .-_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.type	_Z4linkPiS_S_S_S_S_S_S_S_S_S_, @function
_Z4linkPiS_S_S_S_S_S_S_S_S_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z4linkPiS_S_S_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2052:
	.size	_Z4linkPiS_S_S_S_S_S_S_S_S_S_, .-_Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4linkPiS_S_S_S_S_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4linkPiS_S_S_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include "link.h"

using namespace std;

__global__ void link(int *bin, int *list, int *bnei, int *bnum,
	int *potCon, int *potConSize, int *npcnpt, 
	int *nsegpt, int *nxbinpt, int *nybinpt, int *nzbinpt){

	int npcn = *npcnpt;
	int nseg = *nsegpt;
	int nxbin = *nxbinpt;
	int nybin = *nybinpt;
	int nzbin = *nzbinpt;

	int mi = blockIdx.x; 
	int tid = threadIdx.x; 
	int miBin = bnum[mi]; 
	int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin]; 
	int nextTot = bin[nextBin]; 

	int nj, i, pos; 

	if (tid == 0){
		potConSize[mi] = 0; 
	}
	__syncthreads(); 

	for (i = 0; i < nextTot; i++){
		nj = list[nextBin + i*nxbin*nybin*nzbin];
		// skip when segments are connected
		if (mi >= nj){
			continue;
		}
		if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
			continue;
		}
		if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
			continue;
		}
		if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
			continue;
		}
		if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
			continue;
		}
		//printf("link mi nj %4d %4d\n", mi, nj); 
		pos = atomicAdd(potConSize + mi, 1); 
		if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos); 
		potCon[mi * npcn + pos] = nj; 
	}
}

	.text
	.file	"link.hip"
	.globl	_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_
	.type	_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_,@function
_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_: # @_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4linkPiS_S_S_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4linkPiS_S_S_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4linkPiS_S_S_S_S_S_S_S_S_S_,@object # @_Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z4linkPiS_S_S_S_S_S_S_S_S_S_:
	.quad	_Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_
	.size	_Z4linkPiS_S_S_S_S_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4linkPiS_S_S_S_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__linkPiS_S_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4linkPiS_S_S_S_S_S_S_S_S_S_ ; -- Begin function _Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.globl	_Z4linkPiS_S_S_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z4linkPiS_S_S_S_S_S_S_S_S_S_,@function
_Z4linkPiS_S_S_S_S_S_S_S_S_S_:          ; @_Z4linkPiS_S_S_S_S_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x2
	s_load_b128 s[20:23], s[0:1], 0x40
	s_load_b512 s[4:19], s[0:1], 0x0
	s_load_b64 s[24:25], s[0:1], 0x50
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_load_b32 s26, s[20:21], 0x0
	s_load_b32 s31, s[22:23], 0x0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_mov_b32 s3, exec_lo
	s_add_u32 s22, s10, s20
	s_addc_u32 s23, s11, s21
	s_load_b32 s10, s[24:25], 0x0
	s_load_b32 s22, s[22:23], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s31, s31, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s31, v0
	v_mad_u64_u32 v[1:2], null, v3, s10, s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v29, v[1:2], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[29:30]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v30, v[1:2], off
	s_load_b32 s33, s[16:17], 0x0
	s_load_b32 s8, s[18:19], 0x0
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mov_b32_e32 v0, 0
	s_add_u32 s4, s14, s20
	s_addc_u32 s5, s15, s21
	global_store_b32 v0, v0, s[4:5]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_i32_e32 0, v30
	s_cbranch_execz .LBB0_185
; %bb.3:                                ; %.lr.ph
	s_add_i32 s3, s2, -1
	s_add_i32 s26, s8, -1
	s_add_i32 s27, s2, 1
	s_add_u32 s4, s14, s20
	s_addc_u32 s5, s15, s21
	s_add_i32 s28, s33, -1
	s_add_u32 s14, s0, 0x58
	s_addc_u32 s15, s1, 0
	s_ashr_i32 s0, s8, 31
	s_ashr_i32 s9, s2, 31
	s_add_i32 s8, s8, s0
	v_mov_b32_e32 v2, 0
	s_xor_b32 s29, s8, s0
	s_add_i32 s8, s2, s9
	v_cvt_f32_u32_e32 v0, s29
	s_sub_i32 s1, 0, s29
	s_xor_b32 s8, s8, s9
	v_mbcnt_lo_u32_b32 v31, -1, 0
	v_mov_b32_e32 v6, 1
	v_rcp_iflag_f32_e32 v0, v0
	s_mul_i32 s31, s31, s10
	s_mul_i32 s33, s33, s2
	s_mov_b32 s34, 0
	s_mov_b32 s37, 0
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v5, 2 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v0, 33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s0
	s_mul_hi_u32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s30, s0, s1
	s_mul_hi_u32 s0, s8, s30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s29
	s_sub_i32 s0, s8, s0
	s_mov_b32 s8, 0
	s_sub_i32 s1, s0, s29
	s_cmp_ge_u32 s0, s29
	s_cselect_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s1, s0, s29
	s_cmp_ge_u32 s0, s29
	s_cselect_b32 s0, s1, s0
	s_xor_b32 s0, s0, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s9
	s_cmp_lg_u32 s0, 0
	s_cselect_b32 s1, -1, 0
	s_cmp_lg_u32 s0, s26
	s_cselect_b32 s0, -1, 0
	s_xor_b32 s35, s1, -1
	s_xor_b32 s36, s0, -1
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;     Child Loop BB0_23 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_38 Depth 2
                                        ;     Child Loop BB0_41 Depth 2
                                        ;       Child Loop BB0_44 Depth 3
                                        ;       Child Loop BB0_52 Depth 3
                                        ;       Child Loop BB0_60 Depth 3
                                        ;       Child Loop BB0_68 Depth 3
                                        ;       Child Loop BB0_76 Depth 3
                                        ;       Child Loop BB0_84 Depth 3
                                        ;       Child Loop BB0_92 Depth 3
                                        ;       Child Loop BB0_100 Depth 3
                                        ;       Child Loop BB0_108 Depth 3
                                        ;       Child Loop BB0_114 Depth 3
                                        ;       Child Loop BB0_123 Depth 3
                                        ;     Child Loop BB0_131 Depth 2
                                        ;     Child Loop BB0_139 Depth 2
                                        ;     Child Loop BB0_145 Depth 2
                                        ;     Child Loop BB0_154 Depth 2
                                        ;     Child Loop BB0_159 Depth 2
                                        ;     Child Loop BB0_167 Depth 2
                                        ;     Child Loop BB0_173 Depth 2
                                        ;     Child Loop BB0_182 Depth 2
	v_mad_u64_u32 v[3:4], null, s31, s37, v[29:30]
	s_mov_b32 s38, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v32, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 s2, v32
	s_cbranch_execz .LBB0_184
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, s3, v32
	s_or_b32 s0, s35, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_184
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v1, 31, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v32, v1
	v_xor_b32_e32 v3, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, s30
	v_mul_lo_u32 v4, v4, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_xor_b32_e32 v3, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v3, v1
	v_add_nc_u32_e32 v3, -1, v32
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, s2, v3
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_184
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, s27, v32
	s_or_b32 s0, s36, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_184
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v3, 1, v32
	v_cmp_eq_u32_e32 vcc_lo, s26, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, s2, v3
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_184
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s1, exec_lo
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v1, s1, 0
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=1
	s_bcnt1_i32_b32 s1, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s1
	global_atomic_add_u32 v3, v2, v3, s[4:5] glc
.LBB0_11:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v3
	s_mov_b32 s39, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v33, s0, v1
	v_cmpx_le_i32_e64 s28, v33
	s_cbranch_execz .LBB0_183
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=1
	s_load_b64 s[16:17], s[14:15], 0x50
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_18
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB0_17
; %bb.14:                               ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, 0
.LBB0_15:                               ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_15
; %bb.16:                               ; %Flow439
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_17:                               ; %Flow441
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_18:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[16:17] offset:40
	global_load_b128 v[7:10], v2, s[16:17]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v11
	v_readfirstlane_b32 s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s21
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB0_20:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s11
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v10, s9
	v_mov_b32_e32 v11, s10
	v_mov_b32_e32 v9, s8
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_28
; %bb.21:                               ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	v_mov_b32_e32 v15, s18
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s19 :: v_dual_and_b32 v1, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v1, vcc_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_24
; %bb.22:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s11, 0
.LBB0_23:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_23
.LBB0_24:                               ; %Flow437
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[16:17] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_4 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_26:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_28:                               ; %Flow438
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v1, vcc_lo, v7, s21
	v_add_co_ci_u32_e32 v4, vcc_lo, s20, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_29:                               ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_31:                               ;   in Loop: Header=BB0_29 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_34
.LBB0_33:                               ;   in Loop: Header=BB0_29 Depth=2
	s_mov_b32 s1, -1
.LBB0_34:                               ; %Flow432
                                        ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_29
; %bb.35:                               ;   in Loop: Header=BB0_4 Depth=1
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_39
; %bb.36:                               ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17] offset:24 glc
	global_load_b64 v[11:12], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_39
; %bb.37:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, 0
.LBB0_38:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_38
.LBB0_39:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_126
; %bb.40:                               ;   in Loop: Header=BB0_4 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v34, 2, v7
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v9, -3, v7
	s_mov_b64 s[18:19], 40
.LBB0_41:                               ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_44 Depth 3
                                        ;       Child Loop BB0_52 Depth 3
                                        ;       Child Loop BB0_60 Depth 3
                                        ;       Child Loop BB0_68 Depth 3
                                        ;       Child Loop BB0_76 Depth 3
                                        ;       Child Loop BB0_84 Depth 3
                                        ;       Child Loop BB0_92 Depth 3
                                        ;       Child Loop BB0_100 Depth 3
                                        ;       Child Loop BB0_108 Depth 3
                                        ;       Child Loop BB0_114 Depth 3
                                        ;       Child Loop BB0_123 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[18:19], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s20, s18, 56
	s_cselect_b32 s21, s19, 0
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_46
; %bb.42:                               ;   in Loop: Header=BB0_41 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_45
; %bb.43:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_lshl_b64 s[0:1], s[20:21], 3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[10:11]
.LBB0_44:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[24:25]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_add_u32 s24, s24, 1
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s0, s22
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB0_44
.LBB0_45:                               ; %Flow408
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_47
.LBB0_46:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr9
.LBB0_47:                               ; %Flow410
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_49
; %bb.48:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[11:12], v2, s[10:11]
	s_add_i32 s9, s20, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_49:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_54
; %bb.50:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_53
; %bb.51:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_52:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s40, s0, s24
	s_addc_u32 s41, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v1, v2, s[40:41]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB0_52
.LBB0_53:                               ; %Flow403
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
	s_mov_b32 s40, 0
	s_branch .LBB0_55
.LBB0_54:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr40
.LBB0_55:                               ; %Flow405
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_57
; %bb.56:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s40, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_57:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s40, 7
	s_cbranch_scc1 .LBB0_62
; %bb.58:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s40, 0
	s_cbranch_scc1 .LBB0_61
; %bb.59:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_60:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s42, s0, s24
	s_addc_u32 s43, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v1, v2, s[42:43]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s40, s24
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB0_60
.LBB0_61:                               ; %Flow398
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_63
.LBB0_62:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $sgpr9
.LBB0_63:                               ; %Flow400
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s9, s40, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_65:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_70
; %bb.66:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_69
; %bb.67:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_68:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s40, s0, s24
	s_addc_u32 s41, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v1, v2, s[40:41]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB0_68
.LBB0_69:                               ; %Flow393
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
	s_mov_b32 s40, 0
	s_branch .LBB0_71
.LBB0_70:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr40
.LBB0_71:                               ; %Flow395
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_73
; %bb.72:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s40, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_73:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s40, 7
	s_cbranch_scc1 .LBB0_78
; %bb.74:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s40, 0
	s_cbranch_scc1 .LBB0_77
; %bb.75:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_76:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s42, s0, s24
	s_addc_u32 s43, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v1, v2, s[42:43]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s40, s24
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_76
.LBB0_77:                               ; %Flow388
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_79
.LBB0_78:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $sgpr9
.LBB0_79:                               ; %Flow390
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_81
; %bb.80:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s9, s40, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_81:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_86
; %bb.82:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_85
; %bb.83:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_84:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s40, s0, s24
	s_addc_u32 s41, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v1, v2, s[40:41]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_84
.LBB0_85:                               ; %Flow383
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
	s_mov_b32 s40, 0
	s_branch .LBB0_87
.LBB0_86:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr40
.LBB0_87:                               ; %Flow385
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_89
; %bb.88:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s40, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_89:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_cmp_gt_u32 s40, 7
	s_cbranch_scc1 .LBB0_94
; %bb.90:                               ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s40, 0
	s_cbranch_scc1 .LBB0_93
; %bb.91:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[0:1]
.LBB0_92:                               ; %.preheader.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[24:25]
	s_add_i32 s40, s40, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s22, v[1:2]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_add_u32 s24, s24, 1
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s40, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_92
.LBB0_93:                               ; %Flow378
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s9, 0
	s_branch .LBB0_95
.LBB0_94:                               ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s9, -1
.LBB0_95:                               ; %Flow380
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_97
; %bb.96:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[23:24], v2, s[0:1]
.LBB0_97:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_103
; %bb.98:                               ;   in Loop: Header=BB0_41 Depth=2
	global_load_b64 v[27:28], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[25:26], v2, s[16:17]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v35, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v35, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB0_102
; %bb.99:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s22, 0
.LBB0_100:                              ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[16:17] offset:40
	global_load_b64 v[35:36], v2, s[16:17]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[35:36]
	v_and_b32_e32 v35, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v35, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_100
; %bb.101:                              ; %Flow373
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_102:                              ; %Flow375
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_103:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[35:36], v2, s[16:17] offset:40
	global_load_b128 v[25:28], v2, s[16:17]
	v_readfirstlane_b32 s22, v3
	v_readfirstlane_b32 s23, v4
	s_mov_b32 s41, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s24, v35
	v_readfirstlane_b32 s25, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[24:25], s[22:23], s[24:25]
	s_mul_i32 s1, s25, 24
	s_mul_hi_u32 s9, s24, 24
	s_mul_i32 s40, s24, 24
	s_and_saveexec_b32 s42, s0
	s_cbranch_execz .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_41 Depth=2
	v_dual_mov_b32 v3, s41 :: v_dual_mov_b32 v4, v2
	s_add_i32 s41, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v35, vcc_lo, v25, s40
	v_add_co_ci_u32_e32 v36, vcc_lo, s41, v26, vcc_lo
	global_store_b128 v[35:36], v[3:6], off offset:8
.LBB0_105:                              ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s42
	v_cmp_gt_u64_e64 vcc_lo, s[18:19], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v34
	s_lshl_b64 s[24:25], s[24:25], 12
	s_lshl_b32 s41, s20, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s41, s41, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s24
	v_add_co_ci_u32_e32 v27, vcc_lo, s25, v28, vcc_lo
	s_and_b32 s41, s41, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s41
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_113
; %bb.106:                              ;   in Loop: Header=BB0_41 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	v_dual_mov_b32 v15, s22 :: v_dual_mov_b32 v16, s23
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s42, v9
	v_readfirstlane_b32 s43, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[42:43], s[42:43], s[22:23]
	s_mul_i32 s25, s43, 24
	s_mul_hi_u32 s41, s42, 24
	s_mul_i32 s42, s42, 24
	s_add_i32 s41, s41, s25
	v_add_co_u32 v13, vcc_lo, v25, s42
	v_add_co_ci_u32_e32 v14, vcc_lo, s41, v26, vcc_lo
	s_mov_b32 s25, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_109
; %bb.107:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s41, 0
.LBB0_108:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s22 :: v_dual_mov_b32 v10, s23
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s41, vcc_lo, s41
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s41
	s_cbranch_execnz .LBB0_108
.LBB0_109:                              ; %Flow371
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	global_load_b64 v[9:10], v2, s[16:17] offset:16
	s_mov_b32 s41, exec_lo
	s_mov_b32 s25, exec_lo
	v_mbcnt_lo_u32_b32 v1, s41, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_41 Depth=2
	s_bcnt1_i32_b32 s41, s41
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s41
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB0_111:                              ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_113
; %bb.112:                              ;   in Loop: Header=BB0_41 Depth=2
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s25, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s25, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_113:                              ; %Flow372
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	s_add_i32 s9, s9, s1
	v_add_co_u32 v1, vcc_lo, v25, s40
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_114:                              ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_116
; %bb.115:                              ;   in Loop: Header=BB0_114 Depth=3
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_116:                              ;   in Loop: Header=BB0_114 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_118
; %bb.117:                              ;   in Loop: Header=BB0_114 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_119
.LBB0_118:                              ;   in Loop: Header=BB0_114 Depth=3
	s_mov_b32 s1, -1
.LBB0_119:                              ; %Flow366
                                        ;   in Loop: Header=BB0_114 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_114
; %bb.120:                              ;   in Loop: Header=BB0_41 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_124
; %bb.121:                              ;   in Loop: Header=BB0_41 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[15:16], v2, s[16:17] offset:24 glc
	global_load_b64 v[13:14], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s22
	v_add_co_ci_u32_e32 v12, vcc_lo, s23, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_124
; %bb.122:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_mov_b32 s0, 0
.LBB0_123:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_123
.LBB0_124:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s18, s18, s20
	s_subb_u32 s19, s19, s21
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s21
	s_cmp_lg_u64 s[18:19], 0
	s_cbranch_scc1 .LBB0_41
; %bb.125:                              ; %Flow411
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_127
.LBB0_126:                              ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_127:                              ; %Flow426
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_156
; %bb.128:                              ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_134
; %bb.129:                              ;   in Loop: Header=BB0_4 Depth=1
	global_load_b64 v[11:12], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[9:10], v2, s[16:17]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB0_133
; %bb.130:                              ; %.preheader3.i.i.i95.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, 0
.LBB0_131:                              ; %.preheader3.i.i.i95
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b64 v[13:14], v2, s[16:17]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_131
; %bb.132:                              ; %Flow423
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_133:                              ; %Flow425
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_134:                              ; %.loopexit4.i.i.i90
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[16:17] offset:40
	global_load_b128 v[11:14], v2, s[16:17]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s21
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB0_136:                              ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v16, s11
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v15, s10
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_144
; %bb.137:                              ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[16:17] offset:32 glc
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v13, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s22, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB0_140
; %bb.138:                              ; %.preheader1.i.i.i93.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s11, 0
.LBB0_139:                              ; %.preheader1.i.i.i93
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s18 :: v_dual_mov_b32 v8, s19
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_139
.LBB0_140:                              ; %Flow421
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v2, s[16:17] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_142
; %bb.141:                              ;   in Loop: Header=BB0_4 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB0_142:                              ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_144
; %bb.143:                              ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_144:                              ; %Flow422
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v1, vcc_lo, v11, s21
	v_add_co_ci_u32_e32 v8, vcc_lo, s20, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_145:                              ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_145 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_147:                              ;   in Loop: Header=BB0_145 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_149
; %bb.148:                              ;   in Loop: Header=BB0_145 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_150
.LBB0_149:                              ;   in Loop: Header=BB0_145 Depth=2
	s_mov_b32 s1, -1
.LBB0_150:                              ; %Flow416
                                        ;   in Loop: Header=BB0_145 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_145
; %bb.151:                              ;   in Loop: Header=BB0_4 Depth=1
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_155
; %bb.152:                              ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17] offset:24 glc
	global_load_b64 v[13:14], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_155
; %bb.153:                              ; %.preheader.i.i.i92.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, 0
.LBB0_154:                              ; %.preheader.i.i.i92
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_154
.LBB0_155:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_156:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_162
; %bb.157:                              ;   in Loop: Header=BB0_4 Depth=1
	global_load_b64 v[13:14], v2, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[7:8], v2, s[16:17]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB0_161
; %bb.158:                              ; %.preheader3.i.i.i102.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s10, 0
.LBB0_159:                              ; %.preheader3.i.i.i102
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_159
; %bb.160:                              ; %Flow359
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_161:                              ; %Flow361
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_162:                              ; %.loopexit4.i.i.i96
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[16:17] offset:40
	global_load_b128 v[13:16], v2, s[16:17]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v14, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB0_164:                              ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v11, v33 :: v_dual_mov_b32 v12, v2
	v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v17, s10
	v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v15, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_172
; %bb.165:                              ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v3, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s22, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB0_168
; %bb.166:                              ; %.preheader1.i.i.i100.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s11, 0
.LBB0_167:                              ; %.preheader1.i.i.i100
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s18 :: v_dual_mov_b32 v8, s19
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_167
.LBB0_168:                              ; %Flow357
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[16:17] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_170
; %bb.169:                              ;   in Loop: Header=BB0_4 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_170:                              ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_172
; %bb.171:                              ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_172:                              ; %Flow358
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v1, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v4, vcc_lo, s20, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_173:                              ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_175
; %bb.174:                              ;   in Loop: Header=BB0_173 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_175:                              ;   in Loop: Header=BB0_173 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_177
; %bb.176:                              ;   in Loop: Header=BB0_173 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_178
.LBB0_177:                              ;   in Loop: Header=BB0_173 Depth=2
	s_mov_b32 s1, -1
.LBB0_178:                              ; %Flow352
                                        ;   in Loop: Header=BB0_173 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_173
; %bb.179:                              ;   in Loop: Header=BB0_4 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_183
; %bb.180:                              ;   in Loop: Header=BB0_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[16:17] offset:40
	global_load_b64 v[11:12], v2, s[16:17] offset:24 glc
	global_load_b64 v[9:10], v2, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_183
; %bb.181:                              ; %.preheader.i.i.i99.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s0, 0
.LBB0_182:                              ; %.preheader.i.i.i99
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_182
.LBB0_183:                              ; %Flow442
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s39
	v_add_nc_u32_e32 v3, s33, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_store_b32 v[3:4], v32, off
.LBB0_184:                              ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s38
	s_add_i32 s37, s37, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s37, v30
	s_or_b32 s34, vcc_lo, s34
	s_and_not1_b32 exec_lo, exec_lo, s34
	s_cbranch_execnz .LBB0_4
.LBB0_185:                              ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4linkPiS_S_S_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4linkPiS_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z4linkPiS_S_S_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7500
; NumSgprs: 46
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"allocate more space for potCon pos %4d\n"
	.size	.str, 40

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4linkPiS_S_S_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z4linkPiS_S_S_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
