#include "includes.h"
//#define DEPTH 2



// dp - cost aggregation array
// cost_image - m x n x D array
// d - use every d channels of input to conserve register memory
// m - image rows
// n - image columns
// D - depth
// depth_stride - pitch along depth dimension
// row_stride - pitch along row dimension


__device__ float dp_criteria(float *dp, int ind, int depth_dim_size, int d, float P_one, float P_two, float * d_zero, float * d_one, float * d_two, float * d_three){
*d_zero = dp[ind];
if (d > 0)
*d_one = dp[ind - depth_dim_size] + P_one;
else
*d_one = 10000000;

if (d < D-1)
*d_two = dp[ind + depth_dim_size] + P_one;
else
*d_two = 10000000;
return fminf(fminf(*d_zero, *d_one), fminf(*d_two, *d_three)) - *d_three + P_two;

}
__global__ void __l_aggregate(float *dp, float *cost_image, int m, int n)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = n - 1 - threadIdx.x;
int depth_dim_size = m*n;
__shared__ float MinArray[SHMEM_SIZE][SHMEM_SIZE];
int K = n-1; // this variable keeps track of the progress in aggregating
// across the columns of the image

while ((col >= 0) & (row < m))
{
int ind = row * n + col;
float prev_min = 100000000.0;

for (int depth = 0; depth < D; depth+=D_STEP){
prev_min = fminf(dp[ind], prev_min);
ind += (depth_dim_size * D_STEP);
}

MinArray[threadIdx.y][SHMEM_SIZE - 1 - threadIdx.x] = prev_min;
__syncthreads();

float d0 = 0;
float d1 = 0;
float d2 = 0;

// when processing a video stream, need to make sure that processing of multiple
// frames can overlap, since after this point only one warp of threads is executing

// threads from only one warp will handle rightward aggregation across the
// region that has been loaded into shared memory
// for threads where threadIdx.y is 0, now threadIdx.x will index the rows
if (threadIdx.y == 0)
{
int agg_row = threadIdx.x + blockIdx.y * blockDim.y;
int start_K = K;
int local_K = SHMEM_SIZE - 1;

if (agg_row < m)
{
for(; (K > 0) && (K > (start_K - SHMEM_SIZE)); K--)
{
float d3 = MinArray[threadIdx.x][local_K] + (float) P2;

int ind = agg_row * n + K - 1;
for (int d = 0; d < D; d+=D_STEP){
dp[ind] += cost_image[ind] + dp_criteria(dp, ind+1, depth_dim_size, d, (float) P1, (float) P2, &d0, &d1, &d2, &d3);
//dp[ind] = cost_image[ind] + dp[ind - 1];
ind += (depth_dim_size * D_STEP);
}
local_K--;
}
}
}

__syncthreads();
col-=blockDim.x;

}

}
	.file	"tmpxft_00328c5b_00000000-6___l_aggregate.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11dp_criteriaPfiiiffS_S_S_S_
	.type	_Z11dp_criteriaPfiiiffS_S_S_S_, @function
_Z11dp_criteriaPfiiiffS_S_S_S_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z11dp_criteriaPfiiiffS_S_S_S_, .-_Z11dp_criteriaPfiiiffS_S_S_S_
	.globl	_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii
	.type	_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii, @function
_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13__l_aggregatePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii, .-_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii
	.globl	_Z13__l_aggregatePfS_ii
	.type	_Z13__l_aggregatePfS_ii, @function
_Z13__l_aggregatePfS_ii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13__l_aggregatePfS_iiPfS_ii
	.cfi_endproc
.LFE2034:
	.size	_Z13__l_aggregatePfS_ii, .-_Z13__l_aggregatePfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13__l_aggregatePfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13__l_aggregatePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
//#define DEPTH 2



// dp - cost aggregation array
// cost_image - m x n x D array
// d - use every d channels of input to conserve register memory
// m - image rows
// n - image columns
// D - depth
// depth_stride - pitch along depth dimension
// row_stride - pitch along row dimension


__device__ float dp_criteria(float *dp, int ind, int depth_dim_size, int d, float P_one, float P_two, float * d_zero, float * d_one, float * d_two, float * d_three){
*d_zero = dp[ind];
if (d > 0)
*d_one = dp[ind - depth_dim_size] + P_one;
else
*d_one = 10000000;

if (d < D-1)
*d_two = dp[ind + depth_dim_size] + P_one;
else
*d_two = 10000000;
return fminf(fminf(*d_zero, *d_one), fminf(*d_two, *d_three)) - *d_three + P_two;

}
__global__ void __l_aggregate(float *dp, float *cost_image, int m, int n)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = n - 1 - threadIdx.x;
int depth_dim_size = m*n;
__shared__ float MinArray[SHMEM_SIZE][SHMEM_SIZE];
int K = n-1; // this variable keeps track of the progress in aggregating
// across the columns of the image

while ((col >= 0) & (row < m))
{
int ind = row * n + col;
float prev_min = 100000000.0;

for (int depth = 0; depth < D; depth+=D_STEP){
prev_min = fminf(dp[ind], prev_min);
ind += (depth_dim_size * D_STEP);
}

MinArray[threadIdx.y][SHMEM_SIZE - 1 - threadIdx.x] = prev_min;
__syncthreads();

float d0 = 0;
float d1 = 0;
float d2 = 0;

// when processing a video stream, need to make sure that processing of multiple
// frames can overlap, since after this point only one warp of threads is executing

// threads from only one warp will handle rightward aggregation across the
// region that has been loaded into shared memory
// for threads where threadIdx.y is 0, now threadIdx.x will index the rows
if (threadIdx.y == 0)
{
int agg_row = threadIdx.x + blockIdx.y * blockDim.y;
int start_K = K;
int local_K = SHMEM_SIZE - 1;

if (agg_row < m)
{
for(; (K > 0) && (K > (start_K - SHMEM_SIZE)); K--)
{
float d3 = MinArray[threadIdx.x][local_K] + (float) P2;

int ind = agg_row * n + K - 1;
for (int d = 0; d < D; d+=D_STEP){
dp[ind] += cost_image[ind] + dp_criteria(dp, ind+1, depth_dim_size, d, (float) P1, (float) P2, &d0, &d1, &d2, &d3);
//dp[ind] = cost_image[ind] + dp[ind - 1];
ind += (depth_dim_size * D_STEP);
}
local_K--;
}
}
}

__syncthreads();
col-=blockDim.x;

}

}
	.text
	.file	"__l_aggregate.hip"
	.globl	_Z28__device_stub____l_aggregatePfS_ii # -- Begin function _Z28__device_stub____l_aggregatePfS_ii
	.type	_Z28__device_stub____l_aggregatePfS_ii,@function
_Z28__device_stub____l_aggregatePfS_ii: # @_Z28__device_stub____l_aggregatePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13__l_aggregatePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub____l_aggregatePfS_ii, .Lfunc_end0-_Z28__device_stub____l_aggregatePfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13__l_aggregatePfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13__l_aggregatePfS_ii,@object # @_Z13__l_aggregatePfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z13__l_aggregatePfS_ii
	.p2align	3, 0x0
_Z13__l_aggregatePfS_ii:
	.quad	_Z28__device_stub____l_aggregatePfS_ii
	.size	_Z13__l_aggregatePfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13__l_aggregatePfS_ii"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub____l_aggregatePfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13__l_aggregatePfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13__l_aggregatePfS_ii ; -- Begin function _Z13__l_aggregatePfS_ii
	.globl	_Z13__l_aggregatePfS_ii
	.p2align	8
	.type	_Z13__l_aggregatePfS_ii,@function
_Z13__l_aggregatePfS_ii:                ; @_Z13__l_aggregatePfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_u32 s4, s0, 24
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_add_i32 s3, s9, -1
	s_mul_i32 s15, s15, s2
	v_sub_nc_u32_e32 v7, s3, v2
	v_add_nc_u32_e32 v0, s15, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s2, -1, v7
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s6, s2
	s_cbranch_execz .LBB0_17
; %bb.1:                                ; %.lr.ph65
	s_load_b32 s11, s[4:5], 0xc
	s_load_b128 s[4:7], s[0:1], 0x0
	v_add_nc_u32_e32 v6, s15, v2
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_mov_b32 s10, s9
	s_mul_i32 s2, s9, s8
	v_dual_mov_b32 v8, s3 :: v_dual_lshlrev_b32 v5, 2, v2
	v_cmp_gt_i32_e64 s0, s8, v6
	v_lshlrev_b32_e32 v9, 6, v1
	v_lshlrev_b32_e32 v10, 6, v2
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 s21, vcc_lo, s0
	v_sub_nc_u32_e32 v9, v9, v5
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, s9, v0, s[10:11]
	s_and_b32 s22, s11, 0xffff
	s_add_u32 s0, s4, 4
	s_addc_u32 s1, s5, 0
	s_ashr_i32 s3, s2, 31
	v_mad_u64_u32 v[0:1], null, v6, s9, -1
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_2)
	v_xad_u32 v1, v2, -1, v3
	s_sub_u32 s8, s4, s2
	s_subb_u32 s9, s5, s3
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s10, s0, s2
	s_addc_u32 s11, s1, s3
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0x4cbebc20
	s_mov_b32 s12, 51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_max_f32_e32 v4, v4, v4
	v_add_co_u32 v2, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s12, 0
	s_waitcnt vmcnt(0)
	v_max_f32_e32 v5, v5, v5
	v_min_f32_e32 v4, v5, v4
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_store_b32 v9, v4 offset:60
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s23, s21
	s_cbranch_execz .LBB0_16
; %bb.5:                                ; %.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, -16, v8
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v11, 0, v2
	v_cmpx_gt_i32_e64 v8, v11
	s_cbranch_execz .LBB0_15
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, v0, v8
	s_mov_b32 s26, 15
	s_mov_b32 s25, 0
.LBB0_7:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
	v_lshl_add_u32 v3, s26, 2, v10
	s_mov_b32 s27, 51
	s_mov_b64 s[12:13], s[0:1]
	s_mov_b64 s[14:15], s[6:7]
	s_mov_b64 s[16:17], s[10:11]
	ds_load_b32 v4, v3
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[18:19], s[8:9]
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v12, 0x47afc800, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_max_f32_e32 v13, v12, v12
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v4, vcc_lo
	v_dual_mov_b32 v17, 0x4b189680 :: v_dual_mov_b32 v16, 0x4b189680
	global_load_b32 v14, v[14:15], off
	global_load_b32 v15, v[5:6], off
	s_cmp_eq_u32 s27, 51
	s_cbranch_scc1 .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=3
	v_add_co_u32 v18, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v19, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v16, v[18:19], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v16, 0x40a00000, v16
.LBB0_10:                               ;   in Loop: Header=BB0_8 Depth=3
	s_cmp_eq_u32 s27, 1
	s_cbranch_scc1 .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_8 Depth=3
	v_add_co_u32 v17, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v18, vcc_lo, s17, v4, vcc_lo
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v17, 0x40a00000, v17
.LBB0_12:                               ; %_Z11dp_criteriaPfiiiffS_S_S_S_.exit
                                        ;   in Loop: Header=BB0_8 Depth=3
	global_load_b32 v18, v[5:6], off offset:-4
	v_max_f32_e32 v17, v17, v17
	s_add_i32 s27, s27, -1
	s_add_u32 s18, s18, s2
	s_addc_u32 s19, s19, s3
	s_add_u32 s16, s16, s2
	v_min_f32_e32 v17, v17, v13
	s_addc_u32 s17, s17, s3
	s_add_u32 s14, s14, s2
	s_addc_u32 s15, s15, s3
	s_add_u32 s12, s12, s2
	s_waitcnt vmcnt(1)
	v_min3_f32 v15, v15, v16, v17
	s_addc_u32 s13, s13, s3
	s_cmp_eq_u32 s27, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v12
	v_add_f32_e32 v15, 0x47afc800, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v14, v15
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v18, v14
	global_store_b32 v[5:6], v14, off offset:-4
	s_cbranch_scc0 .LBB0_8
; %bb.13:                               ;   in Loop: Header=BB0_7 Depth=2
	v_add_nc_u32_e32 v8, -1, v8
	v_add_nc_u32_e32 v2, -1, v2
	s_add_i32 s26, s26, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, v8, v11
	s_or_b32 s25, vcc_lo, s25
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_7
; %bb.14:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
.LBB0_15:                               ; %Flow111
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_16:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s23
	v_subrev_nc_u32_e32 v7, s22, v7
	v_subrev_nc_u32_e32 v1, s22, v1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, 0, v7
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_2
.LBB0_17:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13__l_aggregatePfS_ii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13__l_aggregatePfS_ii, .Lfunc_end0-_Z13__l_aggregatePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 836
; NumSgprs: 30
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13__l_aggregatePfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z13__l_aggregatePfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
