#include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2            // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);

__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
    int global_y;
    int global_x = i*blockDim.y + threadIdx.y;
    for(int j=0;j<N/TILE_SIZE;j++)
    {
        global_y = j*blockDim.z + threadIdx.z;
        write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
    }
    __syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
    int global_y;
    int global_x = i*blockDim.y + threadIdx.y;
    for(int j=0;j<N/TILE_SIZE;j++)
    {
        global_y = j*blockDim.z + threadIdx.z;
        write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
        printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
    }
    __syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
    __syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
    __syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    // printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
    if(threadIdx.z >= threadIdx.y)
        write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
    else
        write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
    __syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    if(threadIdx.z >= threadIdx.y)
        write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
    else
        write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
    __syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
    int t_x = threadIdx.y;
    int t_y = threadIdx.z;
    __shared__ float temp2;
    for(int k=0;k<TILE_SIZE;k++)
    {
        if(t_x==t_y && t_x==k)
        {
            t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
            temp2 = t_A[k*(TILE_SIZE+1) + k];
        }
        __syncthreads();
        if(t_x<t_y && t_x == k)
        {
            t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
        }
        __syncthreads();
        if(k<t_y && k<t_x && t_x<=t_y)
        {
            t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
        }
        __syncthreads();
    }
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    int t_x = threadIdx.y;
    int t_y = threadIdx.z;
    for(int s=0;s<TILE_SIZE;s++)
    {
	if(t_x==s)
        {
	    row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
	}
	__syncthreads();
	if(t_x > s)
        {
	    row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) +  s]*row_data[global_y*(TILE_SIZE+1) + s];
	}
	__syncthreads();
    }
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N) 
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    int t_y = threadIdx.z;
    int t_x = threadIdx.y;
    float valueToSubtract = 0.0;
    for(int r=0;r<TILE_SIZE;r++)
    {
        valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
    }
    edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
    __syncthreads();
}

__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{

    int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0); 
    
    int tx = threadIdx.x;
    float *rA1 = NULL;

    extern __shared__ float row_data[];
    // __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)];                // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
    int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
    // __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
    int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);


    int i,j,k;
    for(i=0;i<N/TILE_SIZE;i++)
    {
        load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
        // printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
        // if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
            // for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
                // printf("%f is at %d\n", row_data[z], z);
            // }
        // }
        
        rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
        // printf("%d\n", tx*shared_size_single_matrix_tile_data);
        // potrf_tile(tile_data);
        potrf_tile(rA1);
        store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
        load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
        for(j=i+1;j<N/TILE_SIZE;j++)
        {
            trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
            for(k=i+1;k<j;k++)
            {
                load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
                rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
                // syrk_tile(row_data,tile_data,k,j,N);
                syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
                store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
            }
            load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
            syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
            store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
        }
        store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
    }
}


int main()
{
    // int n,N;
    // printf("Enter dimension (N) : ");
    // scanf("%d",&n);
    // if((n%TILE_SIZE)==0)
    //     N = n;
    // else
    //     N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
    // size_t size = N*N*sizeof(float);
    // float *M = (float *)malloc(size);
    // if(M == NULL)
    // {
    //     fprintf(stderr,"Failed to allocate host vectors!\n");
    //     exit(EXIT_FAILURE);
    // }
    // int i,j;
    // printf("Enter input matrix: \n");
    // for(i=0;i<N;i++)
    // {
    //     for(j=0;j<N;j++)
    //     {
    //         if(i>=n || j>=n)
    //             M[i*N + j] = 1;     //Padding the matrix with 1
    //         else
    //             scanf("%f",&M[i*N + j]);
    //     }
    // }

    FILE *fptr;
    fptr = fopen("./dim2_256matrices.txt", "r");
    int num_of_matrices, dim_of_matrix;
    fscanf(fptr, "%d", &num_of_matrices);
    fscanf(fptr, "%d", &dim_of_matrix);
    float read_element;
    float* h_A = NULL;
    int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
    size_t size = numElements * sizeof(float);
    cudaDeviceProp devp;
    cudaGetDeviceProperties(&devp, 0);

    h_A = (float *)malloc(size);
    
    int global_id = 0;

    for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
    {
        for (int row = 0; row < dim_of_matrix; row++)
        {
            for (int column = 0; column < dim_of_matrix; column++)
            {
                fscanf(fptr, "%f", &read_element);
                global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
                h_A[global_id] = read_element;
                // printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
                // printf("%0.2f \n ", h_A[global_id]);
            }
        }
    }
    printf("\nRead from the input file successfully!\n");
    fclose(fptr);

    printf("\nPrinting the host-side input array read from the input file:\n");
    for (int i = 0; i < numElements; i++) {    
        printf("%f ", h_A[i]);
    }
    printf("\n\n");



    // cudaError_t err = cudaSuccess;
    // float *read_data = NULL;
    // err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // printf("Coping the matrix from host memory to device memory\n");
    // err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // printf("Testing for matrix M [%dx%d]\n",N,N);

    cudaError_t err = cudaSuccess;

    float *d_A = NULL;

    err = cudaMalloc((void **)&d_A, size);

    if (err != cudaSuccess)
    {
        fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);

    if (err != cudaSuccess)
    {
        fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }
    else {
        printf("Copied the h_A to device side successfully!\n\n");
    }



    // dim3 grid(1,1,1);
    // dim3 block(TILE_SIZE,TILE_SIZE,1);
    // size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
    // right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
    // err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    
    int num_of_matrices_per_block = num_of_matrices;

    dim3 grid(1, 1, 1);
    dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
    // no of tiles in a column
    // int INPUT_SIZE = dim_of_matrix;
    // int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
    int N = dim_of_matrix;
    size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
    
    right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
    //left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);

    cudaError_t cudaerr = cudaDeviceSynchronize();
    if (cudaerr != cudaSuccess) {
        printf("kernel launch failed with error \"%s\".\n",
                cudaGetErrorString(cudaerr));
    }

    // if(TILE_SIZE == INPUT_SIZE)
    // {
    //     // printf("The if statement works.\n");
    //     left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
    // }

    // else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
    // {
    //     //printf("The if statement works.\n");
    //     left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
    //     // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
    // }
    // else
    // {
    //     left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
    // }






    // printf("Printing output matrix\n");
    // for(i=0;i<n;i++)
    // {
    //     for(j=0;j<n;j++)
    //     {
    //         if(j<=i)
    //             printf("%f\t",M[i*N + j]);
    //         else
    //             printf("%f\t",0.0);
    //     }
    //     printf("\n");
    // }
    // err = cudaFree(read_data);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // err = cudaDeviceReset();
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // free(M);
    // printf("DONE!\n");

    err = cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
    
    if (err != cudaSuccess)
    {
        fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }
    else {
        printf("\nCopied d_A to host side successfully!\n");
    }
    
    printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
    for (int i = 0; i < numElements; i++) {    
        printf("%f ", h_A[i]);
    }


    err = cudaFree(d_A);
    if(err != cudaSuccess)
    {
        fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    err = cudaDeviceReset();
    if(err != cudaSuccess)
    {
        fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }


    FILE *fptr1;
    fptr1 = fopen("./output.txt", "w+");
    float write_element;
    fprintf(fptr1, "%d\n", num_of_matrices);
    fprintf(fptr1, "%d\n", dim_of_matrix);

    for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
    {
        for (int row = 0; row < dim_of_matrix; row++)
        {
            for (int column = 0; column < dim_of_matrix; column++)
            {
                //write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
                global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
                write_element = h_A[global_id] ;
                fprintf(fptr1, "%0.2f ", write_element);
            }
         fprintf(fptr1,"\n");
        }
    }
    fclose(fptr1);
    free(h_A);
    printf("\n\nAll tasks completed successfully!\n\n");

    return 0;
}

	.file	"tmpxft_0021cbf5_00000000-6_right_looking_interleaved_latest.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14store_full_rowPfS_iiii
	.type	_Z14store_full_rowPfS_iiii, @function
_Z14store_full_rowPfS_iiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z14store_full_rowPfS_iiii, .-_Z14store_full_rowPfS_iiii
	.globl	_Z13load_full_rowPfS_iiii
	.type	_Z13load_full_rowPfS_iiii, @function
_Z13load_full_rowPfS_iiii:
.LFB2181:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2181:
	.size	_Z13load_full_rowPfS_iiii, .-_Z13load_full_rowPfS_iiii
	.globl	_Z10store_fullPfS_iiiii
	.type	_Z10store_fullPfS_iiiii, @function
_Z10store_fullPfS_iiiii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z10store_fullPfS_iiiii, .-_Z10store_fullPfS_iiiii
	.globl	_Z9load_fullPfS_iiiii
	.type	_Z9load_fullPfS_iiiii, @function
_Z9load_fullPfS_iiiii:
.LFB2183:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2183:
	.size	_Z9load_fullPfS_iiiii, .-_Z9load_fullPfS_iiiii
	.globl	_Z11store_lowerPfS_iiiii
	.type	_Z11store_lowerPfS_iiiii, @function
_Z11store_lowerPfS_iiiii:
.LFB2185:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2185:
	.size	_Z11store_lowerPfS_iiiii, .-_Z11store_lowerPfS_iiiii
	.globl	_Z10load_lowerPfS_iiiii
	.type	_Z10load_lowerPfS_iiiii, @function
_Z10load_lowerPfS_iiiii:
.LFB2187:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2187:
	.size	_Z10load_lowerPfS_iiiii, .-_Z10load_lowerPfS_iiiii
	.globl	_Z10potrf_tilePf
	.type	_Z10potrf_tilePf, @function
_Z10potrf_tilePf:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z10potrf_tilePf, .-_Z10potrf_tilePf
	.globl	_Z9trsm_tilePfiii
	.type	_Z9trsm_tilePfiii, @function
_Z9trsm_tilePfiii:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2034:
	.size	_Z9trsm_tilePfiii, .-_Z9trsm_tilePfiii
	.globl	_Z9syrk_tilePfS_iii
	.type	_Z9syrk_tilePfS_iii, @function
_Z9syrk_tilePfS_iii:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	_Z9syrk_tilePfS_iii, .-_Z9syrk_tilePfS_iii
	.globl	_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
	.type	_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, @function
_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z27right_looking_launch_kernelPfiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L20:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii, .-_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
	.globl	_Z27right_looking_launch_kernelPfiiii
	.type	_Z27right_looking_launch_kernelPfiiii, @function
_Z27right_looking_launch_kernelPfiiii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
	.cfi_endproc
.LFE2062:
	.size	_Z27right_looking_launch_kernelPfiiii, .-_Z27right_looking_launch_kernelPfiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"./dim2_256matrices.txt"
.LC2:
	.string	"%d"
.LC3:
	.string	"%f"
.LC4:
	.string	"\nRead from the input file successfully!\n"
.LC5:
	.string	"\nPrinting the host-side input array read from the input file:\n"
.LC6:
	.string	"%f "
.LC7:
	.string	"\n\n"
.LC8:
	.string	"Failed to allocate device vector A (error code %s)!\n"
.LC9:
	.string	"Failed to copy vector A from host to device (error code %s)!\n"
.LC10:
	.string	"Copied the h_A to device side successfully!\n\n"
.LC11:
	.string	"kernel launch failed with error \"%s\".\n"
.LC12:
	.string	"Failed to copy vector A from device to host (error code %s)!\n"
.LC13:
	.string	"\nCopied d_A to host side successfully!\n"
.LC14:
	.string	"\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n"
.LC15:
	.string	"\nFailed to free device matrix M (error code %s)\n"
.LC16:
	.string	"Failed to deinitialize the CUDA device (error code %s)\n"
.LC17:
	.string	"w+"
.LC18:
	.string	"./output.txt"
.LC19:
	.string	"%d\n"
.LC20:
	.string	"%0.2f "
.LC21:
	.string	"\n"
.LC22:
	.string	"\n\nAll tasks completed successfully!\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC3(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	.LC2(%rip), %rbx
	subq	$1112, %rsp
	.cfi_def_cfa_offset 1168
	movq	%fs:40, %rax
	movq	%rax, 1096(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movq	%rbx, %rsi
	leaq	20(%rsp), %rdx
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	(%rsp), %rdi
	leaq	24(%rsp), %rdx
	xorl	%eax, %eax
	movq	%rbx, %rsi
	call	__isoc23_fscanf@PLT
	movl	24(%rsp), %eax
	movl	20(%rsp), %r12d
	xorl	%esi, %esi
	leaq	64(%rsp), %rdi
	imull	%eax, %r12d
	imull	%eax, %r12d
	movslq	%r12d, %rbp
	leaq	0(,%rbp,4), %rax
	movq	%rax, 8(%rsp)
	call	cudaGetDeviceProperties_v2@PLT
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, %rbx
.L27:
	cmpl	%r15d, 20(%rsp)
	jle	.L56
	xorl	%ebp, %ebp
.L30:
	cmpl	%ebp, 24(%rsp)
	jle	.L57
	xorl	%r13d, %r13d
.L29:
	cmpl	%r13d, 24(%rsp)
	jle	.L58
	movq	(%rsp), %rdi
	leaq	28(%rsp), %rdx
	movq	%r14, %rsi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	24(%rsp), %eax
	movss	28(%rsp), %xmm0
	imull	%ebp, %eax
	addl	%r13d, %eax
	imull	20(%rsp), %eax
	incl	%r13d
	addl	%r15d, %eax
	cltq
	movss	%xmm0, (%rbx,%rax,4)
	jmp	.L29
.L58:
	incl	%ebp
	jmp	.L30
.L57:
	incl	%r15d
	jmp	.L27
.L56:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
	movq	(%rsp), %rdi
	leaq	.LC6(%rip), %r14
	call	fclose@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L31:
	cmpl	%r13d, %r12d
	jle	.L59
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rbx,%r13,4), %xmm0
	call	__printf_chk@PLT
	incq	%r13
	jmp	.L31
.L59:
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L33
	call	cudaGetErrorString@PLT
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L55
.L33:
	movq	32(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	$1, %ecx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L34
	call	cudaGetErrorString@PLT
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rcx
.L55:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L34:
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	imull	$3, 24(%rsp), %r13d
	movl	20(%rsp), %eax
	movabsq	$8589934594, %rcx
	movq	%rcx, 56(%rsp)
	movl	60(%rsp), %ecx
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	movl	%eax, 52(%rsp)
	movl	$1, %esi
	addl	$7, %r13d
	movl	%r13d, %edx
	imull	%eax, %edx
	imull	$6, %eax, %eax
	movslq	%edx, %rdx
	cltq
	addq	%rdx, %rax
	movq	52(%rsp), %rdx
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movl	20(%rsp), %edx
	movl	24(%rsp), %esi
	movl	%r13d, %r8d
	movq	32(%rsp), %rdi
	movl	%edx, %ecx
	call	_Z51__device_stub__Z27right_looking_launch_kernelPfiiiiPfiiii
.L35:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L36
	call	cudaGetErrorString@PLT
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L36:
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L37
	call	cudaGetErrorString@PLT
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L55
.L37:
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	leaq	.LC14(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %r13
.L38:
	cmpl	%ebp, %r12d
	jle	.L60
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbp
	jmp	.L38
.L60:
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L40
	call	cudaGetErrorString@PLT
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L55
.L40:
	call	cudaDeviceReset@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L41
	call	cudaGetErrorString@PLT
	leaq	.LC16(%rip), %rdx
	movq	%rax, %rcx
	jmp	.L55
.L41:
	leaq	.LC17(%rip), %rsi
	leaq	.LC18(%rip), %rdi
	xorl	%r13d, %r13d
	call	fopen@PLT
	leaq	.LC19(%rip), %r12
	movl	20(%rsp), %ecx
	movl	$2, %esi
	movq	%r12, %rdx
	movq	%rax, %rdi
	movq	%rax, %rbp
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	24(%rsp), %ecx
	movq	%r12, %rdx
	movq	%rbp, %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC20(%rip), %r12
	call	__fprintf_chk@PLT
.L42:
	cmpl	%r13d, 20(%rsp)
	jle	.L61
	xorl	%r14d, %r14d
.L45:
	cmpl	%r14d, 24(%rsp)
	jle	.L62
	xorl	%r15d, %r15d
.L44:
	movl	24(%rsp), %eax
	cmpl	%r15d, %eax
	jle	.L63
	imull	%r14d, %eax
	movq	%r12, %rdx
	movl	$2, %esi
	movq	%rbp, %rdi
	addl	%r15d, %eax
	imull	20(%rsp), %eax
	incl	%r15d
	addl	%r13d, %eax
	cltq
	cvtss2sd	(%rbx,%rax,4), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	jmp	.L44
.L63:
	leaq	.LC21(%rip), %rdx
	movq	%rbp, %rdi
	xorl	%eax, %eax
	incl	%r14d
	movl	$2, %esi
	call	__fprintf_chk@PLT
	jmp	.L45
.L62:
	incl	%r13d
	jmp	.L42
.L61:
	movq	%rbp, %rdi
	call	fclose@PLT
	movq	%rbx, %rdi
	call	free@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC22(%rip), %rsi
	call	__printf_chk@PLT
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$1112, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	main, .-main
	.section	.rodata.str1.1
.LC23:
	.string	"_Z27right_looking_launch_kernelPfiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z27right_looking_launch_kernelPfiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<hip/hip_runtime.h>

#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2            // Tile size and block size, both are taken as 32
__device__ void store_full_row(float*,float*,int,int, int, int);
__device__ void load_full_row(float*,float*,int,int, int, int);
__device__ void store_full(float*,float*,int,int,int, int, int);
__device__ void load_full(float*,float*,int,int,int, int, int);
__device__ void store_lower(float*,float*,int,int,int, int, int);
__device__ void load_lower(float*,float*,int,int,int, int, int);
__device__ void potrf_tile(float*);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,float*,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);

__device__ void store_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
    int global_y;
    int global_x = i*blockDim.y + threadIdx.y;
    for(int j=0;j<N/TILE_SIZE;j++)
    {
        global_y = j*blockDim.z + threadIdx.z;
        write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix];
    }
    __syncthreads();
}
__device__ void load_full_row(float* read_data,float* write_data,int i,int N, int M, int shared_size_single_matrix)
{
    int global_y;
    int global_x = i*blockDim.y + threadIdx.y;
    for(int j=0;j<N/TILE_SIZE;j++)
    {
        global_y = j*blockDim.z + threadIdx.z;
        write_data[threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
        printf("%d, %d\n", threadIdx.y + (TILE_SIZE+1)*global_y + threadIdx.x*shared_size_single_matrix, global_y*N*M + global_x*M + threadIdx.x);
    }
    __syncthreads();
}
__device__ void store_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
    __syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
    __syncthreads();
}
__device__ void store_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    // printf("%f is at %d\n", read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix], threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix);
    if(threadIdx.z >= threadIdx.y)
        write_data[global_y*N*M + global_x*M + threadIdx.x] = read_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix];
    else
        write_data[global_y*N*M + global_x*M + threadIdx.x] = 0.0;
    __syncthreads();
}
__device__ void load_lower(float* read_data,float* write_data,int i,int j,int N, int M, int shared_size_single_matrix)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    if(threadIdx.z >= threadIdx.y)
        write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = read_data[global_y*N*M + global_x*M + threadIdx.x];
    else
        write_data[threadIdx.y + (TILE_SIZE+1)*threadIdx.z + threadIdx.x*shared_size_single_matrix] = 0.0;
    __syncthreads();
}
__device__ void potrf_tile(float* t_A)
{
    int t_x = threadIdx.y;
    int t_y = threadIdx.z;
    __shared__ float temp2;
    for(int k=0;k<TILE_SIZE;k++)
    {
        if(t_x==t_y && t_x==k)
        {
            t_A[k*(TILE_SIZE+1) + k] = sqrtf(t_A[k*(TILE_SIZE+1) + k]);
            temp2 = t_A[k*(TILE_SIZE+1) + k];
        }
        __syncthreads();
        if(t_x<t_y && t_x == k)
        {
            t_A[t_y*(TILE_SIZE+1) + k]/= temp2;
        }
        __syncthreads();
        if(k<t_y && k<t_x && t_x<=t_y)
        {
            t_A[t_y*(TILE_SIZE+1) + t_x]-= t_A[t_x*(TILE_SIZE+1) + k]*t_A[t_y*(TILE_SIZE+1) + k];
        }
        __syncthreads();
    }
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    int t_x = threadIdx.y;
    int t_y = threadIdx.z;
    for(int s=0;s<TILE_SIZE;s++)
    {
	if(t_x==s)
        {
	    row_data[global_y*(TILE_SIZE+1) + t_x]/= row_data[global_x*(TILE_SIZE+1) + t_x];
	}
	__syncthreads();
	if(t_x > s)
        {
	    row_data[global_y*(TILE_SIZE+1) + t_x]-= row_data[global_x*(TILE_SIZE+1) +  s]*row_data[global_y*(TILE_SIZE+1) + s];
	}
	__syncthreads();
    }
}
__device__ void syrk_tile(float* row_data,float* edit_data,int i,int j,int N) 
{
    int global_y = j*blockDim.z + threadIdx.z;
    int global_x = i*blockDim.y + threadIdx.y;
    int t_y = threadIdx.z;
    int t_x = threadIdx.y;
    float valueToSubtract = 0.0;
    for(int r=0;r<TILE_SIZE;r++)
    {
        valueToSubtract+= row_data[r + global_y*(TILE_SIZE+1)]*row_data[r + global_x*(TILE_SIZE+1)];
    }
    edit_data[t_y*(TILE_SIZE+1) + t_x]-= valueToSubtract;
    __syncthreads();
}

__global__ void right_looking_launch_kernel(float* read_data,int N, int M , int num_of_matrices_per_block, int shared_size_single_matrix) // N -> dim, M -> num of matrices per block
{

    int no_of_tiles = (N / TILE_SIZE) + (N % TILE_SIZE != 0); 
    
    int tx = threadIdx.x;
    float *rA1 = NULL;

    extern __shared__ float row_data[];
    // __shared__ float tile_data[TILE_SIZE*(TILE_SIZE+1)];                // Using TILE_SIZE+1 to avoid Band-conflict in Shared Memory
    int tile_data_index = M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1);
    // __shared__ float* tile_data = &row_data[M * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)];
    int shared_size_single_matrix_tile_data = TILE_SIZE * (TILE_SIZE + 1);


    int i,j,k;
    for(i=0;i<N/TILE_SIZE;i++)
    {
        load_lower(read_data,&row_data[tile_data_index],i,i,N, M, shared_size_single_matrix_tile_data);
        // printf("%d \n", tile_data_index + shared_size_single_matrix_tile_data * M);
        // if (threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0) {
            // for (int z = tile_data_index; z < tile_data_index + shared_size_single_matrix_tile_data * M; z++) {
                // printf("%f is at %d\n", row_data[z], z);
            // }
        // }
        
        rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
        // printf("%d\n", tx*shared_size_single_matrix_tile_data);
        // potrf_tile(tile_data);
        potrf_tile(rA1);
        store_lower(&row_data[tile_data_index],read_data,i,i,N, M, shared_size_single_matrix_tile_data);
        load_full_row(read_data,row_data,i,N, M, shared_size_single_matrix);
        for(j=i+1;j<N/TILE_SIZE;j++)
        {
            trsm_tile(&row_data[tx*shared_size_single_matrix],i,j,N);
            for(k=i+1;k<j;k++)
            {
                load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
                rA1 = &row_data[tile_data_index + tx*shared_size_single_matrix_tile_data];
                // syrk_tile(row_data,tile_data,k,j,N);
                syrk_tile(&row_data[tx*shared_size_single_matrix],rA1,k,j,N);
                store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
            }
            load_full(read_data,&row_data[tile_data_index],k,j,N, M, shared_size_single_matrix_tile_data);
            syrk_tile(&row_data[tx*shared_size_single_matrix],&row_data[tile_data_index + tx*shared_size_single_matrix_tile_data],k,j,N);
            store_full(&row_data[tile_data_index],read_data,k,j,N, M, shared_size_single_matrix_tile_data);
        }
        store_full_row(row_data,read_data,i,N, M, shared_size_single_matrix);
    }
}


int main()
{
    // int n,N;
    // printf("Enter dimension (N) : ");
    // scanf("%d",&n);
    // if((n%TILE_SIZE)==0)
    //     N = n;
    // else
    //     N = (((int) (n/TILE_SIZE)) + 1)*TILE_SIZE;
    // size_t size = N*N*sizeof(float);
    // float *M = (float *)malloc(size);
    // if(M == NULL)
    // {
    //     fprintf(stderr,"Failed to allocate host vectors!\n");
    //     exit(EXIT_FAILURE);
    // }
    // int i,j;
    // printf("Enter input matrix: \n");
    // for(i=0;i<N;i++)
    // {
    //     for(j=0;j<N;j++)
    //     {
    //         if(i>=n || j>=n)
    //             M[i*N + j] = 1;     //Padding the matrix with 1
    //         else
    //             scanf("%f",&M[i*N + j]);
    //     }
    // }

    FILE *fptr;
    fptr = fopen("./dim2_256matrices.txt", "r");
    int num_of_matrices, dim_of_matrix;
    fscanf(fptr, "%d", &num_of_matrices);
    fscanf(fptr, "%d", &dim_of_matrix);
    float read_element;
    float* h_A = NULL;
    int numElements = num_of_matrices * dim_of_matrix * dim_of_matrix;
    size_t size = numElements * sizeof(float);
    hipDeviceProp_t devp;
    hipGetDeviceProperties(&devp, 0);

    h_A = (float *)malloc(size);
    
    int global_id = 0;

    for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
    {
        for (int row = 0; row < dim_of_matrix; row++)
        {
            for (int column = 0; column < dim_of_matrix; column++)
            {
                fscanf(fptr, "%f", &read_element);
                global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
                h_A[global_id] = read_element;
                // printf("At pos %d we get %0.2f\n", global_id, h_A[global_id]);
                // printf("%0.2f \n ", h_A[global_id]);
            }
        }
    }
    printf("\nRead from the input file successfully!\n");
    fclose(fptr);

    printf("\nPrinting the host-side input array read from the input file:\n");
    for (int i = 0; i < numElements; i++) {    
        printf("%f ", h_A[i]);
    }
    printf("\n\n");



    // cudaError_t err = cudaSuccess;
    // float *read_data = NULL;
    // err = cudaMalloc((void **)&read_data,N*N*sizeof(float));
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr,"Failed to allocate matrix on the CUDA device! (error code %s)\n",cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // printf("Coping the matrix from host memory to device memory\n");
    // err = cudaMemcpy(read_data,M,size,cudaMemcpyHostToDevice);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr,"Failed to copy matrix from host to device (error code %s)\n",cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // printf("Testing for matrix M [%dx%d]\n",N,N);

    hipError_t err = hipSuccess;

    float *d_A = NULL;

    err = hipMalloc((void **)&d_A, size);

    if (err != hipSuccess)
    {
        fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);

    if (err != hipSuccess)
    {
        fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }
    else {
        printf("Copied the h_A to device side successfully!\n\n");
    }



    // dim3 grid(1,1,1);
    // dim3 block(TILE_SIZE,TILE_SIZE,1);
    // size_t shared_size = (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float);
    // right_looking_launch_kernel<<<grid,block,shared_size>>>(read_data,N);
    // err = cudaMemcpy(M,read_data,size,cudaMemcpyDeviceToHost);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to copy the output matrix M from device to Host (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    
    int num_of_matrices_per_block = num_of_matrices;

    dim3 grid(1, 1, 1);
    dim3 block(num_of_matrices, TILE_SIZE, TILE_SIZE);
    // no of tiles in a column
    // int INPUT_SIZE = dim_of_matrix;
    // int no_of_tiles = (INPUT_SIZE / TILE_SIZE) + (INPUT_SIZE % TILE_SIZE != 0); // ceil of (INPUT_SIZE / TILE_SIZE)
    int N = dim_of_matrix;
    size_t shared_size = num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1)*sizeof(float) + num_of_matrices_per_block * TILE_SIZE*(TILE_SIZE+1) * sizeof(float);
    
    right_looking_launch_kernel<<<grid,block,shared_size>>>(d_A, dim_of_matrix, num_of_matrices, num_of_matrices ,(num_of_matrices * (N*(TILE_SIZE+1) + TILE_SIZE*(TILE_SIZE+1) + 1))/num_of_matrices);
    //left_looking_kernel<<<grid, block, num_of_matrices_per_block * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);

    hipError_t cudaerr = hipDeviceSynchronize();
    if (cudaerr != hipSuccess) {
        printf("kernel launch failed with error \"%s\".\n",
                hipGetErrorString(cudaerr));
    }

    // if(TILE_SIZE == INPUT_SIZE)
    // {
    //     // printf("The if statement works.\n");
    //     left_looking_kernel<<<grid, block, num_of_matrices * 1 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,1 * TILE_SIZE * TILE_SIZE);
    // }

    // else if((no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float) < devp.sharedMemPerBlock)
    // {
    //     //printf("The if statement works.\n");
    //     left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
    //     // left_looking_kernel<<<grid, block,num_of_matrices * (no_of_tiles + 2) * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,(no_of_tiles + 2) * TILE_SIZE * TILE_SIZE);
    // }
    // else
    // {
    //     left_looking_kernel_less_mem<<<grid, block, num_of_matrices * 4 * TILE_SIZE * TILE_SIZE * sizeof(float)>>>(d_A, dim_of_matrix, num_of_matrices ,4 * TILE_SIZE * TILE_SIZE);
    // }






    // printf("Printing output matrix\n");
    // for(i=0;i<n;i++)
    // {
    //     for(j=0;j<n;j++)
    //     {
    //         if(j<=i)
    //             printf("%f\t",M[i*N + j]);
    //         else
    //             printf("%f\t",0.0);
    //     }
    //     printf("\n");
    // }
    // err = cudaFree(read_data);
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to free device matrix M (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // err = cudaDeviceReset();
    // if(err != cudaSuccess)
    // {
    //     fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", cudaGetErrorString(err));
    //     exit(EXIT_FAILURE);
    // }
    // free(M);
    // printf("DONE!\n");

    err = hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
    
    if (err != hipSuccess)
    {
        fprintf(stderr, "Failed to copy vector A from device to host (error code %s)!\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }
    else {
        printf("\nCopied d_A to host side successfully!\n");
    }
    
    printf("\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:\n");
    for (int i = 0; i < numElements; i++) {    
        printf("%f ", h_A[i]);
    }


    err = hipFree(d_A);
    if(err != hipSuccess)
    {
        fprintf(stderr, "\nFailed to free device matrix M (error code %s)\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    err = hipDeviceReset();
    if(err != hipSuccess)
    {
        fprintf(stderr, "Failed to deinitialize the CUDA device (error code %s)\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }


    FILE *fptr1;
    fptr1 = fopen("./output.txt", "w+");
    float write_element;
    fprintf(fptr1, "%d\n", num_of_matrices);
    fprintf(fptr1, "%d\n", dim_of_matrix);

    for (int matrix_index = 0; matrix_index < num_of_matrices; matrix_index++)
    {
        for (int row = 0; row < dim_of_matrix; row++)
        {
            for (int column = 0; column < dim_of_matrix; column++)
            {
                //write_element = h_A[matrix_index * dim_of_matrix * dim_of_matrix + row * dim_of_matrix + column];
                global_id = row * dim_of_matrix * num_of_matrices + column * num_of_matrices + matrix_index;
                write_element = h_A[global_id] ;
                fprintf(fptr1, "%0.2f ", write_element);
            }
         fprintf(fptr1,"\n");
        }
    }
    fclose(fptr1);
    free(h_A);
    printf("\n\nAll tasks completed successfully!\n\n");

    return 0;
}

	.text
	.file	"right_looking_interleaved_latest.hip"
	.globl	_Z42__device_stub__right_looking_launch_kernelPfiiii # -- Begin function _Z42__device_stub__right_looking_launch_kernelPfiiii
	.type	_Z42__device_stub__right_looking_launch_kernelPfiiii,@function
_Z42__device_stub__right_looking_launch_kernelPfiiii: # @_Z42__device_stub__right_looking_launch_kernelPfiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27right_looking_launch_kernelPfiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z42__device_stub__right_looking_launch_kernelPfiiii, .Lfunc_end0-_Z42__device_stub__right_looking_launch_kernelPfiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 1568
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r15
	leaq	12(%rsp), %r12
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	8(%rsp), %rbx
	movl	$.L.str.2, %esi
	movq	%r15, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	(%rbx), %eax
	movl	(%r12), %ecx
	imull	%eax, %ecx
	imull	%eax, %ecx
	movl	%ecx, 24(%rsp)                  # 4-byte Spill
	movslq	%ecx, %rbx
	shlq	$2, %rbx
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbx
	movl	(%r12), %eax
	testl	%eax, %eax
	jle	.LBB1_9
# %bb.1:                                # %.preheader103.preheader
	movl	8(%rsp), %ecx
	leaq	28(%rsp), %r12
	xorl	%r13d, %r13d
.LBB1_2:                                # %.preheader103
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_6 Depth 3
	testl	%ecx, %ecx
	jle	.LBB1_8
# %bb.3:                                # %.preheader102.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	xorl	%r14d, %r14d
.LBB1_4:                                # %.preheader102
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_6 Depth 3
	testl	%ecx, %ecx
	jle	.LBB1_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_4 Depth=2
	xorl	%ebp, %ebp
.LBB1_6:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	$.L.str.3, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	8(%rsp), %ecx
	movl	12(%rsp), %eax
	movl	%r14d, %edx
	imull	%ecx, %edx
	addl	%ebp, %edx
	imull	%eax, %edx
	addl	%r13d, %edx
	movss	28(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	movslq	%edx, %rdx
	movss	%xmm0, (%rbx,%rdx,4)
	incl	%ebp
	cmpl	%ecx, %ebp
	jl	.LBB1_6
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_4 Depth=2
	incl	%r14d
	cmpl	%ecx, %r14d
	jl	.LBB1_4
.LBB1_8:                                # %._crit_edge106
                                        #   in Loop: Header=BB1_2 Depth=1
	incl	%r13d
	cmpl	%eax, %r13d
	jl	.LBB1_2
.LBB1_9:                                # %._crit_edge108
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	%r15, %rdi
	callq	fclose
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	24(%rsp), %ebp                  # 4-byte Reload
	movl	%ebp, %r12d
	testl	%ebp, %ebp
	jle	.LBB1_12
# %bb.10:                               # %.lr.ph111.preheader
	xorl	%r14d, %r14d
.LBB1_11:                               # %.lr.ph111
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r14,4), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	%r14, %r12
	jne	.LBB1_11
.LBB1_12:                               # %._crit_edge112
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	leaq	16(%rsp), %rdi
	movq	$0, (%rdi)
	movq	32(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.15:
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.17:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	12(%rsp), %edx
	movslq	%edx, %rax
	btsq	$33, %rdx
	movslq	8(%rsp), %rcx
	leaq	(%rcx,%rcx,2), %r15
	addq	$7, %r15
	movq	%r15, %rcx
	imulq	%rax, %rcx
	leaq	(%rax,%rax,2), %rax
	leaq	(%rcx,%rax,2), %r8
	shlq	$2, %r8
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$2, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.18:
	movq	16(%rsp), %rdi
	movl	8(%rsp), %esi
	movl	12(%rsp), %ecx
	movl	%ecx, %edx
	movl	%r15d, %r8d
	callq	_Z42__device_stub__right_looking_launch_kernelPfiiii
.LBB1_19:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB1_21
# %bb.20:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.11, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_21:
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_22
# %bb.23:
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	testl	%ebp, %ebp
	jle	.LBB1_26
# %bb.24:                               # %.lr.ph115.preheader
	xorl	%r14d, %r14d
.LBB1_25:                               # %.lr.ph115
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r14,4), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	%r14, %r12
	jne	.LBB1_25
.LBB1_26:                               # %._crit_edge116
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_27
# %bb.28:
	callq	hipDeviceReset
	testl	%eax, %eax
	jne	.LBB1_29
# %bb.30:
	movl	$.L.str.17, %edi
	movl	$.L.str.18, %esi
	callq	fopen
	movq	%rax, %r14
	movl	12(%rsp), %edx
	xorl	%ebp, %ebp
	movl	$.L.str.19, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	8(%rsp), %edx
	movl	$.L.str.19, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	12(%rsp), %ecx
	testl	%ecx, %ecx
	jle	.LBB1_40
# %bb.31:                               # %.preheader101.preheader
	movl	8(%rsp), %eax
.LBB1_32:                               # %.preheader101
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_34 Depth 2
                                        #       Child Loop BB1_36 Depth 3
	testl	%eax, %eax
	jle	.LBB1_39
# %bb.33:                               # %.preheader.preheader
                                        #   in Loop: Header=BB1_32 Depth=1
	xorl	%r15d, %r15d
.LBB1_34:                               # %.preheader
                                        #   Parent Loop BB1_32 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_36 Depth 3
	testl	%eax, %eax
	jle	.LBB1_37
# %bb.35:                               # %.lr.ph118.preheader
                                        #   in Loop: Header=BB1_34 Depth=2
	xorl	%r12d, %r12d
.LBB1_36:                               # %.lr.ph118
                                        #   Parent Loop BB1_32 Depth=1
                                        #     Parent Loop BB1_34 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	imull	%r15d, %eax
	addl	%r12d, %eax
	imull	12(%rsp), %eax
	addl	%ebp, %eax
	cltq
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%rax,4), %xmm0
	movl	$.L.str.20, %esi
	movq	%r14, %rdi
	movb	$1, %al
	callq	fprintf
	incl	%r12d
	movl	8(%rsp), %eax
	cmpl	%eax, %r12d
	jl	.LBB1_36
.LBB1_37:                               # %._crit_edge119
                                        #   in Loop: Header=BB1_34 Depth=2
	movl	$10, %edi
	movq	%r14, %rsi
	callq	fputc@PLT
	incl	%r15d
	movl	8(%rsp), %eax
	cmpl	%eax, %r15d
	jl	.LBB1_34
# %bb.38:                               # %._crit_edge121.loopexit
                                        #   in Loop: Header=BB1_32 Depth=1
	movl	12(%rsp), %ecx
.LBB1_39:                               # %._crit_edge121
                                        #   in Loop: Header=BB1_32 Depth=1
	incl	%ebp
	cmpl	%ecx, %ebp
	jl	.LBB1_32
.LBB1_40:                               # %._crit_edge123
	movq	%r14, %rdi
	callq	fclose
	movq	%rbx, %rdi
	callq	free
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$1512, %rsp                     # imm = 0x5E8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_13:
	.cfi_def_cfa_offset 1568
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %esi
	jmp	.LBB1_14
.LBB1_16:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.9, %esi
	jmp	.LBB1_14
.LBB1_22:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	jmp	.LBB1_14
.LBB1_27:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	jmp	.LBB1_14
.LBB1_29:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.16, %esi
.LBB1_14:
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27right_looking_launch_kernelPfiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z27right_looking_launch_kernelPfiiii,@object # @_Z27right_looking_launch_kernelPfiiii
	.section	.rodata,"a",@progbits
	.globl	_Z27right_looking_launch_kernelPfiiii
	.p2align	3, 0x0
_Z27right_looking_launch_kernelPfiiii:
	.quad	_Z42__device_stub__right_looking_launch_kernelPfiiii
	.size	_Z27right_looking_launch_kernelPfiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"./dim2_256matrices.txt"
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%f"
	.size	.L.str.3, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%f "
	.size	.L.str.6, 4

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device vector A (error code %s)!\n"
	.size	.L.str.8, 53

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to copy vector A from host to device (error code %s)!\n"
	.size	.L.str.9, 62

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"kernel launch failed with error \"%s\".\n"
	.size	.L.str.11, 39

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Failed to copy vector A from device to host (error code %s)!\n"
	.size	.L.str.12, 62

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"\nFailed to free device matrix M (error code %s)\n"
	.size	.L.str.15, 49

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Failed to deinitialize the CUDA device (error code %s)\n"
	.size	.L.str.16, 56

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"./output.txt"
	.size	.L.str.17, 13

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"w+"
	.size	.L.str.18, 3

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"%d\n"
	.size	.L.str.19, 4

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"%0.2f "
	.size	.L.str.20, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z27right_looking_launch_kernelPfiiii"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\nRead from the input file successfully!"
	.size	.Lstr, 40

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\nPrinting the host-side input array read from the input file:"
	.size	.Lstr.1, 62

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"\n"
	.size	.Lstr.2, 2

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Copied the h_A to device side successfully!\n"
	.size	.Lstr.3, 45

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"\nCopied d_A to host side successfully!"
	.size	.Lstr.4, 39

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"\nPrinting the output of cudememcopyDeviceToHost, i.e. the host-side array returned from device side:"
	.size	.Lstr.5, 101

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"\n\nAll tasks completed successfully!\n"
	.size	.Lstr.6, 37

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__right_looking_launch_kernelPfiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z27right_looking_launch_kernelPfiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27right_looking_launch_kernelPfiiii ; -- Begin function _Z27right_looking_launch_kernelPfiiii
	.globl	_Z27right_looking_launch_kernelPfiiii
	.p2align	8
	.type	_Z27right_looking_launch_kernelPfiiii,@function
_Z27right_looking_launch_kernelPfiiii:  ; @_Z27right_looking_launch_kernelPfiiii
; %bb.0:
	s_load_b64 s[6:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 2
	s_cbranch_scc1 .LBB0_228
; %bb.1:                                ; %.lr.ph143
	v_bfe_u32 v35, v0, 10, 10
	v_mov_b32_e32 v3, 0
	v_and_b32_e32 v33, 0x3ff, v0
	v_bfe_u32 v34, v0, 20, 10
	s_mul_i32 s3, s6, 3
	v_lshlrev_b32_e32 v6, 2, v35
	global_load_b32 v2, v3, s[0:1] offset:38
	s_clause 0x1
	s_load_b64 s[12:13], s[0:1], 0x0
	s_load_b32 s9, s[0:1], 0x14
	v_mul_u32_u24_e32 v5, 6, v33
	s_add_i32 s3, s3, 7
	v_mad_u64_u32 v[0:1], null, v34, s6, v[35:36]
	s_mul_i32 s10, s3, s7
	v_mul_u32_u24_e32 v4, 3, v34
	v_lshlrev_b32_e32 v1, 2, v5
	s_lshl_b32 s10, s10, 2
	s_lshr_b32 s2, s6, 31
	s_add_i32 s10, s10, 4
	v_add_lshl_u32 v5, v4, v35, 2
	v_add_nc_u32_e32 v8, s10, v1
	s_add_i32 s2, s6, s2
	s_load_b64 s[14:15], s[0:1], 0x68
	s_ashr_i32 s5, s2, 1
	s_add_u32 s16, s0, 24
	v_lshl_add_u32 v46, v35, 4, v8
	v_add_nc_u32_e32 v47, v8, v5
	v_lshl_add_u32 v48, v4, 2, v8
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, v33, s9
	v_mov_b32_e32 v8, 33
	v_add3_u32 v45, s10, v5, v1
	s_addc_u32 s17, s1, 0
	v_sub_nc_u32_e32 v49, v46, v6
	v_cmp_lt_u32_e32 vcc_lo, v34, v35
	v_mbcnt_lo_u32_b32 v43, -1, 0
	v_cmp_ge_u32_e64 s2, v34, v35
	v_lshlrev_b32_e32 v5, 2, v7
	v_cmp_eq_u32_e64 s3, v35, v34
	v_cmp_lt_u32_e64 s4, v35, v34
	v_min_u32_e32 v44, v34, v35
	s_mov_b32 s8, 0
	v_add_nc_u32_e32 v38, 4, v5
	v_mad_u32_u24 v4, v34, 12, v5
	s_xor_b32 s34, vcc_lo, -1
	s_mov_b32 s35, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v50, v38, v6
	v_add3_u32 v52, v4, v6, 4
	v_mov_b32_e32 v6, 2
	v_mad_u64_u32 v[36:37], null, s7, v0, v[33:34]
	v_add_nc_u32_e32 v37, v7, v35
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s26, s0, 0xffff
	s_lshr_b32 s27, s0, 16
	v_add_nc_u32_e32 v0, s26, v35
	v_add_nc_u32_e32 v7, s27, v34
	s_mul_i32 s30, s6, s27
	s_mul_i32 s28, s26, 12
	s_add_i32 s0, s30, s26
	s_mul_i32 s29, s7, s26
	v_mad_u64_u32 v[1:2], null, s6, v7, v[0:1]
	v_mov_b32_e32 v7, 1
	v_mul_u32_u24_e32 v0, 12, v0
	s_mul_i32 s30, s30, s7
	s_mul_i32 s31, s7, s0
	s_mul_i32 s33, s27, 12
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[39:40], null, s7, v1, v[33:34]
	v_add3_u32 v51, v5, v0, 4
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;       Child Loop BB0_26 Depth 3
                                        ;       Child Loop BB0_32 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_44 Depth 3
                                        ;         Child Loop BB0_47 Depth 4
                                        ;         Child Loop BB0_55 Depth 4
                                        ;         Child Loop BB0_63 Depth 4
                                        ;         Child Loop BB0_71 Depth 4
                                        ;         Child Loop BB0_79 Depth 4
                                        ;         Child Loop BB0_87 Depth 4
                                        ;         Child Loop BB0_95 Depth 4
                                        ;         Child Loop BB0_103 Depth 4
                                        ;         Child Loop BB0_111 Depth 4
                                        ;         Child Loop BB0_117 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
                                        ;       Child Loop BB0_134 Depth 3
                                        ;       Child Loop BB0_142 Depth 3
                                        ;       Child Loop BB0_148 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;       Child Loop BB0_162 Depth 3
                                        ;       Child Loop BB0_170 Depth 3
                                        ;       Child Loop BB0_176 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_189 Depth 3
                                        ;       Child Loop BB0_197 Depth 3
                                        ;       Child Loop BB0_203 Depth 3
                                        ;       Child Loop BB0_212 Depth 3
                                        ;     Child Loop BB0_216 Depth 2
                                        ;       Child Loop BB0_217 Depth 3
                                        ;       Child Loop BB0_223 Depth 3
                                        ;     Child Loop BB0_226 Depth 2
	v_mov_b32_e32 v0, v3
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v3, s[16:17] offset:14
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v4, 16, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s35, v4, v[34:35]
	v_and_b32_e32 v1, 0xffff, v2
	v_mul_lo_u32 v1, s35, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s6
	v_add3_u32 v2, v1, v35, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s7, v[33:34]
	v_mov_b32_e32 v1, v3
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
.LBB0_4:                                ; %_Z10load_lowerPfS_iiiii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s10, 0
	s_mov_b32 s9, -1
	s_waitcnt vmcnt(0)
	ds_store_b32 v45, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s10, v35
	s_and_b32 s0, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	ds_load_b32 v0, v46
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e64 s0, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v1, s0
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v2, v1, v0
	v_fma_f32 v9, -v4, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v5
	v_cndmask_b32_e64 v1, v1, v2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, 0, v9
	v_cndmask_b32_e64 v1, v1, v4, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x37800000, v1
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cmp_class_f32_e64 s0, v0, 0x260
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v1, v0, s0
	ds_store_b32 v46, v0
	ds_store_b32 v3, v0
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_and_b32 s1, s4, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=2
	ds_load_b32 v0, v3
	ds_load_b32 v1, v47
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v2, null, v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v5, v4
	v_fma_f32 v10, -v2, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v4
	v_fma_f32 v2, -v2, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v9
	v_div_fixup_f32 v0, v2, v0, v1
	ds_store_b32 v47, v0
.LBB0_9:                                ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_u32_e32 vcc_lo, s10, v44
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s1, s34, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=2
	s_lshl_b32 s1, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v0, s1, v48
	v_add_nc_u32_e32 v1, s1, v49
	ds_load_b32 v0, v0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v47
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v0, -v1, v0, v2
	ds_store_b32 v47, v0
.LBB0_11:                               ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_xor_b32 s0, s9, -1
	s_mov_b32 s10, 1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_5
; %bb.12:                               ; %_Z10potrf_tilePf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v0, 0
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v0, v45
.LBB0_14:                               ; %_Z11store_lowerPfS_iiiii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mad_u64_u32 v[1:2], null, s35, s27, v[34:35]
	v_mad_u64_u32 v[40:41], null, s35, s26, v[35:36]
	s_mov_b32 s36, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v1, s6, v[40:41]
	v_mad_u64_u32 v[1:2], null, v4, s7, v[33:34]
	v_mov_b32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v0, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_15:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;       Child Loop BB0_26 Depth 3
                                        ;       Child Loop BB0_32 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_44 Depth 3
                                        ;         Child Loop BB0_47 Depth 4
                                        ;         Child Loop BB0_55 Depth 4
                                        ;         Child Loop BB0_63 Depth 4
                                        ;         Child Loop BB0_71 Depth 4
                                        ;         Child Loop BB0_79 Depth 4
                                        ;         Child Loop BB0_87 Depth 4
                                        ;         Child Loop BB0_95 Depth 4
                                        ;         Child Loop BB0_103 Depth 4
                                        ;         Child Loop BB0_111 Depth 4
                                        ;         Child Loop BB0_117 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
                                        ;       Child Loop BB0_134 Depth 3
                                        ;       Child Loop BB0_142 Depth 3
                                        ;       Child Loop BB0_148 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;       Child Loop BB0_162 Depth 3
                                        ;       Child Loop BB0_170 Depth 3
                                        ;       Child Loop BB0_176 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_189 Depth 3
                                        ;       Child Loop BB0_197 Depth 3
                                        ;       Child Loop BB0_203 Depth 3
                                        ;       Child Loop BB0_212 Depth 3
	v_mad_u64_u32 v[0:1], null, s36, s27, v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, v0, s6, v[40:41]
	v_mad_u64_u32 v[41:42], null, v0, 3, v[37:38]
	v_mov_b32_e32 v0, v43
	v_mad_u64_u32 v[4:5], null, v1, s7, v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v4
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b32 v1, v[4:5], off
	v_lshl_add_u32 v4, v41, 2, 4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_21
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[11:12], v3, s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v5, v12
	v_and_b32_e32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v9, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v1, vcc_lo
	global_load_b64 v[9:10], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[9:12], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[11:12]
	s_cbranch_execz .LBB0_20
; %bb.17:                               ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s10, 0
.LBB0_18:                               ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b64 v[13:14], v3, s[14:15]
	v_dual_mov_b32 v12, v5 :: v_dual_mov_b32 v11, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v1, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v5
	v_mad_u64_u32 v[9:10], null, v13, 24, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v9
	global_load_b64 v[9:10], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[9:12], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[11:12]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %Flow562
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_20:                               ; %Flow564
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_21:                               ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b128 v[13:16], v3, s[14:15]
	v_readfirstlane_b32 s18, v4
	v_readfirstlane_b32 s19, v5
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s23, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v14, vcc_lo
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, v3
	global_store_b128 v[9:10], v[4:7], off offset:8
.LBB0_23:                               ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	s_mov_b32 s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v18, s11
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v16, s9
	v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v17, s10
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	v_mov_b32_e32 v11, v3
	v_mov_b32_e32 v15, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	s_clause 0x3
	global_store_b128 v[0:1], v[8:11], off
	global_store_b128 v[0:1], v[15:18], off offset:16
	global_store_b128 v[0:1], v[15:18], off offset:32
	global_store_b128 v[0:1], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_31
; %bb.24:                               ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v3, s[14:15] offset:32 glc
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v4, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s22, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[15:18], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s11, 0
.LBB0_26:                               ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_sleep 1
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[9:12], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_26
.LBB0_27:                               ; %Flow560
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[4:5], v3, s[14:15] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v9, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v9
	s_cbranch_execz .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_15 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[9:10], off offset:8
.LBB0_29:                               ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_15 Depth=2
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, v3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[4:5], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_31:                               ; %Flow561
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
	s_add_i32 s20, s20, s1
	v_add_co_u32 v2, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v5, vcc_lo, s20, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_32:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b32 v2, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_34:                               ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_37
.LBB0_36:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s1, -1
.LBB0_37:                               ; %Flow555
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_32
; %bb.38:                               ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_42
; %bb.39:                               ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15] offset:24 glc
	global_load_b64 v[15:16], v3, s[14:15]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v2, s18
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v2
	v_and_b32_e32 v2, v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v13, v4
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v15, v4
	v_mov_b32_e32 v15, v9
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v16, v2, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[4:5], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_42
; %bb.40:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, 0
.LBB0_41:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_41
.LBB0_42:                               ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_129
; %bb.43:                               ;   in Loop: Header=BB0_15 Depth=2
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v42, 2, v0
	v_dual_mov_b32 v14, v1 :: v_dual_and_b32 v13, -3, v0
	s_mov_b64 s[18:19], 8
.LBB0_44:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_47 Depth 4
                                        ;         Child Loop BB0_55 Depth 4
                                        ;         Child Loop BB0_63 Depth 4
                                        ;         Child Loop BB0_71 Depth 4
                                        ;         Child Loop BB0_79 Depth 4
                                        ;         Child Loop BB0_87 Depth 4
                                        ;         Child Loop BB0_95 Depth 4
                                        ;         Child Loop BB0_103 Depth 4
                                        ;         Child Loop BB0_111 Depth 4
                                        ;         Child Loop BB0_117 Depth 4
                                        ;         Child Loop BB0_126 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[18:19], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s20, s18, 56
	s_cselect_b32 s21, s19, 0
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB0_49
; %bb.45:                               ;   in Loop: Header=BB0_44 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_lshl_b64 s[0:1], s[20:21], 3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[10:11]
.LBB0_47:                               ; %.preheader31.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v2, v3, s[24:25]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_add_u32 s24, s24, 1
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s0, s22
	v_or_b32_e32 v15, v4, v15
	v_or_b32_e32 v16, v5, v16
	s_cbranch_scc1 .LBB0_47
.LBB0_48:                               ; %Flow531
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_50
.LBB0_49:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr9
.LBB0_50:                               ; %Flow533
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[15:16], v3, s[10:11]
	s_add_i32 s9, s20, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_52:                               ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_55:                               ; %.preheader29.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s24
	s_addc_u32 s39, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v2, v3, s[38:39]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v17, v4, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v5, v18
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow526
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
	s_mov_b32 s37, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr37
.LBB0_58:                               ; %Flow528
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[17:18], v3, s[0:1]
	s_add_i32 s37, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_60:                               ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s37, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s37, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_63:                               ; %.preheader27.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s24
	s_addc_u32 s39, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v2, v3, s[38:39]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s37, s24
	v_or_b32_e32 v19, v4, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v5, v20
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow521
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $sgpr9
.LBB0_66:                               ; %Flow523
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[19:20], v3, s[0:1]
	s_add_i32 s9, s37, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_68:                               ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_71:                               ; %.preheader25.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s24
	s_addc_u32 s39, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v2, v3, s[38:39]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v21, v4, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v5, v22
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow516
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
	s_mov_b32 s37, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr37
.LBB0_74:                               ; %Flow518
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[21:22], v3, s[0:1]
	s_add_i32 s37, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_76:                               ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s37, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s37, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_79:                               ; %.preheader23.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s24
	s_addc_u32 s39, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v2, v3, s[38:39]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s37, s24
	v_or_b32_e32 v23, v4, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v5, v24
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow511
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $sgpr9
.LBB0_82:                               ; %Flow513
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[23:24], v3, s[0:1]
	s_add_i32 s9, s37, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_84:                               ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_89
; %bb.85:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_88
; %bb.86:                               ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], 0
.LBB0_87:                               ; %.preheader21.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s0, s24
	s_addc_u32 s39, s1, s25
	s_add_u32 s24, s24, 1
	global_load_u8 v2, v3, s[38:39]
	s_addc_u32 s25, s25, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s9, s24
	v_or_b32_e32 v25, v4, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v5, v26
	s_cbranch_scc1 .LBB0_87
.LBB0_88:                               ; %Flow506
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
	s_mov_b32 s37, 0
	s_branch .LBB0_90
.LBB0_89:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr37
.LBB0_90:                               ; %Flow508
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[25:26], v3, s[0:1]
	s_add_i32 s37, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_92:                               ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_cmp_gt_u32 s37, 7
	s_cbranch_scc1 .LBB0_97
; %bb.93:                               ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s37, 0
	s_cbranch_scc1 .LBB0_96
; %bb.94:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[0:1]
.LBB0_95:                               ; %.preheader.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v2, v3, s[24:25]
	s_add_i32 s37, s37, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s22, v[2:3]
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_add_u32 s24, s24, 1
	s_addc_u32 s25, s25, 0
	s_cmp_lg_u32 s37, 0
	v_or_b32_e32 v27, v4, v27
	v_or_b32_e32 v28, v5, v28
	s_cbranch_scc1 .LBB0_95
.LBB0_96:                               ; %Flow501
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s9, 0
	s_branch .LBB0_98
.LBB0_97:                               ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s9, -1
.LBB0_98:                               ; %Flow503
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[27:28], v3, s[0:1]
.LBB0_100:                              ; %.loopexit.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	v_mov_b32_e32 v2, v43
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_106
; %bb.101:                              ;   in Loop: Header=BB0_44 Depth=3
	global_load_b64 v[31:32], v3, s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v32
	v_and_b32_e32 v4, v4, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v29, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v29, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v9, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
	global_load_b64 v[29:30], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[29:32], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[31:32]
	s_cbranch_execz .LBB0_105
; %bb.102:                              ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s22, 0
.LBB0_103:                              ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b64 v[29:30], v3, s[14:15]
	v_dual_mov_b32 v32, v5 :: v_dual_mov_b32 v31, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v9, 24, v[29:30]
	v_and_b32_e32 v29, v10, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v29, 24, v[5:6]
	v_mov_b32_e32 v5, v9
	global_load_b64 v[29:30], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[29:32], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[31:32]
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_103
; %bb.104:                              ; %Flow496
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_105:                              ; %Flow498
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_106:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b128 v[29:32], v3, s[14:15]
	v_readfirstlane_b32 s22, v4
	v_readfirstlane_b32 s23, v5
	s_mov_b32 s38, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s24, v9
	v_readfirstlane_b32 s25, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[24:25], s[22:23], s[24:25]
	s_mul_i32 s1, s25, 24
	s_mul_hi_u32 s9, s24, 24
	s_mul_i32 s37, s24, 24
	s_and_saveexec_b32 s39, s0
	s_cbranch_execz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_44 Depth=3
	s_add_i32 s40, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v29, s37
	v_add_co_ci_u32_e32 v10, vcc_lo, s40, v30, vcc_lo
	v_dual_mov_b32 v4, s38 :: v_dual_mov_b32 v5, v3
	global_store_b128 v[9:10], v[4:7], off offset:8
.LBB0_108:                              ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s39
	v_cmp_gt_u64_e64 vcc_lo, s[18:19], 56
	v_or_b32_e32 v4, 0, v14
	v_or_b32_e32 v5, v13, v42
	s_lshl_b64 s[24:25], s[24:25], 12
	s_lshl_b32 s38, s20, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s38, s38, 28
	v_dual_cndmask_b32 v14, v4, v14 :: v_dual_cndmask_b32 v9, v5, v13
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v31, s24
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v32, vcc_lo
	s_and_b32 s38, s38, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v2, v4
	v_and_or_b32 v13, 0xffffff1f, v9, s38
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
	s_clause 0x3
	global_store_b128 v[4:5], v[13:16], off
	global_store_b128 v[4:5], v[17:20], off offset:16
	global_store_b128 v[4:5], v[21:24], off offset:32
	global_store_b128 v[4:5], v[25:28], off offset:48
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_116
; %bb.109:                              ;   in Loop: Header=BB0_44 Depth=3
	s_clause 0x1
	global_load_b64 v[17:18], v3, s[14:15] offset:32 glc
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	v_dual_mov_b32 v15, s22 :: v_dual_mov_b32 v16, s23
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s38, v9
	v_readfirstlane_b32 s39, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[38:39], s[38:39], s[22:23]
	s_mul_i32 s25, s39, 24
	s_mul_hi_u32 s39, s38, 24
	s_mul_i32 s38, s38, 24
	s_add_i32 s39, s39, s25
	v_add_co_u32 v9, vcc_lo, v29, s38
	v_add_co_ci_u32_e32 v10, vcc_lo, s39, v30, vcc_lo
	s_mov_b32 s25, exec_lo
	global_store_b64 v[9:10], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[15:18], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_112
; %bb.110:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s38, 0
.LBB0_111:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v13, s22 :: v_dual_mov_b32 v14, s23
	s_sleep 1
	global_store_b64 v[9:10], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[13:16], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s38, vcc_lo, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB0_111
.LBB0_112:                              ; %Flow494
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s25
	global_load_b64 v[9:10], v3, s[14:15] offset:16
	s_mov_b32 s38, exec_lo
	s_mov_b32 s25, exec_lo
	v_mbcnt_lo_u32_b32 v2, s38, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_44 Depth=3
	s_bcnt1_i32_b32 s38, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s38
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[2:3], off offset:8
.LBB0_114:                              ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s25
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_116
; %bb.115:                              ;   in Loop: Header=BB0_44 Depth=3
	global_load_b32 v2, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s25, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[2:3], off
	s_and_b32 m0, s25, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_116:                              ; %Flow495
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s24
	s_add_i32 s9, s9, s1
	v_add_co_u32 v2, vcc_lo, v29, s37
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_117:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_119
; %bb.118:                              ;   in Loop: Header=BB0_117 Depth=4
	global_load_b32 v2, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_119:                              ;   in Loop: Header=BB0_117 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_121
; %bb.120:                              ;   in Loop: Header=BB0_117 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_122
.LBB0_121:                              ;   in Loop: Header=BB0_117 Depth=4
	s_mov_b32 s1, -1
.LBB0_122:                              ; %Flow489
                                        ;   in Loop: Header=BB0_117 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_117
; %bb.123:                              ;   in Loop: Header=BB0_44 Depth=3
	global_load_b128 v[13:16], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_127
; %bb.124:                              ;   in Loop: Header=BB0_44 Depth=3
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15] offset:24 glc
	global_load_b64 v[17:18], v3, s[14:15]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v2, s22
	v_add_co_ci_u32_e32 v16, vcc_lo, s23, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v2
	v_and_b32_e32 v2, v16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v15, v4
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v17, v4
	v_mov_b32_e32 v17, v9
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v18, v2, vcc_lo
	v_mov_b32_e32 v18, v10
	global_store_b64 v[4:5], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_mov_b32 s0, 0
.LBB0_126:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_44 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[17:18]
	v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB0_44 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s18, s18, s20
	s_subb_u32 s19, s19, s21
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s21
	s_cmp_lg_u64 s[18:19], 0
	s_cbranch_scc1 .LBB0_44
; %bb.128:                              ; %Flow534
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB0_130
.LBB0_129:                              ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_130:                              ; %Flow549
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_159
; %bb.131:                              ;   in Loop: Header=BB0_15 Depth=2
	v_mov_b32_e32 v2, v43
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_137
; %bb.132:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[15:16], v3, s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v16
	v_and_b32_e32 v4, v4, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v13, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v13, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v9, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
	global_load_b64 v[13:14], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[15:16]
	s_cbranch_execz .LBB0_136
; %bb.133:                              ; %.preheader3.i.i.i26.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s10, 0
.LBB0_134:                              ; %.preheader3.i.i.i26.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b64 v[13:14], v3, s[14:15]
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v15, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[5:6]
	v_mov_b32_e32 v5, v9
	global_load_b64 v[13:14], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[15:16]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_134
; %bb.135:                              ; %Flow546
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_136:                              ; %Flow548
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_137:                              ; %.loopexit4.i.i.i21.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v3, s[14:15] offset:40
	global_load_b128 v[13:16], v3, s[14:15]
	v_readfirstlane_b32 s18, v4
	v_readfirstlane_b32 s19, v5
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_139
; %bb.138:                              ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s23, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v14, vcc_lo
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, v3
	global_store_b128 v[9:10], v[4:7], off offset:8
.LBB0_139:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v15, s8
	v_dual_mov_b32 v17, s10 :: v_dual_mov_b32 v16, s9
	s_clause 0x3
	global_store_b128 v[4:5], v[0:3], off
	global_store_b128 v[4:5], v[15:18], off offset:16
	global_store_b128 v[4:5], v[15:18], off offset:32
	global_store_b128 v[4:5], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_147
; %bb.140:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x1
	global_load_b64 v[19:20], v3, s[14:15] offset:32 glc
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	v_dual_mov_b32 v17, s18 :: v_dual_mov_b32 v18, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v0, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s22, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[0:1], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[17:20], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[17:18], v[19:20]
	s_cbranch_execz .LBB0_143
; %bb.141:                              ; %.preheader1.i.i.i24.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s11, 0
.LBB0_142:                              ; %.preheader1.i.i.i24.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[15:18], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[17:18]
	v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_142
.LBB0_143:                              ; %Flow544
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[0:1], v3, s[14:15] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_145
; %bb.144:                              ;   in Loop: Header=BB0_15 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_145:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b32 v2, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[2:3], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_147:                              ; %Flow545
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v0, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v1, vcc_lo, s20, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_148:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_150
; %bb.149:                              ;   in Loop: Header=BB0_148 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_150:                              ;   in Loop: Header=BB0_148 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_152
; %bb.151:                              ;   in Loop: Header=BB0_148 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_153
.LBB0_152:                              ;   in Loop: Header=BB0_148 Depth=3
	s_mov_b32 s1, -1
.LBB0_153:                              ; %Flow539
                                        ;   in Loop: Header=BB0_148 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_148
; %bb.154:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b128 v[13:16], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_158
; %bb.155:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	global_load_b64 v[4:5], v3, s[14:15] offset:24 glc
	global_load_b64 v[9:10], v3, s[14:15]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v2, s18
	v_add_co_ci_u32_e32 v16, vcc_lo, s19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_cndmask_b32 v15, v15, v2
	v_mov_b32_e32 v17, v4
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v2, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	global_store_b64 v[0:1], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_158
; %bb.156:                              ; %.preheader.i.i.i23.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, 0
.LBB0_157:                              ; %.preheader.i.i.i23.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[17:18]
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v17, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_157
.LBB0_158:                              ; %__ockl_hostcall_preview.exit.i.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_159:                              ; %__ockl_printf_append_string_n.exit.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	v_mov_b32_e32 v2, v43
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_165
; %bb.160:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[17:18], v3, s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	global_load_b64 v[4:5], v3, s[14:15]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v18
	v_and_b32_e32 v0, v0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v9, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v9, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[17:18]
	s_cbranch_execz .LBB0_164
; %bb.161:                              ; %.preheader3.i.i.i33.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s10, 0
.LBB0_162:                              ; %.preheader3.i.i.i33.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[9:10], v3, s[14:15]
	v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v4, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[9:10]
	v_and_b32_e32 v9, v5, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v9, 24, v[1:2]
	v_mov_b32_e32 v1, v4
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[15:18], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[17:18]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_162
; %bb.163:                              ; %Flow482
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_164:                              ; %Flow484
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_165:                              ; %.loopexit4.i.i.i27.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b128 v[17:20], v3, s[14:15]
	v_readfirstlane_b32 s18, v0
	v_readfirstlane_b32 s19, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_167
; %bb.166:                              ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s23, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s21
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v18, vcc_lo
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, v3
	global_store_b128 v[0:1], v[4:7], off offset:8
.LBB0_167:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v19, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v20, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v15, v41 :: v_dual_mov_b32 v16, v3
	v_dual_mov_b32 v22, s11 :: v_dual_mov_b32 v21, s10
	v_dual_mov_b32 v20, s9 :: v_dual_mov_b32 v19, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_175
; %bb.168:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x1
	global_load_b64 v[21:22], v3, s[14:15] offset:32 glc
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v20, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v4, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s22, v18, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[4:5], v[21:22], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[19:22], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[21:22]
	s_cbranch_execz .LBB0_171
; %bb.169:                              ; %.preheader1.i.i.i31.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s11, 0
.LBB0_170:                              ; %.preheader1.i.i.i31.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s18 :: v_dual_mov_b32 v14, s19
	s_sleep 1
	global_store_b64 v[4:5], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v3, v[13:16], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_170
.LBB0_171:                              ; %Flow480
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[4:5], v3, s[14:15] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_173
; %bb.172:                              ;   in Loop: Header=BB0_15 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[2:3], off offset:8
.LBB0_173:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_175
; %bb.174:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b32 v2, v[4:5], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[2:3], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_175:                              ; %Flow481
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v2, vcc_lo, v17, s21
	v_add_co_ci_u32_e32 v5, vcc_lo, s20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_176:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_178
; %bb.177:                              ;   in Loop: Header=BB0_176 Depth=3
	global_load_b32 v2, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_178:                              ;   in Loop: Header=BB0_176 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_180
; %bb.179:                              ;   in Loop: Header=BB0_176 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_181
.LBB0_180:                              ;   in Loop: Header=BB0_176 Depth=3
	s_mov_b32 s1, -1
.LBB0_181:                              ; %Flow475
                                        ;   in Loop: Header=BB0_176 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_176
; %bb.182:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[9:10], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_186
; %bb.183:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	global_load_b64 v[4:5], v3, s[14:15] offset:24 glc
	global_load_b64 v[15:16], v3, s[14:15]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v2, s18
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v2
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v13, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v2, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v5
	global_store_b64 v[0:1], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_186
; %bb.184:                              ; %.preheader.i.i.i30.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, 0
.LBB0_185:                              ; %.preheader.i.i.i30.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[15:16]
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v15, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_185
.LBB0_186:                              ; %__ockl_printf_append_args.exit.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v43
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_192
; %bb.187:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b64 v[15:16], v3, s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	global_load_b64 v[4:5], v3, s[14:15]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_191
; %bb.188:                              ; %.preheader3.i.i.i40.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s10, 0
.LBB0_189:                              ; %.preheader3.i.i.i40.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b64 v[13:14], v3, s[14:15]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v4, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[13:14]
	v_and_b32_e32 v13, v5, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v4
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[13:16], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_189
; %bb.190:                              ; %Flow468
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_191:                              ; %Flow470
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_192:                              ; %.loopexit4.i.i.i34.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[14:15] offset:40
	global_load_b128 v[13:16], v3, s[14:15]
	v_readfirstlane_b32 s18, v0
	v_readfirstlane_b32 s19, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[18:19], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s20, s10, 24
	s_mul_i32 s21, s10, 24
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_194
; %bb.193:                              ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s23, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v14, vcc_lo
	v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, v3
	global_store_b128 v[0:1], v[4:7], off offset:8
.LBB0_194:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v17, s10
	v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v15, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[9:12], off
	global_store_b128 v[0:1], v[15:18], off offset:16
	global_store_b128 v[0:1], v[15:18], off offset:32
	global_store_b128 v[0:1], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_202
; %bb.195:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v3, s[14:15] offset:32 glc
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[18:19]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s22, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s22, s22, s11
	v_add_co_u32 v0, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s22, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[15:18], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_198
; %bb.196:                              ; %.preheader1.i.i.i38.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s11, 0
.LBB0_197:                              ; %.preheader1.i.i.i38.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_sleep 1
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v3, v[9:12], s[14:15] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[11:12]
	v_dual_mov_b32 v12, v5 :: v_dual_mov_b32 v11, v4
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_197
.LBB0_198:                              ; %Flow466
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[0:1], v3, s[14:15] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_200
; %bb.199:                              ;   in Loop: Header=BB0_15 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_200:                              ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_202
; %bb.201:                              ;   in Loop: Header=BB0_15 Depth=2
	global_load_b32 v2, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_202:                              ; %Flow467
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s20, s20, s1
	v_add_co_u32 v0, vcc_lo, v13, s21
	v_add_co_ci_u32_e32 v1, vcc_lo, s20, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_203:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_205
; %bb.204:                              ;   in Loop: Header=BB0_203 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_205:                              ;   in Loop: Header=BB0_203 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_207
; %bb.206:                              ;   in Loop: Header=BB0_203 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_208
.LBB0_207:                              ;   in Loop: Header=BB0_203 Depth=3
	s_mov_b32 s1, -1
.LBB0_208:                              ; %Flow461
                                        ;   in Loop: Header=BB0_203 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_203
; %bb.209:                              ;   in Loop: Header=BB0_15 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_213
; %bb.210:                              ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[14:15] offset:40
	global_load_b64 v[4:5], v3, s[14:15] offset:24 glc
	global_load_b64 v[11:12], v3, s[14:15]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v2, s18
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v13 :: v_dual_cndmask_b32 v9, v9, v2
	v_and_b32_e32 v1, v10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v9, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v2, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_mov_b32_e32 v11, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v5
	global_store_b64 v[0:1], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[9:12], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_213
; %bb.211:                              ; %.preheader.i.i.i37.i.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s0, 0
.LBB0_212:                              ; %.preheader.i.i.i37.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v3, v[9:12], s[14:15] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[11:12]
	v_dual_mov_b32 v12, v5 :: v_dual_mov_b32 v11, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_212
.LBB0_213:                              ; %__ockl_printf_append_args.exit41.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s36, s36, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s36, s5
	s_cbranch_scc1 .LBB0_15
; %bb.214:                              ; %_Z13load_full_rowPfS_iiii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s35, s35, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cmp_ge_i32 s35, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_225
; %bb.215:                              ; %.lr.ph138
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v0, v40, 12
	s_mov_b32 s0, s35
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v9, v39 :: v_dual_add_nc_u32 v4, v50, v0
	v_add_nc_u32_e32 v5, v38, v0
.LBB0_216:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_217 Depth 3
                                        ;       Child Loop BB0_223 Depth 3
	v_mad_u64_u32 v[0:1], null, s0, s27, v[34:35]
	s_mov_b32 s9, 0
	s_mov_b32 s1, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, 12
	v_add_nc_u32_e32 v2, v50, v1
	v_add_nc_u32_e32 v1, v38, v1
.LBB0_217:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_216 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_mov_b32 s10, exec_lo
	v_cmpx_eq_u32_e64 s9, v35
	s_cbranch_execz .LBB0_219
; %bb.218:                              ;   in Loop: Header=BB0_217 Depth=3
	ds_load_b32 v10, v4
	ds_load_b32 v11, v2
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v12, null, v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v12, v13, 1.0
	v_fmac_f32_e32 v13, v14, v13
	v_div_scale_f32 v14, vcc_lo, v11, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v14, v13
	v_fma_f32 v16, -v12, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v13
	v_fma_f32 v12, -v12, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v12, v12, v13, v15
	v_div_fixup_f32 v10, v12, v10, v11
	ds_store_b32 v2, v10
.LBB0_219:                              ;   in Loop: Header=BB0_217 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_lt_u32_e64 s9, v35
	s_cbranch_execz .LBB0_221
; %bb.220:                              ;   in Loop: Header=BB0_217 Depth=3
	s_lshl_b32 s9, s9, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v10, s9, v1
	v_add_nc_u32_e32 v11, s9, v5
	ds_load_b32 v10, v10
	ds_load_b32 v11, v11
	ds_load_b32 v12, v2
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v10, -v11, v10, v12
	ds_store_b32 v2, v10
.LBB0_221:                              ;   in Loop: Header=BB0_217 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_xor_b32 s1, s1, -1
	s_mov_b32 s9, 1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_217
; %bb.222:                              ; %_Z9trsm_tilePfiii.exit.preheader
                                        ;   in Loop: Header=BB0_216 Depth=2
	v_mov_b32_e32 v2, v9
	v_mov_b32_e32 v10, v51
	s_cmp_ge_u32 s35, s0
	s_mov_b32 s1, s35
	s_cbranch_scc1 .LBB0_224
.LBB0_223:                              ; %_Z9trsm_tilePfiii.exit
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_216 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	s_add_i32 s1, s1, 1
	v_add_nc_u32_e32 v2, s29, v2
	s_cmp_lt_u32 s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v13, v[11:12], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v45, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[13:14], v10 offset1:1
	ds_load_2addr_b32 v[15:16], v1 offset1:1
	ds_load_b32 v17, v47
	v_add_nc_u32_e32 v10, s28, v10
	s_waitcnt lgkmcnt(1)
	v_fma_f32 v13, v15, v13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v16, v14
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v13, v17, v13
	ds_store_b32 v47, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v13, v45
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[11:12], v13, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_223
.LBB0_224:                              ; %_Z9trsm_tilePfiii.exit._crit_edge
                                        ;   in Loop: Header=BB0_216 Depth=2
	v_mad_u64_u32 v[10:11], null, s1, s26, v[35:36]
	s_add_i32 s0, s0, 1
	v_add_nc_u32_e32 v9, s30, v9
	s_cmp_lt_i32 s0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v0, s6, v[10:11]
	v_mad_u64_u32 v[12:13], null, v11, s7, v[33:34]
	v_mov_b32_e32 v13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[12:13]
	v_mad_u64_u32 v[13:14], null, v10, 12, v[38:39]
	v_add_co_u32 v11, vcc_lo, s12, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b32 v0, v[11:12], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v45, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[13:14], v13 offset1:1
	ds_load_2addr_b32 v[0:1], v1 offset1:1
	ds_load_b32 v2, v47
	s_waitcnt lgkmcnt(1)
	v_fma_f32 v0, v0, v13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v1, v14
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v0, v2, v0
	ds_store_b32 v47, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v45
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[11:12], v0, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_216
.LBB0_225:                              ; %.lr.ph.i114.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v0, v52
	v_mov_b32_e32 v2, v36
	s_mov_b32 s0, s5
.LBB0_226:                              ; %.lr.ph.i114
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v1, v0
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v2, s30, v2
	v_add_nc_u32_e32 v0, s33, v0
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_cmp_lg_u32 s0, 0
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[4:5], v1, off
	s_cbranch_scc1 .LBB0_226
; %bb.227:                              ; %_Z14store_full_rowPfS_iiii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v51, s28, v51
	v_add_nc_u32_e32 v39, s31, v39
	v_add_nc_u32_e32 v36, s29, v36
	s_cmp_lg_u32 s35, s5
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_2
.LBB0_228:                              ; %._crit_edge144
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27right_looking_launch_kernelPfiiii
		.amdhsa_group_segment_fixed_size 4
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 53
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27right_looking_launch_kernelPfiiii, .Lfunc_end0-_Z27right_looking_launch_kernelPfiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10092
; NumSgprs: 43
; NumVgprs: 53
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 53
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d, %d\n"
	.size	.str, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 4
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27right_looking_launch_kernelPfiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     43
    .sgpr_spill_count: 0
    .symbol:         _Z27right_looking_launch_kernelPfiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     53
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
