/*
    Programming on Massively Parallel Systems
    Fall 2018
    Project # 3
    Student: Patricia Wilthew

    Compile: nvcc proj3.cu -o proj3
    Usage: ./proj3 {#of_elements_in_array1} {#of_elements_in_array2}
*/

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <assert.h>
#include <thrust/scan.h>
#define RAND_RANGE(N) ((double)rand()/((double)RAND_MAX + 1)*(N))
#define PARTITION_LENGTH 128
#define SECTION_LENGTH 4

cudaError_t err;
__device__ int matches = 0;

/*
    Function: catch_error

    Description: Prints any CUDA error to stdout.
*/
void catch_error(cudaError_t error)
{
    if (error)
    {
        printf("Error: %s\n", cudaGetErrorString(err));
    }
}

/*
    Function: data_generator

    Description: Uses Knuth Shuffle to generate integers in data.
*/
void data_generator(int* data, int count, int first, int step)
{
    assert(data != NULL);

    for (int i = 0; i < count; ++i)
    {
        data[i] = first + i * step;
    }
    
    srand(time(NULL));
    
    for (int i = count-1; i>0; i--) //knuth shuffle
    {
        int j = RAND_RANGE(i);
        int k_tmp = data[i];
        data[i] = data[j];
        data[j] = k_tmp;
    }
}

/*
    Function: bfe

    Description: This function embeds PTX code of CUDA to extract bit
        field from x.

    Input:
        start (uint): Starting bit position relative to the LSB.
        nbits (uint): The bit field length.

    Output: The extracted bit field as an unsigned integer.
*/
__device__ uint bfe(uint x, uint start, uint nbits)
{
    uint bits;
    asm("bfe.u32 %0, %1, %2, %3;" : "=r"(bits) : "r"(x), "r"(start), "r"(nbits));
    return bits;
}

/*
    Function: histogram

    Description: In order to efficiently partition the input in parallel,
        first we need to compute a histogram of the radix values by
        scanning the array of keys so that we know the number of keys
        that should go to each partition.
*/
__global__ void histogram(int *array, int array_length, int *hist)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int radix;

    if (idx < array_length)
    {
        radix = (int) bfe(array[idx], 0, 31-__builtin_clz(PARTITION_LENGTH));
        atomicAdd(&hist[blockIdx.x * PARTITION_LENGTH + radix], 1);
    }
}

/*
    Function: organize_histogram

    Description: Given a histogram `hist` of the form:
        [w1, x1, y1, z1,   w2, x2, y2, z2,   w3, x3, y3, z3], create an
        `organized` histogram of the form:
        [w1, w2, w3,   x1, x2, x3,   y1, y2, y3,   z1, z2, z3].
*/
__global__ void organize_histogram(int *hist, int hist_length, int *organized)
{
    int number_of_sections = hist_length / PARTITION_LENGTH;
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int value, section_offset;

    if (idx < hist_length)
    {
        section_offset = idx/number_of_sections;
        value = hist[
                    PARTITION_LENGTH * (idx % number_of_sections)
                    + section_offset
                ];
        organized[idx] = value;
    }
}

/*
    Function: Kogge_Stone_scan_kernel

    Description: This is the first of the three kernels needed to implement the
        hierarchical scan with three kernels. It uses Kogge Stone scan
        algorithm to compute the prefix sum of each block of length
        SECTION_LENGTH.
*/
__global__ void Kogge_Stone_block_scan_kernel(int *X, int *Y, int *S, int length)
{
    __shared__ int XY[SECTION_LENGTH];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < length)
    {
        XY[threadIdx.x] = X[idx];
    }

    for (unsigned int stride = 1; stride < blockDim.x; stride *= 2)
    {
        __syncthreads();
        if (threadIdx.x >= stride) XY[threadIdx.x] += XY[threadIdx.x-stride];
    }

    Y[idx] = XY[threadIdx.x];

    __syncthreads();
    
    // If this is the last thread of the block:
    if (threadIdx.x == blockDim.x - 1)
    {
       S[blockIdx.x] = XY[SECTION_LENGTH - 1];
    }
}

/*
    Function: parallel_scan_kernel

    Description: The second kernel of the hierarchical scan is simply one of the
        three parallel scan kernels, which takes S as input and writes S as
        output.

*/
__global__ void parallel_scan_kernel(int *X, int *Y, int length)
{
    __shared__ int XY[SECTION_LENGTH];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < length)
    {
        XY[threadIdx.x] = X[idx];
    }

    for (unsigned int stride = 1; stride < blockDim.x; stride *= 2)
    {
        __syncthreads();
        if (threadIdx.x >= stride) XY[threadIdx.x] += XY[threadIdx.x-stride];
    }

    Y[idx] = XY[threadIdx.x];
}

/*
    Function: add_S_to_Y_kernel

    Description: The third kernel of the hierarchical scan takes the S and Y
        arrays as inputs and writes its output back into Y. Assuming that we
        launch the kernel with SECTION_LENGTH threads in each block, each thread
        adds one of the S elements (selected by blockIdx.x-1) to one Y element.
*/
__global__ void add_S_to_Y_kernel(int *Y, int *S, int length)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int j, sum;

    if (blockIdx.x > 0 && idx < length)
    {
        Y[idx] += S[blockIdx.x - 1];
    
        // Also add the prefix sum of previous sections.
        if (blockIdx.x >= SECTION_LENGTH)
        {
            sum = 0;
            for (j = SECTION_LENGTH - 1; j < blockIdx.x - 1; j += 4)
            {
                sum += S[j];
            }
            Y[idx] += sum;
        }
    }
}

/* 
    Function: shift_right

    Description: Performs 1-shift right on original array and stores it in a new
        array. This is performed to convert an inclusive prefix sum into
        exclusive.
*/
__global__ void shift_right(int *original, int *shifted)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    if (idx == 0)
    {
        shifted[idx] = 0;
    }
    else
    {
        shifted[idx] = original[idx - 1];
    }
}

/*
    Function: reduce_prefix_sum

    Description: Given a `prefix_sum` array of the form:
        [0, 6, 15, 24, 30, 37, 44, 51, 60, 71, 79, 87, 90, 98, 106, 114],
        Create a `reduced` array of PARTITION_LENGTH length, 4, of the form:
        [0, 30, 60, 90] that contains the index in which each partition starts.
*/
__global__ void reduce_prefix_sum(int *prefix_sum, int *reduced, int *reduced_copy, int p_length)
{
    int number;
    number = prefix_sum[blockIdx.x * p_length];
    reduced[blockIdx.x] = number;
    reduced_copy[blockIdx.x] = number;
}

/*
    Function: re_order

    Description: Re-order original `array` by radix into a partitioned new
        array, `ordered`.
*/
__global__ void re_order(int *prefix_sum, int *array, int *ordered, int length)
{
    int offset;
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int radix = (int) bfe(array[idx], 0, 31-__builtin_clz(PARTITION_LENGTH));

    if (idx < length)
    {
        // `offset` will have the value of prefix_sum[radix]
        // before it is incremented by one.
        offset = atomicAdd(&prefix_sum[radix], 1);
        ordered[offset] = array[idx];
    }
}

/*
    Function: probe

    Description: With the reordered keys from both input arrays, we can
        now perform the probe stage by only comparing the keys from the
        corresponding partitions of both input arrays. This can be done
        by nested-loop comparisons.
*/
__global__ void probe(int *r_delim, int *s_delim, int *r, int *s, int r_length, int s_length)
{
    int r_start, r_end, s_start, s_end;
    int i, j, count = 0;

    // Get delimiters of current partition.
    r_start = r_delim[blockIdx.x];
    s_start = s_delim[blockIdx.x];

    if (blockIdx.x == PARTITION_LENGTH - 1)
    {
        r_end = r_length - 1;
        s_end = s_length - 1;
    }
    else
    {
        r_end = r_delim[blockIdx.x + 1] - 1;
        s_end = s_delim[blockIdx.x + 1] - 1;
    }
    
    for (i=r_start; i <= r_end; i++)
    {
        for (j=s_start; j <= s_end; j++)
        {
            if (r[i] == s[j])
            {   
                count += 1;
            }
        }
    }
    atomicAdd(&matches, count);

}

__global__ void print_matches()
{
    printf("---> %d matches\n", matches);
}


int main(int argc, char const *argv[])
{
    if (argc <= 2)
    {
        printf("Usage: ./proj3.out {#of_elements_in_array1} {#of_elements_in_array2}\n");
        exit(1);
    }

    int r_length = atoi(argv[1]);
    int s_length = atoi(argv[2]);
    int r_size = sizeof(int)*r_length;
    int s_size = sizeof(int)*s_length;
    int r_hist_len, r_hist_size;
    int s_hist_len, s_hist_size;
    int blocks;
    double threads = 1024.0;
    float time, total_time = 0.0;

    int *r_host, *r_hist, *r_prefix_sum, *r_ordered, *r_reduced_prefix, 
        *r_reduced_prefix_copy;
    int *s_host, *s_hist, *s_prefix_sum, *s_ordered, *s_reduced_prefix,
        *s_reduced_prefix_copy;
    
    int *X, *Y, *S, *S2;
    
    // Allocate arrays in host and device.
    cudaMallocHost((void**)&r_host, r_size);
    cudaMallocHost((void**)&s_host, s_size);

    // Populate arrays.
    data_generator(r_host, r_length, 0, 1);
    data_generator(s_host, s_length, 0, 1);

    // Recording variables.
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);


    /************************************
    *                                   *
    *   Order r into partitioned array  *
    *                                   *
    ************************************/
    blocks = ceil(r_length/threads);
    r_hist_len = PARTITION_LENGTH * blocks;
    r_hist_size = sizeof(int)*r_hist_len;
    cudaMalloc((void**)&r_hist, r_hist_size); cudaMemset(r_hist, 0, r_hist_size);
    cudaMalloc((void**)&X, r_hist_size);
    cudaMalloc((void**)&Y, r_hist_size);
    cudaMalloc((void**)&S, r_hist_size/SECTION_LENGTH);
    cudaMalloc((void**)&S2, r_hist_size/SECTION_LENGTH);
    cudaMalloc((void**)&r_prefix_sum, r_hist_size);
    cudaMalloc((void**)&r_reduced_prefix, PARTITION_LENGTH*sizeof(int));
    cudaMalloc((void**)&r_reduced_prefix_copy, PARTITION_LENGTH*sizeof(int));
    cudaMalloc((void**)&r_ordered, r_size); cudaMemset(r_ordered, 0, r_size);

    // Histogram for r: r_hist.
    cudaEventRecord(start, 0);
    histogram<<<blocks, threads>>>(r_host, r_length, r_hist);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Organized histogram for r: X
    cudaEventRecord(start, 0);
    organize_histogram<<<ceil(r_hist_len/threads), threads>>>(
        r_hist, r_hist_len, X);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part I): Y and S.
    cudaEventRecord(start, 0);
    Kogge_Stone_block_scan_kernel<<<
        ceil(r_hist_len/(SECTION_LENGTH)),
        SECTION_LENGTH>>>(X, Y, S, r_hist_len);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part II): S2.
    cudaEventRecord(start, 0);
    parallel_scan_kernel<<<ceil(r_hist_len/SECTION_LENGTH), SECTION_LENGTH>>>(
        S, S2, r_hist_len/SECTION_LENGTH);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part III): Y.
    cudaEventRecord(start, 0);
    add_S_to_Y_kernel<<<
        ceil(r_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, S2, r_hist_len);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Convert to exclusive prefix sum.
    cudaEventRecord(start, 0);
    shift_right<<<
        ceil(r_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, r_prefix_sum);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Obtain reduced prefix sum (of partition size)
    cudaEventRecord(start, 0);
    reduce_prefix_sum<<<PARTITION_LENGTH, 1>>>(
        r_prefix_sum, r_reduced_prefix, r_reduced_prefix_copy, blocks);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Reorder R array.
    cudaEventRecord(start, 0);
    re_order<<<ceil(r_length/threads), threads>>>(
        r_reduced_prefix, r_host, r_ordered, r_length);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;


    /************************************
    *                                   *
    *   Order s into partitioned array  *
    *                                   *
    ************************************/
    blocks = ceil(s_length/threads);
    s_hist_len = PARTITION_LENGTH * blocks;
    s_hist_size = sizeof(int)*s_hist_len;
    cudaMalloc((void**)&s_hist, s_hist_size); cudaMemset(s_hist, 0, s_hist_size);
    cudaMalloc((void**)&X, s_hist_size);
    cudaMalloc((void**)&Y, s_hist_size);
    cudaMalloc((void**)&S, s_hist_size/SECTION_LENGTH);
    cudaMalloc((void**)&S2, s_hist_size/SECTION_LENGTH);
    cudaMalloc((void**)&s_prefix_sum, s_hist_size);
    cudaMalloc((void**)&s_reduced_prefix, PARTITION_LENGTH*sizeof(int));
    cudaMalloc((void**)&s_reduced_prefix_copy, PARTITION_LENGTH*sizeof(int));
    cudaMalloc((void**)&s_ordered, s_size); cudaMemset(s_ordered, 0, s_size);

    // Histogram for s: s_hist.
    cudaEventRecord(start, 0);
    histogram<<<blocks, threads>>>(s_host, s_length, s_hist);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Organized histogram for s: X
    cudaEventRecord(start, 0);
    organize_histogram<<<ceil(s_hist_len/threads), threads>>>(
        s_hist, s_hist_len, X);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part I): Y and S.
    cudaEventRecord(start, 0);
    Kogge_Stone_block_scan_kernel<<<
        ceil(s_hist_len/(SECTION_LENGTH)),
        SECTION_LENGTH>>>(X, Y, S, s_hist_len);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part II): S2.
    cudaEventRecord(start, 0);
    parallel_scan_kernel<<<ceil(s_hist_len/SECTION_LENGTH), SECTION_LENGTH>>>(
        S, S2, s_hist_len/SECTION_LENGTH);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part III): Y.
    cudaEventRecord(start, 0);
    add_S_to_Y_kernel<<<
        ceil(s_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, S2, s_hist_len);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Convert to exclusive prefix sum.
    cudaEventRecord(start, 0);
    shift_right<<<
        ceil(s_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, s_prefix_sum);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Obtain reduced prefix sum (of partition size)
    cudaEventRecord(start, 0);
    reduce_prefix_sum<<<PARTITION_LENGTH, 1>>>(
        s_prefix_sum, s_reduced_prefix, s_reduced_prefix_copy, blocks);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    // Reorder s array.
    cudaEventRecord(start, 0);
    re_order<<<
        ceil(s_length/threads),
        threads>>>(s_reduced_prefix, s_host, s_ordered, s_length);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;


    /************************************
    *                                   *
    *               Probing             *
    *                                   *
    ************************************/
    cudaEventRecord(start, 0);
    probe<<<PARTITION_LENGTH, 1>>>(
        r_reduced_prefix_copy, s_reduced_prefix_copy, r_ordered, s_ordered,
        r_length, s_length);
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&time, start, stop);
    total_time += time;

    cudaEventDestroy(start);
    cudaEventDestroy(stop);
    
    cudaDeviceSynchronize();
    printf(
        "******** Total Running Time of All Kernels = %.5f sec ********\n",
        total_time/1000.0);

    print_matches<<<1, 1>>>();
    cudaDeviceSynchronize();

    cudaFree(X);
    cudaFree(Y);
    cudaFree(S);
    cudaFree(S2);
    cudaFree(r_hist);
    cudaFree(r_prefix_sum);
    cudaFree(r_reduced_prefix);
    cudaFree(r_ordered);
    cudaFree(s_hist);
    cudaFree(s_prefix_sum);
    cudaFree(s_reduced_prefix);
    cudaFree(s_ordered);

    return 0;
}



	.file	"tmpxft_0026d0f8_00000000-6_radix_join.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.weak	nvtxEtiGetModuleFunctionTable_v3
	.hidden	nvtxEtiGetModuleFunctionTable_v3
	.type	nvtxEtiGetModuleFunctionTable_v3, @function
nvtxEtiGetModuleFunctionTable_v3:
.LFB6203:
	.cfi_startproc
	endbr64
	decl	%edi
	xorl	%eax, %eax
	cmpl	$5, %edi
	ja	.L1
	leaq	.L4(%rip), %rcx
	movslq	(%rcx,%rdi,4), %rax
	addq	%rcx, %rax
	notrack jmp	*%rax
	.section	.rodata.nvtxEtiGetModuleFunctionTable_v3,"aG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.align 4
	.align 4
.L4:
	.long	.L9-.L4
	.long	.L14-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
.L9:
	leaq	560+nvtxGlobals_v3(%rip), %rcx
	jmp	.L18
.L7:
	leaq	776+nvtxGlobals_v3(%rip), %rcx
	movl	$128, %eax
	jmp	.L8
.L6:
	leaq	904+nvtxGlobals_v3(%rip), %rcx
	jmp	.L19
.L5:
	leaq	968+nvtxGlobals_v3(%rip), %rcx
.L18:
	movl	$136, %eax
	jmp	.L8
.L3:
	leaq	1104+nvtxGlobals_v3(%rip), %rcx
.L19:
	movl	$64, %eax
	jmp	.L8
.L14:
	leaq	696+nvtxGlobals_v3(%rip), %rcx
	movl	$80, %eax
.L8:
	testq	%rdx, %rdx
	je	.L10
	shrl	$3, %eax
	decl	%eax
	movl	%eax, (%rdx)
.L10:
	testq	%rsi, %rsi
	jne	.L11
.L12:
	movl	$1, %eax
	ret
.L11:
	movq	%rcx, (%rsi)
	jmp	.L12
.L1:
	ret
	.cfi_endproc
.LFE6203:
	.size	nvtxEtiGetModuleFunctionTable_v3, .-nvtxEtiGetModuleFunctionTable_v3
	.section	.text.nvtxGetExportTable_v3,"axG",@progbits,nvtxGetExportTable_v3,comdat
	.weak	nvtxGetExportTable_v3
	.hidden	nvtxGetExportTable_v3
	.type	nvtxGetExportTable_v3, @function
nvtxGetExportTable_v3:
.LFB6204:
	.cfi_startproc
	endbr64
	leaq	8+nvtxGlobals_v3(%rip), %rax
	cmpl	$1, %edi
	je	.L21
	cmpl	$3, %edi
	leaq	16(%rax), %rax
	movl	$0, %edx
	cmovne	%rdx, %rax
.L21:
	ret
	.cfi_endproc
.LFE6204:
	.size	nvtxGetExportTable_v3, .-nvtxGetExportTable_v3
	.section	.text.nvtxEtiSetInjectionNvtxVersion_v3,"axG",@progbits,nvtxEtiSetInjectionNvtxVersion_v3,comdat
	.weak	nvtxEtiSetInjectionNvtxVersion_v3
	.hidden	nvtxEtiSetInjectionNvtxVersion_v3
	.type	nvtxEtiSetInjectionNvtxVersion_v3, @function
nvtxEtiSetInjectionNvtxVersion_v3:
.LFB6205:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE6205:
	.size	nvtxEtiSetInjectionNvtxVersion_v3, .-nvtxEtiSetInjectionNvtxVersion_v3
	.text
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10466:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE10466:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,"axG",@progbits,_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,comdat
	.weak	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.hidden	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.type	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, @function
_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:
.LFB10897:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L28:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10897:
	.size	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, .-_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.section	.text.nvtxSetInitFunctionsToNoops_v3,"axG",@progbits,nvtxSetInitFunctionsToNoops_v3,comdat
	.weak	nvtxSetInitFunctionsToNoops_v3
	.hidden	nvtxSetInitFunctionsToNoops_v3
	.type	nvtxSetInitFunctionsToNoops_v3, @function
nvtxSetInitFunctionsToNoops_v3:
.LFB6270:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	leaq	nvtxMarkEx_impl_init_v3(%rip), %rdx
	setne	%al
	cmpq	%rdx, 48+nvtxGlobals_v3(%rip)
	je	.L161
	testb	%al, %al
	je	.L33
.L161:
	xorl	%r10d, %r10d
	movq	%r10, 48+nvtxGlobals_v3(%rip)
.L33:
	leaq	nvtxMarkA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 56+nvtxGlobals_v3(%rip)
	je	.L162
	testb	%al, %al
	je	.L35
.L162:
	xorl	%r9d, %r9d
	movq	%r9, 56+nvtxGlobals_v3(%rip)
.L35:
	leaq	nvtxMarkW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 64+nvtxGlobals_v3(%rip)
	je	.L163
	testb	%al, %al
	je	.L37
.L163:
	xorl	%r8d, %r8d
	movq	%r8, 64+nvtxGlobals_v3(%rip)
.L37:
	leaq	nvtxRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 72+nvtxGlobals_v3(%rip)
	je	.L164
	testb	%al, %al
	je	.L39
.L164:
	xorl	%edi, %edi
	movq	%rdi, 72+nvtxGlobals_v3(%rip)
.L39:
	leaq	nvtxRangeStartA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 80+nvtxGlobals_v3(%rip)
	je	.L165
	testb	%al, %al
	je	.L41
.L165:
	xorl	%esi, %esi
	movq	%rsi, 80+nvtxGlobals_v3(%rip)
.L41:
	leaq	nvtxRangeStartW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 88+nvtxGlobals_v3(%rip)
	je	.L166
	testb	%al, %al
	je	.L43
.L166:
	xorl	%ecx, %ecx
	movq	%rcx, 88+nvtxGlobals_v3(%rip)
.L43:
	leaq	nvtxRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 96+nvtxGlobals_v3(%rip)
	je	.L167
	testb	%al, %al
	je	.L45
.L167:
	xorl	%edx, %edx
	movq	%rdx, 96+nvtxGlobals_v3(%rip)
.L45:
	leaq	nvtxRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 104+nvtxGlobals_v3(%rip)
	je	.L168
	testb	%al, %al
	je	.L47
.L168:
	xorl	%r11d, %r11d
	movq	%r11, 104+nvtxGlobals_v3(%rip)
.L47:
	leaq	nvtxRangePushA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 112+nvtxGlobals_v3(%rip)
	je	.L169
	testb	%al, %al
	je	.L49
.L169:
	xorl	%r10d, %r10d
	movq	%r10, 112+nvtxGlobals_v3(%rip)
.L49:
	leaq	nvtxRangePushW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 120+nvtxGlobals_v3(%rip)
	je	.L170
	testb	%al, %al
	je	.L51
.L170:
	xorl	%r9d, %r9d
	movq	%r9, 120+nvtxGlobals_v3(%rip)
.L51:
	leaq	nvtxRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 128+nvtxGlobals_v3(%rip)
	je	.L171
	testb	%al, %al
	je	.L53
.L171:
	xorl	%r8d, %r8d
	movq	%r8, 128+nvtxGlobals_v3(%rip)
.L53:
	leaq	nvtxNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 136+nvtxGlobals_v3(%rip)
	je	.L172
	testb	%al, %al
	je	.L55
.L172:
	xorl	%edi, %edi
	movq	%rdi, 136+nvtxGlobals_v3(%rip)
.L55:
	leaq	nvtxNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 144+nvtxGlobals_v3(%rip)
	je	.L173
	testb	%al, %al
	je	.L57
.L173:
	xorl	%esi, %esi
	movq	%rsi, 144+nvtxGlobals_v3(%rip)
.L57:
	leaq	nvtxNameOsThreadA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 152+nvtxGlobals_v3(%rip)
	je	.L174
	testb	%al, %al
	je	.L59
.L174:
	xorl	%ecx, %ecx
	movq	%rcx, 152+nvtxGlobals_v3(%rip)
.L59:
	leaq	nvtxNameOsThreadW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 160+nvtxGlobals_v3(%rip)
	je	.L175
	testb	%al, %al
	je	.L61
.L175:
	xorl	%edx, %edx
	movq	%rdx, 160+nvtxGlobals_v3(%rip)
.L61:
	leaq	nvtxNameCuDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 168+nvtxGlobals_v3(%rip)
	je	.L176
	testb	%al, %al
	je	.L63
.L176:
	xorl	%r11d, %r11d
	movq	%r11, 168+nvtxGlobals_v3(%rip)
.L63:
	leaq	nvtxNameCuDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 176+nvtxGlobals_v3(%rip)
	je	.L177
	testb	%al, %al
	je	.L65
.L177:
	xorl	%r10d, %r10d
	movq	%r10, 176+nvtxGlobals_v3(%rip)
.L65:
	leaq	nvtxNameCuContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 184+nvtxGlobals_v3(%rip)
	je	.L178
	testb	%al, %al
	je	.L67
.L178:
	xorl	%r9d, %r9d
	movq	%r9, 184+nvtxGlobals_v3(%rip)
.L67:
	leaq	nvtxNameCuContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 192+nvtxGlobals_v3(%rip)
	je	.L179
	testb	%al, %al
	je	.L69
.L179:
	xorl	%r8d, %r8d
	movq	%r8, 192+nvtxGlobals_v3(%rip)
.L69:
	leaq	nvtxNameCuStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 200+nvtxGlobals_v3(%rip)
	je	.L180
	testb	%al, %al
	je	.L71
.L180:
	xorl	%edi, %edi
	movq	%rdi, 200+nvtxGlobals_v3(%rip)
.L71:
	leaq	nvtxNameCuStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 208+nvtxGlobals_v3(%rip)
	je	.L181
	testb	%al, %al
	je	.L73
.L181:
	xorl	%esi, %esi
	movq	%rsi, 208+nvtxGlobals_v3(%rip)
.L73:
	leaq	nvtxNameCuEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 216+nvtxGlobals_v3(%rip)
	je	.L182
	testb	%al, %al
	je	.L75
.L182:
	xorl	%ecx, %ecx
	movq	%rcx, 216+nvtxGlobals_v3(%rip)
.L75:
	leaq	nvtxNameCuEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 224+nvtxGlobals_v3(%rip)
	je	.L183
	testb	%al, %al
	je	.L77
.L183:
	xorl	%edx, %edx
	movq	%rdx, 224+nvtxGlobals_v3(%rip)
.L77:
	leaq	nvtxNameClDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 232+nvtxGlobals_v3(%rip)
	je	.L184
	testb	%al, %al
	je	.L79
.L184:
	xorl	%r11d, %r11d
	movq	%r11, 232+nvtxGlobals_v3(%rip)
.L79:
	leaq	nvtxNameClDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 240+nvtxGlobals_v3(%rip)
	je	.L185
	testb	%al, %al
	je	.L81
.L185:
	xorl	%r10d, %r10d
	movq	%r10, 240+nvtxGlobals_v3(%rip)
.L81:
	leaq	nvtxNameClContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 248+nvtxGlobals_v3(%rip)
	je	.L186
	testb	%al, %al
	je	.L83
.L186:
	xorl	%r9d, %r9d
	movq	%r9, 248+nvtxGlobals_v3(%rip)
.L83:
	leaq	nvtxNameClContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 256+nvtxGlobals_v3(%rip)
	je	.L187
	testb	%al, %al
	je	.L85
.L187:
	xorl	%r8d, %r8d
	movq	%r8, 256+nvtxGlobals_v3(%rip)
.L85:
	leaq	nvtxNameClCommandQueueA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 264+nvtxGlobals_v3(%rip)
	je	.L188
	testb	%al, %al
	je	.L87
.L188:
	xorl	%edi, %edi
	movq	%rdi, 264+nvtxGlobals_v3(%rip)
.L87:
	leaq	nvtxNameClCommandQueueW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 272+nvtxGlobals_v3(%rip)
	je	.L189
	testb	%al, %al
	je	.L89
.L189:
	xorl	%esi, %esi
	movq	%rsi, 272+nvtxGlobals_v3(%rip)
.L89:
	leaq	nvtxNameClMemObjectA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 280+nvtxGlobals_v3(%rip)
	je	.L190
	testb	%al, %al
	je	.L91
.L190:
	xorl	%ecx, %ecx
	movq	%rcx, 280+nvtxGlobals_v3(%rip)
.L91:
	leaq	nvtxNameClMemObjectW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 288+nvtxGlobals_v3(%rip)
	je	.L191
	testb	%al, %al
	je	.L93
.L191:
	xorl	%edx, %edx
	movq	%rdx, 288+nvtxGlobals_v3(%rip)
.L93:
	leaq	nvtxNameClSamplerA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 296+nvtxGlobals_v3(%rip)
	je	.L192
	testb	%al, %al
	je	.L95
.L192:
	xorl	%r11d, %r11d
	movq	%r11, 296+nvtxGlobals_v3(%rip)
.L95:
	leaq	nvtxNameClSamplerW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 304+nvtxGlobals_v3(%rip)
	je	.L193
	testb	%al, %al
	je	.L97
.L193:
	xorl	%r10d, %r10d
	movq	%r10, 304+nvtxGlobals_v3(%rip)
.L97:
	leaq	nvtxNameClProgramA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 312+nvtxGlobals_v3(%rip)
	je	.L194
	testb	%al, %al
	je	.L99
.L194:
	xorl	%r9d, %r9d
	movq	%r9, 312+nvtxGlobals_v3(%rip)
.L99:
	leaq	nvtxNameClProgramW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 320+nvtxGlobals_v3(%rip)
	je	.L195
	testb	%al, %al
	je	.L101
.L195:
	xorl	%r8d, %r8d
	movq	%r8, 320+nvtxGlobals_v3(%rip)
.L101:
	leaq	nvtxNameClEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 328+nvtxGlobals_v3(%rip)
	je	.L196
	testb	%al, %al
	je	.L103
.L196:
	xorl	%edi, %edi
	movq	%rdi, 328+nvtxGlobals_v3(%rip)
.L103:
	leaq	nvtxNameClEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 336+nvtxGlobals_v3(%rip)
	je	.L197
	testb	%al, %al
	je	.L105
.L197:
	xorl	%esi, %esi
	movq	%rsi, 336+nvtxGlobals_v3(%rip)
.L105:
	leaq	nvtxNameCudaDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 344+nvtxGlobals_v3(%rip)
	je	.L198
	testb	%al, %al
	je	.L107
.L198:
	xorl	%ecx, %ecx
	movq	%rcx, 344+nvtxGlobals_v3(%rip)
.L107:
	leaq	nvtxNameCudaDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 352+nvtxGlobals_v3(%rip)
	je	.L199
	testb	%al, %al
	je	.L109
.L199:
	xorl	%edx, %edx
	movq	%rdx, 352+nvtxGlobals_v3(%rip)
.L109:
	leaq	nvtxNameCudaStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 360+nvtxGlobals_v3(%rip)
	je	.L200
	testb	%al, %al
	je	.L111
.L200:
	xorl	%r11d, %r11d
	movq	%r11, 360+nvtxGlobals_v3(%rip)
.L111:
	leaq	nvtxNameCudaStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 368+nvtxGlobals_v3(%rip)
	je	.L201
	testb	%al, %al
	je	.L113
.L201:
	xorl	%r10d, %r10d
	movq	%r10, 368+nvtxGlobals_v3(%rip)
.L113:
	leaq	nvtxNameCudaEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 376+nvtxGlobals_v3(%rip)
	je	.L202
	testb	%al, %al
	je	.L115
.L202:
	xorl	%r9d, %r9d
	movq	%r9, 376+nvtxGlobals_v3(%rip)
.L115:
	leaq	nvtxNameCudaEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 384+nvtxGlobals_v3(%rip)
	je	.L203
	testb	%al, %al
	je	.L117
.L203:
	xorl	%r8d, %r8d
	movq	%r8, 384+nvtxGlobals_v3(%rip)
.L117:
	leaq	nvtxDomainMarkEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 392+nvtxGlobals_v3(%rip)
	je	.L204
	testb	%al, %al
	je	.L119
.L204:
	xorl	%edi, %edi
	movq	%rdi, 392+nvtxGlobals_v3(%rip)
.L119:
	leaq	nvtxDomainRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 400+nvtxGlobals_v3(%rip)
	je	.L205
	testb	%al, %al
	je	.L121
.L205:
	xorl	%esi, %esi
	movq	%rsi, 400+nvtxGlobals_v3(%rip)
.L121:
	leaq	nvtxDomainRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 408+nvtxGlobals_v3(%rip)
	je	.L206
	testb	%al, %al
	je	.L123
.L206:
	xorl	%ecx, %ecx
	movq	%rcx, 408+nvtxGlobals_v3(%rip)
.L123:
	leaq	nvtxDomainRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 416+nvtxGlobals_v3(%rip)
	je	.L207
	testb	%al, %al
	je	.L125
.L207:
	xorl	%edx, %edx
	movq	%rdx, 416+nvtxGlobals_v3(%rip)
.L125:
	leaq	nvtxDomainRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 424+nvtxGlobals_v3(%rip)
	je	.L208
	testb	%al, %al
	je	.L127
.L208:
	xorl	%r11d, %r11d
	movq	%r11, 424+nvtxGlobals_v3(%rip)
.L127:
	leaq	nvtxDomainResourceCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 432+nvtxGlobals_v3(%rip)
	je	.L209
	testb	%al, %al
	je	.L129
.L209:
	xorl	%r10d, %r10d
	movq	%r10, 432+nvtxGlobals_v3(%rip)
.L129:
	leaq	nvtxDomainResourceDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 440+nvtxGlobals_v3(%rip)
	je	.L210
	testb	%al, %al
	je	.L131
.L210:
	xorl	%r9d, %r9d
	movq	%r9, 440+nvtxGlobals_v3(%rip)
.L131:
	leaq	nvtxDomainNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 448+nvtxGlobals_v3(%rip)
	je	.L211
	testb	%al, %al
	je	.L133
.L211:
	xorl	%r8d, %r8d
	movq	%r8, 448+nvtxGlobals_v3(%rip)
.L133:
	leaq	nvtxDomainNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 456+nvtxGlobals_v3(%rip)
	je	.L212
	testb	%al, %al
	je	.L135
.L212:
	xorl	%edi, %edi
	movq	%rdi, 456+nvtxGlobals_v3(%rip)
.L135:
	leaq	nvtxDomainRegisterStringA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 464+nvtxGlobals_v3(%rip)
	je	.L213
	testb	%al, %al
	je	.L137
.L213:
	xorl	%esi, %esi
	movq	%rsi, 464+nvtxGlobals_v3(%rip)
.L137:
	leaq	nvtxDomainRegisterStringW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 472+nvtxGlobals_v3(%rip)
	je	.L214
	testb	%al, %al
	je	.L139
.L214:
	xorl	%ecx, %ecx
	movq	%rcx, 472+nvtxGlobals_v3(%rip)
.L139:
	leaq	nvtxDomainCreateA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 480+nvtxGlobals_v3(%rip)
	je	.L215
	testb	%al, %al
	je	.L141
.L215:
	xorl	%edx, %edx
	movq	%rdx, 480+nvtxGlobals_v3(%rip)
.L141:
	leaq	nvtxDomainCreateW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 488+nvtxGlobals_v3(%rip)
	je	.L216
	testb	%al, %al
	je	.L143
.L216:
	xorl	%r11d, %r11d
	movq	%r11, 488+nvtxGlobals_v3(%rip)
.L143:
	leaq	nvtxDomainDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 496+nvtxGlobals_v3(%rip)
	je	.L217
	testb	%al, %al
	je	.L145
.L217:
	xorl	%r10d, %r10d
	movq	%r10, 496+nvtxGlobals_v3(%rip)
.L145:
	leaq	nvtxInitialize_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 504+nvtxGlobals_v3(%rip)
	je	.L218
	testb	%al, %al
	je	.L147
.L218:
	xorl	%r9d, %r9d
	movq	%r9, 504+nvtxGlobals_v3(%rip)
.L147:
	leaq	nvtxDomainSyncUserCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 512+nvtxGlobals_v3(%rip)
	je	.L219
	testb	%al, %al
	je	.L149
.L219:
	xorl	%r8d, %r8d
	movq	%r8, 512+nvtxGlobals_v3(%rip)
.L149:
	leaq	nvtxDomainSyncUserDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 520+nvtxGlobals_v3(%rip)
	je	.L220
	testb	%al, %al
	je	.L151
.L220:
	xorl	%edi, %edi
	movq	%rdi, 520+nvtxGlobals_v3(%rip)
.L151:
	leaq	nvtxDomainSyncUserAcquireStart_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 528+nvtxGlobals_v3(%rip)
	je	.L221
	testb	%al, %al
	je	.L153
.L221:
	xorl	%esi, %esi
	movq	%rsi, 528+nvtxGlobals_v3(%rip)
.L153:
	leaq	nvtxDomainSyncUserAcquireFailed_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 536+nvtxGlobals_v3(%rip)
	je	.L222
	testb	%al, %al
	je	.L155
.L222:
	xorl	%ecx, %ecx
	movq	%rcx, 536+nvtxGlobals_v3(%rip)
.L155:
	leaq	nvtxDomainSyncUserAcquireSuccess_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 544+nvtxGlobals_v3(%rip)
	je	.L223
	testb	%al, %al
	je	.L157
.L223:
	xorl	%edx, %edx
	movq	%rdx, 544+nvtxGlobals_v3(%rip)
.L157:
	leaq	nvtxDomainSyncUserReleasing_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 552+nvtxGlobals_v3(%rip)
	je	.L224
	testb	%al, %al
	je	.L32
.L224:
	xorl	%eax, %eax
	movq	%rax, 552+nvtxGlobals_v3(%rip)
.L32:
	ret
	.cfi_endproc
.LFE6270:
	.size	nvtxSetInitFunctionsToNoops_v3, .-nvtxSetInitFunctionsToNoops_v3
	.section	.rodata.nvtxInitializeInjectionLibrary_v3.str1.1,"aMS",@progbits,1
.LC0:
	.string	"NVTX_INJECTION64_PATH"
.LC1:
	.string	"InitializeInjectionNvtx2"
	.section	.text.nvtxInitializeInjectionLibrary_v3,"axG",@progbits,nvtxInitializeInjectionLibrary_v3,comdat
	.weak	nvtxInitializeInjectionLibrary_v3
	.hidden	nvtxInitializeInjectionLibrary_v3
	.type	nvtxInitializeInjectionLibrary_v3, @function
nvtxInitializeInjectionLibrary_v3:
.LFB6271:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC0(%rip), %rdi
	call	getenv@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L418
	movl	$1, %esi
	movq	%rax, %rdi
	call	dlopen@PLT
	movl	$4, %edx
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L417
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	dlsym@PLT
	testq	%rax, %rax
	jne	.L420
	movq	%rbx, %rdi
	call	dlclose@PLT
	movl	$5, %edx
	jmp	.L417
.L418:
	movq	InitializeInjectionNvtx2_fnptr(%rip), %rax
	movl	$7, %edx
	testq	%rax, %rax
	je	.L417
.L420:
	leaq	nvtxGetExportTable_v3(%rip), %rdi
	call	*%rax
	xorl	%edx, %edx
	testl	%eax, %eax
	jne	.L417
	testq	%rbx, %rbx
	je	.L421
	movq	%rbx, %rdi
	call	dlclose@PLT
.L421:
	movl	$6, %edx
.L417:
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6271:
	.size	nvtxInitializeInjectionLibrary_v3, .-nvtxInitializeInjectionLibrary_v3
	.section	.text.nvtxInitOnce_v3,"axG",@progbits,nvtxInitOnce_v3,comdat
	.weak	nvtxInitOnce_v3
	.hidden	nvtxInitOnce_v3
	.type	nvtxInitOnce_v3, @function
nvtxInitOnce_v3:
.LFB6272:
	.cfi_startproc
	endbr64
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L437
	pushq	%rdx
	.cfi_def_cfa_offset 16
	movl	$1, %eax
	xorl	%edx, %edx
	mfence
	lock cmpxchgl	%edx, nvtxGlobals_v3(%rip)
	testl	%eax, %eax
	jne	.L440
	call	nvtxInitializeInjectionLibrary_v3
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	call	nvtxSetInitFunctionsToNoops_v3
	movl	$2, %eax
	mfence
	xchgl	nvtxGlobals_v3(%rip), %eax
	jmp	.L429
.L440:
	mfence
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L429
	call	sched_yield@PLT
	jmp	.L440
.L429:
	popq	%rax
	.cfi_def_cfa_offset 8
	ret
.L437:
	ret
	.cfi_endproc
.LFE6272:
	.size	nvtxInitOnce_v3, .-nvtxInitOnce_v3
	.section	.text.nvtxDomainSyncUserReleasing_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserReleasing_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserReleasing_impl_init_v3
	.hidden	nvtxDomainSyncUserReleasing_impl_init_v3
	.type	nvtxDomainSyncUserReleasing_impl_init_v3, @function
nvtxDomainSyncUserReleasing_impl_init_v3:
.LFB6269:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	552+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L441
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L441:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6269:
	.size	nvtxDomainSyncUserReleasing_impl_init_v3, .-nvtxDomainSyncUserReleasing_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireSuccess_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireSuccess_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.type	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, @function
nvtxDomainSyncUserAcquireSuccess_impl_init_v3:
.LFB6268:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	544+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L444
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L444:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6268:
	.size	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, .-nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireFailed_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireFailed_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.type	nvtxDomainSyncUserAcquireFailed_impl_init_v3, @function
nvtxDomainSyncUserAcquireFailed_impl_init_v3:
.LFB6267:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	536+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L447
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L447:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6267:
	.size	nvtxDomainSyncUserAcquireFailed_impl_init_v3, .-nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireStart_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireStart_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.type	nvtxDomainSyncUserAcquireStart_impl_init_v3, @function
nvtxDomainSyncUserAcquireStart_impl_init_v3:
.LFB6266:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	528+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L450
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L450:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6266:
	.size	nvtxDomainSyncUserAcquireStart_impl_init_v3, .-nvtxDomainSyncUserAcquireStart_impl_init_v3
	.section	.text.nvtxDomainSyncUserDestroy_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserDestroy_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserDestroy_impl_init_v3
	.hidden	nvtxDomainSyncUserDestroy_impl_init_v3
	.type	nvtxDomainSyncUserDestroy_impl_init_v3, @function
nvtxDomainSyncUserDestroy_impl_init_v3:
.LFB6265:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	520+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L453
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L453:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6265:
	.size	nvtxDomainSyncUserDestroy_impl_init_v3, .-nvtxDomainSyncUserDestroy_impl_init_v3
	.section	.text.nvtxDomainSyncUserCreate_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserCreate_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserCreate_impl_init_v3
	.hidden	nvtxDomainSyncUserCreate_impl_init_v3
	.type	nvtxDomainSyncUserCreate_impl_init_v3, @function
nvtxDomainSyncUserCreate_impl_init_v3:
.LFB6264:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	512+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L457
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L457:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6264:
	.size	nvtxDomainSyncUserCreate_impl_init_v3, .-nvtxDomainSyncUserCreate_impl_init_v3
	.section	.text.nvtxInitialize_impl_init_v3,"axG",@progbits,nvtxInitialize_impl_init_v3,comdat
	.weak	nvtxInitialize_impl_init_v3
	.hidden	nvtxInitialize_impl_init_v3
	.type	nvtxInitialize_impl_init_v3, @function
nvtxInitialize_impl_init_v3:
.LFB6235:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	504+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L459
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L459:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6235:
	.size	nvtxInitialize_impl_init_v3, .-nvtxInitialize_impl_init_v3
	.section	.text.nvtxDomainDestroy_impl_init_v3,"axG",@progbits,nvtxDomainDestroy_impl_init_v3,comdat
	.weak	nvtxDomainDestroy_impl_init_v3
	.hidden	nvtxDomainDestroy_impl_init_v3
	.type	nvtxDomainDestroy_impl_init_v3, @function
nvtxDomainDestroy_impl_init_v3:
.LFB6234:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	496+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L462
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L462:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6234:
	.size	nvtxDomainDestroy_impl_init_v3, .-nvtxDomainDestroy_impl_init_v3
	.section	.text.nvtxDomainCreateW_impl_init_v3,"axG",@progbits,nvtxDomainCreateW_impl_init_v3,comdat
	.weak	nvtxDomainCreateW_impl_init_v3
	.hidden	nvtxDomainCreateW_impl_init_v3
	.type	nvtxDomainCreateW_impl_init_v3, @function
nvtxDomainCreateW_impl_init_v3:
.LFB6233:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	488+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L466
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L466:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6233:
	.size	nvtxDomainCreateW_impl_init_v3, .-nvtxDomainCreateW_impl_init_v3
	.section	.text.nvtxDomainCreateA_impl_init_v3,"axG",@progbits,nvtxDomainCreateA_impl_init_v3,comdat
	.weak	nvtxDomainCreateA_impl_init_v3
	.hidden	nvtxDomainCreateA_impl_init_v3
	.type	nvtxDomainCreateA_impl_init_v3, @function
nvtxDomainCreateA_impl_init_v3:
.LFB6232:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	480+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L469
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L469:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6232:
	.size	nvtxDomainCreateA_impl_init_v3, .-nvtxDomainCreateA_impl_init_v3
	.section	.text.nvtxDomainRegisterStringW_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringW_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringW_impl_init_v3
	.hidden	nvtxDomainRegisterStringW_impl_init_v3
	.type	nvtxDomainRegisterStringW_impl_init_v3, @function
nvtxDomainRegisterStringW_impl_init_v3:
.LFB6231:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	472+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L472
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L472:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6231:
	.size	nvtxDomainRegisterStringW_impl_init_v3, .-nvtxDomainRegisterStringW_impl_init_v3
	.section	.text.nvtxDomainRegisterStringA_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringA_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringA_impl_init_v3
	.hidden	nvtxDomainRegisterStringA_impl_init_v3
	.type	nvtxDomainRegisterStringA_impl_init_v3, @function
nvtxDomainRegisterStringA_impl_init_v3:
.LFB6230:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	464+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L475
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L475:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6230:
	.size	nvtxDomainRegisterStringA_impl_init_v3, .-nvtxDomainRegisterStringA_impl_init_v3
	.section	.text.nvtxDomainNameCategoryW_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryW_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryW_impl_init_v3
	.hidden	nvtxDomainNameCategoryW_impl_init_v3
	.type	nvtxDomainNameCategoryW_impl_init_v3, @function
nvtxDomainNameCategoryW_impl_init_v3:
.LFB6229:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	456+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L477
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L477:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6229:
	.size	nvtxDomainNameCategoryW_impl_init_v3, .-nvtxDomainNameCategoryW_impl_init_v3
	.section	.text.nvtxDomainNameCategoryA_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryA_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryA_impl_init_v3
	.hidden	nvtxDomainNameCategoryA_impl_init_v3
	.type	nvtxDomainNameCategoryA_impl_init_v3, @function
nvtxDomainNameCategoryA_impl_init_v3:
.LFB6228:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	448+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L480
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L480:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6228:
	.size	nvtxDomainNameCategoryA_impl_init_v3, .-nvtxDomainNameCategoryA_impl_init_v3
	.section	.text.nvtxDomainResourceDestroy_impl_init_v3,"axG",@progbits,nvtxDomainResourceDestroy_impl_init_v3,comdat
	.weak	nvtxDomainResourceDestroy_impl_init_v3
	.hidden	nvtxDomainResourceDestroy_impl_init_v3
	.type	nvtxDomainResourceDestroy_impl_init_v3, @function
nvtxDomainResourceDestroy_impl_init_v3:
.LFB6227:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	440+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L483
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L483:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6227:
	.size	nvtxDomainResourceDestroy_impl_init_v3, .-nvtxDomainResourceDestroy_impl_init_v3
	.section	.text.nvtxDomainResourceCreate_impl_init_v3,"axG",@progbits,nvtxDomainResourceCreate_impl_init_v3,comdat
	.weak	nvtxDomainResourceCreate_impl_init_v3
	.hidden	nvtxDomainResourceCreate_impl_init_v3
	.type	nvtxDomainResourceCreate_impl_init_v3, @function
nvtxDomainResourceCreate_impl_init_v3:
.LFB6226:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	432+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L487
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L487:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6226:
	.size	nvtxDomainResourceCreate_impl_init_v3, .-nvtxDomainResourceCreate_impl_init_v3
	.section	.text.nvtxDomainRangePop_impl_init_v3,"axG",@progbits,nvtxDomainRangePop_impl_init_v3,comdat
	.weak	nvtxDomainRangePop_impl_init_v3
	.hidden	nvtxDomainRangePop_impl_init_v3
	.type	nvtxDomainRangePop_impl_init_v3, @function
nvtxDomainRangePop_impl_init_v3:
.LFB6225:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	424+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L490
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L490:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6225:
	.size	nvtxDomainRangePop_impl_init_v3, .-nvtxDomainRangePop_impl_init_v3
	.section	.text.nvtxDomainRangePushEx_impl_init_v3,"axG",@progbits,nvtxDomainRangePushEx_impl_init_v3,comdat
	.weak	nvtxDomainRangePushEx_impl_init_v3
	.hidden	nvtxDomainRangePushEx_impl_init_v3
	.type	nvtxDomainRangePushEx_impl_init_v3, @function
nvtxDomainRangePushEx_impl_init_v3:
.LFB6224:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	416+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L493
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L493:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6224:
	.size	nvtxDomainRangePushEx_impl_init_v3, .-nvtxDomainRangePushEx_impl_init_v3
	.section	.text.nvtxDomainRangeEnd_impl_init_v3,"axG",@progbits,nvtxDomainRangeEnd_impl_init_v3,comdat
	.weak	nvtxDomainRangeEnd_impl_init_v3
	.hidden	nvtxDomainRangeEnd_impl_init_v3
	.type	nvtxDomainRangeEnd_impl_init_v3, @function
nvtxDomainRangeEnd_impl_init_v3:
.LFB6223:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	408+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L495
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L495:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6223:
	.size	nvtxDomainRangeEnd_impl_init_v3, .-nvtxDomainRangeEnd_impl_init_v3
	.section	.text.nvtxDomainRangeStartEx_impl_init_v3,"axG",@progbits,nvtxDomainRangeStartEx_impl_init_v3,comdat
	.weak	nvtxDomainRangeStartEx_impl_init_v3
	.hidden	nvtxDomainRangeStartEx_impl_init_v3
	.type	nvtxDomainRangeStartEx_impl_init_v3, @function
nvtxDomainRangeStartEx_impl_init_v3:
.LFB6222:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	400+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L499
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L499:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6222:
	.size	nvtxDomainRangeStartEx_impl_init_v3, .-nvtxDomainRangeStartEx_impl_init_v3
	.section	.text.nvtxDomainMarkEx_impl_init_v3,"axG",@progbits,nvtxDomainMarkEx_impl_init_v3,comdat
	.weak	nvtxDomainMarkEx_impl_init_v3
	.hidden	nvtxDomainMarkEx_impl_init_v3
	.type	nvtxDomainMarkEx_impl_init_v3, @function
nvtxDomainMarkEx_impl_init_v3:
.LFB6221:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	392+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L501
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L501:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6221:
	.size	nvtxDomainMarkEx_impl_init_v3, .-nvtxDomainMarkEx_impl_init_v3
	.section	.text.nvtxNameCudaEventW_impl_init_v3,"axG",@progbits,nvtxNameCudaEventW_impl_init_v3,comdat
	.weak	nvtxNameCudaEventW_impl_init_v3
	.hidden	nvtxNameCudaEventW_impl_init_v3
	.type	nvtxNameCudaEventW_impl_init_v3, @function
nvtxNameCudaEventW_impl_init_v3:
.LFB6249:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	384+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L504
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L504:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6249:
	.size	nvtxNameCudaEventW_impl_init_v3, .-nvtxNameCudaEventW_impl_init_v3
	.section	.text.nvtxNameCudaEventA_impl_init_v3,"axG",@progbits,nvtxNameCudaEventA_impl_init_v3,comdat
	.weak	nvtxNameCudaEventA_impl_init_v3
	.hidden	nvtxNameCudaEventA_impl_init_v3
	.type	nvtxNameCudaEventA_impl_init_v3, @function
nvtxNameCudaEventA_impl_init_v3:
.LFB6248:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	376+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L507
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L507:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6248:
	.size	nvtxNameCudaEventA_impl_init_v3, .-nvtxNameCudaEventA_impl_init_v3
	.section	.text.nvtxNameCudaStreamW_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamW_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamW_impl_init_v3
	.hidden	nvtxNameCudaStreamW_impl_init_v3
	.type	nvtxNameCudaStreamW_impl_init_v3, @function
nvtxNameCudaStreamW_impl_init_v3:
.LFB6247:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	368+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L510
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L510:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6247:
	.size	nvtxNameCudaStreamW_impl_init_v3, .-nvtxNameCudaStreamW_impl_init_v3
	.section	.text.nvtxNameCudaStreamA_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamA_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamA_impl_init_v3
	.hidden	nvtxNameCudaStreamA_impl_init_v3
	.type	nvtxNameCudaStreamA_impl_init_v3, @function
nvtxNameCudaStreamA_impl_init_v3:
.LFB6246:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	360+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L513
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L513:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6246:
	.size	nvtxNameCudaStreamA_impl_init_v3, .-nvtxNameCudaStreamA_impl_init_v3
	.section	.text.nvtxNameCudaDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceW_impl_init_v3
	.hidden	nvtxNameCudaDeviceW_impl_init_v3
	.type	nvtxNameCudaDeviceW_impl_init_v3, @function
nvtxNameCudaDeviceW_impl_init_v3:
.LFB6245:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	352+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L516
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L516:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6245:
	.size	nvtxNameCudaDeviceW_impl_init_v3, .-nvtxNameCudaDeviceW_impl_init_v3
	.section	.text.nvtxNameCudaDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceA_impl_init_v3
	.hidden	nvtxNameCudaDeviceA_impl_init_v3
	.type	nvtxNameCudaDeviceA_impl_init_v3, @function
nvtxNameCudaDeviceA_impl_init_v3:
.LFB6244:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	344+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L519
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L519:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6244:
	.size	nvtxNameCudaDeviceA_impl_init_v3, .-nvtxNameCudaDeviceA_impl_init_v3
	.section	.text.nvtxNameClEventW_impl_init_v3,"axG",@progbits,nvtxNameClEventW_impl_init_v3,comdat
	.weak	nvtxNameClEventW_impl_init_v3
	.hidden	nvtxNameClEventW_impl_init_v3
	.type	nvtxNameClEventW_impl_init_v3, @function
nvtxNameClEventW_impl_init_v3:
.LFB6263:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	336+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L522
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L522:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6263:
	.size	nvtxNameClEventW_impl_init_v3, .-nvtxNameClEventW_impl_init_v3
	.section	.text.nvtxNameClEventA_impl_init_v3,"axG",@progbits,nvtxNameClEventA_impl_init_v3,comdat
	.weak	nvtxNameClEventA_impl_init_v3
	.hidden	nvtxNameClEventA_impl_init_v3
	.type	nvtxNameClEventA_impl_init_v3, @function
nvtxNameClEventA_impl_init_v3:
.LFB6262:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	328+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L525
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L525:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6262:
	.size	nvtxNameClEventA_impl_init_v3, .-nvtxNameClEventA_impl_init_v3
	.section	.text.nvtxNameClProgramW_impl_init_v3,"axG",@progbits,nvtxNameClProgramW_impl_init_v3,comdat
	.weak	nvtxNameClProgramW_impl_init_v3
	.hidden	nvtxNameClProgramW_impl_init_v3
	.type	nvtxNameClProgramW_impl_init_v3, @function
nvtxNameClProgramW_impl_init_v3:
.LFB6261:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	320+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L528
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L528:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6261:
	.size	nvtxNameClProgramW_impl_init_v3, .-nvtxNameClProgramW_impl_init_v3
	.section	.text.nvtxNameClProgramA_impl_init_v3,"axG",@progbits,nvtxNameClProgramA_impl_init_v3,comdat
	.weak	nvtxNameClProgramA_impl_init_v3
	.hidden	nvtxNameClProgramA_impl_init_v3
	.type	nvtxNameClProgramA_impl_init_v3, @function
nvtxNameClProgramA_impl_init_v3:
.LFB6260:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	312+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L531
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L531:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6260:
	.size	nvtxNameClProgramA_impl_init_v3, .-nvtxNameClProgramA_impl_init_v3
	.section	.text.nvtxNameClSamplerW_impl_init_v3,"axG",@progbits,nvtxNameClSamplerW_impl_init_v3,comdat
	.weak	nvtxNameClSamplerW_impl_init_v3
	.hidden	nvtxNameClSamplerW_impl_init_v3
	.type	nvtxNameClSamplerW_impl_init_v3, @function
nvtxNameClSamplerW_impl_init_v3:
.LFB6259:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	304+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L534
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L534:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6259:
	.size	nvtxNameClSamplerW_impl_init_v3, .-nvtxNameClSamplerW_impl_init_v3
	.section	.text.nvtxNameClSamplerA_impl_init_v3,"axG",@progbits,nvtxNameClSamplerA_impl_init_v3,comdat
	.weak	nvtxNameClSamplerA_impl_init_v3
	.hidden	nvtxNameClSamplerA_impl_init_v3
	.type	nvtxNameClSamplerA_impl_init_v3, @function
nvtxNameClSamplerA_impl_init_v3:
.LFB6258:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	296+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L537
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L537:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6258:
	.size	nvtxNameClSamplerA_impl_init_v3, .-nvtxNameClSamplerA_impl_init_v3
	.section	.text.nvtxNameClMemObjectW_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectW_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectW_impl_init_v3
	.hidden	nvtxNameClMemObjectW_impl_init_v3
	.type	nvtxNameClMemObjectW_impl_init_v3, @function
nvtxNameClMemObjectW_impl_init_v3:
.LFB6257:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	288+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L540
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L540:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6257:
	.size	nvtxNameClMemObjectW_impl_init_v3, .-nvtxNameClMemObjectW_impl_init_v3
	.section	.text.nvtxNameClMemObjectA_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectA_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectA_impl_init_v3
	.hidden	nvtxNameClMemObjectA_impl_init_v3
	.type	nvtxNameClMemObjectA_impl_init_v3, @function
nvtxNameClMemObjectA_impl_init_v3:
.LFB6256:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	280+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L543
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L543:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6256:
	.size	nvtxNameClMemObjectA_impl_init_v3, .-nvtxNameClMemObjectA_impl_init_v3
	.section	.text.nvtxNameClCommandQueueW_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueW_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueW_impl_init_v3
	.hidden	nvtxNameClCommandQueueW_impl_init_v3
	.type	nvtxNameClCommandQueueW_impl_init_v3, @function
nvtxNameClCommandQueueW_impl_init_v3:
.LFB6255:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	272+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L546
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L546:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6255:
	.size	nvtxNameClCommandQueueW_impl_init_v3, .-nvtxNameClCommandQueueW_impl_init_v3
	.section	.text.nvtxNameClCommandQueueA_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueA_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueA_impl_init_v3
	.hidden	nvtxNameClCommandQueueA_impl_init_v3
	.type	nvtxNameClCommandQueueA_impl_init_v3, @function
nvtxNameClCommandQueueA_impl_init_v3:
.LFB6254:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	264+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L549
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L549:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6254:
	.size	nvtxNameClCommandQueueA_impl_init_v3, .-nvtxNameClCommandQueueA_impl_init_v3
	.section	.text.nvtxNameClContextW_impl_init_v3,"axG",@progbits,nvtxNameClContextW_impl_init_v3,comdat
	.weak	nvtxNameClContextW_impl_init_v3
	.hidden	nvtxNameClContextW_impl_init_v3
	.type	nvtxNameClContextW_impl_init_v3, @function
nvtxNameClContextW_impl_init_v3:
.LFB6253:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	256+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L552
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L552:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6253:
	.size	nvtxNameClContextW_impl_init_v3, .-nvtxNameClContextW_impl_init_v3
	.section	.text.nvtxNameClContextA_impl_init_v3,"axG",@progbits,nvtxNameClContextA_impl_init_v3,comdat
	.weak	nvtxNameClContextA_impl_init_v3
	.hidden	nvtxNameClContextA_impl_init_v3
	.type	nvtxNameClContextA_impl_init_v3, @function
nvtxNameClContextA_impl_init_v3:
.LFB6252:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	248+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L555
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L555:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6252:
	.size	nvtxNameClContextA_impl_init_v3, .-nvtxNameClContextA_impl_init_v3
	.section	.text.nvtxNameClDeviceW_impl_init_v3,"axG",@progbits,nvtxNameClDeviceW_impl_init_v3,comdat
	.weak	nvtxNameClDeviceW_impl_init_v3
	.hidden	nvtxNameClDeviceW_impl_init_v3
	.type	nvtxNameClDeviceW_impl_init_v3, @function
nvtxNameClDeviceW_impl_init_v3:
.LFB6251:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	240+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L558
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L558:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6251:
	.size	nvtxNameClDeviceW_impl_init_v3, .-nvtxNameClDeviceW_impl_init_v3
	.section	.text.nvtxNameClDeviceA_impl_init_v3,"axG",@progbits,nvtxNameClDeviceA_impl_init_v3,comdat
	.weak	nvtxNameClDeviceA_impl_init_v3
	.hidden	nvtxNameClDeviceA_impl_init_v3
	.type	nvtxNameClDeviceA_impl_init_v3, @function
nvtxNameClDeviceA_impl_init_v3:
.LFB6250:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	232+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L561
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L561:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6250:
	.size	nvtxNameClDeviceA_impl_init_v3, .-nvtxNameClDeviceA_impl_init_v3
	.section	.text.nvtxNameCuEventW_impl_init_v3,"axG",@progbits,nvtxNameCuEventW_impl_init_v3,comdat
	.weak	nvtxNameCuEventW_impl_init_v3
	.hidden	nvtxNameCuEventW_impl_init_v3
	.type	nvtxNameCuEventW_impl_init_v3, @function
nvtxNameCuEventW_impl_init_v3:
.LFB6243:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	224+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L564
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L564:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6243:
	.size	nvtxNameCuEventW_impl_init_v3, .-nvtxNameCuEventW_impl_init_v3
	.section	.text.nvtxNameCuEventA_impl_init_v3,"axG",@progbits,nvtxNameCuEventA_impl_init_v3,comdat
	.weak	nvtxNameCuEventA_impl_init_v3
	.hidden	nvtxNameCuEventA_impl_init_v3
	.type	nvtxNameCuEventA_impl_init_v3, @function
nvtxNameCuEventA_impl_init_v3:
.LFB6242:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	216+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L567
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L567:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6242:
	.size	nvtxNameCuEventA_impl_init_v3, .-nvtxNameCuEventA_impl_init_v3
	.section	.text.nvtxNameCuStreamW_impl_init_v3,"axG",@progbits,nvtxNameCuStreamW_impl_init_v3,comdat
	.weak	nvtxNameCuStreamW_impl_init_v3
	.hidden	nvtxNameCuStreamW_impl_init_v3
	.type	nvtxNameCuStreamW_impl_init_v3, @function
nvtxNameCuStreamW_impl_init_v3:
.LFB6241:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	208+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L570
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L570:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6241:
	.size	nvtxNameCuStreamW_impl_init_v3, .-nvtxNameCuStreamW_impl_init_v3
	.section	.text.nvtxNameCuStreamA_impl_init_v3,"axG",@progbits,nvtxNameCuStreamA_impl_init_v3,comdat
	.weak	nvtxNameCuStreamA_impl_init_v3
	.hidden	nvtxNameCuStreamA_impl_init_v3
	.type	nvtxNameCuStreamA_impl_init_v3, @function
nvtxNameCuStreamA_impl_init_v3:
.LFB6240:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	200+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L573
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L573:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6240:
	.size	nvtxNameCuStreamA_impl_init_v3, .-nvtxNameCuStreamA_impl_init_v3
	.section	.text.nvtxNameCuContextW_impl_init_v3,"axG",@progbits,nvtxNameCuContextW_impl_init_v3,comdat
	.weak	nvtxNameCuContextW_impl_init_v3
	.hidden	nvtxNameCuContextW_impl_init_v3
	.type	nvtxNameCuContextW_impl_init_v3, @function
nvtxNameCuContextW_impl_init_v3:
.LFB6239:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	192+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L576
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L576:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6239:
	.size	nvtxNameCuContextW_impl_init_v3, .-nvtxNameCuContextW_impl_init_v3
	.section	.text.nvtxNameCuContextA_impl_init_v3,"axG",@progbits,nvtxNameCuContextA_impl_init_v3,comdat
	.weak	nvtxNameCuContextA_impl_init_v3
	.hidden	nvtxNameCuContextA_impl_init_v3
	.type	nvtxNameCuContextA_impl_init_v3, @function
nvtxNameCuContextA_impl_init_v3:
.LFB6238:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	184+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L579
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L579:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6238:
	.size	nvtxNameCuContextA_impl_init_v3, .-nvtxNameCuContextA_impl_init_v3
	.section	.text.nvtxNameCuDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceW_impl_init_v3
	.hidden	nvtxNameCuDeviceW_impl_init_v3
	.type	nvtxNameCuDeviceW_impl_init_v3, @function
nvtxNameCuDeviceW_impl_init_v3:
.LFB6237:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	176+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L582
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L582:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6237:
	.size	nvtxNameCuDeviceW_impl_init_v3, .-nvtxNameCuDeviceW_impl_init_v3
	.section	.text.nvtxNameCuDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceA_impl_init_v3
	.hidden	nvtxNameCuDeviceA_impl_init_v3
	.type	nvtxNameCuDeviceA_impl_init_v3, @function
nvtxNameCuDeviceA_impl_init_v3:
.LFB6236:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	168+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L585
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L585:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6236:
	.size	nvtxNameCuDeviceA_impl_init_v3, .-nvtxNameCuDeviceA_impl_init_v3
	.section	.text.nvtxNameOsThreadW_impl_init_v3,"axG",@progbits,nvtxNameOsThreadW_impl_init_v3,comdat
	.weak	nvtxNameOsThreadW_impl_init_v3
	.hidden	nvtxNameOsThreadW_impl_init_v3
	.type	nvtxNameOsThreadW_impl_init_v3, @function
nvtxNameOsThreadW_impl_init_v3:
.LFB6220:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	160+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L588
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L588:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6220:
	.size	nvtxNameOsThreadW_impl_init_v3, .-nvtxNameOsThreadW_impl_init_v3
	.section	.text.nvtxNameOsThreadA_impl_init_v3,"axG",@progbits,nvtxNameOsThreadA_impl_init_v3,comdat
	.weak	nvtxNameOsThreadA_impl_init_v3
	.hidden	nvtxNameOsThreadA_impl_init_v3
	.type	nvtxNameOsThreadA_impl_init_v3, @function
nvtxNameOsThreadA_impl_init_v3:
.LFB6219:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	152+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L591
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L591:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6219:
	.size	nvtxNameOsThreadA_impl_init_v3, .-nvtxNameOsThreadA_impl_init_v3
	.section	.text.nvtxNameCategoryW_impl_init_v3,"axG",@progbits,nvtxNameCategoryW_impl_init_v3,comdat
	.weak	nvtxNameCategoryW_impl_init_v3
	.hidden	nvtxNameCategoryW_impl_init_v3
	.type	nvtxNameCategoryW_impl_init_v3, @function
nvtxNameCategoryW_impl_init_v3:
.LFB6218:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	144+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L594
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L594:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6218:
	.size	nvtxNameCategoryW_impl_init_v3, .-nvtxNameCategoryW_impl_init_v3
	.section	.text.nvtxNameCategoryA_impl_init_v3,"axG",@progbits,nvtxNameCategoryA_impl_init_v3,comdat
	.weak	nvtxNameCategoryA_impl_init_v3
	.hidden	nvtxNameCategoryA_impl_init_v3
	.type	nvtxNameCategoryA_impl_init_v3, @function
nvtxNameCategoryA_impl_init_v3:
.LFB6217:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	136+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L597
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L597:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6217:
	.size	nvtxNameCategoryA_impl_init_v3, .-nvtxNameCategoryA_impl_init_v3
	.section	.text.nvtxRangePop_impl_init_v3,"axG",@progbits,nvtxRangePop_impl_init_v3,comdat
	.weak	nvtxRangePop_impl_init_v3
	.hidden	nvtxRangePop_impl_init_v3
	.type	nvtxRangePop_impl_init_v3, @function
nvtxRangePop_impl_init_v3:
.LFB6216:
	.cfi_startproc
	endbr64
	pushq	%rsi
	.cfi_def_cfa_offset 16
	call	nvtxInitOnce_v3
	movq	128+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L601
	popq	%rcx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L601:
	.cfi_restore_state
	movl	$-2, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6216:
	.size	nvtxRangePop_impl_init_v3, .-nvtxRangePop_impl_init_v3
	.section	.text.nvtxRangePushW_impl_init_v3,"axG",@progbits,nvtxRangePushW_impl_init_v3,comdat
	.weak	nvtxRangePushW_impl_init_v3
	.hidden	nvtxRangePushW_impl_init_v3
	.type	nvtxRangePushW_impl_init_v3, @function
nvtxRangePushW_impl_init_v3:
.LFB6215:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	120+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L604
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L604:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6215:
	.size	nvtxRangePushW_impl_init_v3, .-nvtxRangePushW_impl_init_v3
	.section	.text.nvtxRangePushA_impl_init_v3,"axG",@progbits,nvtxRangePushA_impl_init_v3,comdat
	.weak	nvtxRangePushA_impl_init_v3
	.hidden	nvtxRangePushA_impl_init_v3
	.type	nvtxRangePushA_impl_init_v3, @function
nvtxRangePushA_impl_init_v3:
.LFB6214:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	112+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L607
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L607:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6214:
	.size	nvtxRangePushA_impl_init_v3, .-nvtxRangePushA_impl_init_v3
	.section	.text.nvtxRangePushEx_impl_init_v3,"axG",@progbits,nvtxRangePushEx_impl_init_v3,comdat
	.weak	nvtxRangePushEx_impl_init_v3
	.hidden	nvtxRangePushEx_impl_init_v3
	.type	nvtxRangePushEx_impl_init_v3, @function
nvtxRangePushEx_impl_init_v3:
.LFB6213:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	104+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L610
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L610:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6213:
	.size	nvtxRangePushEx_impl_init_v3, .-nvtxRangePushEx_impl_init_v3
	.section	.text.nvtxRangeEnd_impl_init_v3,"axG",@progbits,nvtxRangeEnd_impl_init_v3,comdat
	.weak	nvtxRangeEnd_impl_init_v3
	.hidden	nvtxRangeEnd_impl_init_v3
	.type	nvtxRangeEnd_impl_init_v3, @function
nvtxRangeEnd_impl_init_v3:
.LFB6212:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	96+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L612
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L612:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6212:
	.size	nvtxRangeEnd_impl_init_v3, .-nvtxRangeEnd_impl_init_v3
	.section	.text.nvtxRangeStartW_impl_init_v3,"axG",@progbits,nvtxRangeStartW_impl_init_v3,comdat
	.weak	nvtxRangeStartW_impl_init_v3
	.hidden	nvtxRangeStartW_impl_init_v3
	.type	nvtxRangeStartW_impl_init_v3, @function
nvtxRangeStartW_impl_init_v3:
.LFB6211:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	88+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L616
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L616:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6211:
	.size	nvtxRangeStartW_impl_init_v3, .-nvtxRangeStartW_impl_init_v3
	.section	.text.nvtxRangeStartA_impl_init_v3,"axG",@progbits,nvtxRangeStartA_impl_init_v3,comdat
	.weak	nvtxRangeStartA_impl_init_v3
	.hidden	nvtxRangeStartA_impl_init_v3
	.type	nvtxRangeStartA_impl_init_v3, @function
nvtxRangeStartA_impl_init_v3:
.LFB6210:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	80+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L619
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L619:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6210:
	.size	nvtxRangeStartA_impl_init_v3, .-nvtxRangeStartA_impl_init_v3
	.section	.text.nvtxRangeStartEx_impl_init_v3,"axG",@progbits,nvtxRangeStartEx_impl_init_v3,comdat
	.weak	nvtxRangeStartEx_impl_init_v3
	.hidden	nvtxRangeStartEx_impl_init_v3
	.type	nvtxRangeStartEx_impl_init_v3, @function
nvtxRangeStartEx_impl_init_v3:
.LFB6209:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	72+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L622
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L622:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6209:
	.size	nvtxRangeStartEx_impl_init_v3, .-nvtxRangeStartEx_impl_init_v3
	.section	.text.nvtxMarkW_impl_init_v3,"axG",@progbits,nvtxMarkW_impl_init_v3,comdat
	.weak	nvtxMarkW_impl_init_v3
	.hidden	nvtxMarkW_impl_init_v3
	.type	nvtxMarkW_impl_init_v3, @function
nvtxMarkW_impl_init_v3:
.LFB6208:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	64+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L624
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L624:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6208:
	.size	nvtxMarkW_impl_init_v3, .-nvtxMarkW_impl_init_v3
	.section	.text.nvtxMarkA_impl_init_v3,"axG",@progbits,nvtxMarkA_impl_init_v3,comdat
	.weak	nvtxMarkA_impl_init_v3
	.hidden	nvtxMarkA_impl_init_v3
	.type	nvtxMarkA_impl_init_v3, @function
nvtxMarkA_impl_init_v3:
.LFB6207:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	56+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L627
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L627:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6207:
	.size	nvtxMarkA_impl_init_v3, .-nvtxMarkA_impl_init_v3
	.section	.text.nvtxMarkEx_impl_init_v3,"axG",@progbits,nvtxMarkEx_impl_init_v3,comdat
	.weak	nvtxMarkEx_impl_init_v3
	.hidden	nvtxMarkEx_impl_init_v3
	.type	nvtxMarkEx_impl_init_v3, @function
nvtxMarkEx_impl_init_v3:
.LFB6206:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	48+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L630
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L630:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6206:
	.size	nvtxMarkEx_impl_init_v3, .-nvtxMarkEx_impl_init_v3
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Error: %s\n"
	.text
	.globl	_Z11catch_error9cudaError
	.type	_Z11catch_error9cudaError, @function
_Z11catch_error9cudaError:
.LFB10460:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L633
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	err(%rip), %edi
	call	cudaGetErrorString@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	popq	%rcx
	.cfi_def_cfa_offset 8
	movq	%rax, %rdx
	xorl	%eax, %eax
	jmp	__printf_chk@PLT
.L633:
	ret
	.cfi_endproc
.LFE10460:
	.size	_Z11catch_error9cudaError, .-_Z11catch_error9cudaError
	.globl	_Z14data_generatorPiiii
	.type	_Z14data_generatorPiiii, @function
_Z14data_generatorPiiii:
.LFB10461:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	xorl	%eax, %eax
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	pushq	%r8
	.cfi_def_cfa_offset 32
.L639:
	cmpl	%eax, %ebx
	jle	.L644
	movl	%edx, 0(%rbp,%rax,4)
	incq	%rax
	addl	%ecx, %edx
	jmp	.L639
.L644:
	xorl	%edi, %edi
	decl	%ebx
	call	time@PLT
	movslq	%ebx, %rbx
	movl	%eax, %edi
	call	srand@PLT
.L641:
	testl	%ebx, %ebx
	jle	.L645
	call	rand@PLT
	cvtsi2sdl	%ebx, %xmm1
	movl	0(%rbp,%rbx,4), %edx
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC3(%rip), %xmm0
	mulsd	%xmm1, %xmm0
	cvttsd2sil	%xmm0, %eax
	cltq
	leaq	0(%rbp,%rax,4), %rax
	movl	(%rax), %ecx
	movl	%ecx, 0(%rbp,%rbx,4)
	decq	%rbx
	movl	%edx, (%rax)
	jmp	.L641
.L645:
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10461:
	.size	_Z14data_generatorPiiii, .-_Z14data_generatorPiiii
	.globl	_Z3bfejjj
	.type	_Z3bfejjj, @function
_Z3bfejjj:
.LFB10462:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE10462:
	.size	_Z3bfejjj, .-_Z3bfejjj
	.globl	_Z31__device_stub__Z9histogramPiiS_PiiS_
	.type	_Z31__device_stub__Z9histogramPiiS_PiiS_, @function
_Z31__device_stub__Z9histogramPiiS_PiiS_:
.LFB10488:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L648
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9histogramPiiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L648:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L650
	call	__stack_chk_fail@PLT
.L650:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10488:
	.size	_Z31__device_stub__Z9histogramPiiS_PiiS_, .-_Z31__device_stub__Z9histogramPiiS_PiiS_
	.globl	_Z9histogramPiiS_
	.type	_Z9histogramPiiS_, @function
_Z9histogramPiiS_:
.LFB10489:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9histogramPiiS_PiiS_
	.cfi_endproc
.LFE10489:
	.size	_Z9histogramPiiS_, .-_Z9histogramPiiS_
	.globl	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_
	.type	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_, @function
_Z41__device_stub__Z18organize_histogramPiiS_PiiS_:
.LFB10490:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L653
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18organize_histogramPiiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L653:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L655
	call	__stack_chk_fail@PLT
.L655:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10490:
	.size	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_, .-_Z41__device_stub__Z18organize_histogramPiiS_PiiS_
	.globl	_Z18organize_histogramPiiS_
	.type	_Z18organize_histogramPiiS_, @function
_Z18organize_histogramPiiS_:
.LFB10491:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_
	.cfi_endproc
.LFE10491:
	.size	_Z18organize_histogramPiiS_, .-_Z18organize_histogramPiiS_
	.globl	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i
	.type	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i, @function
_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i:
.LFB10492:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L658
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z29Kogge_Stone_block_scan_kernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L658:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L660
	call	__stack_chk_fail@PLT
.L660:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10492:
	.size	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i, .-_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i
	.globl	_Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.type	_Z29Kogge_Stone_block_scan_kernelPiS_S_i, @function
_Z29Kogge_Stone_block_scan_kernelPiS_S_i:
.LFB10493:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE10493:
	.size	_Z29Kogge_Stone_block_scan_kernelPiS_S_i, .-_Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.globl	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i
	.type	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i, @function
_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i:
.LFB10494:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L663
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z20parallel_scan_kernelPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L663:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L665
	call	__stack_chk_fail@PLT
.L665:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10494:
	.size	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i, .-_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i
	.globl	_Z20parallel_scan_kernelPiS_i
	.type	_Z20parallel_scan_kernelPiS_i, @function
_Z20parallel_scan_kernelPiS_i:
.LFB10495:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i
	.cfi_endproc
.LFE10495:
	.size	_Z20parallel_scan_kernelPiS_i, .-_Z20parallel_scan_kernelPiS_i
	.globl	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i
	.type	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i, @function
_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i:
.LFB10496:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L668
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17add_S_to_Y_kernelPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L668:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L670
	call	__stack_chk_fail@PLT
.L670:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10496:
	.size	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i, .-_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i
	.globl	_Z17add_S_to_Y_kernelPiS_i
	.type	_Z17add_S_to_Y_kernelPiS_i, @function
_Z17add_S_to_Y_kernelPiS_i:
.LFB10497:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i
	.cfi_endproc
.LFE10497:
	.size	_Z17add_S_to_Y_kernelPiS_i, .-_Z17add_S_to_Y_kernelPiS_i
	.globl	_Z33__device_stub__Z11shift_rightPiS_PiS_
	.type	_Z33__device_stub__Z11shift_rightPiS_PiS_, @function
_Z33__device_stub__Z11shift_rightPiS_PiS_:
.LFB10498:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L673
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11shift_rightPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L673:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L675
	call	__stack_chk_fail@PLT
.L675:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10498:
	.size	_Z33__device_stub__Z11shift_rightPiS_PiS_, .-_Z33__device_stub__Z11shift_rightPiS_PiS_
	.globl	_Z11shift_rightPiS_
	.type	_Z11shift_rightPiS_, @function
_Z11shift_rightPiS_:
.LFB10499:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z11shift_rightPiS_PiS_
	.cfi_endproc
.LFE10499:
	.size	_Z11shift_rightPiS_, .-_Z11shift_rightPiS_
	.globl	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i
	.type	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i, @function
_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i:
.LFB10500:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L678
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17reduce_prefix_sumPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L678:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L680
	call	__stack_chk_fail@PLT
.L680:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10500:
	.size	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i, .-_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i
	.globl	_Z17reduce_prefix_sumPiS_S_i
	.type	_Z17reduce_prefix_sumPiS_S_i, @function
_Z17reduce_prefix_sumPiS_S_i:
.LFB10501:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i
	.cfi_endproc
.LFE10501:
	.size	_Z17reduce_prefix_sumPiS_S_i, .-_Z17reduce_prefix_sumPiS_S_i
	.globl	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i
	.type	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i:
.LFB10502:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L683
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8re_orderPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L683:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L685
	call	__stack_chk_fail@PLT
.L685:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10502:
	.size	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i
	.globl	_Z8re_orderPiS_S_i
	.type	_Z8re_orderPiS_S_i, @function
_Z8re_orderPiS_S_i:
.LFB10503:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i
	.cfi_endproc
.LFE10503:
	.size	_Z8re_orderPiS_S_i, .-_Z8re_orderPiS_S_i
	.globl	_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii
	.type	_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii, @function
_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii:
.LFB10504:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L688
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z5probePiS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L688:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L690
	call	__stack_chk_fail@PLT
.L690:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10504:
	.size	_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii, .-_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii
	.globl	_Z5probePiS_S_S_ii
	.type	_Z5probePiS_S_S_ii, @function
_Z5probePiS_S_S_ii:
.LFB10505:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii
	.cfi_endproc
.LFE10505:
	.size	_Z5probePiS_S_S_ii, .-_Z5probePiS_S_S_ii
	.globl	_Z32__device_stub__Z13print_matchesvv
	.type	_Z32__device_stub__Z13print_matchesvv, @function
_Z32__device_stub__Z13print_matchesvv:
.LFB10506:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L693
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13print_matchesv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L693:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L695
	call	__stack_chk_fail@PLT
.L695:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10506:
	.size	_Z32__device_stub__Z13print_matchesvv, .-_Z32__device_stub__Z13print_matchesvv
	.globl	_Z13print_matchesv
	.type	_Z13print_matchesv, @function
_Z13print_matchesv:
.LFB10507:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z13print_matchesvv
	.cfi_endproc
.LFE10507:
	.size	_Z13print_matchesv, .-_Z13print_matchesv
	.section	.rodata.str1.1
.LC4:
	.string	"Usage: ./proj3.out {#of_elements_in_array1} {#of_elements_in_array2}\n"
.LC8:
	.string	"******** Total Running Time of All Kernels = %.5f sec ********\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB10463:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	jg	.L699
	movl	$2, %edi
	leaq	.LC4(%rip), %rsi
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L699:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %r15d
	call	atoi@PLT
	leal	0(,%r15,4), %r12d
	leaq	64(%rsp), %rdi
	movslq	%r12d, %r12
	movl	%eax, %ebx
	movq	%r12, %rsi
	call	cudaMallocHost@PLT
	leal	0(,%rbx,4), %eax
	leaq	112(%rsp), %rdi
	cltq
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMallocHost@PLT
	movq	64(%rsp), %rdi
	xorl	%edx, %edx
	movl	%r15d, %esi
	movl	$1, %ecx
	call	_Z14data_generatorPiiii
	movq	112(%rsp), %rdi
	xorl	%edx, %edx
	movl	%ebx, %esi
	movl	$1, %ecx
	call	_Z14data_generatorPiiii
	leaq	192(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	200(%rsp), %rdi
	call	cudaEventCreate@PLT
	cvtsi2sdl	%r15d, %xmm0
	mulsd	.LC5(%rip), %xmm0
	call	ceil@PLT
	leaq	72(%rsp), %rdi
	cvttsd2sil	%xmm0, %r14d
	movsd	%xmm0, 32(%rsp)
	movl	%r14d, %ebp
	movl	%r14d, %eax
	sall	$9, %ebp
	sall	$7, %eax
	movslq	%ebp, %r13
	movl	%eax, 8(%rsp)
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movq	72(%rsp), %rdi
	movq	%r13, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	160(%rsp), %rax
	movq	%r13, %rsi
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	leaq	168(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	movl	$4, %ecx
	leaq	176(%rsp), %rdi
	cltd
	idivl	%ecx
	movslq	%eax, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	184(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	96(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	88(%rsp), %rdi
	movq	%r12, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	192(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r14d, 208(%rsp)
	movl	$4194305, %edx
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	salq	$10, %rdx
	xorl	%r9d, %r9d
	movl	216(%rsp), %esi
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L700
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	%r15d, %esi
	call	_Z31__device_stub__Z9histogramPiiS_PiiS_
.L700:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$4294968320, %r12
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	leaq	60(%rsp), %rdi
	movq	192(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	xorps	%xmm0, %xmm0
	addss	60(%rsp), %xmm0
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm0, %ebp
	call	cudaEventRecord@PLT
	cvtsi2sdl	8(%rsp), %xmm0
	mulsd	.LC5(%rip), %xmm0
	movq	%r12, 220(%rsp)
	movl	$1, 228(%rsp)
	call	ceil@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	cvttsd2siq	%xmm0, %rax
	movl	$1, %ecx
	movl	%eax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L701
	movq	160(%rsp), %rdx
	movl	8(%rsp), %esi
	movq	72(%rsp), %rdi
	call	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_
.L701:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	leaq	60(%rsp), %r13
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%r13, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm1
	addss	60(%rsp), %xmm1
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm1, %ebp
	call	cudaEventRecord@PLT
	movl	8(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4, %esi
	movl	$1073741825, %ecx
	movl	$1, 228(%rsp)
	cltd
	salq	$2, %rcx
	idivl	%esi
	movq	%rcx, 220(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 208(%rsp)
	movl	%eax, %r12d
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L702
	movl	8(%rsp), %ecx
	movq	176(%rsp), %rdx
	movq	168(%rsp), %rsi
	movq	160(%rsp), %rdi
	call	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i
.L702:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	leaq	60(%rsp), %rax
	movq	192(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm2
	addss	60(%rsp), %xmm2
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm2, %ebp
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r12d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L703
	movq	184(%rsp), %rsi
	movq	176(%rsp), %rdi
	movl	%r12d, %edx
	call	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i
.L703:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	leaq	60(%rsp), %rdi
	movq	192(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm3
	addss	60(%rsp), %xmm3
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm3, %ebp
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r12d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L704
	movl	8(%rsp), %edx
	movq	184(%rsp), %rsi
	movq	168(%rsp), %rdi
	call	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i
.L704:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	leaq	60(%rsp), %rdi
	movq	192(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm4
	addss	60(%rsp), %xmm4
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm4, %ebp
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r12d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L705
	movq	80(%rsp), %rsi
	movq	168(%rsp), %rdi
	call	_Z33__device_stub__Z11shift_rightPiS_PiS_
.L705:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	leaq	60(%rsp), %r12
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm5
	addss	60(%rsp), %xmm5
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm5, %ebp
	call	cudaEventRecord@PLT
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdx
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	movq	%rdi, 208(%rsp)
	movl	$1, 216(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L706
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	%r14d, %ecx
	movq	80(%rsp), %rdi
	call	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i
.L706:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%r12, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%ebp, %xmm6
	addss	60(%rsp), %xmm6
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm6, %ebp
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	32(%rsp), %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, 228(%rsp)
	movq	%rdx, 220(%rsp)
	movl	%eax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L707
	movq	88(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%r15d, %ecx
	movq	96(%rsp), %rdi
	call	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i
.L707:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%r13, %rdi
	call	cudaEventElapsedTime@PLT
	cvtsi2sdl	%ebx, %xmm0
	movd	%ebp, %xmm7
	addss	60(%rsp), %xmm7
	mulsd	.LC5(%rip), %xmm0
	movss	%xmm7, 32(%rsp)
	call	ceil@PLT
	leaq	120(%rsp), %rdi
	cvttsd2sil	%xmm0, %r14d
	movsd	%xmm0, 8(%rsp)
	movl	%r14d, %ebp
	movl	%r14d, %r12d
	sall	$9, %ebp
	sall	$7, %r12d
	movslq	%ebp, %r13
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movq	120(%rsp), %rdi
	movq	%r13, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	40(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	168(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	movl	$4, %ecx
	leaq	176(%rsp), %rdi
	cltd
	idivl	%ecx
	movslq	%eax, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	184(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	144(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	152(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	leaq	136(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	136(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	192(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	%r14d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L708
	movq	120(%rsp), %rdx
	movq	112(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z31__device_stub__Z9histogramPiiS_PiiS_
.L708:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4194305, %ebp
	salq	$10, %rbp
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	192(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	movss	32(%rsp), %xmm1
	addss	60(%rsp), %xmm1
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm1, %r13d
	call	cudaEventRecord@PLT
	cvtsi2sdl	%r12d, %xmm0
	mulsd	.LC5(%rip), %xmm0
	movq	%rbp, 220(%rsp)
	movl	$1, 228(%rsp)
	call	ceil@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	cvttsd2siq	%xmm0, %rax
	movl	$1, %ecx
	movl	%eax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L709
	movq	160(%rsp), %rdx
	movq	120(%rsp), %rdi
	movl	%r12d, %esi
	call	_Z41__device_stub__Z18organize_histogramPiiS_PiiS_
.L709:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	leaq	60(%rsp), %rbp
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%r13d, %xmm2
	addss	60(%rsp), %xmm2
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movss	%xmm2, 16(%rsp)
	call	cudaEventRecord@PLT
	movl	%r12d, %eax
	movl	$4, %esi
	xorl	%r9d, %r9d
	cltd
	movl	$1073741825, %ecx
	xorl	%r8d, %r8d
	movl	$1, 228(%rsp)
	idivl	%esi
	salq	$2, %rcx
	movq	%rcx, 220(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 208(%rsp)
	movl	%eax, %r13d
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L710
	movq	176(%rsp), %rdx
	movq	168(%rsp), %rsi
	movl	%r12d, %ecx
	movq	160(%rsp), %rdi
	call	_Z54__device_stub__Z29Kogge_Stone_block_scan_kernelPiS_S_iPiS_S_i
.L710:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movss	16(%rsp), %xmm3
	addss	60(%rsp), %xmm3
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movss	%xmm3, 16(%rsp)
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r13d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L711
	movq	184(%rsp), %rsi
	movq	176(%rsp), %rdi
	movl	%r13d, %edx
	call	_Z43__device_stub__Z20parallel_scan_kernelPiS_iPiS_i
.L711:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movss	16(%rsp), %xmm4
	addss	60(%rsp), %xmm4
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movss	%xmm4, 16(%rsp)
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r13d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L712
	movq	184(%rsp), %rsi
	movq	168(%rsp), %rdi
	movl	%r12d, %edx
	call	_Z40__device_stub__Z17add_S_to_Y_kernelPiS_iPiS_i
.L712:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movss	16(%rsp), %xmm5
	addss	60(%rsp), %xmm5
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm5, %r12d
	call	cudaEventRecord@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	salq	$2, %rdx
	movl	$1, %ecx
	movl	%r13d, 208(%rsp)
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L713
	movq	128(%rsp), %rsi
	movq	168(%rsp), %rdi
	call	_Z33__device_stub__Z11shift_rightPiS_PiS_
.L713:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%r12d, %xmm6
	addss	60(%rsp), %xmm6
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm6, %r12d
	call	cudaEventRecord@PLT
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdx
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	movq	%rdi, 208(%rsp)
	movl	$1, 216(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L714
	movq	152(%rsp), %rdx
	movq	144(%rsp), %rsi
	movl	%r14d, %ecx
	movq	128(%rsp), %rdi
	call	_Z42__device_stub__Z17reduce_prefix_sumPiS_S_iPiS_S_i
.L714:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%r12d, %xmm7
	addss	60(%rsp), %xmm7
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm7, %r12d
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	8(%rsp), %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, 228(%rsp)
	movq	%rdx, 220(%rsp)
	movl	%eax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 212(%rsp)
	movq	208(%rsp), %rdi
	movl	216(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L715
	movq	136(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	%ebx, %ecx
	movq	144(%rsp), %rdi
	call	_Z32__device_stub__Z8re_orderPiS_S_iPiS_S_i
.L715:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	%rbp, %rdi
	call	cudaEventElapsedTime@PLT
	movd	%r12d, %xmm1
	addss	60(%rsp), %xmm1
	xorl	%esi, %esi
	movq	192(%rsp), %rdi
	movd	%xmm1, %r12d
	call	cudaEventRecord@PLT
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdx
	movq	%rdx, 220(%rsp)
	movl	$1, 228(%rsp)
	movq	%rdi, 208(%rsp)
	movl	$1, 216(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L716
	movq	88(%rsp), %rdx
	movq	104(%rsp), %rdi
	movl	%ebx, %r9d
	movl	%r15d, %r8d
	movq	136(%rsp), %rcx
	movq	152(%rsp), %rsi
	call	_Z32__device_stub__Z5probePiS_S_S_iiPiS_S_S_ii
.L716:
	movq	200(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	200(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	200(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	192(%rsp), %rsi
	call	cudaEventElapsedTime@PLT
	movd	%r12d, %xmm2
	addss	60(%rsp), %xmm2
	movq	192(%rsp), %rdi
	movd	%xmm2, %r12d
	call	cudaEventDestroy@PLT
	movq	200(%rsp), %rdi
	call	cudaEventDestroy@PLT
	call	cudaDeviceSynchronize@PLT
	movd	%r12d, %xmm3
	leaq	.LC8(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm3, %xmm0
	divsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 228(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 220(%rsp)
	movq	%rdi, 208(%rsp)
	movl	$1, 216(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L717
	call	_Z32__device_stub__Z13print_matchesvv
.L717:
	call	cudaDeviceSynchronize@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L718
	call	__stack_chk_fail@PLT
.L718:
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10463:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv"
.LC10:
	.string	"_Z13print_matchesv"
.LC11:
	.string	"_Z5probePiS_S_S_ii"
.LC12:
	.string	"_Z8re_orderPiS_S_i"
.LC13:
	.string	"_Z17reduce_prefix_sumPiS_S_i"
.LC14:
	.string	"_Z11shift_rightPiS_"
.LC15:
	.string	"_Z17add_S_to_Y_kernelPiS_i"
.LC16:
	.string	"_Z20parallel_scan_kernelPiS_i"
.LC17:
	.string	"_Z29Kogge_Stone_block_scan_kernelPiS_S_i"
.LC18:
	.string	"_Z18organize_histogramPiiS_"
.LC19:
	.string	"_Z9histogramPiiS_"
.LC20:
	.string	"matches"
.LC21:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo5beginE"
.LC22:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo3endE"
.LC23:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo6cbeginE"
.LC24:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo4cendE"
.LC25:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo6rbeginE"
.LC26:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo4rendE"
.LC27:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo7crbeginE"
.LC28:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__45__cpo5crendE"
.LC29:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__445_GLOBAL__N__3b0661e0_13_radix_join_cu_matches6ignoreE"
.LC30:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__419piecewise_constructE"
.LC31:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__48in_placeE"
.LC32:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__420unreachable_sentinelE"
.LC33:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std3__47nulloptE"
.LC34:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4swapE"
.LC35:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo9iter_moveE"
.LC36:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo7advanceE"
.LC37:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo5beginE"
.LC38:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo3endE"
.LC39:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo6cbeginE"
.LC40:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4cendE"
.LC41:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo9iter_swapE"
.LC42:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4nextE"
.LC43:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4prevE"
.LC44:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4dataE"
.LC45:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo5cdataE"
.LC46:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo4sizeE"
.LC47:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo5ssizeE"
.LC48:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches4cuda3std6ranges3__45__cpo8distanceE"
.LC49:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS8cuda_cub3parE"
.LC50:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS8cuda_cub10par_nosyncE"
.LC51:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
.LC52:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_1E"
.LC53:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_2E"
.LC54:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_3E"
.LC55:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_4E"
.LC56:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_5E"
.LC57:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_6E"
.LC58:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_7E"
.LC59:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_8E"
.LC60:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders2_9E"
.LC61:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS12placeholders3_10E"
.LC62:
	.string	"_ZN43_INTERNAL_3b0661e0_13_radix_join_cu_matches6thrust20THRUST_200700_890_NS3seqE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10511:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13print_matchesv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5probePiS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8re_orderPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17reduce_prefix_sumPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11shift_rightPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17add_S_to_Y_kernelPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20parallel_scan_kernelPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC17(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z29Kogge_Stone_block_scan_kernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18organize_histogramPiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9histogramPiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL7matches(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6rbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4rendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo7crbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5crendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__445_GLOBAL__N__3b0661e0_13_radix_join_cu_matches6ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__420unreachable_sentinelE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__47nulloptE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4nextE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4prevE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4dataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5cdataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC46(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4sizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5ssizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC48(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo8distanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC49(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC50(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC51(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC52(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC53(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC54(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN6thrust20THRUST_200700_890_NSL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE10511:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7matches
	.comm	_ZL7matches,4,4
	.globl	err
	.bss
	.align 4
	.type	err, @object
	.size	err, 4
err:
	.zero	4
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NSL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NSL3seqE, 1
_ZN6thrust20THRUST_200700_890_NSL3seqE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E:
	.zero	1
	.weak	_ZN4cuda3std3__47nulloptE
	.section	.rodata._ZN4cuda3std3__47nulloptE,"aG",@progbits,_ZN4cuda3std3__47nulloptE,comdat
	.type	_ZN4cuda3std3__47nulloptE, @gnu_unique_object
	.size	_ZN4cuda3std3__47nulloptE, 1
_ZN4cuda3std3__47nulloptE:
	.zero	1
	.hidden	InitializeInjectionNvtx2_fnptr
	.weak	InitializeInjectionNvtx2_fnptr
	.bss
	.align 8
	.type	InitializeInjectionNvtx2_fnptr, @object
	.size	InitializeInjectionNvtx2_fnptr, 8
InitializeInjectionNvtx2_fnptr:
	.zero	8
	.hidden	nvtxGlobals_v3
	.weak	nvtxGlobals_v3
	.section	.data.rel.local,"aw"
	.align 32
	.type	nvtxGlobals_v3, @object
	.size	nvtxGlobals_v3, 1168
nvtxGlobals_v3:
	.long	0
	.zero	4
	.quad	16
	.quad	nvtxEtiGetModuleFunctionTable_v3
	.quad	24
	.long	3
	.long	0
	.quad	nvtxEtiSetInjectionNvtxVersion_v3
	.quad	nvtxMarkEx_impl_init_v3
	.quad	nvtxMarkA_impl_init_v3
	.quad	nvtxMarkW_impl_init_v3
	.quad	nvtxRangeStartEx_impl_init_v3
	.quad	nvtxRangeStartA_impl_init_v3
	.quad	nvtxRangeStartW_impl_init_v3
	.quad	nvtxRangeEnd_impl_init_v3
	.quad	nvtxRangePushEx_impl_init_v3
	.quad	nvtxRangePushA_impl_init_v3
	.quad	nvtxRangePushW_impl_init_v3
	.quad	nvtxRangePop_impl_init_v3
	.quad	nvtxNameCategoryA_impl_init_v3
	.quad	nvtxNameCategoryW_impl_init_v3
	.quad	nvtxNameOsThreadA_impl_init_v3
	.quad	nvtxNameOsThreadW_impl_init_v3
	.quad	nvtxNameCuDeviceA_impl_init_v3
	.quad	nvtxNameCuDeviceW_impl_init_v3
	.quad	nvtxNameCuContextA_impl_init_v3
	.quad	nvtxNameCuContextW_impl_init_v3
	.quad	nvtxNameCuStreamA_impl_init_v3
	.quad	nvtxNameCuStreamW_impl_init_v3
	.quad	nvtxNameCuEventA_impl_init_v3
	.quad	nvtxNameCuEventW_impl_init_v3
	.quad	nvtxNameClDeviceA_impl_init_v3
	.quad	nvtxNameClDeviceW_impl_init_v3
	.quad	nvtxNameClContextA_impl_init_v3
	.quad	nvtxNameClContextW_impl_init_v3
	.quad	nvtxNameClCommandQueueA_impl_init_v3
	.quad	nvtxNameClCommandQueueW_impl_init_v3
	.quad	nvtxNameClMemObjectA_impl_init_v3
	.quad	nvtxNameClMemObjectW_impl_init_v3
	.quad	nvtxNameClSamplerA_impl_init_v3
	.quad	nvtxNameClSamplerW_impl_init_v3
	.quad	nvtxNameClProgramA_impl_init_v3
	.quad	nvtxNameClProgramW_impl_init_v3
	.quad	nvtxNameClEventA_impl_init_v3
	.quad	nvtxNameClEventW_impl_init_v3
	.quad	nvtxNameCudaDeviceA_impl_init_v3
	.quad	nvtxNameCudaDeviceW_impl_init_v3
	.quad	nvtxNameCudaStreamA_impl_init_v3
	.quad	nvtxNameCudaStreamW_impl_init_v3
	.quad	nvtxNameCudaEventA_impl_init_v3
	.quad	nvtxNameCudaEventW_impl_init_v3
	.quad	nvtxDomainMarkEx_impl_init_v3
	.quad	nvtxDomainRangeStartEx_impl_init_v3
	.quad	nvtxDomainRangeEnd_impl_init_v3
	.quad	nvtxDomainRangePushEx_impl_init_v3
	.quad	nvtxDomainRangePop_impl_init_v3
	.quad	nvtxDomainResourceCreate_impl_init_v3
	.quad	nvtxDomainResourceDestroy_impl_init_v3
	.quad	nvtxDomainNameCategoryA_impl_init_v3
	.quad	nvtxDomainNameCategoryW_impl_init_v3
	.quad	nvtxDomainRegisterStringA_impl_init_v3
	.quad	nvtxDomainRegisterStringW_impl_init_v3
	.quad	nvtxDomainCreateA_impl_init_v3
	.quad	nvtxDomainCreateW_impl_init_v3
	.quad	nvtxDomainDestroy_impl_init_v3
	.quad	nvtxInitialize_impl_init_v3
	.quad	nvtxDomainSyncUserCreate_impl_init_v3
	.quad	nvtxDomainSyncUserDestroy_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.quad	nvtxDomainSyncUserReleasing_impl_init_v3
	.quad	0
	.quad	nvtxGlobals_v3+48
	.quad	nvtxGlobals_v3+56
	.quad	nvtxGlobals_v3+64
	.quad	nvtxGlobals_v3+72
	.quad	nvtxGlobals_v3+80
	.quad	nvtxGlobals_v3+88
	.quad	nvtxGlobals_v3+96
	.quad	nvtxGlobals_v3+104
	.quad	nvtxGlobals_v3+112
	.quad	nvtxGlobals_v3+120
	.quad	nvtxGlobals_v3+128
	.quad	nvtxGlobals_v3+136
	.quad	nvtxGlobals_v3+144
	.quad	nvtxGlobals_v3+152
	.quad	nvtxGlobals_v3+160
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+168
	.quad	nvtxGlobals_v3+176
	.quad	nvtxGlobals_v3+184
	.quad	nvtxGlobals_v3+192
	.quad	nvtxGlobals_v3+200
	.quad	nvtxGlobals_v3+208
	.quad	nvtxGlobals_v3+216
	.quad	nvtxGlobals_v3+224
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+232
	.quad	nvtxGlobals_v3+240
	.quad	nvtxGlobals_v3+248
	.quad	nvtxGlobals_v3+256
	.quad	nvtxGlobals_v3+264
	.quad	nvtxGlobals_v3+272
	.quad	nvtxGlobals_v3+280
	.quad	nvtxGlobals_v3+288
	.quad	nvtxGlobals_v3+296
	.quad	nvtxGlobals_v3+304
	.quad	nvtxGlobals_v3+312
	.quad	nvtxGlobals_v3+320
	.quad	nvtxGlobals_v3+328
	.quad	nvtxGlobals_v3+336
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+344
	.quad	nvtxGlobals_v3+352
	.quad	nvtxGlobals_v3+360
	.quad	nvtxGlobals_v3+368
	.quad	nvtxGlobals_v3+376
	.quad	nvtxGlobals_v3+384
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+392
	.quad	nvtxGlobals_v3+400
	.quad	nvtxGlobals_v3+408
	.quad	nvtxGlobals_v3+416
	.quad	nvtxGlobals_v3+424
	.quad	nvtxGlobals_v3+432
	.quad	nvtxGlobals_v3+440
	.quad	nvtxGlobals_v3+448
	.quad	nvtxGlobals_v3+456
	.quad	nvtxGlobals_v3+464
	.quad	nvtxGlobals_v3+472
	.quad	nvtxGlobals_v3+480
	.quad	nvtxGlobals_v3+488
	.quad	nvtxGlobals_v3+496
	.quad	nvtxGlobals_v3+504
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+512
	.quad	nvtxGlobals_v3+520
	.quad	nvtxGlobals_v3+528
	.quad	nvtxGlobals_v3+536
	.quad	nvtxGlobals_v3+544
	.quad	nvtxGlobals_v3+552
	.quad	0
	.weak	_ZN4cuda3std3__420unreachable_sentinelE
	.section	.rodata._ZN4cuda3std3__420unreachable_sentinelE,"aG",@progbits,_ZN4cuda3std3__420unreachable_sentinelE,comdat
	.type	_ZN4cuda3std3__420unreachable_sentinelE, @gnu_unique_object
	.size	_ZN4cuda3std3__420unreachable_sentinelE, 1
_ZN4cuda3std3__420unreachable_sentinelE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo5crendE
	.section	.rodata._ZN4cuda3std3__45__cpo5crendE,"aG",@progbits,_ZN4cuda3std3__45__cpo5crendE,comdat
	.type	_ZN4cuda3std3__45__cpo5crendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5crendE, 1
_ZN4cuda3std3__45__cpo5crendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo7crbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo7crbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo7crbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo7crbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo7crbeginE, 1
_ZN4cuda3std3__45__cpo7crbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4rendE
	.section	.rodata._ZN4cuda3std3__45__cpo4rendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4rendE,comdat
	.type	_ZN4cuda3std3__45__cpo4rendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4rendE, 1
_ZN4cuda3std3__45__cpo4rendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6rbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6rbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6rbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6rbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6rbeginE, 1
_ZN4cuda3std3__45__cpo6rbeginE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo8distanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo8distanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo8distanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo8distanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo8distanceE, 1
_ZN4cuda3std6ranges3__45__cpo8distanceE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo5ssizeE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5ssizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5ssizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5ssizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo5ssizeE, 1
_ZN4cuda3std6ranges3__45__cpo5ssizeE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4sizeE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4sizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4sizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4sizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4sizeE, 1
_ZN4cuda3std6ranges3__45__cpo4sizeE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo5cdataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5cdataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5cdataE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5cdataE, @gnu_unique_object
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_ZN4cuda3std6ranges3__45__cpo5cdataE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4dataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4dataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4dataE,comdat
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	.size	_ZN4cuda3std6ranges3__45__cpo4dataE, 1
_ZN4cuda3std6ranges3__45__cpo4dataE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4prevE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4prevE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4prevE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4prevE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4prevE, 1
_ZN4cuda3std6ranges3__45__cpo4prevE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4nextE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4nextE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4nextE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4nextE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4nextE, 1
_ZN4cuda3std6ranges3__45__cpo4nextE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_swapE,comdat
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_ZN4cuda3std6ranges3__45__cpo9iter_swapE:
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_ZN4cuda3std6ranges3__45__cpo4cendE:
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	.section	.rodata._ZN4cuda3std6ranges3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo6cbeginE,comdat
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_ZN4cuda3std6ranges3__45__cpo6cbeginE:
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	.section	.rodata._ZN4cuda3std6ranges3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo3endE,comdat
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_ZN4cuda3std6ranges3__45__cpo3endE:
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	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5beginE,comdat
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_ZN4cuda3std6ranges3__45__cpo5beginE:
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	.section	.rodata
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_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo7advanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
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_ZN4cuda3std6ranges3__45__cpo7advanceE:
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	.weak	_ZN4cuda3std3__445_GLOBAL__N__3b0661e0_13_radix_join_cu_matches6ignoreE
	.section	.rodata._ZN4cuda3std3__445_GLOBAL__N__3b0661e0_13_radix_join_cu_matches6ignoreE,"aG",@progbits,_ZN4cuda3std3__445_GLOBAL__N__3b0661e0_13_radix_join_cu_matches6ignoreE,comdat
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/*
    Programming on Massively Parallel Systems
    Fall 2018
    Project # 3
    Student: Patricia Wilthew

    Compile: nvcc proj3.cu -o proj3
    Usage: ./proj3 {#of_elements_in_array1} {#of_elements_in_array2}
*/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <assert.h>
#include <thrust/scan.h>
#define RAND_RANGE(N) ((double)rand()/((double)RAND_MAX + 1)*(N))
#define PARTITION_LENGTH 128
#define SECTION_LENGTH 4

hipError_t err;
__device__ int matches = 0;

/*
    Function: catch_error

    Description: Prints any CUDA error to stdout.
*/
void catch_error(hipError_t error)
{
    if (error)
    {
        printf("Error: %s\n", hipGetErrorString(err));
    }
}

/*
    Function: data_generator

    Description: Uses Knuth Shuffle to generate integers in data.
*/
void data_generator(int* data, int count, int first, int step)
{
    assert(data != NULL);

    for (int i = 0; i < count; ++i)
    {
        data[i] = first + i * step;
    }
    
    srand(time(NULL));
    
    for (int i = count-1; i>0; i--) //knuth shuffle
    {
        int j = RAND_RANGE(i);
        int k_tmp = data[i];
        data[i] = data[j];
        data[j] = k_tmp;
    }
}

/*
    Function: bfe

    Description: This function embeds PTX code of CUDA to extract bit
        field from x.

    Input:
        start (uint): Starting bit position relative to the LSB.
        nbits (uint): The bit field length.

    Output: The extracted bit field as an unsigned integer.
*/
__device__ uint bfe(uint x, uint start, uint nbits)
{
    uint bits;
    asm("bfe.u32 %0, %1, %2, %3;" : "=r"(bits) : "r"(x), "r"(start), "r"(nbits));
    return bits;
}

/*
    Function: histogram

    Description: In order to efficiently partition the input in parallel,
        first we need to compute a histogram of the radix values by
        scanning the array of keys so that we know the number of keys
        that should go to each partition.
*/
__global__ void histogram(int *array, int array_length, int *hist)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int radix;

    if (idx < array_length)
    {
        radix = (int) bfe(array[idx], 0, 31-__builtin_clz(PARTITION_LENGTH));
        atomicAdd(&hist[blockIdx.x * PARTITION_LENGTH + radix], 1);
    }
}

/*
    Function: organize_histogram

    Description: Given a histogram `hist` of the form:
        [w1, x1, y1, z1,   w2, x2, y2, z2,   w3, x3, y3, z3], create an
        `organized` histogram of the form:
        [w1, w2, w3,   x1, x2, x3,   y1, y2, y3,   z1, z2, z3].
*/
__global__ void organize_histogram(int *hist, int hist_length, int *organized)
{
    int number_of_sections = hist_length / PARTITION_LENGTH;
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int value, section_offset;

    if (idx < hist_length)
    {
        section_offset = idx/number_of_sections;
        value = hist[
                    PARTITION_LENGTH * (idx % number_of_sections)
                    + section_offset
                ];
        organized[idx] = value;
    }
}

/*
    Function: Kogge_Stone_scan_kernel

    Description: This is the first of the three kernels needed to implement the
        hierarchical scan with three kernels. It uses Kogge Stone scan
        algorithm to compute the prefix sum of each block of length
        SECTION_LENGTH.
*/
__global__ void Kogge_Stone_block_scan_kernel(int *X, int *Y, int *S, int length)
{
    __shared__ int XY[SECTION_LENGTH];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < length)
    {
        XY[threadIdx.x] = X[idx];
    }

    for (unsigned int stride = 1; stride < blockDim.x; stride *= 2)
    {
        __syncthreads();
        if (threadIdx.x >= stride) XY[threadIdx.x] += XY[threadIdx.x-stride];
    }

    Y[idx] = XY[threadIdx.x];

    __syncthreads();
    
    // If this is the last thread of the block:
    if (threadIdx.x == blockDim.x - 1)
    {
       S[blockIdx.x] = XY[SECTION_LENGTH - 1];
    }
}

/*
    Function: parallel_scan_kernel

    Description: The second kernel of the hierarchical scan is simply one of the
        three parallel scan kernels, which takes S as input and writes S as
        output.

*/
__global__ void parallel_scan_kernel(int *X, int *Y, int length)
{
    __shared__ int XY[SECTION_LENGTH];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < length)
    {
        XY[threadIdx.x] = X[idx];
    }

    for (unsigned int stride = 1; stride < blockDim.x; stride *= 2)
    {
        __syncthreads();
        if (threadIdx.x >= stride) XY[threadIdx.x] += XY[threadIdx.x-stride];
    }

    Y[idx] = XY[threadIdx.x];
}

/*
    Function: add_S_to_Y_kernel

    Description: The third kernel of the hierarchical scan takes the S and Y
        arrays as inputs and writes its output back into Y. Assuming that we
        launch the kernel with SECTION_LENGTH threads in each block, each thread
        adds one of the S elements (selected by blockIdx.x-1) to one Y element.
*/
__global__ void add_S_to_Y_kernel(int *Y, int *S, int length)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int j, sum;

    if (blockIdx.x > 0 && idx < length)
    {
        Y[idx] += S[blockIdx.x - 1];
    
        // Also add the prefix sum of previous sections.
        if (blockIdx.x >= SECTION_LENGTH)
        {
            sum = 0;
            for (j = SECTION_LENGTH - 1; j < blockIdx.x - 1; j += 4)
            {
                sum += S[j];
            }
            Y[idx] += sum;
        }
    }
}

/* 
    Function: shift_right

    Description: Performs 1-shift right on original array and stores it in a new
        array. This is performed to convert an inclusive prefix sum into
        exclusive.
*/
__global__ void shift_right(int *original, int *shifted)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    if (idx == 0)
    {
        shifted[idx] = 0;
    }
    else
    {
        shifted[idx] = original[idx - 1];
    }
}

/*
    Function: reduce_prefix_sum

    Description: Given a `prefix_sum` array of the form:
        [0, 6, 15, 24, 30, 37, 44, 51, 60, 71, 79, 87, 90, 98, 106, 114],
        Create a `reduced` array of PARTITION_LENGTH length, 4, of the form:
        [0, 30, 60, 90] that contains the index in which each partition starts.
*/
__global__ void reduce_prefix_sum(int *prefix_sum, int *reduced, int *reduced_copy, int p_length)
{
    int number;
    number = prefix_sum[blockIdx.x * p_length];
    reduced[blockIdx.x] = number;
    reduced_copy[blockIdx.x] = number;
}

/*
    Function: re_order

    Description: Re-order original `array` by radix into a partitioned new
        array, `ordered`.
*/
__global__ void re_order(int *prefix_sum, int *array, int *ordered, int length)
{
    int offset;
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int radix = (int) bfe(array[idx], 0, 31-__builtin_clz(PARTITION_LENGTH));

    if (idx < length)
    {
        // `offset` will have the value of prefix_sum[radix]
        // before it is incremented by one.
        offset = atomicAdd(&prefix_sum[radix], 1);
        ordered[offset] = array[idx];
    }
}

/*
    Function: probe

    Description: With the reordered keys from both input arrays, we can
        now perform the probe stage by only comparing the keys from the
        corresponding partitions of both input arrays. This can be done
        by nested-loop comparisons.
*/
__global__ void probe(int *r_delim, int *s_delim, int *r, int *s, int r_length, int s_length)
{
    int r_start, r_end, s_start, s_end;
    int i, j, count = 0;

    // Get delimiters of current partition.
    r_start = r_delim[blockIdx.x];
    s_start = s_delim[blockIdx.x];

    if (blockIdx.x == PARTITION_LENGTH - 1)
    {
        r_end = r_length - 1;
        s_end = s_length - 1;
    }
    else
    {
        r_end = r_delim[blockIdx.x + 1] - 1;
        s_end = s_delim[blockIdx.x + 1] - 1;
    }
    
    for (i=r_start; i <= r_end; i++)
    {
        for (j=s_start; j <= s_end; j++)
        {
            if (r[i] == s[j])
            {   
                count += 1;
            }
        }
    }
    atomicAdd(&matches, count);

}

__global__ void print_matches()
{
    printf("---> %d matches\n", matches);
}


int main(int argc, char const *argv[])
{
    if (argc <= 2)
    {
        printf("Usage: ./proj3.out {#of_elements_in_array1} {#of_elements_in_array2}\n");
        exit(1);
    }

    int r_length = atoi(argv[1]);
    int s_length = atoi(argv[2]);
    int r_size = sizeof(int)*r_length;
    int s_size = sizeof(int)*s_length;
    int r_hist_len, r_hist_size;
    int s_hist_len, s_hist_size;
    int blocks;
    double threads = 1024.0;
    float time, total_time = 0.0;

    int *r_host, *r_hist, *r_prefix_sum, *r_ordered, *r_reduced_prefix, 
        *r_reduced_prefix_copy;
    int *s_host, *s_hist, *s_prefix_sum, *s_ordered, *s_reduced_prefix,
        *s_reduced_prefix_copy;
    
    int *X, *Y, *S, *S2;
    
    // Allocate arrays in host and device.
    hipHostMalloc((void**)&r_host, r_size, hipHostMallocDefault);
    hipHostMalloc((void**)&s_host, s_size, hipHostMallocDefault);

    // Populate arrays.
    data_generator(r_host, r_length, 0, 1);
    data_generator(s_host, s_length, 0, 1);

    // Recording variables.
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);


    /************************************
    *                                   *
    *   Order r into partitioned array  *
    *                                   *
    ************************************/
    blocks = ceil(r_length/threads);
    r_hist_len = PARTITION_LENGTH * blocks;
    r_hist_size = sizeof(int)*r_hist_len;
    hipMalloc((void**)&r_hist, r_hist_size); hipMemset(r_hist, 0, r_hist_size);
    hipMalloc((void**)&X, r_hist_size);
    hipMalloc((void**)&Y, r_hist_size);
    hipMalloc((void**)&S, r_hist_size/SECTION_LENGTH);
    hipMalloc((void**)&S2, r_hist_size/SECTION_LENGTH);
    hipMalloc((void**)&r_prefix_sum, r_hist_size);
    hipMalloc((void**)&r_reduced_prefix, PARTITION_LENGTH*sizeof(int));
    hipMalloc((void**)&r_reduced_prefix_copy, PARTITION_LENGTH*sizeof(int));
    hipMalloc((void**)&r_ordered, r_size); hipMemset(r_ordered, 0, r_size);

    // Histogram for r: r_hist.
    hipEventRecord(start, 0);
    histogram<<<blocks, threads>>>(r_host, r_length, r_hist);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Organized histogram for r: X
    hipEventRecord(start, 0);
    organize_histogram<<<ceil(r_hist_len/threads), threads>>>(
        r_hist, r_hist_len, X);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part I): Y and S.
    hipEventRecord(start, 0);
    Kogge_Stone_block_scan_kernel<<<
        ceil(r_hist_len/(SECTION_LENGTH)),
        SECTION_LENGTH>>>(X, Y, S, r_hist_len);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part II): S2.
    hipEventRecord(start, 0);
    parallel_scan_kernel<<<ceil(r_hist_len/SECTION_LENGTH), SECTION_LENGTH>>>(
        S, S2, r_hist_len/SECTION_LENGTH);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for r (Part III): Y.
    hipEventRecord(start, 0);
    add_S_to_Y_kernel<<<
        ceil(r_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, S2, r_hist_len);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Convert to exclusive prefix sum.
    hipEventRecord(start, 0);
    shift_right<<<
        ceil(r_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, r_prefix_sum);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Obtain reduced prefix sum (of partition size)
    hipEventRecord(start, 0);
    reduce_prefix_sum<<<PARTITION_LENGTH, 1>>>(
        r_prefix_sum, r_reduced_prefix, r_reduced_prefix_copy, blocks);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Reorder R array.
    hipEventRecord(start, 0);
    re_order<<<ceil(r_length/threads), threads>>>(
        r_reduced_prefix, r_host, r_ordered, r_length);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;


    /************************************
    *                                   *
    *   Order s into partitioned array  *
    *                                   *
    ************************************/
    blocks = ceil(s_length/threads);
    s_hist_len = PARTITION_LENGTH * blocks;
    s_hist_size = sizeof(int)*s_hist_len;
    hipMalloc((void**)&s_hist, s_hist_size); hipMemset(s_hist, 0, s_hist_size);
    hipMalloc((void**)&X, s_hist_size);
    hipMalloc((void**)&Y, s_hist_size);
    hipMalloc((void**)&S, s_hist_size/SECTION_LENGTH);
    hipMalloc((void**)&S2, s_hist_size/SECTION_LENGTH);
    hipMalloc((void**)&s_prefix_sum, s_hist_size);
    hipMalloc((void**)&s_reduced_prefix, PARTITION_LENGTH*sizeof(int));
    hipMalloc((void**)&s_reduced_prefix_copy, PARTITION_LENGTH*sizeof(int));
    hipMalloc((void**)&s_ordered, s_size); hipMemset(s_ordered, 0, s_size);

    // Histogram for s: s_hist.
    hipEventRecord(start, 0);
    histogram<<<blocks, threads>>>(s_host, s_length, s_hist);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Organized histogram for s: X
    hipEventRecord(start, 0);
    organize_histogram<<<ceil(s_hist_len/threads), threads>>>(
        s_hist, s_hist_len, X);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part I): Y and S.
    hipEventRecord(start, 0);
    Kogge_Stone_block_scan_kernel<<<
        ceil(s_hist_len/(SECTION_LENGTH)),
        SECTION_LENGTH>>>(X, Y, S, s_hist_len);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part II): S2.
    hipEventRecord(start, 0);
    parallel_scan_kernel<<<ceil(s_hist_len/SECTION_LENGTH), SECTION_LENGTH>>>(
        S, S2, s_hist_len/SECTION_LENGTH);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Hierarchical scan for s (Part III): Y.
    hipEventRecord(start, 0);
    add_S_to_Y_kernel<<<
        ceil(s_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, S2, s_hist_len);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Convert to exclusive prefix sum.
    hipEventRecord(start, 0);
    shift_right<<<
        ceil(s_hist_len/SECTION_LENGTH),
        SECTION_LENGTH>>>(Y, s_prefix_sum);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Obtain reduced prefix sum (of partition size)
    hipEventRecord(start, 0);
    reduce_prefix_sum<<<PARTITION_LENGTH, 1>>>(
        s_prefix_sum, s_reduced_prefix, s_reduced_prefix_copy, blocks);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    // Reorder s array.
    hipEventRecord(start, 0);
    re_order<<<
        ceil(s_length/threads),
        threads>>>(s_reduced_prefix, s_host, s_ordered, s_length);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;


    /************************************
    *                                   *
    *               Probing             *
    *                                   *
    ************************************/
    hipEventRecord(start, 0);
    probe<<<PARTITION_LENGTH, 1>>>(
        r_reduced_prefix_copy, s_reduced_prefix_copy, r_ordered, s_ordered,
        r_length, s_length);
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&time, start, stop);
    total_time += time;

    hipEventDestroy(start);
    hipEventDestroy(stop);
    
    hipDeviceSynchronize();
    printf(
        "******** Total Running Time of All Kernels = %.5f sec ********\n",
        total_time/1000.0);

    print_matches<<<1, 1>>>();
    hipDeviceSynchronize();

    hipFree(X);
    hipFree(Y);
    hipFree(S);
    hipFree(S2);
    hipFree(r_hist);
    hipFree(r_prefix_sum);
    hipFree(r_reduced_prefix);
    hipFree(r_ordered);
    hipFree(s_hist);
    hipFree(s_prefix_sum);
    hipFree(s_reduced_prefix);
    hipFree(s_ordered);

    return 0;
}



	.text
	.file	"radix_join.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z11catch_error10hipError_t     # -- Begin function _Z11catch_error10hipError_t
	.type	_Z11catch_error10hipError_t,@function
_Z11catch_error10hipError_t:            # @_Z11catch_error10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	je	.LBB0_1
# %bb.2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	err(%rip), %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB0_1:
	retq
.Lfunc_end0:
	.size	_Z11catch_error10hipError_t, .Lfunc_end0-_Z11catch_error10hipError_t
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z14data_generatorPiiii
.LCPI1_0:
	.quad	0x3e00000000000000              # double 4.6566128730773926E-10
	.text
	.globl	_Z14data_generatorPiiii
	.type	_Z14data_generatorPiiii,@function
_Z14data_generatorPiiii:                # @_Z14data_generatorPiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	%esi, %r14d
	testl	%esi, %esi
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%eax, %eax
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	addl	%ecx, %edx
	cmpq	%rax, %r14
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	cmpl	$2, %ebp
	jl	.LBB1_5
.LBB1_4:                                # %.lr.ph25
                                        # =>This Inner Loop Header: Depth=1
	leaq	-1(%r14), %r15
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sd	%r15d, %xmm1
	mulsd	.LCPI1_0(%rip), %xmm0
	mulsd	%xmm0, %xmm1
	cvttsd2si	%xmm1, %eax
	movl	-4(%rbx,%r14,4), %ecx
	cltq
	movl	(%rbx,%rax,4), %edx
	movl	%edx, -4(%rbx,%r14,4)
	movl	%ecx, (%rbx,%rax,4)
	cmpq	$2, %r14
	movq	%r15, %r14
	ja	.LBB1_4
.LBB1_5:                                # %._crit_edge26
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z14data_generatorPiiii, .Lfunc_end1-_Z14data_generatorPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__histogramPiiS_ # -- Begin function _Z24__device_stub__histogramPiiS_
	.type	_Z24__device_stub__histogramPiiS_,@function
_Z24__device_stub__histogramPiiS_:      # @_Z24__device_stub__histogramPiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9histogramPiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__histogramPiiS_, .Lfunc_end2-_Z24__device_stub__histogramPiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__organize_histogramPiiS_ # -- Begin function _Z33__device_stub__organize_histogramPiiS_
	.type	_Z33__device_stub__organize_histogramPiiS_,@function
_Z33__device_stub__organize_histogramPiiS_: # @_Z33__device_stub__organize_histogramPiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18organize_histogramPiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z33__device_stub__organize_histogramPiiS_, .Lfunc_end3-_Z33__device_stub__organize_histogramPiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i # -- Begin function _Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
	.type	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i,@function
_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i: # @_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29Kogge_Stone_block_scan_kernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i, .Lfunc_end4-_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__parallel_scan_kernelPiS_i # -- Begin function _Z35__device_stub__parallel_scan_kernelPiS_i
	.type	_Z35__device_stub__parallel_scan_kernelPiS_i,@function
_Z35__device_stub__parallel_scan_kernelPiS_i: # @_Z35__device_stub__parallel_scan_kernelPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20parallel_scan_kernelPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z35__device_stub__parallel_scan_kernelPiS_i, .Lfunc_end5-_Z35__device_stub__parallel_scan_kernelPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__add_S_to_Y_kernelPiS_i # -- Begin function _Z32__device_stub__add_S_to_Y_kernelPiS_i
	.type	_Z32__device_stub__add_S_to_Y_kernelPiS_i,@function
_Z32__device_stub__add_S_to_Y_kernelPiS_i: # @_Z32__device_stub__add_S_to_Y_kernelPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17add_S_to_Y_kernelPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z32__device_stub__add_S_to_Y_kernelPiS_i, .Lfunc_end6-_Z32__device_stub__add_S_to_Y_kernelPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__shift_rightPiS_ # -- Begin function _Z26__device_stub__shift_rightPiS_
	.type	_Z26__device_stub__shift_rightPiS_,@function
_Z26__device_stub__shift_rightPiS_:     # @_Z26__device_stub__shift_rightPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11shift_rightPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z26__device_stub__shift_rightPiS_, .Lfunc_end7-_Z26__device_stub__shift_rightPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__reduce_prefix_sumPiS_S_i # -- Begin function _Z32__device_stub__reduce_prefix_sumPiS_S_i
	.type	_Z32__device_stub__reduce_prefix_sumPiS_S_i,@function
_Z32__device_stub__reduce_prefix_sumPiS_S_i: # @_Z32__device_stub__reduce_prefix_sumPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17reduce_prefix_sumPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z32__device_stub__reduce_prefix_sumPiS_S_i, .Lfunc_end8-_Z32__device_stub__reduce_prefix_sumPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__re_orderPiS_S_i # -- Begin function _Z23__device_stub__re_orderPiS_S_i
	.type	_Z23__device_stub__re_orderPiS_S_i,@function
_Z23__device_stub__re_orderPiS_S_i:     # @_Z23__device_stub__re_orderPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8re_orderPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z23__device_stub__re_orderPiS_S_i, .Lfunc_end9-_Z23__device_stub__re_orderPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__probePiS_S_S_ii # -- Begin function _Z20__device_stub__probePiS_S_S_ii
	.type	_Z20__device_stub__probePiS_S_S_ii,@function
_Z20__device_stub__probePiS_S_S_ii:     # @_Z20__device_stub__probePiS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5probePiS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z20__device_stub__probePiS_S_S_ii, .Lfunc_end10-_Z20__device_stub__probePiS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__print_matchesv # -- Begin function _Z28__device_stub__print_matchesv
	.type	_Z28__device_stub__print_matchesv,@function
_Z28__device_stub__print_matchesv:      # @_Z28__device_stub__print_matchesv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z13print_matchesv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z28__device_stub__print_matchesv, .Lfunc_end11-_Z28__device_stub__print_matchesv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI12_0:
	.quad	0x3f50000000000000              # double 9.765625E-4
.LCPI12_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jle	.LBB12_38
# %bb.1:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r13d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %r12d
	leal	(,%r13,4), %eax
	leal	(,%r12,4), %ebp
	movslq	%eax, %r15
	leaq	200(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	%ebp, %rsi
	leaq	184(%rsp), %r14
	movq	%r14, %rdi
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%rbx), %rdi
	movl	%r13d, %esi
	xorl	%edx, %edx
	movl	$1, %ecx
	callq	_Z14data_generatorPiiii
	movq	(%r14), %rdi
	movq	%r12, 80(%rsp)                  # 8-byte Spill
	movl	%r12d, %esi
	xorl	%edx, %edx
	movl	$1, %ecx
	callq	_Z14data_generatorPiiii
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	%r13, 96(%rsp)                  # 8-byte Spill
	cvtsi2sd	%r13d, %xmm0
	mulsd	.LCPI12_0(%rip), %xmm0
	callq	ceil@PLT
	movsd	%xmm0, 88(%rsp)                 # 8-byte Spill
	cvttsd2si	%xmm0, %r14d
	movl	%r14d, %ebx
	shll	$7, %ebx
	movl	%r14d, %eax
	shll	$9, %eax
	movslq	%eax, %r13
	leaq	160(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	movq	%r13, %rdx
	callq	hipMemset
	leaq	64(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	%r13d, %eax
	sarl	$2, %eax
	movslq	%eax, %rbp
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	152(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	136(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	192(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	144(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	xorl	%esi, %esi
	movq	%r15, %rdx
	callq	hipMemset
	movq	(%r12), %rdi
	movabsq	$4294967296, %r12               # imm = 0x100000000
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r14, %rdi
	btsq	$32, %rdi
	leaq	1024(%r12), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_3
# %bb.2:
	movq	200(%rsp), %rdi
	movq	160(%rsp), %rdx
	movq	96(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_Z24__device_stub__histogramPiiS_
.LBB12_3:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	xorpd	%xmm0, %xmm0
	addss	(%r15), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	mulsd	.LCPI12_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %edi
	orq	%r12, %rdi
	leaq	1024(%r12), %rdx
	movl	$1, %esi
	movq	%rdx, 168(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%r12, %r13
	jne	.LBB12_5
# %bb.4:
	movq	160(%rsp), %rdi
	movq	64(%rsp), %rdx
	movl	%ebx, %esi
	callq	_Z33__device_stub__organize_histogramPiiS_
.LBB12_5:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%r15), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%r14d, %ebp
	shll	$5, %ebp
	movq	%rbp, %r12
	orq	%r13, %r12
	addq	$4, %r13
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_7
# %bb.6:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
.LBB12_7:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%r15), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_9
# %bb.8:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	%ebp, %edx
	callq	_Z35__device_stub__parallel_scan_kernelPiS_i
.LBB12_9:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%r15), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_11
# %bb.10:
	movq	40(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	%ebx, %edx
	callq	_Z32__device_stub__add_S_to_Y_kernelPiS_i
.LBB12_11:
	movq	%r14, %rbp
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	168(%rsp), %r15                 # 8-byte Reload
	jne	.LBB12_13
# %bb.12:
	movq	40(%rsp), %rdi
	movq	152(%rsp), %rsi
	callq	_Z26__device_stub__shift_rightPiS_
.LBB12_13:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967296, %r14               # imm = 0x100000000
	leaq	1(%r14), %rdx
	leaq	128(%r14), %rdi
	movq	%rdi, 216(%rsp)                 # 8-byte Spill
	movl	$1, %esi
	movq	%rdx, 224(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_15
# %bb.14:
	movq	152(%rsp), %rdi
	movq	136(%rsp), %rsi
	movq	192(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z32__device_stub__reduce_prefix_sumPiS_S_i
.LBB12_15:
	movq	%r13, 208(%rsp)                 # 8-byte Spill
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cvttsd2si	88(%rsp), %rax          # 8-byte Folded Reload
	movl	%eax, %edi
	orq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%r15, %r12
	jne	.LBB12_17
# %bb.16:
	movq	136(%rsp), %rdi
	movq	200(%rsp), %rsi
	movq	144(%rsp), %rdx
	movq	96(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z23__device_stub__re_orderPiS_S_i
.LBB12_17:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2sdl	80(%rsp), %xmm0         # 4-byte Folded Reload
	mulsd	.LCPI12_0(%rip), %xmm0
	callq	ceil@PLT
	movsd	%xmm0, 88(%rsp)                 # 8-byte Spill
	cvttsd2si	%xmm0, %r13d
	movl	%r13d, %ebp
	shll	$7, %ebp
	movl	%r13d, %eax
	shll	$9, %eax
	movslq	%eax, %rbx
	leaq	128(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	hipMemset
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	%ebx, %eax
	sarl	$2, %eax
	movslq	%eax, %r15
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	120(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	104(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	176(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	callq	hipMalloc
	leaq	112(%rsp), %rbx
	movq	%rbx, %rdi
	movq	72(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	movq	%r15, %rdx
	callq	hipMemset
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r13, 72(%rsp)                  # 8-byte Spill
	orq	%r14, %r13
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_19
# %bb.18:
	movq	184(%rsp), %rdi
	movq	128(%rsp), %rdx
	movq	80(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_Z24__device_stub__histogramPiiS_
.LBB12_19:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebp, %xmm0
	mulsd	.LCPI12_0(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %edi
	orq	%r14, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	208(%rsp), %r13                 # 8-byte Reload
	jne	.LBB12_21
# %bb.20:
	movq	128(%rsp), %rdi
	movq	64(%rsp), %rdx
	movl	%ebp, %esi
	callq	_Z33__device_stub__organize_histogramPiiS_
.LBB12_21:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	72(%rsp), %rbx                  # 8-byte Reload
                                        # kill: def $ebx killed $ebx killed $rbx def $rbx
	shll	$5, %ebx
	movq	%rbx, %r15
	orq	%r14, %r15
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_23
# %bb.22:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
.LBB12_23:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%r12), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_25
# %bb.24:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	%ebx, %edx
	callq	_Z35__device_stub__parallel_scan_kernelPiS_i
.LBB12_25:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	224(%rsp), %r12                 # 8-byte Reload
	jne	.LBB12_27
# %bb.26:
	movq	40(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	%ebp, %edx
	callq	_Z32__device_stub__add_S_to_Y_kernelPiS_i
.LBB12_27:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movabsq	$4294967296, %r15               # imm = 0x100000000
	jne	.LBB12_29
# %bb.28:
	movq	40(%rsp), %rdi
	movq	120(%rsp), %rsi
	callq	_Z26__device_stub__shift_rightPiS_
.LBB12_29:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	216(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_31
# %bb.30:
	movq	120(%rsp), %rdi
	movq	104(%rsp), %rsi
	movq	176(%rsp), %rdx
	movq	72(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z32__device_stub__reduce_prefix_sumPiS_S_i
.LBB12_31:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cvttsd2si	88(%rsp), %rax          # 8-byte Folded Reload
	movl	%eax, %edi
	orq	%r15, %rdi
	movl	$1, %esi
	movq	168(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_33
# %bb.32:
	movq	104(%rsp), %rdi
	movq	184(%rsp), %rsi
	movq	112(%rsp), %rdx
	movq	80(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z23__device_stub__re_orderPiS_S_i
.LBB12_33:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_35
# %bb.34:
	movq	192(%rsp), %rdi
	movq	176(%rsp), %rsi
	movq	144(%rsp), %rdx
	movq	112(%rsp), %rcx
	movq	96(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movq	80(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	callq	_Z20__device_stub__probePiS_S_S_ii
.LBB12_35:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx), %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	callq	hipDeviceSynchronize
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	divsd	.LCPI12_1(%rip), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_37
# %bb.36:
	callq	_Z28__device_stub__print_matchesv
.LBB12_37:
	callq	hipDeviceSynchronize
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	160(%rsp), %rdi
	callq	hipFree
	movq	152(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	144(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$232, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB12_38:
	.cfi_def_cfa_offset 288
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end12:
	.size	main, .Lfunc_end12-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9histogramPiiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18organize_histogramPiiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29Kogge_Stone_block_scan_kernelPiS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20parallel_scan_kernelPiS_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17add_S_to_Y_kernelPiS_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11shift_rightPiS_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17reduce_prefix_sumPiS_S_i, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8re_orderPiS_S_i, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5probePiS_S_S_ii, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13print_matchesv, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$matches, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	err,@object                     # @err
	.bss
	.globl	err
	.p2align	2, 0x0
err:
	.long	0                               # 0x0
	.size	err, 4

	.type	matches,@object                 # @matches
	.local	matches
	.comm	matches,4,4
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error: %s\n"
	.size	.L.str, 11

	.type	_Z9histogramPiiS_,@object       # @_Z9histogramPiiS_
	.section	.rodata,"a",@progbits
	.globl	_Z9histogramPiiS_
	.p2align	3, 0x0
_Z9histogramPiiS_:
	.quad	_Z24__device_stub__histogramPiiS_
	.size	_Z9histogramPiiS_, 8

	.type	_Z18organize_histogramPiiS_,@object # @_Z18organize_histogramPiiS_
	.globl	_Z18organize_histogramPiiS_
	.p2align	3, 0x0
_Z18organize_histogramPiiS_:
	.quad	_Z33__device_stub__organize_histogramPiiS_
	.size	_Z18organize_histogramPiiS_, 8

	.type	_Z29Kogge_Stone_block_scan_kernelPiS_S_i,@object # @_Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.globl	_Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.p2align	3, 0x0
_Z29Kogge_Stone_block_scan_kernelPiS_S_i:
	.quad	_Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
	.size	_Z29Kogge_Stone_block_scan_kernelPiS_S_i, 8

	.type	_Z20parallel_scan_kernelPiS_i,@object # @_Z20parallel_scan_kernelPiS_i
	.globl	_Z20parallel_scan_kernelPiS_i
	.p2align	3, 0x0
_Z20parallel_scan_kernelPiS_i:
	.quad	_Z35__device_stub__parallel_scan_kernelPiS_i
	.size	_Z20parallel_scan_kernelPiS_i, 8

	.type	_Z17add_S_to_Y_kernelPiS_i,@object # @_Z17add_S_to_Y_kernelPiS_i
	.globl	_Z17add_S_to_Y_kernelPiS_i
	.p2align	3, 0x0
_Z17add_S_to_Y_kernelPiS_i:
	.quad	_Z32__device_stub__add_S_to_Y_kernelPiS_i
	.size	_Z17add_S_to_Y_kernelPiS_i, 8

	.type	_Z11shift_rightPiS_,@object     # @_Z11shift_rightPiS_
	.globl	_Z11shift_rightPiS_
	.p2align	3, 0x0
_Z11shift_rightPiS_:
	.quad	_Z26__device_stub__shift_rightPiS_
	.size	_Z11shift_rightPiS_, 8

	.type	_Z17reduce_prefix_sumPiS_S_i,@object # @_Z17reduce_prefix_sumPiS_S_i
	.globl	_Z17reduce_prefix_sumPiS_S_i
	.p2align	3, 0x0
_Z17reduce_prefix_sumPiS_S_i:
	.quad	_Z32__device_stub__reduce_prefix_sumPiS_S_i
	.size	_Z17reduce_prefix_sumPiS_S_i, 8

	.type	_Z8re_orderPiS_S_i,@object      # @_Z8re_orderPiS_S_i
	.globl	_Z8re_orderPiS_S_i
	.p2align	3, 0x0
_Z8re_orderPiS_S_i:
	.quad	_Z23__device_stub__re_orderPiS_S_i
	.size	_Z8re_orderPiS_S_i, 8

	.type	_Z5probePiS_S_S_ii,@object      # @_Z5probePiS_S_S_ii
	.globl	_Z5probePiS_S_S_ii
	.p2align	3, 0x0
_Z5probePiS_S_S_ii:
	.quad	_Z20__device_stub__probePiS_S_S_ii
	.size	_Z5probePiS_S_S_ii, 8

	.type	_Z13print_matchesv,@object      # @_Z13print_matchesv
	.globl	_Z13print_matchesv
	.p2align	3, 0x0
_Z13print_matchesv:
	.quad	_Z28__device_stub__print_matchesv
	.size	_Z13print_matchesv, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"******** Total Running Time of All Kernels = %.5f sec ********\n"
	.size	.L.str.2, 64

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9histogramPiiS_"
	.size	.L__unnamed_1, 18

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18organize_histogramPiiS_"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z29Kogge_Stone_block_scan_kernelPiS_S_i"
	.size	.L__unnamed_3, 41

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z20parallel_scan_kernelPiS_i"
	.size	.L__unnamed_4, 30

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z17add_S_to_Y_kernelPiS_i"
	.size	.L__unnamed_5, 27

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z11shift_rightPiS_"
	.size	.L__unnamed_6, 20

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z17reduce_prefix_sumPiS_S_i"
	.size	.L__unnamed_7, 29

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z8re_orderPiS_S_i"
	.size	.L__unnamed_8, 19

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z5probePiS_S_S_ii"
	.size	.L__unnamed_9, 19

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z13print_matchesv"
	.size	.L__unnamed_10, 19

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"matches"
	.size	.L__unnamed_11, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Usage: ./proj3.out {#of_elements_in_array1} {#of_elements_in_array2}"
	.size	.Lstr, 69

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__histogramPiiS_
	.addrsig_sym _Z33__device_stub__organize_histogramPiiS_
	.addrsig_sym _Z44__device_stub__Kogge_Stone_block_scan_kernelPiS_S_i
	.addrsig_sym _Z35__device_stub__parallel_scan_kernelPiS_i
	.addrsig_sym _Z32__device_stub__add_S_to_Y_kernelPiS_i
	.addrsig_sym _Z26__device_stub__shift_rightPiS_
	.addrsig_sym _Z32__device_stub__reduce_prefix_sumPiS_S_i
	.addrsig_sym _Z23__device_stub__re_orderPiS_S_i
	.addrsig_sym _Z20__device_stub__probePiS_S_S_ii
	.addrsig_sym _Z28__device_stub__print_matchesv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym matches
	.addrsig_sym _Z9histogramPiiS_
	.addrsig_sym _Z18organize_histogramPiiS_
	.addrsig_sym _Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.addrsig_sym _Z20parallel_scan_kernelPiS_i
	.addrsig_sym _Z17add_S_to_Y_kernelPiS_i
	.addrsig_sym _Z11shift_rightPiS_
	.addrsig_sym _Z17reduce_prefix_sumPiS_S_i
	.addrsig_sym _Z8re_orderPiS_S_i
	.addrsig_sym _Z5probePiS_S_S_ii
	.addrsig_sym _Z13print_matchesv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9histogramPiiS_       ; -- Begin function _Z9histogramPiiS_
	.globl	_Z9histogramPiiS_
	.p2align	8
	.type	_Z9histogramPiiS_,@function
_Z9histogramPiiS_:                      ; @_Z9histogramPiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s3, 0
	s_mov_b32 s2, 7
	global_load_b32 v0, v[0:1], off
	v_mbcnt_lo_u32_b32 v1, s4, 0
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	bfe.u32 s2, v0, s3, s2;
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 s5, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s5
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_load_b64 s[0:1], s[0:1], 0x10
	s_lshl_b32 s5, s15, 7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s5
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_bcnt1_i32_b32 s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9histogramPiiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9histogramPiiS_, .Lfunc_end0-_Z9histogramPiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18organize_histogramPiiS_ ; -- Begin function _Z18organize_histogramPiiS_
	.globl	_Z18organize_histogramPiiS_
	.p2align	8
	.type	_Z18organize_histogramPiiS_,@function
_Z18organize_histogramPiiS_:            ; @_Z18organize_histogramPiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_ashr_i32 s3, s2, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_lshr_b32 s3, s3, 25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, s3
	v_add_nc_u32_e32 v4, v1, v2
	s_ashr_i32 s3, s2, 7
	s_ashr_i32 s2, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s4, s3, s2
	v_xor_b32_e32 v4, v4, v2
	s_xor_b32 s4, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s5, 0, s4
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s3
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_sub_nc_u32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, v3, 7, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18organize_histogramPiiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18organize_histogramPiiS_, .Lfunc_end1-_Z18organize_histogramPiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z29Kogge_Stone_block_scan_kernelPiS_S_i ; -- Begin function _Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.globl	_Z29Kogge_Stone_block_scan_kernelPiS_S_i
	.p2align	8
	.type	_Z29Kogge_Stone_block_scan_kernelPiS_S_i,@function
_Z29Kogge_Stone_block_scan_kernelPiS_S_i: ; @_Z29Kogge_Stone_block_scan_kernelPiS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s2, s15
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s8, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB2_7
; %bb.3:                                ; %.lr.ph
	s_mov_b32 s4, 1
.LBB2_4:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_le_u32_e64 s4, v0
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=1
	v_subrev_nc_u32_e32 v4, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 2, v4
	ds_load_b32 v4, v4
	ds_load_b32 v5, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v5, v4
	ds_store_b32 v3, v4
.LBB2_6:                                ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_lshl_b32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s4, s3
	s_cbranch_scc0 .LBB2_4
.LBB2_7:                                ; %._crit_edge
	ds_load_b32 v3, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s3, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v3, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB2_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s0, s0, s2
	ds_load_b32 v1, v0 offset:12
	s_addc_u32 s1, s1, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29Kogge_Stone_block_scan_kernelPiS_S_i
		.amdhsa_group_segment_fixed_size 16
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z29Kogge_Stone_block_scan_kernelPiS_S_i, .Lfunc_end2-_Z29Kogge_Stone_block_scan_kernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20parallel_scan_kernelPiS_i ; -- Begin function _Z20parallel_scan_kernelPiS_i
	.globl	_Z20parallel_scan_kernelPiS_i
	.p2align	8
	.type	_Z20parallel_scan_kernelPiS_i,@function
_Z20parallel_scan_kernelPiS_i:          ; @_Z20parallel_scan_kernelPiS_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_lt_u32 s4, 2
	s_cbranch_scc1 .LBB3_7
; %bb.3:                                ; %.lr.ph
	s_mov_b32 s0, 1
.LBB3_4:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_le_u32_e64 s0, v0
	s_cbranch_execz .LBB3_6
; %bb.5:                                ;   in Loop: Header=BB3_4 Depth=1
	v_subrev_nc_u32_e32 v4, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 2, v4
	ds_load_b32 v4, v4
	ds_load_b32 v5, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v5, v4
	ds_store_b32 v3, v4
.LBB3_6:                                ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshl_b32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s0, s4
	s_cbranch_scc0 .LBB3_4
.LBB3_7:                                ; %._crit_edge
	ds_load_b32 v3, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20parallel_scan_kernelPiS_i
		.amdhsa_group_segment_fixed_size 16
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z20parallel_scan_kernelPiS_i, .Lfunc_end3-_Z20parallel_scan_kernelPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 288
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17add_S_to_Y_kernelPiS_i ; -- Begin function _Z17add_S_to_Y_kernelPiS_i
	.globl	_Z17add_S_to_Y_kernelPiS_i
	.p2align	8
	.type	_Z17add_S_to_Y_kernelPiS_i,@function
_Z17add_S_to_Y_kernelPiS_i:             ; @_Z17add_S_to_Y_kernelPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lg_u32 s15, 0
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_6
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s4, s15, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	global_load_b32 v2, v[0:1], off
	s_addc_u32 s1, s3, s1
	s_cmp_lt_u32 s15, 4
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v2, s0, v2
	global_store_b32 v[0:1], v2, off
	s_cbranch_scc1 .LBB4_6
; %bb.2:                                ; %.preheader
	v_mov_b32_e32 v3, 0
	s_cmp_lt_u32 s4, 4
	s_cbranch_scc1 .LBB4_5
; %bb.3:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
	s_add_u32 s0, s2, 12
	s_addc_u32 s1, s3, 0
	s_mov_b32 s2, 3
.LBB4_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v4, s[0:1]
	s_add_i32 s2, s2, 4
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_cmp_lt_u32 s2, s4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v5, v3
	s_cbranch_scc1 .LBB4_4
.LBB4_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB4_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17add_S_to_Y_kernelPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z17add_S_to_Y_kernelPiS_i, .Lfunc_end4-_Z17add_S_to_Y_kernelPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11shift_rightPiS_     ; -- Begin function _Z11shift_rightPiS_
	.globl	_Z11shift_rightPiS_
	.p2align	8
	.type	_Z11shift_rightPiS_,@function
_Z11shift_rightPiS_:                    ; @_Z11shift_rightPiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB5_2:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB5_4
; %bb.3:
	v_mov_b32_e32 v0, 0
	global_store_b32 v0, v0, s[2:3]
.LBB5_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11shift_rightPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z11shift_rightPiS_, .Lfunc_end5-_Z11shift_rightPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17reduce_prefix_sumPiS_S_i ; -- Begin function _Z17reduce_prefix_sumPiS_S_i
	.globl	_Z17reduce_prefix_sumPiS_S_i
	.p2align	8
	.type	_Z17reduce_prefix_sumPiS_S_i,@function
_Z17reduce_prefix_sumPiS_S_i:           ; @_Z17reduce_prefix_sumPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s9, 0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s15, s3
	s_mov_b32 s3, s9
	s_lshl_b64 s[10:11], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s4, s4, s10
	s_addc_u32 s5, s5, s11
	s_lshl_b64 s[2:3], s[2:3], 2
	s_load_b32 s4, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
	s_add_u32 s4, s6, s2
	s_addc_u32 s5, s7, s3
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_clause 0x1
	global_store_b32 v0, v1, s[4:5]
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17reduce_prefix_sumPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z17reduce_prefix_sumPiS_S_i, .Lfunc_end6-_Z17reduce_prefix_sumPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 136
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8re_orderPiS_S_i      ; -- Begin function _Z8re_orderPiS_S_i
	.globl	_Z8re_orderPiS_S_i
	.p2align	8
	.type	_Z8re_orderPiS_S_i,@function
_Z8re_orderPiS_S_i:                     ; @_Z8re_orderPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s3, 7
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_load_b32 s2, s[0:1], 0x18
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_mov_b32 s2, 0
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	bfe.u32 s2, v3, s2, s3;
	;;#ASMEND
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB7_4
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB7_3
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_bcnt1_i32_b32 s4, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4
	global_atomic_add_u32 v3, v3, v4, s[2:3] glc
.LBB7_3:
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s2, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB7_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8re_orderPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z8re_orderPiS_S_i, .Lfunc_end7-_Z8re_orderPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5probePiS_S_S_ii      ; -- Begin function _Z5probePiS_S_S_ii
	.globl	_Z5probePiS_S_S_ii
	.p2align	8
	.type	_Z5probePiS_S_S_ii,@function
_Z5probePiS_S_S_ii:                     ; @_Z5probePiS_S_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[14:15], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s4, s14
	s_addc_u32 s13, s5, s15
	s_add_u32 s14, s6, s14
	s_load_b32 s12, s[12:13], 0x0
	s_addc_u32 s15, s7, s15
	s_cmpk_eq_i32 s2, 0x7f
	s_cbranch_scc1 .LBB8_2
; %bb.1:
	s_add_i32 s0, s2, 1
	s_mov_b32 s1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s6, s6, s0
	s_addc_u32 s7, s7, s1
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_load_b32 s0, s[0:1], 0x0
	s_load_b32 s1, s[6:7], 0x0
	s_branch .LBB8_3
.LBB8_2:
	s_load_b64 s[0:1], s[0:1], 0x20
.LBB8_3:
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s12, s0
	s_cbranch_scc1 .LBB8_9
; %bb.4:                                ; %.preheader.lr.ph
	s_load_b32 s2, s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, s1
	s_cselect_b32 s14, -1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[2:3], 2
	s_mov_b32 s3, 0
	s_add_u32 s4, s10, s4
	s_addc_u32 s5, s11, s5
.LBB8_5:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_7 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB8_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB8_5 Depth=1
	s_ashr_i32 s13, s12, 31
	s_mov_b32 s11, s2
	s_lshl_b64 s[6:7], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s8, s6
	s_addc_u32 s7, s9, s7
	s_load_b32 s10, s[6:7], 0x0
	s_mov_b64 s[6:7], s[4:5]
.LBB8_7:                                ;   Parent Loop BB8_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b32 s13, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s10, s13
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s13, 0
	s_addc_u32 s3, s3, 0
	s_add_i32 s11, s11, 1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_lt_i32 s11, s1
	s_cbranch_scc1 .LBB8_7
.LBB8_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB8_5 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s12, s0
	s_cbranch_scc1 .LBB8_5
.LBB8_9:                                ; %._crit_edge34
	s_mov_b32 s0, exec_lo
	s_mov_b32 s1, exec_lo
	v_mbcnt_lo_u32_b32 v0, s0, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB8_11
; %bb.10:
	s_bcnt1_i32_b32 s0, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s3, s0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, matches@rel32@lo+4
	s_addc_u32 s1, s1, matches@rel32@hi+12
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB8_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5probePiS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z5probePiS_S_S_ii, .Lfunc_end8-_Z5probePiS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 18
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13print_matchesv      ; -- Begin function _Z13print_matchesv
	.globl	_Z13print_matchesv
	.p2align	8
	.type	_Z13print_matchesv,@function
_Z13print_matchesv:                     ; @_Z13print_matchesv
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, matches@rel32@lo+4
	s_addc_u32 s3, s3, matches@rel32@hi+12
	v_mbcnt_lo_u32_b32 v30, -1, 0
	s_load_b32 s14, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x50
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v30
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_6
; %bb.1:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB9_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB9_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB9_3
; %bb.4:                                ; %Flow315
	s_or_b32 exec_lo, exec_lo, s5
.LBB9_5:                                ; %Flow317
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB9_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB9_8
; %bb.7:
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB9_8:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB9_16
; %bb.9:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB9_12
; %bb.10:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB9_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB9_11
.LBB9_12:                               ; %Flow313
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB9_14
; %bb.13:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB9_14:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB9_16
; %bb.15:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB9_16:                               ; %Flow314
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB9_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_19
; %bb.18:                               ;   in Loop: Header=BB9_17 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB9_19:                               ;   in Loop: Header=BB9_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB9_21
; %bb.20:                               ;   in Loop: Header=BB9_17 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB9_22
.LBB9_21:                               ;   in Loop: Header=BB9_17 Depth=1
	s_mov_b32 s1, -1
.LBB9_22:                               ; %Flow308
                                        ;   in Loop: Header=BB9_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB9_17
; %bb.23:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_27
; %bb.24:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB9_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB9_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB9_26
.LBB9_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB9_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, 2 :: v_dual_and_b32 v31, 2, v0
	v_dual_mov_b32 v29, 0 :: v_dual_and_b32 v2, -3, v0
	v_mov_b32_e32 v3, v1
	v_mov_b32_e32 v7, 1
	s_mov_b64 s[6:7], 17
.LBB9_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB9_32 Depth 2
                                        ;     Child Loop BB9_39 Depth 2
                                        ;     Child Loop BB9_47 Depth 2
                                        ;     Child Loop BB9_55 Depth 2
                                        ;     Child Loop BB9_63 Depth 2
                                        ;     Child Loop BB9_71 Depth 2
                                        ;     Child Loop BB9_79 Depth 2
                                        ;     Child Loop BB9_87 Depth 2
                                        ;     Child Loop BB9_95 Depth 2
                                        ;     Child Loop BB9_101 Depth 2
                                        ;     Child Loop BB9_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr16
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB9_34
; %bb.30:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB9_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB9_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v29, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB9_32
.LBB9_33:                               ; %Flow284
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s16, 0
.LBB9_34:                               ; %Flow286
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB9_36
; %bb.35:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[10:11], v29, s[4:5]
	s_add_i32 s16, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB9_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB9_41
; %bb.37:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB9_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB9_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s12
	s_addc_u32 s19, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v29, s[18:19]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s16, s12
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB9_39
.LBB9_40:                               ; %Flow279
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB9_42
.LBB9_41:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr15
.LBB9_42:                               ; %Flow281
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_44
; %bb.43:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[12:13], v29, s[0:1]
	s_add_i32 s15, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB9_49
; %bb.45:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB9_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB9_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v29, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB9_47
.LBB9_48:                               ; %Flow274
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s16, 0
	s_branch .LBB9_50
.LBB9_49:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr16
.LBB9_50:                               ; %Flow276
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_52
; %bb.51:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[14:15], v29, s[0:1]
	s_add_i32 s16, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB9_57
; %bb.53:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB9_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB9_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s12
	s_addc_u32 s19, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v29, s[18:19]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s16, s12
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB9_55
.LBB9_56:                               ; %Flow269
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB9_58
.LBB9_57:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr15
.LBB9_58:                               ; %Flow271
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_60
; %bb.59:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[16:17], v29, s[0:1]
	s_add_i32 s15, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB9_65
; %bb.61:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB9_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB9_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v29, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB9_63
.LBB9_64:                               ; %Flow264
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s16, 0
	s_branch .LBB9_66
.LBB9_65:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr16
.LBB9_66:                               ; %Flow266
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_68
; %bb.67:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[18:19], v29, s[0:1]
	s_add_i32 s16, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB9_73
; %bb.69:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB9_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB9_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s12
	s_addc_u32 s19, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v29, s[18:19]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s16, s12
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB9_71
.LBB9_72:                               ; %Flow259
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB9_74
.LBB9_73:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr15
.LBB9_74:                               ; %Flow261
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_76
; %bb.75:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[20:21], v29, s[0:1]
	s_add_i32 s15, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB9_81
; %bb.77:                               ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB9_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB9_79:                               ; %.preheader.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v29, s[12:13]
	s_add_i32 s15, s15, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[28:29]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s15, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB9_79
.LBB9_80:                               ; %Flow254
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB9_82
.LBB9_81:                               ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s10, -1
.LBB9_82:                               ; %Flow256
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB9_84
; %bb.83:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[22:23], v29, s[0:1]
.LBB9_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	v_mov_b32_e32 v28, v30
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v28
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_90
; %bb.85:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b64 v[26:27], v29, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v29, s[2:3] offset:40
	global_load_b64 v[8:9], v29, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v29, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB9_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s11, 0
.LBB9_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v29, s[2:3] offset:40
	global_load_b64 v[24:25], v29, s[2:3]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v29, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB9_87
; %bb.88:                               ; %Flow249
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB9_89:                               ; %Flow251
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB9_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v29, s[2:3] offset:40
	global_load_b128 v[24:27], v29, s[2:3]
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_mov_b32 s17, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s15, s12, 24
	s_mul_i32 s16, s12, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB9_92
; %bb.91:                               ;   in Loop: Header=BB9_29 Depth=1
	v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v5, v29
	s_add_i32 s17, s15, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB9_92:                               ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v31
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s17, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s17, s17, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s12
	v_add_co_ci_u32_e32 v27, vcc_lo, s13, v27, vcc_lo
	s_and_b32 s17, s17, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s17
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB9_100
; %bb.93:                               ;   in Loop: Header=BB9_29 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v29, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v29, s[2:3] offset:40
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v2
	v_readfirstlane_b32 s19, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[18:19], s[10:11]
	s_mul_i32 s13, s19, 24
	s_mul_hi_u32 s17, s18, 24
	s_mul_i32 s18, s18, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v8, vcc_lo, v24, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v25, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v29, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB9_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s17, 0
.LBB9_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v29, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB9_95
.LBB9_96:                               ; %Flow247
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[2:3], v29, s[2:3] offset:16
	s_mov_b32 s17, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v4, s17, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB9_98
; %bb.97:                               ;   in Loop: Header=BB9_29 Depth=1
	s_bcnt1_i32_b32 s17, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v28, s17
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[28:29], off offset:8
.LBB9_98:                               ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB9_100
; %bb.99:                               ;   in Loop: Header=BB9_29 Depth=1
	global_load_b32 v28, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v28
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[28:29], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB9_100:                              ; %Flow248
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s15, s15, s1
	v_add_co_u32 v2, vcc_lo, v24, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB9_101:                              ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_103
; %bb.102:                              ;   in Loop: Header=BB9_101 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB9_103:                              ;   in Loop: Header=BB9_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB9_105
; %bb.104:                              ;   in Loop: Header=BB9_101 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB9_106
.LBB9_105:                              ;   in Loop: Header=BB9_101 Depth=2
	s_mov_b32 s1, -1
.LBB9_106:                              ; %Flow242
                                        ;   in Loop: Header=BB9_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB9_101
; %bb.107:                              ;   in Loop: Header=BB9_29 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_111
; %bb.108:                              ;   in Loop: Header=BB9_29 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v29, s[2:3] offset:40
	global_load_b64 v[12:13], v29, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v29, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v29, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB9_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_mov_b32 s0, 0
.LBB9_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB9_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v29, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB9_110
.LBB9_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB9_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB9_29
; %bb.112:                              ; %Flow287
	s_mov_b32 s0, 0
	s_branch .LBB9_114
.LBB9_113:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB9_114:                              ; %Flow302
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB9_143
; %bb.115:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v30
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_121
; %bb.116:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB9_120
; %bb.117:                              ; %.preheader3.i.i.i6.preheader
	s_mov_b32 s5, 0
.LBB9_118:                              ; %.preheader3.i.i.i6
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB9_118
; %bb.119:                              ; %Flow299
	s_or_b32 exec_lo, exec_lo, s5
.LBB9_120:                              ; %Flow301
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB9_121:                              ; %.loopexit4.i.i.i1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB9_123
; %bb.122:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB9_123:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v11, s19
	v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v10, s18
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB9_131
; %bb.124:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB9_127
; %bb.125:                              ; %.preheader1.i.i.i4.preheader
	s_mov_b32 s10, 0
.LBB9_126:                              ; %.preheader1.i.i.i4
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB9_126
.LBB9_127:                              ; %Flow297
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB9_129
; %bb.128:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB9_129:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB9_131
; %bb.130:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB9_131:                              ; %Flow298
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB9_132:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_134
; %bb.133:                              ;   in Loop: Header=BB9_132 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB9_134:                              ;   in Loop: Header=BB9_132 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB9_136
; %bb.135:                              ;   in Loop: Header=BB9_132 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB9_137
.LBB9_136:                              ;   in Loop: Header=BB9_132 Depth=1
	s_mov_b32 s1, -1
.LBB9_137:                              ; %Flow292
                                        ;   in Loop: Header=BB9_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB9_132
; %bb.138:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_142
; %bb.139:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB9_142
; %bb.140:                              ; %.preheader.i.i.i3.preheader
	s_mov_b32 s0, 0
.LBB9_141:                              ; %.preheader.i.i.i3
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB9_141
.LBB9_142:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB9_143:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, v30
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v4
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_149
; %bb.144:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[8:9], v5, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[2:3] offset:40
	global_load_b64 v[6:7], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB9_148
; %bb.145:                              ; %.preheader3.i.i.i13.preheader
	s_mov_b32 s5, 0
.LBB9_146:                              ; %.preheader3.i.i.i13
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v5, s[2:3] offset:40
	global_load_b64 v[10:11], v5, s[2:3]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB9_146
; %bb.147:                              ; %Flow235
	s_or_b32 exec_lo, exec_lo, s5
.LBB9_148:                              ; %Flow237
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB9_149:                              ; %.loopexit4.i.i.i7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v5, s[2:3] offset:40
	global_load_b128 v[6:9], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB9_151
; %bb.150:
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB9_151:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v2, 0xffffff1d, v2, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	v_mov_b32_e32 v4, s14
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v11, s19
	v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v10, s18
	s_clause 0x3
	global_store_b128 v[0:1], v[2:5], off
	global_store_b128 v[0:1], v[8:11], off offset:16
	global_store_b128 v[0:1], v[8:11], off offset:32
	global_store_b128 v[0:1], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB9_159
; %bb.152:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v4, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB9_155
; %bb.153:                              ; %.preheader1.i.i.i11.preheader
	s_mov_b32 s10, 0
.LBB9_154:                              ; %.preheader1.i.i.i11
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB9_154
.LBB9_155:                              ; %Flow233
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB9_157
; %bb.156:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB9_157:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB9_159
; %bb.158:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB9_159:                              ; %Flow234
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB9_160:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_162
; %bb.161:                              ;   in Loop: Header=BB9_160 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB9_162:                              ;   in Loop: Header=BB9_160 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB9_164
; %bb.163:                              ;   in Loop: Header=BB9_160 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB9_165
.LBB9_164:                              ;   in Loop: Header=BB9_160 Depth=1
	s_mov_b32 s1, -1
.LBB9_165:                              ; %Flow228
                                        ;   in Loop: Header=BB9_160 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB9_160
; %bb.166:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_170
; %bb.167:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB9_170
; %bb.168:                              ; %.preheader.i.i.i10.preheader
	s_mov_b32 s0, 0
.LBB9_169:                              ; %.preheader.i.i.i10
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB9_169
.LBB9_170:                              ; %__ockl_printf_append_args.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13print_matchesv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z13print_matchesv, .Lfunc_end9-_Z13print_matchesv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6700
; NumSgprs: 22
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	matches                 ; @matches
	.type	matches,@object
	.section	.bss,"aw",@nobits
	.globl	matches
	.p2align	2, 0x0
matches:
	.long	0                               ; 0x0
	.size	matches, 4

	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"---> %d matches\n"
	.size	.str, 17

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym matches
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9histogramPiiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9histogramPiiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18organize_histogramPiiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18organize_histogramPiiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
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        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z29Kogge_Stone_block_scan_kernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z29Kogge_Stone_block_scan_kernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
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        .size:           8
        .value_kind:     hidden_global_offset_z
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20parallel_scan_kernelPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20parallel_scan_kernelPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .size:           8
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    .language:       OpenCL C
    .language_version:
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      - 0
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    .sgpr_spill_count: 0
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        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13print_matchesv
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z13print_matchesv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
