#include "includes.h"

static unsigned int GRID_SIZE_N;
static unsigned int GRID_SIZE_4N;
static unsigned int MAX_STATE_VALUE;

__global__ static void cudaIIGammaKernel(double *extEV, double *x1, double *x2, double *x3, double *left, double *right) {
__shared__ volatile double al[64], ar[64], v[64], x1px2[16];
const int tid = (threadIdx.z * 16) + (threadIdx.y * 4) + threadIdx.x;
const int offset = 16 * blockIdx.x + 4 * threadIdx.z;
al[tid] = x1[offset + threadIdx.x] * left[tid];
ar[tid] = x2[offset + threadIdx.x] * right[tid];
__syncthreads();
if (threadIdx.x <= 1) {
al[tid] += al[tid + 2];
ar[tid] += ar[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0) {
al[tid] += al[tid + 1];
ar[tid] += ar[tid + 1];
x1px2[(threadIdx.z * 4) + threadIdx.y] = al[tid] * ar[tid];
}
__syncthreads();
v[tid] = x1px2[threadIdx.y + (threadIdx.z * 4)] *
extEV[threadIdx.y * 4 + threadIdx.x];
__syncthreads();
if (threadIdx.y <= 1) {
v[tid] += v[tid + 8];
}
__syncthreads();
if (threadIdx.y == 0) {
v[tid] += v[tid + 4];
x3[offset + threadIdx.x] = v[tid];
}
}
	.file	"tmpxft_0026350f_00000000-6_cudaIIGammaKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL17cudaIIGammaKernelPdS_S_S_S_S_, @function
_ZL17cudaIIGammaKernelPdS_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	48(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZL17cudaIIGammaKernelPdS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_ZL17cudaIIGammaKernelPdS_S_S_S_S_, .-_ZL17cudaIIGammaKernelPdS_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17cudaIIGammaKernelPdS_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL17cudaIIGammaKernelPdS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

static unsigned int GRID_SIZE_N;
static unsigned int GRID_SIZE_4N;
static unsigned int MAX_STATE_VALUE;

__global__ static void cudaIIGammaKernel(double *extEV, double *x1, double *x2, double *x3, double *left, double *right) {
__shared__ volatile double al[64], ar[64], v[64], x1px2[16];
const int tid = (threadIdx.z * 16) + (threadIdx.y * 4) + threadIdx.x;
const int offset = 16 * blockIdx.x + 4 * threadIdx.z;
al[tid] = x1[offset + threadIdx.x] * left[tid];
ar[tid] = x2[offset + threadIdx.x] * right[tid];
__syncthreads();
if (threadIdx.x <= 1) {
al[tid] += al[tid + 2];
ar[tid] += ar[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0) {
al[tid] += al[tid + 1];
ar[tid] += ar[tid + 1];
x1px2[(threadIdx.z * 4) + threadIdx.y] = al[tid] * ar[tid];
}
__syncthreads();
v[tid] = x1px2[threadIdx.y + (threadIdx.z * 4)] *
extEV[threadIdx.y * 4 + threadIdx.x];
__syncthreads();
if (threadIdx.y <= 1) {
v[tid] += v[tid + 8];
}
__syncthreads();
if (threadIdx.y == 0) {
v[tid] += v[tid + 4];
x3[offset + threadIdx.x] = v[tid];
}
}
	.text
	.file	"cudaIIGammaKernel.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL17cudaIIGammaKernelPdS_S_S_S_S_,"axG",@progbits,_ZL17cudaIIGammaKernelPdS_S_S_S_S_,comdat
	.globl	_ZL17cudaIIGammaKernelPdS_S_S_S_S_ ; -- Begin function _ZL17cudaIIGammaKernelPdS_S_S_S_S_
	.p2align	8
	.type	_ZL17cudaIIGammaKernelPdS_S_S_S_S_,@function
_ZL17cudaIIGammaKernelPdS_S_S_S_S_:     ; @_ZL17cudaIIGammaKernelPdS_S_S_S_S_
; %bb.0:
	v_bfe_u32 v2, v0, 20, 10
	v_bfe_u32 v6, v0, 10, 10
	s_load_b256 s[4:11], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v8, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 2, v2
	v_lshlrev_b32_e32 v9, 2, v6
	s_load_b128 s[0:3], s[0:1], 0x20
	s_lshl_b32 s12, s15, 4
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, v11, v8, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v10, v2, 4, v9
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v10, v8
	v_lshlrev_b32_e32 v7, 3, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[4:5], v7, s[0:1]
	global_load_b64 v[2:3], v[2:3], off
	s_mov_b64 s[0:1], src_shared_base
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[2:3], v[4:5]
	v_add_nc_u32_e32 v2, 0x200, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v1, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	global_load_b64 v[4:5], v[12:13], off
	global_load_b64 v[12:13], v7, s[2:3]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[4:5], v[12:13]
	v_add_nc_u32_e32 v4, 0x400, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_store_b64 v[4:5], v[12:13] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v8
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_add_nc_u32_e32 v12, 0x210, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v12
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cndmask_b32_e64 v13, 0, s1, vcc_lo
	flat_load_b64 v[12:13], v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[14:15], v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_nc_u32_e32 v14, 0x410, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v14
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cndmask_b32_e64 v15, 0, s1, vcc_lo
	flat_store_b64 v[2:3], v[12:13] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[12:13], v[14:15] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[14:15], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	flat_store_b64 v[4:5], v[12:13] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v12, v11, v6
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_ne_u32_e32 0, v8
	s_xor_b32 s0, exec_lo, s0
; %bb.3:                                ; %._crit_edge
	v_add_nc_u32_e32 v12, v11, v6
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr4_vgpr5
; %bb.4:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshlrev_b32_e32 v15, 3, v10
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, 0x208, v15
	v_cmp_ne_u32_e32 vcc_lo, -1, v10
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cndmask_b32_e64 v11, 0, s3, vcc_lo
	flat_load_b64 v[10:11], v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[13:14], v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], v[10:11], v[13:14]
	v_add_nc_u32_e32 v13, 0x408, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v13
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cndmask_b32_e64 v14, 0, s3, vcc_lo
	flat_store_b64 v[2:3], v[10:11] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[10:11], v[13:14] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[13:14], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], v[10:11], v[13:14]
	flat_store_b64 v[4:5], v[10:11] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[2:3], v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_lshl_add_u32 v4, v12, 3, 0x600
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s3, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, v12, 3, 0x600
	s_mov_b64 s[0:1], src_shared_base
	v_add_lshl_u32 v4, v9, v8, 3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b64 v[2:3], v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v4, s[4:5]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[4:5], v[2:3], v[4:5]
	v_cndmask_b32_e32 v2, 0, v7, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v6
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_add_nc_u32_e32 v4, 64, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[8:9], v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_add_nc_u32_e32 v4, 32, v7
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[6:7], v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[2:3], v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL17cudaIIGammaKernelPdS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 1664
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL17cudaIIGammaKernelPdS_S_S_S_S_,"axG",@progbits,_ZL17cudaIIGammaKernelPdS_S_S_S_S_,comdat
.Lfunc_end0:
	.size	_ZL17cudaIIGammaKernelPdS_S_S_S_S_, .Lfunc_end0-_ZL17cudaIIGammaKernelPdS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1104
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1664 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 1664
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL17cudaIIGammaKernelPdS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL17cudaIIGammaKernelPdS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
