/*
Center assignments
Written by Jiageng Mao
*/

#include <math.h>
#include <stdio.h>

#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))

__device__ float limit_period(float val, float offset, float period){
    float rval = val - floor(val / period + offset) * period;
    return rval;
}

__device__ float gaussian_radius(float height, float width, float min_overlap){
    float a1 = 1;
    float b1 = (height + width);
    float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
    float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
    float r1 = (b1 + sq1) / 2;

    float a2 = 4;
    float b2 = 2 * (height + width);
    float c2 = (1 - min_overlap) * width * height;
    float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
    float r2 = (b2 + sq2) / 2;

    float a3 = 4 * min_overlap;
    float b3 = -2 * min_overlap * (height + width);
    float c3 = (min_overlap - 1) * width * height;
    float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
    float r3 = (b3 + sq3) / 2;
    return min(min(r1, r2), r3);
}

__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
                                    float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
                                    const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){

    /*
        Args:
            gt_boxes: (B, max_boxes, 8 or 10) with class labels
            heatmap: (B, num_cls, H, W)
            gt_ind: (B, num_cls, max_objs)
            gt_mask: (B, num_cls, max_objs)
            gt_cat: (B, num_cls, max_objs)
            gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
            gt_cnt: (B, num_cls)
    */
    int bs_idx = blockIdx.x;
    int box_idx = threadIdx.x;
    if (bs_idx >= batch_size || box_idx >= max_boxes) return;

    // move pointer
    gt_boxes += bs_idx * max_boxes * code_size;
    heatmap += bs_idx * num_cls * H * W;
    gt_ind += bs_idx * num_cls * max_objs;
    gt_mask += bs_idx * num_cls * max_objs;
    gt_cat += bs_idx * num_cls * max_objs;
    gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
    gt_cnt += bs_idx * num_cls;

    // gt box parameters
    float x = gt_boxes[box_idx * code_size + 0];
    float y = gt_boxes[box_idx * code_size + 1];
    float z = gt_boxes[box_idx * code_size + 2];
    float dx = gt_boxes[box_idx * code_size + 3];
    float dy = gt_boxes[box_idx * code_size + 4];
    float dz = gt_boxes[box_idx * code_size + 5];
    // origin dx/dy/dz is for box_encodings
    float origin_dx = gt_boxes[box_idx * code_size + 3];
    float origin_dy = gt_boxes[box_idx * code_size + 4];
    float origin_dz = gt_boxes[box_idx * code_size + 5];
    float rot = gt_boxes[box_idx * code_size + 6];
    float vel_x = 0;
    float vel_y = 0;
    float cls = 0;
    if (code_size == 10) {
        vel_x = gt_boxes[box_idx * code_size + 7];
        vel_y = gt_boxes[box_idx * code_size + 8];
        cls = gt_boxes[box_idx * code_size + 9];
    } else if (code_size == 8) {
        cls = gt_boxes[box_idx * code_size + 7];
    } else {
        return;
    }

    // box not defined
    if (dx == 0 || dy == 0 || dz == 0) return;

    // cls begin from 1
    int cls_idx = (int) cls - 1;
    heatmap += cls_idx * H * W;
    gt_ind += cls_idx * max_objs;
    gt_mask += cls_idx * max_objs;
    gt_cat += cls_idx * max_objs;
    gt_box_encoding += cls_idx * max_objs * code_size;
    gt_cnt += cls_idx;

    // transform to bev map coords
    float offset = 0.5;
    float period = 6.283185307179586;
    rot = limit_period(rot, offset, period);
    dx = dx / voxel_x / out_factor;
    dy = dy / voxel_y / out_factor;
    float radius = gaussian_radius(dy, dx, gaussian_overlap);
    int radius_int = max(min_radius, (int) radius);
    float coor_x = (x - range_x) / voxel_x / out_factor;
    float coor_y = (y - range_y) / voxel_y / out_factor;
    int coor_x_int = (int) coor_x;
    int coor_y_int = (int) coor_y;
    if (coor_x_int >= W || coor_x_int < 0) return;
    if (coor_y_int >= H || coor_y_int < 0) return;

    // draw gaussian map
    float div_factor = 6.0;
    float sigma = (2 * radius_int + 1) / div_factor;
    for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
        if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
        for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
            if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
            float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
            float eps = 0.0000001;
            if (weight < eps) weight = 0;
            float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
            float old_weight = atomicExch(w_addr, weight);
            if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
        }
    }
    int obj_idx = atomicAdd(gt_cnt, 1);
    if (obj_idx >= max_objs) return;
    gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
    gt_mask[obj_idx] = 1;
    gt_cat[obj_idx] = cls_idx + 1; // begin from 1
    gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
    gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
    gt_box_encoding[obj_idx * code_size + 2] = z;
    gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
    gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
    gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
    gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
    gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
    if (code_size == 10) {
        gt_box_encoding[obj_idx * code_size + 8] = vel_x;
        gt_box_encoding[obj_idx * code_size + 9] = vel_y;
    }
    return;
}

void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
                                    float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
                                    const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
    cudaError_t err;

    dim3 blocks(batch_size);
    dim3 threads(THREADS_PER_BLOCK);
    draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
                                            voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
                                            gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);

    err = cudaGetLastError();
    if (cudaSuccess != err) {
        fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
        exit(-1);
    }

#ifdef DEBUG
    cudaDeviceSynchronize();  // for using printf in kernel function
#endif
}
	.file	"tmpxft_00230c06_00000000-6_draw_center_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12limit_periodfff
	.type	_Z12limit_periodfff, @function
_Z12limit_periodfff:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z12limit_periodfff, .-_Z12limit_periodfff
	.globl	_Z15gaussian_radiusfff
	.type	_Z15gaussian_radiusfff, @function
_Z15gaussian_radiusfff:
.LFB2174:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2174:
	.size	_Z15gaussian_radiusfff, .-_Z15gaussian_radiusfff
	.globl	_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.type	_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$360, %rsp
	.cfi_def_cfa_offset 368
	movq	384(%rsp), %rax
	movl	%edi, 108(%rsp)
	leaq	128(%rsp), %rdi
	movl	%esi, 104(%rsp)
	leaq	140(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	392(%rsp), %rax
	movl	%edx, 100(%rsp)
	leaq	112(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	400(%rsp), %rax
	movl	%ecx, 96(%rsp)
	leaq	120(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	408(%rsp), %rax
	movl	%r8d, 92(%rsp)
	movq	%rax, 32(%rsp)
	movq	416(%rsp), %rax
	movl	%r9d, 88(%rsp)
	movq	%rax, 24(%rsp)
	movq	424(%rsp), %rax
	movss	%xmm0, 84(%rsp)
	movq	%rax, 16(%rsp)
	movq	432(%rsp), %rax
	movss	%xmm1, 80(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm2, 76(%rsp)
	movss	%xmm3, 72(%rsp)
	movss	%xmm4, 68(%rsp)
	movss	%xmm5, 64(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 344(%rsp)
	xorl	%eax, %eax
	leaq	108(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	100(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	92(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 336(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 128(%rsp)
	movl	$1, 136(%rsp)
	movq	%rax, 140(%rsp)
	movl	$1, 148(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	120(%rsp)
	.cfi_def_cfa_offset 376
	leaq	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rdi
	pushq	120(%rsp)
	.cfi_def_cfa_offset 384
	movq	156(%rsp), %rcx
	movl	164(%rsp), %r8d
	movq	144(%rsp), %rsi
	movl	152(%rsp), %edx
	leaq	192(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 376
	popq	%rdx
	.cfi_def_cfa_offset 368
.L6:
	movq	344(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$360, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.globl	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.type	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.cfi_endproc
.LFE2055:
	.size	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA kernel failed : %s\n"
	.text
	.globl	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.type	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, @function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
.LFB2029:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	movl	$16777217, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	salq	$8, %rdx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rax, 44(%rsp)
	movl	48(%rsp), %esi
	movl	%edi, 40(%rsp)
	movq	40(%rsp), %rdi
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 20(%rsp)
	movss	%xmm3, 16(%rsp)
	movss	%xmm4, 12(%rsp)
	movss	%xmm5, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm5
	movss	12(%rsp), %xmm4
	testl	%eax, %eax
	movss	16(%rsp), %xmm3
	movss	20(%rsp), %xmm2
	movss	24(%rsp), %xmm1
	movss	28(%rsp), %xmm0
	jne	.L13
	pushq	%rax
	.cfi_def_cfa_offset 136
	movl	%r15d, %r9d
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	pushq	200(%rsp)
	.cfi_def_cfa_offset 144
	movl	%r12d, %edx
	movl	%ebp, %esi
	movl	%ebx, %edi
	pushq	200(%rsp)
	.cfi_def_cfa_offset 152
	pushq	200(%rsp)
	.cfi_def_cfa_offset 160
	pushq	200(%rsp)
	.cfi_def_cfa_offset 168
	pushq	200(%rsp)
	.cfi_def_cfa_offset 176
	pushq	200(%rsp)
	.cfi_def_cfa_offset 184
	pushq	200(%rsp)
	.cfi_def_cfa_offset 192
	movl	200(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	200(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 208
	call	_Z69__device_stub__Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_iiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	addq	$80, %rsp
	.cfi_def_cfa_offset 128
.L13:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L12
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L12:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.section	.rodata.str1.1
.LC1:
	.string	"_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
Center assignments
Written by Jiageng Mao
*/


#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>

#define THREADS_PER_BLOCK 256
#define DIVUP(m,n) ((m) / (n) + ((m) % (n) > 0))

__device__ float limit_period(float val, float offset, float period){
    float rval = val - floor(val / period + offset) * period;
    return rval;
}

__device__ float gaussian_radius(float height, float width, float min_overlap){
    float a1 = 1;
    float b1 = (height + width);
    float c1 = width * height * (1 - min_overlap) / (1 + min_overlap);
    float sq1 = sqrt(b1 * b1 - 4 * a1 * c1);
    float r1 = (b1 + sq1) / 2;

    float a2 = 4;
    float b2 = 2 * (height + width);
    float c2 = (1 - min_overlap) * width * height;
    float sq2 = sqrt(b2 * b2 - 4 * a2 * c2);
    float r2 = (b2 + sq2) / 2;

    float a3 = 4 * min_overlap;
    float b3 = -2 * min_overlap * (height + width);
    float c3 = (min_overlap - 1) * width * height;
    float sq3 = sqrt(b3 * b3 - 4 * a3 * c3);
    float r3 = (b3 + sq3) / 2;
    return min(min(r1, r2), r3);
}

__global__ void draw_center_kernel(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
                                    float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
                                    const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){

    /*
        Args:
            gt_boxes: (B, max_boxes, 8 or 10) with class labels
            heatmap: (B, num_cls, H, W)
            gt_ind: (B, num_cls, max_objs)
            gt_mask: (B, num_cls, max_objs)
            gt_cat: (B, num_cls, max_objs)
            gt_box_encoding: (B, num_cls, max_objs, code_size) sin/cos
            gt_cnt: (B, num_cls)
    */
    int bs_idx = blockIdx.x;
    int box_idx = threadIdx.x;
    if (bs_idx >= batch_size || box_idx >= max_boxes) return;

    // move pointer
    gt_boxes += bs_idx * max_boxes * code_size;
    heatmap += bs_idx * num_cls * H * W;
    gt_ind += bs_idx * num_cls * max_objs;
    gt_mask += bs_idx * num_cls * max_objs;
    gt_cat += bs_idx * num_cls * max_objs;
    gt_box_encoding += bs_idx * num_cls * max_objs * code_size;
    gt_cnt += bs_idx * num_cls;

    // gt box parameters
    float x = gt_boxes[box_idx * code_size + 0];
    float y = gt_boxes[box_idx * code_size + 1];
    float z = gt_boxes[box_idx * code_size + 2];
    float dx = gt_boxes[box_idx * code_size + 3];
    float dy = gt_boxes[box_idx * code_size + 4];
    float dz = gt_boxes[box_idx * code_size + 5];
    // origin dx/dy/dz is for box_encodings
    float origin_dx = gt_boxes[box_idx * code_size + 3];
    float origin_dy = gt_boxes[box_idx * code_size + 4];
    float origin_dz = gt_boxes[box_idx * code_size + 5];
    float rot = gt_boxes[box_idx * code_size + 6];
    float vel_x = 0;
    float vel_y = 0;
    float cls = 0;
    if (code_size == 10) {
        vel_x = gt_boxes[box_idx * code_size + 7];
        vel_y = gt_boxes[box_idx * code_size + 8];
        cls = gt_boxes[box_idx * code_size + 9];
    } else if (code_size == 8) {
        cls = gt_boxes[box_idx * code_size + 7];
    } else {
        return;
    }

    // box not defined
    if (dx == 0 || dy == 0 || dz == 0) return;

    // cls begin from 1
    int cls_idx = (int) cls - 1;
    heatmap += cls_idx * H * W;
    gt_ind += cls_idx * max_objs;
    gt_mask += cls_idx * max_objs;
    gt_cat += cls_idx * max_objs;
    gt_box_encoding += cls_idx * max_objs * code_size;
    gt_cnt += cls_idx;

    // transform to bev map coords
    float offset = 0.5;
    float period = 6.283185307179586;
    rot = limit_period(rot, offset, period);
    dx = dx / voxel_x / out_factor;
    dy = dy / voxel_y / out_factor;
    float radius = gaussian_radius(dy, dx, gaussian_overlap);
    int radius_int = max(min_radius, (int) radius);
    float coor_x = (x - range_x) / voxel_x / out_factor;
    float coor_y = (y - range_y) / voxel_y / out_factor;
    int coor_x_int = (int) coor_x;
    int coor_y_int = (int) coor_y;
    if (coor_x_int >= W || coor_x_int < 0) return;
    if (coor_y_int >= H || coor_y_int < 0) return;

    // draw gaussian map
    float div_factor = 6.0;
    float sigma = (2 * radius_int + 1) / div_factor;
    for (int scan_y = -radius_int; scan_y < radius_int + 1; scan_y++){
        if (coor_y_int + scan_y < 0 || coor_y_int + scan_y >= H) continue;
        for (int scan_x = -radius_int; scan_x < radius_int + 1; scan_x++){
            if (coor_x_int + scan_x < 0 || coor_x_int + scan_x >= W) continue;
            float weight = exp(-(scan_x * scan_x + scan_y * scan_y) / (2 * sigma * sigma)); // force convert float sigma
            float eps = 0.0000001;
            if (weight < eps) weight = 0;
            float *w_addr = heatmap + (coor_y_int + scan_y) * W + (coor_x_int + scan_x);
            float old_weight = atomicExch(w_addr, weight);
            if (old_weight > weight) weight = atomicExch(w_addr, old_weight);
        }
    }
    int obj_idx = atomicAdd(gt_cnt, 1);
    if (obj_idx >= max_objs) return;
    gt_ind[obj_idx] = coor_y_int * W + coor_x_int;
    gt_mask[obj_idx] = 1;
    gt_cat[obj_idx] = cls_idx + 1; // begin from 1
    gt_box_encoding[obj_idx * code_size + 0] = coor_x - coor_x_int;
    gt_box_encoding[obj_idx * code_size + 1] = coor_y - coor_y_int;
    gt_box_encoding[obj_idx * code_size + 2] = z;
    gt_box_encoding[obj_idx * code_size + 3] = origin_dx;
    gt_box_encoding[obj_idx * code_size + 4] = origin_dy;
    gt_box_encoding[obj_idx * code_size + 5] = origin_dz;
    gt_box_encoding[obj_idx * code_size + 6] = sin(rot);
    gt_box_encoding[obj_idx * code_size + 7] = cos(rot);
    if (code_size == 10) {
        gt_box_encoding[obj_idx * code_size + 8] = vel_x;
        gt_box_encoding[obj_idx * code_size + 9] = vel_y;
    }
    return;
}

void draw_center_kernel_launcher(int batch_size, int max_boxes, int max_objs, int num_cls, int H, int W, int code_size, int min_radius,
                                    float voxel_x, float voxel_y, float range_x, float range_y, float out_factor, float gaussian_overlap,
                                    const float *gt_boxes, float *heatmap, int *gt_ind, int *gt_mask, int *gt_cat, float *gt_box_encoding, int *gt_cnt){
    hipError_t err;

    dim3 blocks(batch_size);
    dim3 threads(THREADS_PER_BLOCK);
    draw_center_kernel<<<blocks, threads>>>(batch_size, max_boxes, max_objs, num_cls, H, W, code_size, min_radius,
                                            voxel_x, voxel_y, range_x, range_y, out_factor, gaussian_overlap,
                                            gt_boxes, heatmap, gt_ind, gt_mask, gt_cat, gt_box_encoding, gt_cnt);

    err = hipGetLastError();
    if (hipSuccess != err) {
        fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
        exit(-1);
    }

#ifdef DEBUG
    hipDeviceSynchronize();  // for using printf in kernel function
#endif
}
	.text
	.file	"draw_center_kernel.hip"
	.globl	_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.type	_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	44(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	36(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	28(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	24(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	20(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	8(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	4(%rsp), %r15
	movss	%xmm4, (%r15)
	movq	%rsp, %r12
	movss	%xmm5, (%r12)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	movq	%r14, 88(%rbx)
	movq	%r15, 96(%rbx)
	movq	%r12, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end0-_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ # -- Begin function _Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.type	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: # @_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm5, 20(%rsp)                 # 4-byte Spill
	movss	%xmm4, 16(%rsp)                 # 4-byte Spill
	movss	%xmm3, 12(%rsp)                 # 4-byte Spill
	movss	%xmm2, 8(%rsp)                  # 4-byte Spill
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movl	%edi, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movl	88(%rsp), %r10d
	movl	80(%rsp), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	28(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
.LBB1_2:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_4:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end1-_Z27draw_center_kernel_launcheriiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@object # @_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.section	.rodata,"a",@progbits
	.globl	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.p2align	3, 0x0
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_:
	.quad	_Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.size	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA kernel failed : %s\n"
	.size	.L.str, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_"
	.size	.L__unnamed_1, 56

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_ ; -- Begin function _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.globl	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
	.p2align	8
	.type	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_,@function
_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_: ; @_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_cmp_lt_i32 s15, s4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_32
; %bb.1:
	s_load_b256 s[16:23], s[0:1], 0x38
	v_mul_lo_u32 v11, v0, s10
	s_mul_i32 s2, s15, s5
	s_load_b256 s[24:31], s[0:1], 0x20
	s_mul_i32 s2, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[0:1], 2, v[11:12]
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s16, s2
	s_addc_u32 s3, s17, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_cmp_eq_u32 s10, 10
	s_clause 0x1
	global_load_b96 v[4:6], v[0:1], off offset:16
	global_load_b128 v[0:3], v[0:1], off
	s_cselect_b32 s12, -1, 0
	s_cmp_lg_u32 s10, 10
	s_cbranch_scc0 .LBB0_4
; %bb.2:
	s_cmp_eq_u32 s10, 8
	s_mov_b32 s5, 0
	s_cbranch_scc0 .LBB0_5
; %bb.3:
	v_or_b32_e32 v7, 7, v11
	v_mov_b32_e32 v8, 0
	s_mov_b32 s4, -1
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	s_branch .LBB0_6
.LBB0_4:
	s_mov_b32 s5, -1
.LBB0_5:
	s_mov_b32 s4, 0
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_6:                                ; %Flow360
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s13
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_8
; %bb.7:
	v_mov_b32_e32 v12, 0
	s_mov_b32 s4, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[9:10], off offset:28
	v_add_co_u32 v9, vcc_lo, v9, 36
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_8:                                ; %Flow362
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_32
; %bb.9:
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_cmp_neq_f32_e64 s2, 0, v4
	v_cmp_neq_f32_e64 s3, 0, v5
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_32
; %bb.10:
	v_subrev_f32_e32 v0, s26, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v11, null, s24, s24, v0
	v_div_scale_f32 v14, vcc_lo, v0, s24, v0
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v12
	v_mul_f32_e32 v13, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, -v11, v13, v14
	v_fmac_f32_e32 v13, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v11, v13, v14
	v_div_fmas_f32 v11, v11, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v11, s24, v0
	v_div_scale_f32 v11, null, s28, s28, v0
	v_div_scale_f32 v14, vcc_lo, v0, s28, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v14, v12
	v_fma_f32 v15, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v12
	v_fma_f32 v11, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v12, v13
	v_div_fixup_f32 v14, v11, s28, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v0, v14
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_32
; %bb.11:
	v_subrev_f32_e32 v1, s27, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v11, null, s25, s25, v1
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v12
	v_div_scale_f32 v15, vcc_lo, v1, s25, v1
	v_mul_f32_e32 v13, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v11, v13, v15
	v_fmac_f32_e32 v13, v16, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v11, v13, v15
	v_div_fmas_f32 v11, v11, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v11, s25, v1
	v_div_scale_f32 v11, null, s28, s28, v1
	v_div_scale_f32 v15, vcc_lo, v1, s28, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v15, v12
	v_fma_f32 v16, -v11, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v16, v12
	v_fma_f32 v11, -v11, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v12, v13
	v_div_fixup_f32 v15, v11, s28, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v16, v15
	v_cmp_gt_i32_e32 vcc_lo, s8, v16
	v_cmp_lt_i32_e64 s2, -1, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_32
; %bb.12:
	v_div_scale_f32 v1, null, s24, s24, v3
	global_load_b32 v9, v[9:10], off
	v_div_scale_f32 v12, vcc_lo, v3, s24, v3
	v_rcp_f32_e32 v10, v1
	v_add_f32_e64 v23, s29, -1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v1, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v10
	v_mul_f32_e32 v11, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v1, v11, v12
	v_fmac_f32_e32 v11, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v11, v12
	v_div_fmas_f32 v1, v1, v10, v11
	v_div_scale_f32 v11, null, s25, s25, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v1, s24, v3
	v_rcp_f32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v10, null, s28, s28, v1
	v_div_scale_f32 v19, vcc_lo, v1, s28, v1
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v11, v13, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v18, v13
	v_fma_f32 v17, -v10, v12, 1.0
	v_fmac_f32_e32 v12, v17, v12
	v_div_scale_f32 v17, s2, v4, s25, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v19, v12
	v_mul_f32_e32 v20, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v10, v18, v19
	v_fma_f32 v22, -v11, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v21, v12
	v_fmac_f32_e32 v20, v22, v13
	v_mul_f32_e64 v22, s29, 4.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, -v10, v18, v19
	v_fma_f32 v11, -v11, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v22, 4.0, v22
	v_div_fmas_f32 v10, v10, v12, v18
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v11, v11, v13, v20
	v_div_fixup_f32 v1, v10, s28, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v11, v11, s25, v4
	v_mul_f32_e32 v23, v23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v12, null, s28, s28, v11
	v_div_scale_f32 v18, vcc_lo, v11, s28, v11
	v_rcp_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v12, v13, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v17, v13
	v_mul_f32_e32 v17, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v12, v17, v18
	v_fmac_f32_e32 v17, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v12, v17, v18
	v_div_fmas_f32 v12, v12, v13, v17
	v_add_f32_e64 v13, s29, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v10, v12, s28, v11
	v_sub_f32_e64 v11, 1.0, s29
	v_mul_f32_e32 v12, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, v11, v12
	v_mul_f32_e32 v11, v11, v1
	v_add_f32_e32 v1, v1, v10
	v_div_scale_f32 v17, null, v13, v13, v12
	v_div_scale_f32 v20, vcc_lo, v12, v13, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, v11, v10
	v_rcp_f32_e32 v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0xc1800000, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	v_fmac_f32_e32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v20, v18
	v_fma_f32 v21, -v17, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v21, v18
	v_mul_f32_e64 v21, s29, -2.0
	v_fma_f32 v17, -v17, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v17, v17, v18, v19
	v_div_fixup_f32 v12, v17, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, 4.0, v12
	v_add_f32_e32 v18, v1, v1
	v_dual_mul_f32 v10, v23, v10 :: v_dual_mul_f32 v19, v21, v1
	v_fma_f32 v12, v1, v1, -v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v18, v18
	v_mul_f32_e32 v10, v22, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e64 s3, 0xf800000, v12
	v_mul_f32_e32 v13, 0x4f800000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v19, v19, -v10
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v11
	v_mul_f32_e32 v17, 0x4f800000, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v11, v13, vcc_lo
	v_cmp_gt_f32_e64 s2, 0xf800000, v10
	v_mul_f32_e32 v13, 0x4f800000, v12
	v_cndmask_b32_e64 v10, v10, v17, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v17, v11
	v_cndmask_b32_e64 v12, v12, v13, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v13, v10
	v_sqrt_f32_e32 v18, v12
	s_delay_alu instid0(TRANS32_DEP_3)
	v_add_nc_u32_e32 v19, -1, v17
	v_add_nc_u32_e32 v20, 1, v17
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v22, -1, v13
	v_fma_f32 v24, -v19, v17, v11
	v_add_nc_u32_e32 v25, -1, v18
	v_add_nc_u32_e32 v23, 1, v13
	v_fma_f32 v26, -v20, v17, v11
	v_fma_f32 v27, -v22, v13, v10
	v_cmp_ge_f32_e64 s4, 0, v24
	v_fma_f32 v30, -v25, v18, v12
	v_fma_f32 v28, -v23, v13, v10
	v_add_nc_u32_e32 v29, 1, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v19, s4
	v_cmp_ge_f32_e64 s4, 0, v27
	v_fma_f32 v19, -v29, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, v13, v22, s4
	v_cmp_ge_f32_e64 s4, 0, v30
	v_cndmask_b32_e64 v18, v18, v25, s4
	v_cmp_lt_f32_e64 s4, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v17, v20, s4
	v_cmp_lt_f32_e64 s4, 0, v28
	v_cndmask_b32_e64 v13, v13, v23, s4
	v_cmp_lt_f32_e64 s4, 0, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v19, 0x37800000, v17
	v_mul_f32_e32 v20, 0x37800000, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v29, s4
	v_cndmask_b32_e32 v17, v17, v19, vcc_lo
	s_clause 0x1
	s_load_b128 s[24:27], s[0:1], 0x58
	s_load_b64 s[4:5], s[0:1], 0x68
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v13, v13, v20, s2
	v_mul_f32_e32 v22, 0x37800000, v18
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
	s_mul_i32 s2, s15, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v22, s3
	v_cndmask_b32_e32 v11, v17, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	s_mov_b32 s3, 0
	v_dual_fmac_f32 v11, 2.0, v1 :: v_dual_cndmask_b32 v10, v13, v10
	v_cmp_class_f32_e64 vcc_lo, v12, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, 0.5, v11 :: v_dual_fmac_f32 v10, v21, v1
	v_cndmask_b32_e32 v12, v18, v12, vcc_lo
	v_dual_mul_f32 v10, 0.5, v10 :: v_dual_add_f32 v1, v1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0.5, v1
	v_min3_f32 v1, v1, v11, v10
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v1, v1
	v_add_nc_u32_e32 v17, -1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v18, s11, v1
	v_cmpx_lt_i32_e32 -1, v18
	s_cbranch_execz .LBB0_21
; %bb.13:                               ; %.lr.ph282
	v_lshl_or_b32 v1, v18, 1, 1
	s_mul_i32 s0, s9, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v1
	v_div_scale_f32 v10, null, 0x40c00000, 0x40c00000, v1
	v_div_scale_f32 v13, vcc_lo, v1, 0x40c00000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v10, v12, 1.0
	v_fmac_f32_e32 v12, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v13, v12
	v_fma_f32 v9, -v10, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fmac_f32_e32 v19, v9, v12
	v_mul_lo_u32 v9, s0, v17
	s_mul_i32 s0, s2, s8
	s_mul_i32 s14, s0, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f32 v10, -v10, v19, v13
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[14:15], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s0, s18, s14
	v_div_fmas_f32 v12, v10, v12, v19
	v_ashrrev_i32_e32 v10, 31, v9
	v_sub_nc_u32_e32 v19, 0, v18
	s_addc_u32 s7, s19, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v1, v12, 0x40c00000, v1
	v_lshlrev_b64 v[12:13], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v23, v19
	v_add_f32_e32 v9, v1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v22, v1, v9
.LBB0_14:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v23, v16
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	v_cmp_gt_i32_e64 s0, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB0_20
; %bb.15:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_mul_lo_u32 v12, v1, s9
	v_mul_lo_u32 v1, v23, v23
	v_mov_b32_e32 v26, v19
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, v20, v12
	v_add_co_ci_u32_e32 v25, vcc_lo, v21, v13, vcc_lo
.LBB0_16:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v0, v26
	v_cmp_lt_i32_e32 vcc_lo, -1, v9
	v_cmp_gt_i32_e64 s0, s9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s13, vcc_lo, s0
	s_and_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_19
; %bb.17:                               ;   in Loop: Header=BB0_16 Depth=2
	v_mad_u64_u32 v[12:13], null, v26, v26, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, 0, v12
	v_cvt_f32_i32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v13, null, v22, v22, v12
	v_div_scale_f32 v29, vcc_lo, v12, v22, v12
	v_rcp_f32_e32 v27, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v13, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_mul_f32_e32 v28, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v13, v28, v29
	v_fmac_f32_e32 v28, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v13, v28, v29
	v_div_fmas_f32 v13, v13, v27, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v12, v13, v22, v12
	v_mul_f32_e32 v13, 0x3fb8aa3b, v12
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v27, 0x3fb8aa3b, v12, -v13
	v_rndne_f32_e32 v28, v13
	v_fmac_f32_e32 v27, 0x32a5705f, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v28
	v_add_f32_e32 v13, v13, v27
	v_cvt_i32_f32_e32 v27, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v13, v13, v27
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v27, 0x7f800000, v13, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[9:10]
	v_cmp_ngt_f32_e32 vcc_lo, 0x33d6bf95, v27
	v_cndmask_b32_e32 v27, 0, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v24, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v25, v13, vcc_lo
	global_atomic_swap_b32 v9, v[12:13], v27, off glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v27, v9
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_16 Depth=2
	global_atomic_swap_b32 v[12:13], v9, off
.LBB0_19:                               ;   in Loop: Header=BB0_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v9, 1, v26
	v_cmp_ge_i32_e32 vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v26, v9
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_16
.LBB0_20:                               ; %Flow354
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v1, 1, v23
	v_cmp_ge_i32_e32 vcc_lo, v23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v23, v1
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_14
.LBB0_21:                               ; %Flow356
	s_or_b32 exec_lo, exec_lo, s1
	v_ashrrev_i32_e32 v12, 31, v11
	s_ashr_i32 s3, s2, 31
	v_mov_b32_e32 v18, 1
	s_lshl_b64 s[0:1], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s4, s0
	v_lshlrev_b64 v[9:10], 2, v[11:12]
	s_addc_u32 s1, s5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s0, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
	global_atomic_add_u32 v9, v[9:10], v18, off offset:-4 glc
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s6, v9
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_32
; %bb.22:
	v_div_scale_f32 v1, null, 0x40c90fdb, 0x40c90fdb, v6
	v_mul_lo_u32 v12, v17, s6
	v_div_scale_f32 v17, vcc_lo, v6, 0x40c90fdb, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v24, v1
	s_mul_i32 s0, s2, s6
	v_mad_u64_u32 v[19:20], null, v16, s9, v[0:1]
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s2, s0, s10
	s_lshl_b64 s[0:1], s[0:1], 2
	v_mul_lo_u32 v22, v12, s10
	s_add_u32 s4, s20, s0
	s_addc_u32 s5, s21, s1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v1, v24, 1.0
	s_add_u32 s6, s22, s0
	v_ashrrev_i32_e32 v10, 31, v9
	s_addc_u32 s7, s23, s1
	s_add_u32 s8, s24, s0
	v_fmac_f32_e32 v24, v13, v24
	v_ashrrev_i32_e32 v13, 31, v12
	s_addc_u32 s9, s25, s1
	s_ashr_i32 s3, s2, 31
	v_mul_lo_u32 v20, v9, s10
	v_mul_f32_e32 v25, v17, v24
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_lshl_b64 s[0:1], s[2:3], 2
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_add_u32 s2, s26, s0
	v_fma_f32 v23, -v1, v25, v17
	s_addc_u32 s1, s27, s1
	v_ashrrev_i32_e32 v21, 31, v20
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, v23, v24
	v_ashrrev_i32_e32 v23, 31, v22
	v_fma_f32 v1, -v1, v25, v17
	v_add_co_u32 v17, s0, s4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v26, s0, s5, v13, s0
	v_div_fmas_f32 v1, v1, v24, v25
	v_add_co_u32 v24, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v25, vcc_lo, s7, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v1, v1, 0x40c90fdb, v6
	v_add_co_u32 v27, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v28, vcc_lo, s9, v13, vcc_lo
	v_add_f32_e32 v1, 0.5, v1
	v_lshlrev_b64 v[12:13], 2, v[22:23]
	v_add_co_u32 v22, vcc_lo, v17, v9
	v_add_co_ci_u32_e32 v23, vcc_lo, v26, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v1, v1
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmamk_f32 v6, v1, 0xc0c90fdb, v6
	global_store_b32 v[22:23], v19, off
	v_add_co_u32 v22, vcc_lo, v24, v9
	v_lshlrev_b64 v[19:20], 2, v[20:21]
	v_add_co_ci_u32_e32 v23, vcc_lo, v25, v10, vcc_lo
	v_add_co_u32 v24, vcc_lo, v27, v9
	v_dual_sub_f32 v0, v14, v0 :: v_dual_and_b32 v13, 0x7fffffff, v6
	v_add_co_ci_u32_e32 v25, vcc_lo, v28, v10, vcc_lo
	v_cvt_f32_i32_e32 v1, v16
	v_add_co_u32 v9, vcc_lo, v12, v19
	v_add_co_ci_u32_e32 v10, vcc_lo, v17, v20, vcc_lo
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	v_lshrrev_b32_e32 v12, 23, v13
	v_sub_f32_e32 v1, v15, v1
	global_store_b32 v[22:23], v18, off
	global_store_b32 v[24:25], v11, off
	s_clause 0x1
	global_store_b128 v[9:10], v[0:3], off
	global_store_b64 v[9:10], v[4:5], off offset:16
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.23:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v2, 0
	v_and_or_b32 v11, v13, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, 0xfe5163ab, v11, 0
	v_mad_u64_u32 v[3:4], null, 0x3c439041, v11, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	v_mad_u64_u32 v[4:5], null, 0xdb629599, v11, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v5
	v_add_nc_u32_e32 v5, 0xffffff88, v12
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v11, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v5
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v1, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v3, v14, v3 :: v_dual_cndmask_b32 v0, v4, v0
	v_add_nc_u32_e32 v5, v17, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v11, v[1:2]
	v_cmp_lt_u32_e64 s0, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v16
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	v_cndmask_b32_e64 v0, v3, v0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v11, v[1:2]
	v_add_nc_u32_e32 v5, v18, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v5
	v_mov_b32_e32 v1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v11, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v2, v16, v14 :: v_dual_add_nc_u32 v1, v1, v5
	v_dual_cndmask_b32 v11, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_cndmask_b32_e32 v15, v15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 32, v1
	v_cndmask_b32_e64 v5, v11, v2, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v16, v11, s0
	v_cndmask_b32_e64 v2, v2, v15, s0
	v_cndmask_b32_e64 v15, v15, v3, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v5, s1
	v_cndmask_b32_e64 v5, v5, v2, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v15, s1
	v_cndmask_b32_e64 v0, v15, v0, s1
	v_alignbit_b32 v16, v11, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v5, v2, v14
	v_alignbit_b32 v14, v2, v0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v16, v11, vcc_lo
	v_dual_cndmask_b32 v3, v4, v5 :: v_dual_cndmask_b32 v2, v14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v4, v1, 29, 1
	v_alignbit_b32 v5, v1, v3, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v3, v3, v2, 30
	v_alignbit_b32 v0, v2, v0, 30
	v_sub_nc_u32_e32 v11, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v5, v11
	v_xor_b32_e32 v2, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v11
	v_clz_i32_u32_e32 v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v3, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v2, v3
	v_alignbit_b32 v0, v2, v0, v3
	v_lshrrev_b32_e32 v3, 29, v1
	v_alignbit_b32 v2, v5, v0, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v3, 31, v3
	v_lshrrev_b32_e32 v5, 9, v5
	v_clz_i32_u32_e32 v11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, 0.5, v3
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v16
	v_sub_nc_u32_e32 v17, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v0, v2, v0, v17
	v_or_b32_e32 v2, v5, v15
	v_add_lshl_u32 v5, v11, v14, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v0, 9, v0
	v_mul_f32_e32 v11, 0x3fc90fda, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v5
	v_fma_f32 v5, 0x3fc90fda, v2, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, 0x33000000, v0
	v_fmamk_f32 v2, v2, 0x33a22168, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v0, v3
	v_fmac_f32_e32 v2, 0x3fc90fda, v0
	v_lshrrev_b32_e32 v0, 30, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v1, v11, v2 :: v_dual_add_nc_u32 v2, v4, v0
.LBB0_24:                               ; %Flow350
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v0, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.25:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v0
	v_fma_f32 v1, 0xbfc90fda, v2, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0xb3a22168, v1
	v_fmamk_f32 v1, v2, 0xa7c234c4, v1
	v_cvt_i32_f32_e32 v2, v2
; %bb.26:                               ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, v1, v1
	s_mov_b32 s0, 0xb94c1982
	v_and_b32_e32 v11, 1, v2
	v_lshlrev_b32_e32 v2, 30, v2
	s_mov_b32 s1, 0x37d75334
	v_fmaak_f32 v4, s0, v3, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_and_b32_e32 v2, 0x80000000, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v3, v4, 0xbe2aaa9d
	v_dual_fmaak_f32 v5, s1, v3, 0xbab64f3b :: v_dual_mul_f32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v5, v3, v5, 0x3d2aabf7
	v_fmac_f32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v5, v3, v5, 0xbf000004
	v_fma_f32 v3, v3, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_xor_b32_e32 v3, v13, v6
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	v_xor3_b32 v1, v3, v2, v1
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	global_store_b32 v[9:10], v1, off offset:24
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s2
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_28
; %bb.27:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v2, 0
	v_and_or_b32 v15, v13, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, 0xfe5163ab, v15, 0
	v_mad_u64_u32 v[3:4], null, 0x3c439041, v15, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	v_mad_u64_u32 v[4:5], null, 0xdb629599, v15, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v5
	v_mad_u64_u32 v[5:6], null, 0xf534ddc0, v15, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, v6 :: v_dual_add_nc_u32 v6, 0xffffff88, v12
	v_cmp_lt_u32_e64 s0, 63, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0
	v_cndmask_b32_e64 v3, v5, v3, s0
	v_cndmask_b32_e64 v0, v4, v0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v13, v6
	v_mad_u64_u32 v[11:12], null, 0xfc2757d1, v15, v[1:2]
	v_cmp_lt_u32_e64 s1, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
	v_mov_b32_e32 v1, v12
	v_cndmask_b32_e64 v0, v3, v0, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v14, v6
	v_mad_u64_u32 v[12:13], null, 0x4e441529, v15, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v6
	v_mov_b32_e32 v1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xa2f9836e, v15, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v2, v12, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v1, v1, v6
	v_cndmask_b32_e64 v13, v13, v11, s0
	v_cndmask_b32_e64 v12, v14, v12, s0
	v_cndmask_b32_e64 v11, v11, v4, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s0, 0, v1
	v_cndmask_b32_e64 v5, v13, v2, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v12, v13, s1
	v_cndmask_b32_e64 v2, v2, v11, s1
	v_sub_nc_u32_e32 v12, 32, v1
	v_cndmask_b32_e64 v11, v11, v3, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, v5, s2
	v_cndmask_b32_e64 v5, v5, v2, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v11, s2
	v_cndmask_b32_e64 v0, v11, v0, s2
	v_alignbit_b32 v13, v6, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v5, v2, v12
	v_alignbit_b32 v11, v2, v0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v13, v6, s0
	v_cndmask_b32_e64 v3, v4, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v11, v2, s0
	v_bfe_u32 v4, v1, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v1, v3, 30
	v_alignbit_b32 v3, v3, v2, 30
	v_alignbit_b32 v0, v2, v0, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, 0, v4
	v_xor_b32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v3, v6
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v5
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, 31, v11
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v5, v5, v2, v3
	v_alignbit_b32 v0, v2, v0, v3
	v_lshrrev_b32_e32 v3, 29, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v2, v5, v0, 9
	v_lshlrev_b32_e32 v3, 31, v3
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v6, v2
	v_or_b32_e32 v12, 0.5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v6, 32, v6
	v_sub_nc_u32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v6
	v_alignbit_b32 v0, v2, v0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v5, v12
	v_add_lshl_u32 v5, v6, v11, 23
	v_lshrrev_b32_e32 v0, 9, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, 0x3fc90fda, v2
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0x3fc90fda, v2, -v6
	v_add_nc_u32_e32 v0, 0x33000000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v2, v2, 0x33a22168, v5
	v_or_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3fc90fda, v0
	v_lshrrev_b32_e32 v0, 30, v1
	v_dual_add_f32 v1, v6, v2 :: v_dual_add_nc_u32 v2, v4, v0
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr6
.LBB0_28:                               ; %Flow349
	s_and_not1_saveexec_b32 s0, s3
; %bb.29:
	v_rndne_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, 0xbfc90fda, v0, |v6|
	v_cvt_i32_f32_e32 v2, v0
	v_fmamk_f32 v1, v0, 0xb3a22168, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v1, v0, 0xa7c234c4, v1
; %bb.30:                               ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, v1, v1 :: v_dual_and_b32 v5, 1, v2
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_dual_fmaak_f32 v3, s0, v0, 0x3c0881c4 :: v_dual_lshlrev_b32 v2, 30, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 0, v5
	v_fmaak_f32 v3, v0, v3, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v4, s1, v0, 0xbab64f3b :: v_dual_mul_f32 v3, v0, v3
	v_dual_fmaak_f32 v4, v0, v4, 0x3d2aabf7 :: v_dual_fmac_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v4, v0, v4, 0xbf000004
	v_fma_f32 v0, v0, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, -v1, v0, s0
	v_and_b32_e32 v1, 0x80000000, v2
	v_xor_b32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s12
	global_store_b32 v[9:10], v0, off offset:28
	s_cbranch_vccnz .LBB0_32
; %bb.31:
	global_store_b64 v[9:10], v[7:8], off offset:32
.LBB0_32:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 112
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_, .Lfunc_end0-_Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5064
; NumSgprs: 34
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 112
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z18draw_center_kerneliiiiiiiiffffffPKfPfPiS2_S2_S1_S2_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
