#include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>

#define f_(i,j) f_[(i) + (j)*(m)]
#define Z(i,j) Z[(i) + (j)*m]

__constant__ float s_H[121];	



//B is a partition of the images with dimensions thread number + patchSize
//A our extended array with padding 

__global__ void Zcalc(float const * const A,float const * const B, float *Z,float const * const H,int patchSize,float filtsigma, int m, int n)
{	
	int x = blockDim.x * blockIdx.x + threadIdx.x; 
	int y = blockDim.y * blockIdx.y + threadIdx.y;
	int x_local=threadIdx.x;
	int y_local = threadIdx.y;
	int pad =(patchSize-1)/2;
	int dimension=blockDim.x+patchSize-1;
	extern __shared__ float Memory[];
	float *s_A=&Memory[0];//local block position in s_A
	float *g_A=&Memory[dimension*dimension];//blocks global potition in g_A
	if(x<m-2*pad && y<n-2*pad){
		s_A[x_local +y_local*dimension]=B[x_local+y_local*dimension];
		if(x_local>blockDim.x-patchSize){
			s_A[(x_local+patchSize-1) + y_local*dimension]=B[x_local+patchSize-1 +y_local*dimension];
		}
		if(y_local>blockDim.y-patchSize){
			s_A[x_local + (y_local+patchSize-1)*dimension]=B[x_local + (y_local+patchSize-1)*dimension];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			s_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=B[x_local+patchSize-1 + (y_local+patchSize-1)*dimension];
		}

		g_A[x_local +y_local*dimension]=A[x+y*m];
		if(x_local>blockDim.x-patchSize){
			g_A[(x_local+patchSize-1) + y_local*dimension]=A[x+patchSize-1 +y*m];
		}
		if(y_local>blockDim.y-patchSize){
			g_A[x_local + (y_local+patchSize-1)*dimension]=A[x + (y+patchSize-1)*m];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			g_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
		}
		__syncthreads();
	}
	if(x<m-2*pad && y<n-2*pad){
		int counter=0;
		float temp=0,FNij=0,z_local=Z(x+pad,y+pad);
		
		for(int i=pad;i<dimension-pad;i++){
			for(int j=pad;j<dimension-pad;j++){
				for(int p=-pad;p<=pad;p++){
					for(int l=-pad;l<=pad;l++){
						temp=(g_A[(x_local+pad +l)+(y_local+pad + p)*dimension]-s_A[(i+l) + (j+p)*dimension])*s_H[counter];
						FNij=FNij+temp*temp;
						counter++;
					}
				}
				z_local=z_local+expf(-(FNij/filtsigma));
				FNij=0;
				counter=0;
			}
		}
		Z[x+pad + (y+pad)*m]=z_local;
	}
}

__global__ void fCalc(float const * const A,float const * const B,float const * const Z,float const * const H,float *f_,int patchSize, float filtsigma, int m, int n){
	int x = blockDim.x * blockIdx.x + threadIdx.x; 
	int y = blockDim.y * blockIdx.y + threadIdx.y;
	int x_local=threadIdx.x;
	int y_local = threadIdx.y;
	int pad =(patchSize-1)/2;
	int dimension=blockDim.x+patchSize-1;
	extern __shared__ float Memory[];
	float *s_A=&Memory[0];//local block position in s_A
	float *g_A=&Memory[dimension*dimension];//blocks global position g_A
	if(x<m-2*pad && y<n-2*pad){
		s_A[x_local +y_local*dimension]=B[x_local+y_local*dimension];
		if(x_local>blockDim.x-patchSize){
			s_A[(x_local+patchSize-1) + y_local*dimension]=B[x_local+patchSize-1 +y_local*dimension];
		}
		if(y_local>blockDim.y-patchSize){
			s_A[x_local + (y_local+patchSize-1)*dimension]=B[x_local + (y_local+patchSize-1)*dimension];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			s_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=B[x_local+patchSize-1 + (y_local+patchSize-1)*dimension];
		}
		g_A[x_local +y_local*dimension]=A[x+y*m];
		if(x_local>blockDim.x-patchSize){
			g_A[(x_local+patchSize-1) + y_local*dimension]=A[x+patchSize-1 +y*m];
		}
		if(y_local>blockDim.y-patchSize){
			g_A[x_local + (y_local+patchSize-1)*dimension]=A[x + (y+patchSize-1)*m];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			g_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
		}
		__syncthreads();
	}
	if(x<m-2*pad && y<n-2*pad){
		int i,j,k,l,counter=0;
		float temp=0,FNij=0,Z_local=Z(x+pad,y+pad),f_local=f_(x+pad,y+pad);
		
		for(i=pad;i<dimension-pad;i++){
			for(j=pad;j<dimension-pad;j++){
				for(k=-pad;k<=pad;k++){
					for(l=-pad;l<=pad;l++){
						temp=(g_A[(x_local+pad +l)+(y_local+pad + k)*dimension]-s_A[(i+l) + (j+k)*dimension])*s_H[counter];
						FNij=FNij+temp*temp;
						counter++;
					}
				}
				f_local=f_local+(1/Z_local)*(expf(-(FNij/filtsigma)))*s_A[i+j*dimension];
				FNij=0;
				counter=0;
			}
		}
		f_[x+pad + (y+pad)*m]=f_local;
	}
}
/*
__global__ void Zcalc(float const *const A,float const * const B,float const * const H,float *Z,int patchSize,float filtSigma,int m , int n)
{ //global coordinates
  int x=blockIdx.x*blockDim.x + threadIdx.x;
  int y=blockIdx.y*blockDim.y + threadIdx.y;
  //block coordinates
  int xblock=threadIdx.x;
  int yblock=threadIdx.y;
  extern __shared__ float Memory[];
  int dimension=blockDim.x + patchSize-1;
  
  float *s_A=&Memory[0];
  float *g_A=&Memory[dimension*dimension];
  if(x<m-patchSize+1 && y<n-patchSize+1)
  {
    s_A[xblock + yblock*dimension]=B[xblock+yblock*dimension];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      s_A[xblock+patchSize-1+ yblock*dimension]=B[xblock+patchSize-1 + yblock*dimension];
    }
    __syncthreads();    
    if(yblock>blockDim.y-patchSize){
	  s_A[xblock+ (yblock+patchSize-1)*dimension ]=B[xblock+ (yblock+patchSize-1)*dimension ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    s_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=B[xblock+patchSize-1 + (yblock+patchSize-1)*dimension];
	}
	__syncthreads();
    //global coordinates of block
    g_A[xblock + yblock*dimension]=A[x + y*m];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      g_A[xblock+patchSize-1 + yblock*dimension]=A[x+patchSize-1 + y*m];
    }
    __syncthreads();
    if(yblock>blockDim.y-patchSize){
	  g_A[xblock+ (yblock+patchSize-1)*dimension ]=A[x+ (y+patchSize-1)*m ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    g_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
	}
  }
    __syncthreads();
    patchSize=(patchSize-1)/2;

    if(x<m-2*patchSize && y<n-2*patchSize)
    {
	  int i,j,k,l,counter=0;
	  float FNij=0,temp=0;
	  float Z_local=Z(x+patchSize,y+patchSize);
	  for(i=patchSize;i<dimension-patchSize;i++){
	    for(j=patchSize;j<dimension-patchSize;j++){
		  for(k=-patchSize;k<=patchSize;k++){
		    for(l=-patchSize;l<=patchSize;l++){
		      temp=(g_A[xblock+patchSize+l + (yblock+patchSize+k)*dimension]-s_A[i+l + (j+k)*dimension])*H[counter];
		      temp=temp*temp;
		      FNij=FNij+temp;
		      counter++;
		    }
		  }
		  Z_local=Z_local+expf(- (FNij/filtSigma));
		  FNij=0;
		  counter=0;
		}
	  }
	 Z(x+patchSize,y+patchSize)=Z_local;
	}
}

__global__ void fCalc(float const *const A,float const * const B,float const * const H,float const * const Z,float *f_,int patchSize,float filtSigma,int m , int n)
{ //global coordinates
  int x=blockIdx.x*blockDim.x + threadIdx.x;
  int y=blockIdx.y*blockDim.y + threadIdx.y;
  //block coordinates
  int xblock=threadIdx.x;
  int yblock=threadIdx.y;
  extern __shared__ float Memory[];
  int dimension=blockDim.x + patchSize-1;
  
  float *s_A=&Memory[0];
  float *g_A=&Memory[dimension*dimension];
   if(x<m-patchSize+1 && y<n-patchSize+1)
  {
    s_A[xblock + yblock*dimension]=B[xblock+yblock*dimension];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      s_A[xblock+patchSize-1+ yblock*dimension]=B[xblock+patchSize-1 + yblock*dimension];
    }
    __syncthreads();    
    if(yblock>blockDim.y-patchSize){
	  s_A[xblock+ (yblock+patchSize-1)*dimension ]=B[xblock+ (yblock+patchSize-1)*dimension ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    s_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=B[xblock+patchSize-1 + (yblock+patchSize-1)*dimension];
	}
	__syncthreads();
    //global coordinates of block
    g_A[xblock + yblock*dimension]=A[x + y*m];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      g_A[xblock+patchSize-1 + yblock*dimension]=A[x+patchSize-1 + y*m];
    }
    __syncthreads();
    if(yblock>blockDim.y-patchSize){
	  g_A[xblock+ (yblock+patchSize-1)*dimension ]=A[x+ (y+patchSize-1)*m ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    g_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
	}
  }
    __syncthreads();
  patchSize=(patchSize-1)/2;
  if(x<m-2*patchSize && y<n-2*patchSize)
  {
    int i,j,k,l,counter=0;
	  float FNij=0,temp=0;
	  float Z_local=Z(x+patchSize,y+patchSize),f_local=f_(x+patchSize,x+patchSize);
	  for(i=patchSize;i<dimension-patchSize;i++){
	    for(j=patchSize;j<dimension-patchSize;j++){
		  for(k=-patchSize;k<=patchSize;k++){
		    for(l=-patchSize;l<=patchSize;l++){
		      temp=(g_A[xblock+patchSize+l + (yblock+patchSize+k)*dimension]-s_A[i+l + (j+k)*dimension])*H[counter];
		      temp=temp*temp;
		      FNij=FNij+temp;
		      counter++;
		    }
		  }
		  f_local=f_local+(1/Z_local)*(expf(- (FNij/filtSigma)))*(s_A[i+(j)*dimension]);
		  FNij=0;
		  counter=0;
		}
	  }
    f_(x+patchSize,y+patchSize)=f_local;
  }
}
*/

	.file	"tmpxft_002553ad_00000000-6_SharedWithMatlab.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii
	.type	_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii, @function
_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z5ZcalcPKfS0_PfS0_ifii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii, .-_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii
	.globl	_Z5ZcalcPKfS0_PfS0_ifii
	.type	_Z5ZcalcPKfS0_PfS0_ifii, @function
_Z5ZcalcPKfS0_PfS0_ifii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z5ZcalcPKfS0_PfS0_ifiiPKfS0_PfS0_ifii
	.cfi_endproc
.LFE2052:
	.size	_Z5ZcalcPKfS0_PfS0_ifii, .-_Z5ZcalcPKfS0_PfS0_ifii
	.globl	_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii
	.type	_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii, @function
_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z5fCalcPKfS0_S0_S0_Pfifii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii, .-_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii
	.globl	_Z5fCalcPKfS0_S0_S0_Pfifii
	.type	_Z5fCalcPKfS0_S0_S0_Pfifii, @function
_Z5fCalcPKfS0_S0_S0_Pfifii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z5fCalcPKfS0_S0_S0_PfifiiPKfS0_S0_S0_Pfifii
	.cfi_endproc
.LFE2054:
	.size	_Z5fCalcPKfS0_S0_S0_Pfifii, .-_Z5fCalcPKfS0_S0_S0_Pfifii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5fCalcPKfS0_S0_S0_Pfifii"
.LC1:
	.string	"_Z5ZcalcPKfS0_PfS0_ifii"
.LC2:
	.string	"s_H"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z5fCalcPKfS0_S0_S0_Pfifii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5ZcalcPKfS0_PfS0_ifii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movl	$484, %r9d
	leaq	_ZL3s_H(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL3s_H
	.comm	_ZL3s_H,484,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>

#define f_(i,j) f_[(i) + (j)*(m)]
#define Z(i,j) Z[(i) + (j)*m]

__constant__ float s_H[121];	



//B is a partition of the images with dimensions thread number + patchSize
//A our extended array with padding 

__global__ void Zcalc(float const * const A,float const * const B, float *Z,float const * const H,int patchSize,float filtsigma, int m, int n)
{	
	int x = blockDim.x * blockIdx.x + threadIdx.x; 
	int y = blockDim.y * blockIdx.y + threadIdx.y;
	int x_local=threadIdx.x;
	int y_local = threadIdx.y;
	int pad =(patchSize-1)/2;
	int dimension=blockDim.x+patchSize-1;
	extern __shared__ float Memory[];
	float *s_A=&Memory[0];//local block position in s_A
	float *g_A=&Memory[dimension*dimension];//blocks global potition in g_A
	if(x<m-2*pad && y<n-2*pad){
		s_A[x_local +y_local*dimension]=B[x_local+y_local*dimension];
		if(x_local>blockDim.x-patchSize){
			s_A[(x_local+patchSize-1) + y_local*dimension]=B[x_local+patchSize-1 +y_local*dimension];
		}
		if(y_local>blockDim.y-patchSize){
			s_A[x_local + (y_local+patchSize-1)*dimension]=B[x_local + (y_local+patchSize-1)*dimension];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			s_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=B[x_local+patchSize-1 + (y_local+patchSize-1)*dimension];
		}

		g_A[x_local +y_local*dimension]=A[x+y*m];
		if(x_local>blockDim.x-patchSize){
			g_A[(x_local+patchSize-1) + y_local*dimension]=A[x+patchSize-1 +y*m];
		}
		if(y_local>blockDim.y-patchSize){
			g_A[x_local + (y_local+patchSize-1)*dimension]=A[x + (y+patchSize-1)*m];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			g_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
		}
		__syncthreads();
	}
	if(x<m-2*pad && y<n-2*pad){
		int counter=0;
		float temp=0,FNij=0,z_local=Z(x+pad,y+pad);
		
		for(int i=pad;i<dimension-pad;i++){
			for(int j=pad;j<dimension-pad;j++){
				for(int p=-pad;p<=pad;p++){
					for(int l=-pad;l<=pad;l++){
						temp=(g_A[(x_local+pad +l)+(y_local+pad + p)*dimension]-s_A[(i+l) + (j+p)*dimension])*s_H[counter];
						FNij=FNij+temp*temp;
						counter++;
					}
				}
				z_local=z_local+expf(-(FNij/filtsigma));
				FNij=0;
				counter=0;
			}
		}
		Z[x+pad + (y+pad)*m]=z_local;
	}
}

__global__ void fCalc(float const * const A,float const * const B,float const * const Z,float const * const H,float *f_,int patchSize, float filtsigma, int m, int n){
	int x = blockDim.x * blockIdx.x + threadIdx.x; 
	int y = blockDim.y * blockIdx.y + threadIdx.y;
	int x_local=threadIdx.x;
	int y_local = threadIdx.y;
	int pad =(patchSize-1)/2;
	int dimension=blockDim.x+patchSize-1;
	extern __shared__ float Memory[];
	float *s_A=&Memory[0];//local block position in s_A
	float *g_A=&Memory[dimension*dimension];//blocks global position g_A
	if(x<m-2*pad && y<n-2*pad){
		s_A[x_local +y_local*dimension]=B[x_local+y_local*dimension];
		if(x_local>blockDim.x-patchSize){
			s_A[(x_local+patchSize-1) + y_local*dimension]=B[x_local+patchSize-1 +y_local*dimension];
		}
		if(y_local>blockDim.y-patchSize){
			s_A[x_local + (y_local+patchSize-1)*dimension]=B[x_local + (y_local+patchSize-1)*dimension];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			s_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=B[x_local+patchSize-1 + (y_local+patchSize-1)*dimension];
		}
		g_A[x_local +y_local*dimension]=A[x+y*m];
		if(x_local>blockDim.x-patchSize){
			g_A[(x_local+patchSize-1) + y_local*dimension]=A[x+patchSize-1 +y*m];
		}
		if(y_local>blockDim.y-patchSize){
			g_A[x_local + (y_local+patchSize-1)*dimension]=A[x + (y+patchSize-1)*m];
		}
		if(x_local>blockDim.x-patchSize && y_local>blockDim.y-patchSize ){
			g_A[x_local+patchSize-1 + (y_local+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
		}
		__syncthreads();
	}
	if(x<m-2*pad && y<n-2*pad){
		int i,j,k,l,counter=0;
		float temp=0,FNij=0,Z_local=Z(x+pad,y+pad),f_local=f_(x+pad,y+pad);
		
		for(i=pad;i<dimension-pad;i++){
			for(j=pad;j<dimension-pad;j++){
				for(k=-pad;k<=pad;k++){
					for(l=-pad;l<=pad;l++){
						temp=(g_A[(x_local+pad +l)+(y_local+pad + k)*dimension]-s_A[(i+l) + (j+k)*dimension])*s_H[counter];
						FNij=FNij+temp*temp;
						counter++;
					}
				}
				f_local=f_local+(1/Z_local)*(expf(-(FNij/filtsigma)))*s_A[i+j*dimension];
				FNij=0;
				counter=0;
			}
		}
		f_[x+pad + (y+pad)*m]=f_local;
	}
}
/*
__global__ void Zcalc(float const *const A,float const * const B,float const * const H,float *Z,int patchSize,float filtSigma,int m , int n)
{ //global coordinates
  int x=blockIdx.x*blockDim.x + threadIdx.x;
  int y=blockIdx.y*blockDim.y + threadIdx.y;
  //block coordinates
  int xblock=threadIdx.x;
  int yblock=threadIdx.y;
  extern __shared__ float Memory[];
  int dimension=blockDim.x + patchSize-1;
  
  float *s_A=&Memory[0];
  float *g_A=&Memory[dimension*dimension];
  if(x<m-patchSize+1 && y<n-patchSize+1)
  {
    s_A[xblock + yblock*dimension]=B[xblock+yblock*dimension];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      s_A[xblock+patchSize-1+ yblock*dimension]=B[xblock+patchSize-1 + yblock*dimension];
    }
    __syncthreads();    
    if(yblock>blockDim.y-patchSize){
	  s_A[xblock+ (yblock+patchSize-1)*dimension ]=B[xblock+ (yblock+patchSize-1)*dimension ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    s_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=B[xblock+patchSize-1 + (yblock+patchSize-1)*dimension];
	}
	__syncthreads();
    //global coordinates of block
    g_A[xblock + yblock*dimension]=A[x + y*m];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      g_A[xblock+patchSize-1 + yblock*dimension]=A[x+patchSize-1 + y*m];
    }
    __syncthreads();
    if(yblock>blockDim.y-patchSize){
	  g_A[xblock+ (yblock+patchSize-1)*dimension ]=A[x+ (y+patchSize-1)*m ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    g_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
	}
  }
    __syncthreads();
    patchSize=(patchSize-1)/2;

    if(x<m-2*patchSize && y<n-2*patchSize)
    {
	  int i,j,k,l,counter=0;
	  float FNij=0,temp=0;
	  float Z_local=Z(x+patchSize,y+patchSize);
	  for(i=patchSize;i<dimension-patchSize;i++){
	    for(j=patchSize;j<dimension-patchSize;j++){
		  for(k=-patchSize;k<=patchSize;k++){
		    for(l=-patchSize;l<=patchSize;l++){
		      temp=(g_A[xblock+patchSize+l + (yblock+patchSize+k)*dimension]-s_A[i+l + (j+k)*dimension])*H[counter];
		      temp=temp*temp;
		      FNij=FNij+temp;
		      counter++;
		    }
		  }
		  Z_local=Z_local+expf(- (FNij/filtSigma));
		  FNij=0;
		  counter=0;
		}
	  }
	 Z(x+patchSize,y+patchSize)=Z_local;
	}
}

__global__ void fCalc(float const *const A,float const * const B,float const * const H,float const * const Z,float *f_,int patchSize,float filtSigma,int m , int n)
{ //global coordinates
  int x=blockIdx.x*blockDim.x + threadIdx.x;
  int y=blockIdx.y*blockDim.y + threadIdx.y;
  //block coordinates
  int xblock=threadIdx.x;
  int yblock=threadIdx.y;
  extern __shared__ float Memory[];
  int dimension=blockDim.x + patchSize-1;
  
  float *s_A=&Memory[0];
  float *g_A=&Memory[dimension*dimension];
   if(x<m-patchSize+1 && y<n-patchSize+1)
  {
    s_A[xblock + yblock*dimension]=B[xblock+yblock*dimension];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      s_A[xblock+patchSize-1+ yblock*dimension]=B[xblock+patchSize-1 + yblock*dimension];
    }
    __syncthreads();    
    if(yblock>blockDim.y-patchSize){
	  s_A[xblock+ (yblock+patchSize-1)*dimension ]=B[xblock+ (yblock+patchSize-1)*dimension ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    s_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=B[xblock+patchSize-1 + (yblock+patchSize-1)*dimension];
	}
	__syncthreads();
    //global coordinates of block
    g_A[xblock + yblock*dimension]=A[x + y*m];
    __syncthreads();
    if(xblock>blockDim.x-patchSize){
      g_A[xblock+patchSize-1 + yblock*dimension]=A[x+patchSize-1 + y*m];
    }
    __syncthreads();
    if(yblock>blockDim.y-patchSize){
	  g_A[xblock+ (yblock+patchSize-1)*dimension ]=A[x+ (y+patchSize-1)*m ];
	}
	__syncthreads();
    if(xblock>blockDim.x-patchSize && yblock>blockDim.y-patchSize){
	    g_A[xblock+patchSize-1 + (yblock+patchSize-1)*dimension]=A[x+patchSize-1 + (y+patchSize-1)*m];
	}
  }
    __syncthreads();
  patchSize=(patchSize-1)/2;
  if(x<m-2*patchSize && y<n-2*patchSize)
  {
    int i,j,k,l,counter=0;
	  float FNij=0,temp=0;
	  float Z_local=Z(x+patchSize,y+patchSize),f_local=f_(x+patchSize,x+patchSize);
	  for(i=patchSize;i<dimension-patchSize;i++){
	    for(j=patchSize;j<dimension-patchSize;j++){
		  for(k=-patchSize;k<=patchSize;k++){
		    for(l=-patchSize;l<=patchSize;l++){
		      temp=(g_A[xblock+patchSize+l + (yblock+patchSize+k)*dimension]-s_A[i+l + (j+k)*dimension])*H[counter];
		      temp=temp*temp;
		      FNij=FNij+temp;
		      counter++;
		    }
		  }
		  f_local=f_local+(1/Z_local)*(expf(- (FNij/filtSigma)))*(s_A[i+(j)*dimension]);
		  FNij=0;
		  counter=0;
		}
	  }
    f_(x+patchSize,y+patchSize)=f_local;
  }
}
*/

	.text
	.file	"SharedWithMatlab.hip"
	.globl	_Z20__device_stub__ZcalcPKfS0_PfS0_ifii # -- Begin function _Z20__device_stub__ZcalcPKfS0_PfS0_ifii
	.type	_Z20__device_stub__ZcalcPKfS0_PfS0_ifii,@function
_Z20__device_stub__ZcalcPKfS0_PfS0_ifii: # @_Z20__device_stub__ZcalcPKfS0_PfS0_ifii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	4(%rsp), %r10
	movl	%r9d, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5ZcalcPKfS0_PfS0_ifii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__ZcalcPKfS0_PfS0_ifii, .Lfunc_end0-_Z20__device_stub__ZcalcPKfS0_PfS0_ifii
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii # -- Begin function _Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii
	.type	_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii,@function
_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii: # @_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	movq	%rsp, %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5fCalcPKfS0_S0_S0_Pfifii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii, .Lfunc_end1-_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5ZcalcPKfS0_PfS0_ifii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5fCalcPKfS0_S0_S0_Pfifii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$s_H, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$484, %r9d                      # imm = 0x1E4
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	s_H,@object                     # @s_H
	.local	s_H
	.comm	s_H,484,16
	.type	_Z5ZcalcPKfS0_PfS0_ifii,@object # @_Z5ZcalcPKfS0_PfS0_ifii
	.section	.rodata,"a",@progbits
	.globl	_Z5ZcalcPKfS0_PfS0_ifii
	.p2align	3, 0x0
_Z5ZcalcPKfS0_PfS0_ifii:
	.quad	_Z20__device_stub__ZcalcPKfS0_PfS0_ifii
	.size	_Z5ZcalcPKfS0_PfS0_ifii, 8

	.type	_Z5fCalcPKfS0_S0_S0_Pfifii,@object # @_Z5fCalcPKfS0_S0_S0_Pfifii
	.globl	_Z5fCalcPKfS0_S0_S0_Pfifii
	.p2align	3, 0x0
_Z5fCalcPKfS0_S0_S0_Pfifii:
	.quad	_Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii
	.size	_Z5fCalcPKfS0_S0_S0_Pfifii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5ZcalcPKfS0_PfS0_ifii"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z5fCalcPKfS0_S0_S0_Pfifii"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"s_H"
	.size	.L__unnamed_3, 4

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__ZcalcPKfS0_PfS0_ifii
	.addrsig_sym _Z20__device_stub__fCalcPKfS0_S0_S0_Pfifii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym s_H
	.addrsig_sym _Z5ZcalcPKfS0_PfS0_ifii
	.addrsig_sym _Z5fCalcPKfS0_S0_S0_Pfifii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5ZcalcPKfS0_PfS0_ifii ; -- Begin function _Z5ZcalcPKfS0_PfS0_ifii
	.globl	_Z5ZcalcPKfS0_PfS0_ifii
	.p2align	8
	.type	_Z5ZcalcPKfS0_PfS0_ifii,@function
_Z5ZcalcPKfS0_PfS0_ifii:                ; @_Z5ZcalcPKfS0_PfS0_ifii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x20
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s2, 0xffff
	s_lshr_b32 s3, s2, 16
	v_mad_u64_u32 v[1:2], null, s14, s16, v[4:5]
	s_add_i32 s17, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s17, 31
	s_add_i32 s14, s17, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s2, s14, -2
	v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
	s_sub_i32 s8, s6, s2
	s_sub_i32 s2, s7, s2
	v_cmp_gt_i32_e32 vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_25
; %bb.1:
	s_add_i32 s7, s17, s16
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_mul_lo_u32 v3, s7, v0
	s_sub_i32 s0, s16, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e64 s1, s0, v4
	v_add_nc_u32_e32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, s0, v4
	global_load_b32 v7, v[6:7], off
	v_lshl_add_u32 v6, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_add_nc_u32_e32 v7, s17, v5
	v_lshl_add_u32 v6, s17, 2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s10, v7
	v_add_co_ci_u32_e64 v8, s0, s11, v8, s0
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s2
	s_sub_i32 s0, s3, s4
	v_add_nc_u32_e32 v6, s17, v0
	v_cmp_ge_u32_e64 s2, s0, v0
	v_cmp_lt_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_mad_u64_u32 v[7:8], null, s7, v6, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[8:9], 2, v[7:8]
	v_lshl_add_u32 v7, v7, 2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s3, s10, v8
	v_add_co_ci_u32_e64 v9, s3, s11, v9, s3
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v8
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s15
	v_mul_lo_u32 v8, s7, v6
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s1, -1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, s17, v4, v8
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	v_lshl_add_u32 v6, v6, 2, 0
	v_add_co_u32 v9, s1, s10, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s1, s11, v10, s1
	global_load_b32 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s3
	v_mad_u64_u32 v[6:7], null, v2, s6, v[1:2]
	v_lshlrev_b32_e32 v4, 2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s1, s8, v9
	v_add_co_ci_u32_e64 v10, s1, s9, v10, s1
	s_mul_i32 s1, s7, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s1, s1, 2
	global_load_b32 v7, v[9:10], off
	s_add_i32 s1, s1, 0
	v_lshl_add_u32 v5, v5, 2, s1
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v7
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_add_nc_u32_e32 v5, s17, v6
	s_lshl_b32 s10, s4, 2
	v_lshlrev_b32_e32 v3, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	v_add3_u32 v6, s10, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v3, v6, v3, -4
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v3, s17, v2
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v3, s6, v[1:2]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	v_lshlrev_b32_e32 v6, 2, v8
	v_add3_u32 v6, s1, v4, v6
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s10, s14, 1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_mul_lo_u32 v3, v3, s6
	s_lshl_b32 s2, s4, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, s17, v1, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v3, v[5:6], off
	v_add3_u32 v5, s2, s1, v4
	v_lshlrev_b32_e32 v6, 2, v8
	v_add3_u32 v5, v5, v6, -4
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v2, s10, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mul_lo_u32 v2, v2, s6
	s_sub_i32 s6, s7, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_ge_i32 s10, s6
	v_add3_u32 v1, v1, s10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_cbranch_scc1 .LBB0_24
; %bb.14:                               ; %.preheader211.lr.ph
	v_add3_u32 v0, s16, s4, v0
	s_sub_i32 s8, 0, s10
	s_cmp_gt_i32 s4, -1
	s_mov_b32 s11, 0
	s_cselect_b32 s4, -1, 0
	v_lshl_add_u32 v0, v0, 2, -4
	s_abs_i32 s9, s10
	s_mov_b32 s13, s10
	s_add_i32 s12, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_i32 s12, s12, 1
	v_mul_lo_u32 v0, s7, v0
	s_lshl_b32 s7, s7, 2
	v_add3_u32 v0, v0, v4, 0
.LBB0_15:                               ; %.preheader211
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;         Child Loop BB0_19 Depth 4
	s_mov_b32 s14, s11
	s_mov_b32 s15, s10
.LBB0_16:                               ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_18 Depth 3
                                        ;         Child Loop BB0_19 Depth 4
	v_mov_b32_e32 v4, 0
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_22
; %bb.17:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_16 Depth=2
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, v0
	s_mov_b32 s0, 0
	s_mov_b32 s16, s14
	s_mov_b32 s17, s8
.LBB0_18:                               ; %.preheader
                                        ;   Parent Loop BB0_15 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_19 Depth 4
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, s_H@rel32@lo+4
	s_addc_u32 s3, s3, s_H@rel32@hi+12
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v6, v5
	s_lshl_b64 s[18:19], s[0:1], 2
	s_mov_b32 s1, s16
	s_add_u32 s2, s18, s2
	s_addc_u32 s3, s19, s3
	s_mov_b32 s18, s12
.LBB0_19:                               ;   Parent Loop BB0_15 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ;       Parent Loop BB0_18 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v7, s1
	s_add_i32 s18, s18, -1
	s_add_i32 s1, s1, 4
	ds_load_b32 v8, v6
	ds_load_b32 v7, v7
	v_add_nc_u32_e32 v6, 4, v6
	s_load_b32 s19, s[2:3], 0x0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s18, 0
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, s19, v7
	v_fmac_f32_e32 v4, v7, v7
	s_cbranch_scc0 .LBB0_19
; %bb.20:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_18 Depth=3
	v_add_nc_u32_e32 v5, s7, v5
	s_add_i32 s0, s12, s0
	s_add_i32 s1, s17, 1
	s_add_i32 s16, s16, s7
	s_cmp_eq_u32 s17, s9
	s_cbranch_scc1 .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_18 Depth=3
	s_mov_b32 s17, s1
	s_branch .LBB0_18
.LBB0_22:                               ; %._crit_edge223
                                        ;   in Loop: Header=BB0_16 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v5, null, s5, s5, -v4
	v_div_scale_f32 v8, vcc_lo, -v4, s5, -v4
	s_add_i32 s15, s15, 1
	v_rcp_f32_e32 v6, v5
	s_add_i32 s14, s14, s7
	s_cmp_ge_i32 s15, s6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v5, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_mul_f32_e32 v7, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v5, v7, v8
	v_fmac_f32_e32 v7, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v7, v8
	v_div_fmas_f32 v5, v5, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v5, s5, -v4
	v_mul_f32_e32 v5, 0x3fb8aa3b, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3fb8aa3b, v4, -v5
	v_rndne_f32_e32 v7, v5
	v_dual_fmac_f32 v6, 0x32a5705f, v4 :: v_dual_sub_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v6
	v_cvt_i32_f32_e32 v6, v7
	v_exp_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	s_cbranch_scc0 .LBB0_16
; %bb.23:                               ; %._crit_edge228
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_add_i32 s13, s13, 1
	s_add_i32 s11, s11, 4
	s_cmp_ge_i32 s13, s6
	s_cbranch_scc0 .LBB0_15
.LBB0_24:                               ; %._crit_edge232
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v3, off
.LBB0_25:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5ZcalcPKfS0_PfS0_ifii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5ZcalcPKfS0_PfS0_ifii, .Lfunc_end0-_Z5ZcalcPKfS0_PfS0_ifii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1568
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z5fCalcPKfS0_S0_S0_Pfifii ; -- Begin function _Z5fCalcPKfS0_S0_S0_Pfifii
	.globl	_Z5fCalcPKfS0_S0_S0_Pfifii
	.p2align	8
	.type	_Z5fCalcPKfS0_S0_S0_Pfifii,@function
_Z5fCalcPKfS0_S0_S0_Pfifii:             ; @_Z5fCalcPKfS0_S0_S0_Pfifii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[8:11], s[0:1], 0x28
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s2, 0xffff
	s_lshr_b32 s4, s2, 16
	v_mad_u64_u32 v[1:2], null, s14, s16, v[4:5]
	s_add_i32 s17, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s17, 31
	s_add_i32 s18, s17, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s2, s18, -2
	v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
	s_sub_i32 s3, s10, s2
	s_sub_i32 s2, s11, s2
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_25
; %bb.1:
	s_add_i32 s11, s17, s16
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	v_mul_lo_u32 v3, s11, v0
	s_sub_i32 s2, s16, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e64 s3, s2, v4
	v_add_nc_u32_e32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, s2, v4
	global_load_b32 v7, v[6:7], off
	v_lshl_add_u32 v6, v5, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_add_nc_u32_e32 v7, s17, v5
	v_lshl_add_u32 v6, s17, 2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s2, s14, v7
	v_add_co_ci_u32_e64 v8, s2, s15, v8, s2
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s5
	s_sub_i32 s2, s4, s8
	v_add_nc_u32_e32 v6, s17, v0
	v_cmp_ge_u32_e64 s4, s2, v0
	v_cmp_lt_u32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s19, s2
	s_cbranch_execz .LBB1_5
; %bb.4:
	v_mad_u64_u32 v[7:8], null, s11, v6, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[8:9], 2, v[7:8]
	v_lshl_add_u32 v7, v7, 2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s5, s14, v8
	v_add_co_ci_u32_e64 v9, s5, s15, v9, s5
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v8
.LBB1_5:
	s_or_b32 exec_lo, exec_lo, s19
	v_mul_lo_u32 v8, s11, v6
	s_or_b32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s3, -1
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, s17, v4, v8
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	v_lshl_add_u32 v6, v6, 2, 0
	v_add_co_u32 v9, s3, s14, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s3, s15, v10, s3
	global_load_b32 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v7
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s5
	v_mad_u64_u32 v[6:7], null, v2, s10, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	v_lshlrev_b32_e32 v7, 2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s3, s12, v9
	v_add_co_ci_u32_e64 v10, s3, s13, v10, s3
	s_mul_i32 s3, s11, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 2
	global_load_b32 v9, v[9:10], off
	s_add_i32 s3, s3, 0
	v_lshl_add_u32 v5, v5, 2, s3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v9
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_add_nc_u32_e32 v4, s17, v6
	s_lshl_b32 s14, s8, 2
	v_lshlrev_b32_e32 v3, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_add3_u32 v5, s14, s3, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v3, v5, v3, -4
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
.LBB1_9:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v3, s17, v2
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB1_11
; %bb.10:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s10, v[1:2]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_lshlrev_b32_e32 v5, 2, v8
	v_add3_u32 v5, s3, v7, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
.LBB1_11:
	s_or_b32 exec_lo, exec_lo, s5
	s_ashr_i32 s2, s18, 1
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB1_13
; %bb.12:
	v_mul_lo_u32 v3, v3, s10
	s_lshl_b32 s4, s8, 2
	v_lshlrev_b32_e32 v5, 2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, s17, v1, v3
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_add3_u32 v4, s4, s3, v7
	v_add3_u32 v4, v4, v5, -4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB1_13:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v2, s2, v2
	s_load_b64 s[0:1], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mul_lo_u32 v2, v2, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v1, s2, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
	s_sub_i32 s0, s11, s2
	s_cmp_ge_i32 s2, s0
	global_load_b32 v5, v[1:2], off
	s_cbranch_scc1 .LBB1_24
; %bb.14:                               ; %.preheader223.lr.ph
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_add3_u32 v0, s16, s8, v0
	s_sub_i32 s1, 0, s2
	s_cmp_gt_i32 s8, -1
	global_load_b32 v3, v[3:4], off
	s_cselect_b32 s3, -1, 0
	v_lshl_add_u32 v0, v0, 2, -4
	s_abs_i32 s4, s2
	s_mov_b32 s5, 0
	s_add_i32 s6, s2, s4
	s_lshl_b32 s7, s11, 2
	v_mul_lo_u32 v0, s11, v0
	s_add_i32 s6, s6, 1
	s_mov_b32 s8, s2
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, s_H@rel32@lo+4
	s_addc_u32 s23, s23, s_H@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v0, v7, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v3, v3, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v3, 1.0
	v_rcp_f32_e32 v6, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v6
	v_mul_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v4, v8, v9
	v_fmac_f32_e32 v8, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v8, v9
	v_div_fmas_f32 v4, v4, v6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v3, v4, v3, 1.0
.LBB1_15:                               ; %.preheader223
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_16 Depth 2
                                        ;       Child Loop BB1_18 Depth 3
                                        ;         Child Loop BB1_19 Depth 4
	s_lshl_b32 s12, s8, 2
	s_mov_b32 s10, s5
	s_add_i32 s12, s12, 0
	s_mov_b32 s13, s2
.LBB1_16:                               ;   Parent Loop BB1_15 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_18 Depth 3
                                        ;         Child Loop BB1_19 Depth 4
	v_mov_b32_e32 v4, 0
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_22
; %bb.17:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB1_16 Depth=2
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v6, v0
	s_mov_b32 s14, 0
	s_mov_b32 s15, s10
	s_mov_b32 s16, s1
.LBB1_18:                               ; %.preheader
                                        ;   Parent Loop BB1_15 Depth=1
                                        ;     Parent Loop BB1_16 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_19 Depth 4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v6
	s_mov_b32 s17, s15
	s_mov_b32 s18, 0
.LBB1_19:                               ;   Parent Loop BB1_15 Depth=1
                                        ;     Parent Loop BB1_16 Depth=2
                                        ;       Parent Loop BB1_18 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s20, s14, s18
	ds_load_b32 v8, v7
	s_ashr_i32 s21, s20, 31
	v_add_nc_u32_e32 v7, 4, v7
	s_lshl_b64 s[20:21], s[20:21], 2
	s_add_u32 s20, s20, s22
	s_addc_u32 s21, s21, s23
	s_add_i32 s18, s18, 1
	s_load_b32 s19, s[20:21], 0x0
	v_mov_b32_e32 v9, s17
	s_add_i32 s17, s17, 4
	s_cmp_lg_u32 s6, s18
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, s19, v8
	v_fmac_f32_e32 v4, v8, v8
	s_cbranch_scc1 .LBB1_19
; %bb.20:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_18 Depth=3
	v_add_nc_u32_e32 v6, s7, v6
	s_add_i32 s17, s16, 1
	s_add_i32 s14, s14, s6
	s_add_i32 s15, s15, s7
	s_cmp_lg_u32 s16, s4
	s_cbranch_scc0 .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_18 Depth=3
	s_mov_b32 s16, s17
	s_branch .LBB1_18
.LBB1_22:                               ; %._crit_edge235
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, s9, s9, -v4
	v_div_scale_f32 v9, vcc_lo, -v4, s9, -v4
	s_mul_i32 s14, s13, s11
	v_rcp_f32_e32 v7, v6
	s_lshl_b32 s14, s14, 2
	s_add_i32 s13, s13, 1
	s_add_i32 s14, s12, s14
	s_add_i32 s10, s10, s7
	s_cmp_lt_i32 s13, s0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v7
	v_mul_f32_e32 v8, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v6, v8, v9
	v_fmac_f32_e32 v8, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v6, v8, v9
	v_div_fmas_f32 v6, v6, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v6, s9, -v4
	v_mul_f32_e32 v6, 0x3fb8aa3b, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3fb8aa3b, v4, -v6
	v_rndne_f32_e32 v8, v6
	v_fmac_f32_e32 v7, 0x32a5705f, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_cvt_i32_f32_e32 v8, v8
	v_dual_add_f32 v6, v6, v7 :: v_dual_mov_b32 v7, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v6, v6
	ds_load_b32 v7, v7
	v_ldexp_f32 v6, v6, v8
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, 0x7f800000, v6, vcc_lo
	v_mul_f32_e32 v4, v3, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v5, v4, v7
	s_cbranch_scc1 .LBB1_16
; %bb.23:                               ; %._crit_edge240
                                        ;   in Loop: Header=BB1_15 Depth=1
	s_add_i32 s8, s8, 1
	s_add_i32 s5, s5, 4
	s_cmp_lt_i32 s8, s0
	s_cbranch_scc1 .LBB1_15
.LBB1_24:                               ; %._crit_edge244
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v5, off
.LBB1_25:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5fCalcPKfS0_S0_S0_Pfifii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z5fCalcPKfS0_S0_S0_Pfifii, .Lfunc_end1-_Z5fCalcPKfS0_S0_S0_Pfifii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1732
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	s_H                     ; @s_H
	.type	s_H,@object
	.section	.bss,"aw",@nobits
	.globl	s_H
	.p2align	4, 0x0
s_H:
	.zero	484
	.size	s_H, 484

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym s_H
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5ZcalcPKfS0_PfS0_ifii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z5ZcalcPKfS0_PfS0_ifii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5fCalcPKfS0_S0_S0_Pfifii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z5fCalcPKfS0_S0_S0_Pfifii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
