#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__ void add1(int *a, int *b, int *c){
	int idx = blockIdx.x;
	c[idx] = a[idx] + b[idx];
}

__global__ void add2(int* a, int* b, int* c){
	int idx = threadIdx.x;
	c[idx] = a[idx] + b[idx];
}

__global__ void add3(int* a, int* b, int* c){
	int idx = blockIdx.x*blockDim.x + threadIdx.x;
	c[idx] = a[idx] + b[idx];
}

int main(){
	int N; //number of elements
	int *d_a, *d_b, *d_c; //Device copies
	int size = sizeof(int); //size var
	int *A, *B, *C; //vectors

	printf("Enter number of elements: ");
	scanf("%d",&N);

	A = (int*)malloc(sizeof(int)*N);
	B = (int*)malloc(sizeof(int)*N);
	C = (int*)malloc(sizeof(int)*N);

	printf("Enter elements a <space> b:\n");
	for(int i=0; i<N; i++){
		scanf("%d %d",&A[i],&B[i]);
	}

	//Allocate space for device copies of a,b,c
	cudaMalloc((void**)&d_a,size*N);
	cudaMalloc((void**)&d_b,size*N);
	cudaMalloc((void**)&d_c,size*N);

	//setup input values
	cudaMemcpy(d_a,A,size*N,cudaMemcpyHostToDevice);
	cudaMemcpy(d_b,B,size*N,cudaMemcpyHostToDevice);

	printf("\n// LAUNCHING ADD1 //\n");
	//launch add kernel on GPU
	dim3 Blocks1(N,1,1);
	dim3 Threads1(1,1,1);
	add1<<<Blocks1,Threads1>>>(d_a,d_b,d_c);

	//copy result back to host
	cudaMemcpy(C,d_c,size*N,cudaMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);



	printf("\n// LAUNCHING ADD2 //\n");
	//launch add kernel on GPU
	dim3 Blocks2(1,1,1);
	dim3 Threads2(N,1,1);
	add1<<<Blocks2,Threads2>>>(d_a,d_b,d_c);

	//copy result back to host
	cudaMemcpy(C,d_c,size*N,cudaMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);


	printf("\n// LAUNCHING ADD3 //\n");
	//launch add kernel on GPU
	dim3 Blocks3(ceilf(N/256),1,1);
	dim3 Threads3(256,1,1);
	add1<<<Blocks3,Threads3>>>(d_a,d_b,d_c);

	//copy result back to host
	cudaMemcpy(C,d_c,size*N,cudaMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);


	//Cleanup
	cudaFree(d_a);
	cudaFree(d_b);
	cudaFree(d_c);
	return 0;

}

	.file	"tmpxft_002a32df_00000000-6_CUDA_VectorAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z4add1PiS_S_PiS_S_
	.type	_Z27__device_stub__Z4add1PiS_S_PiS_S_, @function
_Z27__device_stub__Z4add1PiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4add1PiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z27__device_stub__Z4add1PiS_S_PiS_S_, .-_Z27__device_stub__Z4add1PiS_S_PiS_S_
	.globl	_Z4add1PiS_S_
	.type	_Z4add1PiS_S_, @function
_Z4add1PiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4add1PiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z4add1PiS_S_, .-_Z4add1PiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter number of elements: "
.LC1:
	.string	"%d"
.LC2:
	.string	"Enter elements a <space> b:\n"
.LC3:
	.string	"%d %d"
.LC4:
	.string	"\n// LAUNCHING ADD1 //\n"
.LC5:
	.string	"Result:\n"
.LC6:
	.string	"%d "
.LC7:
	.string	"\n// LAUNCHING ADD2 //\n"
.LC8:
	.string	"\n// LAUNCHING ADD3 //\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	4(%rsp), %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	4(%rsp), %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%r12, %r15
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rbp, %r14
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	movl	4(%rsp), %esi
	cmpl	%r13d, %esi
	jle	.L22
	movq	%r14, %rdx
	movq	%r15, %rsi
	leaq	.LC3(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	incl	%r13d
	addq	$4, %r15
	addq	$4, %r14
	jmp	.L9
.L22:
	sall	$2, %esi
	leaq	8(%rsp), %rdi
	movslq	%esi, %rsi
	call	cudaMalloc@PLT
	movl	4(%rsp), %eax
	leaq	16(%rsp), %rdi
	leal	0(,%rax,4), %esi
	movslq	%esi, %rsi
	call	cudaMalloc@PLT
	movl	4(%rsp), %eax
	leaq	24(%rsp), %rdi
	leal	0(,%rax,4), %esi
	movslq	%esi, %rsi
	call	cudaMalloc@PLT
	movl	4(%rsp), %eax
	movq	8(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	leal	0(,%rax,4), %edx
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	movl	4(%rsp), %eax
	movq	16(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	leal	0(,%rax,4), %edx
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	4(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdx
	movl	$1, %ecx
	movq	%rdx, 36(%rsp)
	movl	40(%rsp), %esi
	movl	%eax, 32(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z27__device_stub__Z4add1PiS_S_PiS_S_
.L11:
	movl	4(%rsp), %eax
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movl	$2, %ecx
	leaq	.LC5(%rip), %rbp
	leaq	.LC6(%rip), %r13
	leal	0(,%rax,4), %edx
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L12:
	cmpl	%r12d, 4(%rsp)
	jle	.L23
	movl	(%rbx,%r12,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	jmp	.L12
.L23:
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	4(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 72(%rsp)
	movl	76(%rsp), %ecx
	movl	%eax, 68(%rsp)
	movq	68(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z27__device_stub__Z4add1PiS_S_PiS_S_
.L14:
	movl	4(%rsp), %eax
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movl	$2, %ecx
	leaq	.LC6(%rip), %r13
	leal	0(,%rax,4), %edx
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L15:
	cmpl	%r12d, 4(%rsp)
	jle	.L24
	movl	(%rbx,%r12,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	jmp	.L15
.L24:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	4(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$256, %ecx
	cltd
	idivl	%ecx
	movl	$16777217, %edx
	movl	$1, %ecx
	salq	$8, %rdx
	cvtsi2ssl	%eax, %xmm0
	cvttss2siq	%xmm0, %rax
	movl	%eax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z27__device_stub__Z4add1PiS_S_PiS_S_
.L17:
	movl	4(%rsp), %eax
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	leaq	.LC6(%rip), %r12
	leal	0(,%rax,4), %edx
	movslq	%edx, %rdx
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%ebp, %ebp
.L18:
	cmpl	%ebp, 4(%rsp)
	jle	.L25
	movl	(%rbx,%rbp,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	jmp	.L18
.L25:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z27__device_stub__Z4add2PiS_S_PiS_S_
	.type	_Z27__device_stub__Z4add2PiS_S_PiS_S_, @function
_Z27__device_stub__Z4add2PiS_S_PiS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4add2PiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L26:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z27__device_stub__Z4add2PiS_S_PiS_S_, .-_Z27__device_stub__Z4add2PiS_S_PiS_S_
	.globl	_Z4add2PiS_S_
	.type	_Z4add2PiS_S_, @function
_Z4add2PiS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4add2PiS_S_PiS_S_
	.cfi_endproc
.LFE2055:
	.size	_Z4add2PiS_S_, .-_Z4add2PiS_S_
	.globl	_Z27__device_stub__Z4add3PiS_S_PiS_S_
	.type	_Z27__device_stub__Z4add3PiS_S_PiS_S_, @function
_Z27__device_stub__Z4add3PiS_S_PiS_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4add3PiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L31:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z27__device_stub__Z4add3PiS_S_PiS_S_, .-_Z27__device_stub__Z4add3PiS_S_PiS_S_
	.globl	_Z4add3PiS_S_
	.type	_Z4add3PiS_S_, @function
_Z4add3PiS_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4add3PiS_S_PiS_S_
	.cfi_endproc
.LFE2057:
	.size	_Z4add3PiS_S_, .-_Z4add3PiS_S_
	.section	.rodata.str1.1
.LC9:
	.string	"_Z4add3PiS_S_"
.LC10:
	.string	"_Z4add2PiS_S_"
.LC11:
	.string	"_Z4add1PiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z4add3PiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4add2PiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4add1PiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"


#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__ void add1(int *a, int *b, int *c){
	int idx = blockIdx.x;
	c[idx] = a[idx] + b[idx];
}

__global__ void add2(int* a, int* b, int* c){
	int idx = threadIdx.x;
	c[idx] = a[idx] + b[idx];
}

__global__ void add3(int* a, int* b, int* c){
	int idx = blockIdx.x*blockDim.x + threadIdx.x;
	c[idx] = a[idx] + b[idx];
}

int main(){
	int N; //number of elements
	int *d_a, *d_b, *d_c; //Device copies
	int size = sizeof(int); //size var
	int *A, *B, *C; //vectors

	printf("Enter number of elements: ");
	scanf("%d",&N);

	A = (int*)malloc(sizeof(int)*N);
	B = (int*)malloc(sizeof(int)*N);
	C = (int*)malloc(sizeof(int)*N);

	printf("Enter elements a <space> b:\n");
	for(int i=0; i<N; i++){
		scanf("%d %d",&A[i],&B[i]);
	}

	//Allocate space for device copies of a,b,c
	hipMalloc((void**)&d_a,size*N);
	hipMalloc((void**)&d_b,size*N);
	hipMalloc((void**)&d_c,size*N);

	//setup input values
	hipMemcpy(d_a,A,size*N,hipMemcpyHostToDevice);
	hipMemcpy(d_b,B,size*N,hipMemcpyHostToDevice);

	printf("\n// LAUNCHING ADD1 //\n");
	//launch add kernel on GPU
	dim3 Blocks1(N,1,1);
	dim3 Threads1(1,1,1);
	add1<<<Blocks1,Threads1>>>(d_a,d_b,d_c);

	//copy result back to host
	hipMemcpy(C,d_c,size*N,hipMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);



	printf("\n// LAUNCHING ADD2 //\n");
	//launch add kernel on GPU
	dim3 Blocks2(1,1,1);
	dim3 Threads2(N,1,1);
	add1<<<Blocks2,Threads2>>>(d_a,d_b,d_c);

	//copy result back to host
	hipMemcpy(C,d_c,size*N,hipMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);


	printf("\n// LAUNCHING ADD3 //\n");
	//launch add kernel on GPU
	dim3 Blocks3(ceilf(N/256),1,1);
	dim3 Threads3(256,1,1);
	add1<<<Blocks3,Threads3>>>(d_a,d_b,d_c);

	//copy result back to host
	hipMemcpy(C,d_c,size*N,hipMemcpyDeviceToHost);
	printf("Result:\n");

	for(int i=0; i<N; i++)
		printf("%d ",C[i]);


	//Cleanup
	hipFree(d_a);
	hipFree(d_b);
	hipFree(d_c);
	return 0;

}

	.text
	.file	"CUDA_VectorAdd.hip"
	.globl	_Z19__device_stub__add1PiS_S_   # -- Begin function _Z19__device_stub__add1PiS_S_
	.type	_Z19__device_stub__add1PiS_S_,@function
_Z19__device_stub__add1PiS_S_:          # @_Z19__device_stub__add1PiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4add1PiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__add1PiS_S_, .Lfunc_end0-_Z19__device_stub__add1PiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__add2PiS_S_   # -- Begin function _Z19__device_stub__add2PiS_S_
	.type	_Z19__device_stub__add2PiS_S_,@function
_Z19__device_stub__add2PiS_S_:          # @_Z19__device_stub__add2PiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4add2PiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__add2PiS_S_, .Lfunc_end1-_Z19__device_stub__add2PiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__add3PiS_S_   # -- Begin function _Z19__device_stub__add3PiS_S_
	.type	_Z19__device_stub__add3PiS_S_,@function
_Z19__device_stub__add3PiS_S_:          # @_Z19__device_stub__add3PiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4add3PiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z19__device_stub__add3PiS_S_, .Lfunc_end2-_Z19__device_stub__add3PiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	12(%rsp), %r14
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r14), %rbx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbx
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	(%r14), %eax
	testl	%eax, %eax
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%r12, %r14
	movq	%r15, %r13
	xorl	%ebp, %ebp
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movq	%r14, %rsi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%rbp
	movslq	12(%rsp), %rax
	addq	$4, %r13
	addq	$4, %r14
	cmpq	%rax, %rbp
	jl	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movabsq	$4294967296, %r14               # imm = 0x100000000
	shll	$2, %eax
	movslq	%eax, %rsi
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	callq	hipMalloc
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipMalloc
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	12(%rsp), %edi
	btsq	$32, %rdi
	leaq	1(%r14), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	_Z19__device_stub__add1PiS_S_
.LBB3_5:
	movq	16(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	cmpl	$0, 12(%rsp)
	jle	.LBB3_8
# %bb.6:                                # %.lr.ph77.preheader
	xorl	%r15d, %r15d
.LBB3_7:                                # %.lr.ph77
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	movslq	12(%rsp), %rax
	cmpq	%rax, %r15
	jl	.LBB3_7
.LBB3_8:                                # %._crit_edge78
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	12(%rsp), %edx
	orq	%r14, %rdx
	leaq	1(%r14), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	_Z19__device_stub__add1PiS_S_
.LBB3_10:
	movq	16(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	cmpl	$0, 12(%rsp)
	jle	.LBB3_13
# %bb.11:                               # %.lr.ph81.preheader
	xorl	%r15d, %r15d
.LBB3_12:                               # %.lr.ph81
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	movslq	12(%rsp), %rax
	cmpq	%rax, %r15
	jl	.LBB3_12
.LBB3_13:                               # %._crit_edge82
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	12(%rsp), %eax
	leal	255(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$8, %ecx
	cvtsi2ss	%ecx, %xmm0
	cvttss2si	%xmm0, %rax
	movl	%eax, %edi
	orq	%r14, %rdi
	addq	$256, %r14                      # imm = 0x100
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.14:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	_Z19__device_stub__add1PiS_S_
.LBB3_15:
	movq	16(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	cmpl	$0, 12(%rsp)
	jle	.LBB3_18
# %bb.16:                               # %.lr.ph85.preheader
	xorl	%r14d, %r14d
.LBB3_17:                               # %.lr.ph85
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	movslq	12(%rsp), %rax
	cmpq	%rax, %r14
	jl	.LBB3_17
.LBB3_18:                               # %._crit_edge86
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4add1PiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4add2PiS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4add3PiS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4add1PiS_S_,@object           # @_Z4add1PiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z4add1PiS_S_
	.p2align	3, 0x0
_Z4add1PiS_S_:
	.quad	_Z19__device_stub__add1PiS_S_
	.size	_Z4add1PiS_S_, 8

	.type	_Z4add2PiS_S_,@object           # @_Z4add2PiS_S_
	.globl	_Z4add2PiS_S_
	.p2align	3, 0x0
_Z4add2PiS_S_:
	.quad	_Z19__device_stub__add2PiS_S_
	.size	_Z4add2PiS_S_, 8

	.type	_Z4add3PiS_S_,@object           # @_Z4add3PiS_S_
	.globl	_Z4add3PiS_S_
	.p2align	3, 0x0
_Z4add3PiS_S_:
	.quad	_Z19__device_stub__add3PiS_S_
	.size	_Z4add3PiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter number of elements: "
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d %d"
	.size	.L.str.3, 6

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%d "
	.size	.L.str.6, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4add1PiS_S_"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z4add2PiS_S_"
	.size	.L__unnamed_2, 14

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z4add3PiS_S_"
	.size	.L__unnamed_3, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Enter elements a <space> b:"
	.size	.Lstr, 28

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\n// LAUNCHING ADD1 //"
	.size	.Lstr.1, 22

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\n// LAUNCHING ADD2 //"
	.size	.Lstr.3, 22

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"\n// LAUNCHING ADD3 //"
	.size	.Lstr.5, 22

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Result:"
	.size	.Lstr.6, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__add1PiS_S_
	.addrsig_sym _Z19__device_stub__add2PiS_S_
	.addrsig_sym _Z19__device_stub__add3PiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4add1PiS_S_
	.addrsig_sym _Z4add2PiS_S_
	.addrsig_sym _Z4add3PiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4add1PiS_S_           ; -- Begin function _Z4add1PiS_S_
	.globl	_Z4add1PiS_S_
	.p2align	8
	.type	_Z4add1PiS_S_,@function
_Z4add1PiS_S_:                          ; @_Z4add1PiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_ashr_i32 s3, s15, 31
	s_load_b64 s[0:1], s[0:1], 0x10
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s4, s2
	s_addc_u32 s5, s5, s3
	s_add_u32 s6, s6, s2
	s_addc_u32 s7, s7, s3
	s_load_b32 s4, s[4:5], 0x0
	s_load_b32 s5, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4add1PiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4add1PiS_S_, .Lfunc_end0-_Z4add1PiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 112
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4add2PiS_S_           ; -- Begin function _Z4add2PiS_S_
	.globl	_Z4add2PiS_S_
	.p2align	8
	.type	_Z4add2PiS_S_,@function
_Z4add2PiS_S_:                          ; @_Z4add2PiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v1, v0, s[4:5]
	global_load_b32 v2, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4add2PiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z4add2PiS_S_, .Lfunc_end1-_Z4add2PiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 72
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4add3PiS_S_           ; -- Begin function _Z4add3PiS_S_
	.globl	_Z4add3PiS_S_
	.p2align	8
	.type	_Z4add3PiS_S_,@function
_Z4add3PiS_S_:                          ; @_Z4add3PiS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4add3PiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z4add3PiS_S_, .Lfunc_end2-_Z4add3PiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 152
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4add1PiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z4add1PiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4add2PiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z4add2PiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4add3PiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4add3PiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
