#include <float.h>

__device__ float euclid2(
	float* items, 
	float* centers, 
	int itemId, 
	int centerId, 
	int paramsCount)
{
	float sum = 0.0;

	for(int j = 0; j < paramsCount; j++)
	{
		sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]) 
		* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
	}

	return sum;
}


__global__ void clusreringKernel(
	float* items, 
	float* deviceCenters,
	int* clustersIds,
	int itemsCount,
	int clustersCount, 
	int paramsCount)
{

	extern __shared__ float centers[];


	for (int i = threadIdx.x; i < clustersCount; i += blockDim.x) 
	{
        for (int j = 0; j < paramsCount; j++) 
        {
            centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
        }
    }

    __syncthreads();

	int itemId = blockDim.x * blockIdx.x + threadIdx.x;


	if(itemId < itemsCount)
	{
		float minDistance = FLT_MAX;
		float distance;
		int index;

		for(int i = 0; i < clustersCount; i++)
		{
			distance = euclid2(items, centers, itemId, i, paramsCount);

			if(minDistance >= distance)
			{
				minDistance = distance;
				index = i;
			}
		}

		clustersIds[itemId] = index;
	}
}


__global__ void newCentersKernel(
	float* items,
	int* clustersIds,
	float* newCenters,
	int* itemsPerClusters,
	int itemsCount,
	int clustersCount,
	int paramsCount
	)
{
	
	extern __shared__ float center[];

	int clusterId = blockIdx.x;
	int paramId = threadIdx.x;

	center[paramId] = 0.0;
	int count = 0;

	__syncthreads();

	for(int i = 0; i < itemsCount; i++)
	{
		if(clusterId == clustersIds[i])
		{
			center[paramId] += items[i * paramsCount + paramId];
			count += 1;
		}
	}

	newCenters[clusterId * paramsCount + paramId] = center[paramId];
	itemsPerClusters[clusterId] = count;
}
	.file	"tmpxft_003b8474_00000000-6_clustering_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7euclid2PfS_iii
	.type	_Z7euclid2PfS_iii, @function
_Z7euclid2PfS_iii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z7euclid2PfS_iii, .-_Z7euclid2PfS_iii
	.globl	_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
	.type	_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, @function
_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16clusreringKernelPfS_Piiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii, .-_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
	.globl	_Z16clusreringKernelPfS_Piiii
	.type	_Z16clusreringKernelPfS_Piiii, @function
_Z16clusreringKernelPfS_Piiii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16clusreringKernelPfS_PiiiiPfS_Piiii
	.cfi_endproc
.LFE2034:
	.size	_Z16clusreringKernelPfS_Piiii, .-_Z16clusreringKernelPfS_Piiii
	.globl	_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
	.type	_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, @function
_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16newCentersKernelPfPiS_S0_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii, .-_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
	.globl	_Z16newCentersKernelPfPiS_S0_iii
	.type	_Z16newCentersKernelPfPiS_S0_iii, @function
_Z16newCentersKernelPfPiS_S0_iii:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z16newCentersKernelPfPiS_S0_iiiPfPiS_S0_iii
	.cfi_endproc
.LFE2036:
	.size	_Z16newCentersKernelPfPiS_S0_iii, .-_Z16newCentersKernelPfPiS_S0_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16newCentersKernelPfPiS_S0_iii"
.LC1:
	.string	"_Z16clusreringKernelPfS_Piiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16newCentersKernelPfPiS_S0_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16clusreringKernelPfS_Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <float.h>

__device__ float euclid2(
	float* items, 
	float* centers, 
	int itemId, 
	int centerId, 
	int paramsCount)
{
	float sum = 0.0;

	for(int j = 0; j < paramsCount; j++)
	{
		sum = sum + (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]) 
		* (items[itemId * paramsCount + j] - centers[centerId * paramsCount + j]);
	}

	return sum;
}


__global__ void clusreringKernel(
	float* items, 
	float* deviceCenters,
	int* clustersIds,
	int itemsCount,
	int clustersCount, 
	int paramsCount)
{

	extern __shared__ float centers[];


	for (int i = threadIdx.x; i < clustersCount; i += blockDim.x) 
	{
        for (int j = 0; j < paramsCount; j++) 
        {
            centers[clustersCount * j + i] = deviceCenters[clustersCount * j + i];
        }
    }

    __syncthreads();

	int itemId = blockDim.x * blockIdx.x + threadIdx.x;


	if(itemId < itemsCount)
	{
		float minDistance = FLT_MAX;
		float distance;
		int index;

		for(int i = 0; i < clustersCount; i++)
		{
			distance = euclid2(items, centers, itemId, i, paramsCount);

			if(minDistance >= distance)
			{
				minDistance = distance;
				index = i;
			}
		}

		clustersIds[itemId] = index;
	}
}


__global__ void newCentersKernel(
	float* items,
	int* clustersIds,
	float* newCenters,
	int* itemsPerClusters,
	int itemsCount,
	int clustersCount,
	int paramsCount
	)
{
	
	extern __shared__ float center[];

	int clusterId = blockIdx.x;
	int paramId = threadIdx.x;

	center[paramId] = 0.0;
	int count = 0;

	__syncthreads();

	for(int i = 0; i < itemsCount; i++)
	{
		if(clusterId == clustersIds[i])
		{
			center[paramId] += items[i * paramsCount + paramId];
			count += 1;
		}
	}

	newCenters[clusterId * paramsCount + paramId] = center[paramId];
	itemsPerClusters[clusterId] = count;
}
	.text
	.file	"clustering_kernels.hip"
	.globl	_Z31__device_stub__clusreringKernelPfS_Piiii # -- Begin function _Z31__device_stub__clusreringKernelPfS_Piiii
	.type	_Z31__device_stub__clusreringKernelPfS_Piiii,@function
_Z31__device_stub__clusreringKernelPfS_Piiii: # @_Z31__device_stub__clusreringKernelPfS_Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16clusreringKernelPfS_Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__clusreringKernelPfS_Piiii, .Lfunc_end0-_Z31__device_stub__clusreringKernelPfS_Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__newCentersKernelPfPiS_S0_iii # -- Begin function _Z31__device_stub__newCentersKernelPfPiS_S0_iii
	.type	_Z31__device_stub__newCentersKernelPfPiS_S0_iii,@function
_Z31__device_stub__newCentersKernelPfPiS_S0_iii: # @_Z31__device_stub__newCentersKernelPfPiS_S0_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16newCentersKernelPfPiS_S0_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__newCentersKernelPfPiS_S0_iii, .Lfunc_end1-_Z31__device_stub__newCentersKernelPfPiS_S0_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16clusreringKernelPfS_Piiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16newCentersKernelPfPiS_S0_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16clusreringKernelPfS_Piiii,@object # @_Z16clusreringKernelPfS_Piiii
	.section	.rodata,"a",@progbits
	.globl	_Z16clusreringKernelPfS_Piiii
	.p2align	3, 0x0
_Z16clusreringKernelPfS_Piiii:
	.quad	_Z31__device_stub__clusreringKernelPfS_Piiii
	.size	_Z16clusreringKernelPfS_Piiii, 8

	.type	_Z16newCentersKernelPfPiS_S0_iii,@object # @_Z16newCentersKernelPfPiS_S0_iii
	.globl	_Z16newCentersKernelPfPiS_S0_iii
	.p2align	3, 0x0
_Z16newCentersKernelPfPiS_S0_iii:
	.quad	_Z31__device_stub__newCentersKernelPfPiS_S0_iii
	.size	_Z16newCentersKernelPfPiS_S0_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16clusreringKernelPfS_Piiii"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16newCentersKernelPfPiS_S0_iii"
	.size	.L__unnamed_2, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__clusreringKernelPfS_Piiii
	.addrsig_sym _Z31__device_stub__newCentersKernelPfPiS_S0_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16clusreringKernelPfS_Piiii
	.addrsig_sym _Z16newCentersKernelPfPiS_S0_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16clusreringKernelPfS_Piiii ; -- Begin function _Z16clusreringKernelPfS_Piiii
	.globl	_Z16clusreringKernelPfS_Piiii
	.p2align	8
	.type	_Z16clusreringKernelPfS_Piiii,@function
_Z16clusreringKernelPfS_Piiii:          ; @_Z16clusreringKernelPfS_Piiii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $sgpr12_sgpr13
	v_cmpx_le_i32_e64 s5, v0
	s_xor_b32 s7, exec_lo, s7
; %bb.1:                                ; %.._crit_edge43_crit_edge
	s_add_u32 s12, s0, 40
	s_addc_u32 s13, s1, 0
; %bb.2:                                ; %Flow90
	s_or_saveexec_b32 s7, s7
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13
	s_xor_b32 exec_lo, exec_lo, s7
	s_cbranch_execz .LBB0_9
; %bb.3:                                ; %.preheader40.lr.ph
	s_load_b32 s13, s[0:1], 0x34
	s_cmp_gt_i32 s6, 0
	v_lshl_add_u32 v4, v0, 2, 0
	v_mov_b32_e32 v1, v0
	s_cselect_b32 s16, -1, 0
	s_add_u32 s0, s0, 40
	s_mov_b32 s12, s5
	s_addc_u32 s1, s1, 0
	s_mov_b32 s14, 0
	s_lshl_b32 s17, s5, 2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s13, 0xffff
	s_ashr_i32 s13, s5, 31
	s_lshl_b32 s19, s18, 2
	s_lshl_b64 s[12:13], s[12:13], 2
.LBB0_4:                                ; %.preheader40
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_7
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v5, v4
	s_mov_b32 s20, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	s_add_i32 s20, s20, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s20, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, s17, v5
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_add_nc_u32_e32 v1, s18, v1
	v_add_nc_u32_e32 v4, s19, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s5, v1
	s_or_b32 s14, vcc_lo, s14
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_4
; %bb.8:                                ; %Flow89
	s_or_b32 exec_lo, exec_lo, s14
	v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
.LBB0_9:                                ; %Flow91
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_u16 v3, v[1:2], off offset:12
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_18
; %bb.10:                               ; %.preheader
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_16
; %bb.11:                               ; %.lr.ph47
	v_mul_lo_u32 v2, v1, s6
	v_mov_b32_e32 v6, 0x7f7fffff
	s_cmp_gt_i32 s6, 0
	s_mov_b32 s1, 0
	s_cselect_b32 s0, -1, 0
	s_lshl_b32 s4, s6, 2
	s_mov_b32 s7, 0
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_14 Depth 2
	v_mov_b32_e32 v7, 0
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_15
; %bb.13:                               ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_mov_b32 s8, s1
	s_mov_b32 s9, s6
.LBB0_14:                               ;   Parent Loop BB0_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v8, v[4:5], off
	v_mov_b32_e32 v9, s8
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	ds_load_b32 v9, v9
	s_add_i32 s9, s9, -1
	s_add_i32 s8, s8, 4
	s_cmp_lg_u32 s9, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v8
	s_cbranch_scc1 .LBB0_14
.LBB0_15:                               ; %_Z7euclid2PfS_iii.exit
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_cmp_nge_f32_e32 vcc_lo, v6, v7
	s_add_i32 s1, s1, s4
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_cndmask_b32_e32 v0, s7, v0, vcc_lo
	s_add_i32 s7, s7, 1
	s_cmp_eq_u32 s7, s5
	s_cbranch_scc0 .LBB0_12
	s_branch .LBB0_17
.LBB0_16:
                                        ; implicit-def: $vgpr0
.LBB0_17:                               ; %Flow85
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16clusreringKernelPfS_Piiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16clusreringKernelPfS_Piiii, .Lfunc_end0-_Z16clusreringKernelPfS_Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 23
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16newCentersKernelPfPiS_S0_iii ; -- Begin function _Z16newCentersKernelPfPiS_S0_iii
	.globl	_Z16newCentersKernelPfPiS_S0_iii
	.p2align	8
	.type	_Z16newCentersKernelPfPiS_S0_iii,@function
_Z16newCentersKernelPfPiS_S0_iii:       ; @_Z16newCentersKernelPfPiS_S0_iii
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s1, s[0:1], 0x28
	v_lshl_add_u32 v3, v0, 2, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, s15
	s_mov_b32 s0, 0
	ds_store_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v1, v0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s12, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s2, s12
	s_cbranch_scc1 .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	ds_load_b32 v4, v3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v2, v2, v4
	ds_store_b32 v3, v2
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s3, s3, -1
	v_add_nc_u32_e32 v1, s1, v1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %Flow45
	v_mad_u64_u32 v[1:2], null, s2, s1, v[0:1]
	ds_load_b32 v3, v3
	s_ashr_i32 s3, s2, 31
	v_mov_b32_e32 v4, s0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_u32 s0, s10, s0
	v_ashrrev_i32_e32 v2, 31, v1
	s_addc_u32 s1, s11, s1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
	global_store_b32 v2, v4, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16newCentersKernelPfPiS_S0_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16newCentersKernelPfPiS_S0_iii, .Lfunc_end1-_Z16newCentersKernelPfPiS_S0_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16clusreringKernelPfS_Piiii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z16clusreringKernelPfS_Piiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16newCentersKernelPfPiS_S0_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16newCentersKernelPfPiS_S0_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
