#include <iostream>
#include <cmath>
#include <stdio.h>
#include <string.h>

__device__ __constant__ float D_H[ 3*3 ];

__device__ float norm(float val, int length) {
    float mean = length/2;
    float std = length/2;
    return (val-mean)/std;
}

__device__ float unorm(float val, int length) {
    float mean = length/2;
    float std = length/2;
    return val*std + mean;
}

__device__ void projectedCoord(int x, int y, int *xp, int *yp, int xlen, int ylen) {

    //printf("%d, %d \n", x, y);
    //NORMALIZE INPUT
    float nx = norm(x,xlen);
    float ny = norm(y,ylen);

    //printf("%f, %f \n", nx, ny);
    int sH = 3;
    float w = 1; //Assume that the projection starts from y=1


    float hx = nx*D_H[ sH*0+0] + ny*D_H[ sH*0+1 ] + w*D_H[ sH*0+2 ];
    float hy = nx*D_H[ sH*1+0] + ny*D_H[ sH*1+1 ] + w*D_H[ sH*1+2 ];
    float hw = nx*D_H[ sH*2+0] + ny*D_H[ sH*2+1 ] + w*D_H[ sH*2+2 ];

    //printf("%f, %f, %f\n",D_H[ sH*0+0], D_H[ sH*0+1], D_H[ sH*0+2]);
    //printf("%f, %f, %f\n",D_H[ sH*1+0], D_H[ sH*1+1], D_H[ sH*1+2]);
    //printf("%f, %f, %f\n",D_H[ sH*2+0], D_H[ sH*2+1], D_H[ sH*2+2]);
    //printf("%f %f %f \n", hx, hy, hw);

    //Unormalize Output
    *xp = unorm(hx/hw, xlen);
    *yp = unorm(hy/hw, ylen);

    //printf("%d, %d \n", *xp, *yp);

}

__device__ int im_idx(int r, int c, int width, int channels) {
    return channels*(width*r+c);
}

__device__ bool val_rc(int r, int c, int width, int height) {
    return r>=0 && r<height && c>=0 && c<width;
}

__global__ void proj_sub_tresh(unsigned char* img0, unsigned char* img1, unsigned char* out_img, int Width, int Height) {
    const unsigned int c = ( (blockDim.y * blockIdx.y) + threadIdx.y );
    const unsigned int r = ( (blockDim.x * blockIdx.x) + threadIdx.x );

    const unsigned int treshold = 60;
    const unsigned int ch = 3; //Channel
    const unsigned int s = sizeof(unsigned char);
    const unsigned int W = Width;
    int o_img_idx;
    int i_img_idx;
    unsigned int subval, subval0, subval1, subval2;
    int rp;
    int cp;
    //Projection, Background Sub, Treshold

    // Not sure why I wrote the matrix in this manner where the r column is reversed using x,y notation
    // Need to look deeper into and be fixed
    projectedCoord(c,r,  &cp, &rp, Width, Height);

    //printf("%d, %d \n", rp, cp);
    if ( val_rc(rp,cp, Width, Height) && val_rc(r,c, Width, Height) ) {


        o_img_idx = im_idx(r,c,  Width,ch);
        i_img_idx = im_idx(rp,cp,  Width,ch);
        subval0 = abs( img1[ o_img_idx+0 ] - img0[ i_img_idx+0 ] );
        subval1 = abs( img1[ o_img_idx+1 ] - img0[ i_img_idx+1 ] );
        subval2 = abs( img1[ o_img_idx+2 ] - img0[ i_img_idx+2 ] );
        subval = .21265*subval0 + .7152*subval1 + .0722*subval2;

        if (subval > treshold) {
            out_img[ o_img_idx+0 ] = subval;
            out_img[ o_img_idx+1 ] = subval;
            out_img[ o_img_idx+2 ] = subval;
        }
        //out_img[ o_img_idx+0 ] = img0[ i_img_idx+0];
        //out_img[ o_img_idx+1 ] = img0[ i_img_idx+1];
        //out_img[ o_img_idx+2 ] = img0[ i_img_idx+2];


    }
}

	.file	"tmpxft_0036180f_00000000-6_kernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4normfi
	.type	_Z4normfi, @function
_Z4normfi:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z4normfi, .-_Z4normfi
	.globl	_Z5unormfi
	.type	_Z5unormfi, @function
_Z5unormfi:
.LFB4287:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4normfi
	.cfi_endproc
.LFE4287:
	.size	_Z5unormfi, .-_Z5unormfi
	.globl	_Z14projectedCoordiiPiS_ii
	.type	_Z14projectedCoordiiPiS_ii, @function
_Z14projectedCoordiiPiS_ii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z14projectedCoordiiPiS_ii, .-_Z14projectedCoordiiPiS_ii
	.globl	_Z6im_idxiiii
	.type	_Z6im_idxiiii, @function
_Z6im_idxiiii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3638:
	.size	_Z6im_idxiiii, .-_Z6im_idxiiii
	.globl	_Z6val_rciiii
	.type	_Z6val_rciiii, @function
_Z6val_rciiii:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3639:
	.size	_Z6val_rciiii, .-_Z6val_rciiii
	.globl	_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii
	.type	_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii, @function
_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14proj_sub_treshPhS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii, .-_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii
	.globl	_Z14proj_sub_treshPhS_S_ii
	.type	_Z14proj_sub_treshPhS_S_ii, @function
_Z14proj_sub_treshPhS_S_ii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z14proj_sub_treshPhS_S_iiPhS_S_ii
	.cfi_endproc
.LFE3665:
	.size	_Z14proj_sub_treshPhS_S_ii, .-_Z14proj_sub_treshPhS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14proj_sub_treshPhS_S_ii"
.LC1:
	.string	"D_H"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14proj_sub_treshPhS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$36, %r9d
	leaq	_ZL3D_H(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL3D_H
	.comm	_ZL3D_H,36,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <stdio.h>
#include <string.h>

__device__ __constant__ float D_H[ 3*3 ];

__device__ float norm(float val, int length) {
    float mean = length/2;
    float std = length/2;
    return (val-mean)/std;
}

__device__ float unorm(float val, int length) {
    float mean = length/2;
    float std = length/2;
    return val*std + mean;
}

__device__ void projectedCoord(int x, int y, int *xp, int *yp, int xlen, int ylen) {

    //printf("%d, %d \n", x, y);
    //NORMALIZE INPUT
    float nx = norm(x,xlen);
    float ny = norm(y,ylen);

    //printf("%f, %f \n", nx, ny);
    int sH = 3;
    float w = 1; //Assume that the projection starts from y=1


    float hx = nx*D_H[ sH*0+0] + ny*D_H[ sH*0+1 ] + w*D_H[ sH*0+2 ];
    float hy = nx*D_H[ sH*1+0] + ny*D_H[ sH*1+1 ] + w*D_H[ sH*1+2 ];
    float hw = nx*D_H[ sH*2+0] + ny*D_H[ sH*2+1 ] + w*D_H[ sH*2+2 ];

    //printf("%f, %f, %f\n",D_H[ sH*0+0], D_H[ sH*0+1], D_H[ sH*0+2]);
    //printf("%f, %f, %f\n",D_H[ sH*1+0], D_H[ sH*1+1], D_H[ sH*1+2]);
    //printf("%f, %f, %f\n",D_H[ sH*2+0], D_H[ sH*2+1], D_H[ sH*2+2]);
    //printf("%f %f %f \n", hx, hy, hw);

    //Unormalize Output
    *xp = unorm(hx/hw, xlen);
    *yp = unorm(hy/hw, ylen);

    //printf("%d, %d \n", *xp, *yp);

}

__device__ int im_idx(int r, int c, int width, int channels) {
    return channels*(width*r+c);
}

__device__ bool val_rc(int r, int c, int width, int height) {
    return r>=0 && r<height && c>=0 && c<width;
}

__global__ void proj_sub_tresh(unsigned char* img0, unsigned char* img1, unsigned char* out_img, int Width, int Height) {
    const unsigned int c = ( (blockDim.y * blockIdx.y) + threadIdx.y );
    const unsigned int r = ( (blockDim.x * blockIdx.x) + threadIdx.x );

    const unsigned int treshold = 60;
    const unsigned int ch = 3; //Channel
    const unsigned int s = sizeof(unsigned char);
    const unsigned int W = Width;
    int o_img_idx;
    int i_img_idx;
    unsigned int subval, subval0, subval1, subval2;
    int rp;
    int cp;
    //Projection, Background Sub, Treshold

    // Not sure why I wrote the matrix in this manner where the r column is reversed using x,y notation
    // Need to look deeper into and be fixed
    projectedCoord(c,r,  &cp, &rp, Width, Height);

    //printf("%d, %d \n", rp, cp);
    if ( val_rc(rp,cp, Width, Height) && val_rc(r,c, Width, Height) ) {


        o_img_idx = im_idx(r,c,  Width,ch);
        i_img_idx = im_idx(rp,cp,  Width,ch);
        subval0 = abs( img1[ o_img_idx+0 ] - img0[ i_img_idx+0 ] );
        subval1 = abs( img1[ o_img_idx+1 ] - img0[ i_img_idx+1 ] );
        subval2 = abs( img1[ o_img_idx+2 ] - img0[ i_img_idx+2 ] );
        subval = .21265*subval0 + .7152*subval1 + .0722*subval2;

        if (subval > treshold) {
            out_img[ o_img_idx+0 ] = subval;
            out_img[ o_img_idx+1 ] = subval;
            out_img[ o_img_idx+2 ] = subval;
        }
        //out_img[ o_img_idx+0 ] = img0[ i_img_idx+0];
        //out_img[ o_img_idx+1 ] = img0[ i_img_idx+1];
        //out_img[ o_img_idx+2 ] = img0[ i_img_idx+2];


    }
}

	.text
	.file	"kernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z29__device_stub__proj_sub_treshPhS_S_ii # -- Begin function _Z29__device_stub__proj_sub_treshPhS_S_ii
	.type	_Z29__device_stub__proj_sub_treshPhS_S_ii,@function
_Z29__device_stub__proj_sub_treshPhS_S_ii: # @_Z29__device_stub__proj_sub_treshPhS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14proj_sub_treshPhS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__proj_sub_treshPhS_S_ii, .Lfunc_end0-_Z29__device_stub__proj_sub_treshPhS_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14proj_sub_treshPhS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$D_H, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	D_H,@object                     # @D_H
	.local	D_H
	.comm	D_H,36,16
	.type	_Z14proj_sub_treshPhS_S_ii,@object # @_Z14proj_sub_treshPhS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z14proj_sub_treshPhS_S_ii
	.p2align	3, 0x0
_Z14proj_sub_treshPhS_S_ii:
	.quad	_Z29__device_stub__proj_sub_treshPhS_S_ii
	.size	_Z14proj_sub_treshPhS_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14proj_sub_treshPhS_S_ii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"D_H"
	.size	.L__unnamed_2, 4

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__proj_sub_treshPhS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym D_H
	.addrsig_sym _Z14proj_sub_treshPhS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14proj_sub_treshPhS_S_ii ; -- Begin function _Z14proj_sub_treshPhS_S_ii
	.globl	_Z14proj_sub_treshPhS_S_ii
	.p2align	8
	.type	_Z14proj_sub_treshPhS_S_ii,@function
_Z14proj_sub_treshPhS_S_ii:             ; @_Z14proj_sub_treshPhS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	s_lshr_b32 s4, s6, 31
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	s_lshr_b32 s5, s7, 31
	s_add_i32 s2, s6, s4
	s_add_i32 s3, s7, s5
	s_ashr_i32 s2, s2, 1
	s_ashr_i32 s3, s3, 1
	v_cvt_f32_i32_e32 v2, s2
	v_cvt_f32_i32_e32 v3, v0
	v_cvt_f32_i32_e32 v4, s3
	v_cvt_f32_i32_e32 v5, v1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, D_H@rel32@lo+4
	s_addc_u32 s5, s5, D_H@rel32@hi+12
	v_sub_f32_e32 v3, v3, v2
	s_load_b256 s[8:15], s[4:5], 0x0
	v_sub_f32_e32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, v2, v2, v3
	v_div_scale_f32 v7, null, v4, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v6, v8, 1.0
	v_fma_f32 v11, -v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v8, v10, v8
	v_div_scale_f32 v12, vcc_lo, v3, v2, v3
	v_div_scale_f32 v10, s2, v5, v4, v5
	v_fmac_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v12, v8
	v_mul_f32_e32 v13, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, -v6, v11, v12
	v_fma_f32 v15, -v7, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v14, v8
	v_fmac_f32_e32 v13, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v6, v11, v12
	v_fma_f32 v7, -v7, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v8, v11
	s_mov_b32 vcc_lo, s2
	s_load_b32 s2, s[4:5], 0x20
	v_div_fmas_f32 v7, v7, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v6, v2, v3
	v_div_fixup_f32 v5, v7, v4, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, s9, v5
	v_mul_f32_e32 v7, s15, v5
	v_dual_mul_f32 v5, s12, v5 :: v_dual_fmac_f32 v6, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, s14, v3
	v_fmac_f32_e32 v5, s11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, s10, v6 :: v_dual_add_f32 v6, s2, v7
	v_add_f32_e32 v5, s13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v7, null, v6, v6, v3
	v_div_scale_f32 v8, null, v6, v6, v5
	v_div_scale_f32 v13, vcc_lo, v3, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v7
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v7, v9, 1.0
	v_fma_f32 v12, -v8, v10, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, v11, v9
	v_div_scale_f32 v11, s2, v5, v6, v5
	v_fmac_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v13, v9
	v_mul_f32_e32 v14, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v7, v12, v13
	v_fma_f32 v16, -v8, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v15, v9
	v_fmac_f32_e32 v14, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v7, v12, v13
	v_fma_f32 v8, -v8, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v7, v7, v9, v12
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v8, v8, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v7, v6, v3
	v_div_fixup_f32 v5, v8, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, v3, v2
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s6, v2
	v_cmp_lt_i32_e64 s3, -1, v2
	v_cmp_gt_i32_e32 vcc_lo, s7, v3
	v_cmp_lt_i32_e64 s4, -1, v3
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_cmp_gt_i32_e32 vcc_lo, s7, v1
	v_cmp_gt_i32_e64 s2, s6, v0
	v_cmp_lt_i32_e64 s3, -1, v0
	v_cmp_lt_i32_e64 s4, -1, v1
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_4
; %bb.2:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mad_u64_u32 v[4:5], null, v1, s6, v[0:1]
	v_mad_u64_u32 v[5:6], null, v3, s6, v[2:3]
	s_mov_b32 s2, 0x1c432ca5
	s_mov_b32 s3, 0x3fe6e2eb
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v4, 1, v4
	v_lshl_add_u32 v4, v5, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_u16 v6, v[2:3], off
	global_load_u16 v7, v[4:5], off
	global_load_u8 v8, v[2:3], off offset:2
	global_load_u8 v9, v[4:5], off offset:2
	s_waitcnt vmcnt(3)
	v_lshrrev_b32_e32 v2, 8, v6
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v3, 8, v7
	v_and_b32_e32 v4, 0xff, v6
	v_and_b32_e32 v5, 0xff, v7
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v8, v9
	v_sub_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v4, v5
	v_sub_nc_u32_e32 v7, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, 0, v2
	v_sub_nc_u32_e32 v5, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, v6, v7
	v_max_i32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v4, v4, v5
	v_cvt_f64_u32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[4:5], v4
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	s_mov_b32 s2, 0x7dbf4880
	s_mov_b32 s3, 0x3fcb381d
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
	v_cvt_f64_u32_e32 v[4:5], v6
	s_mov_b32 s2, 0xfec56d5d
	s_mov_b32 s3, 0x3fb27bb2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f64_e32 v2, v[2:3]
	v_cmp_lt_u32_e32 vcc_lo, 60, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshlrev_b16 v3, 8, v2
	v_and_b32_e32 v4, 0xff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v3, v4, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x1
	global_store_b8 v[0:1], v2, off offset:2
	global_store_b16 v[0:1], v3, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14proj_sub_treshPhS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14proj_sub_treshPhS_S_ii, .Lfunc_end0-_Z14proj_sub_treshPhS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1144
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	D_H                     ; @D_H
	.type	D_H,@object
	.section	.bss,"aw",@nobits
	.globl	D_H
	.p2align	4, 0x0
D_H:
	.zero	36
	.size	D_H, 36

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym D_H
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14proj_sub_treshPhS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14proj_sub_treshPhS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
