/**
 * Copyright: Fynn Schröder, 2019
 * Author: Fynn Schröder
 * License: MIT
 */

template<typename T, unsigned int blockSize>
__global__ 
void kernelMax(const T* __restrict__ input, 
        T* __restrict__ per_block_results, 
                const size_t n)
{
    __shared__ float sdata[blockSize];
    __shared__ unsigned int sidx[blockSize];

    T x = -1e38;
    unsigned int idx = UINT_MAX;
    for(unsigned int i=threadIdx.x; i < n; i += blockDim.x) {
        const T val = input[i + blockIdx.x * n];
        if (val > x)
        {
            x = val;
            idx = i;
        }
    }

    sdata[threadIdx.x] = x;
    sidx[threadIdx.x] = idx;
    __syncthreads();

    for (unsigned int s=blockDim.x/2; s>0; s>>=1) 
    {
        if (threadIdx.x < s)
        {
            if (sdata[threadIdx.x + s] > sdata[threadIdx.x])
            {
                sdata[threadIdx.x] = sdata[threadIdx.x + s];
                sidx[threadIdx.x] = sidx[threadIdx.x + s];
            }
        }
        __syncthreads();
    }

    // thread 0 writes the final result
    if(threadIdx.x == 0) {
        per_block_results[blockIdx.x * 2] = sdata[0];
        per_block_results[blockIdx.x * 2 + 1] = __int_as_float(sidx[0]);
    }
}

extern "C" void max_idx_all(const float * device_results, const unsigned int rows, const unsigned int columns, float * device_maxima, cudaStream_t stream = NULL)
{
    dim3 blocksize(256); 
    dim3 gridsize(columns);
    kernelMax<float, 256><<<gridsize, blocksize, 0, stream>>>(device_results, device_maxima, rows);
}

template<typename T>
__global__ 
void kernelMaxOpt(const T* __restrict__ input, 
        T* __restrict__ per_block_results, 
                const size_t n, const size_t m, const unsigned int offset, const bool overwrite)
{
    T x = -1e38;
    unsigned int idx = UINT_MAX;

    for (int i = 0; i < n; i += 1)
    {
        if (threadIdx.x + blockIdx.x * blockDim.x < m)
        {
            float val = input[i * m + threadIdx.x + blockIdx.x * blockDim.x];
            if (val > x)
            {
                x = val;
                idx = i;
            }
        }
    }

    if (threadIdx.x + blockIdx.x * blockDim.x < m) {
        if (overwrite || x > per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2]) {
            per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2] = x;
            per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2 + 1] = __int_as_float(idx + offset);
        }
    }
}

extern "C" void max_idx_t(const float * device_results, const unsigned int rows, const unsigned int columns, float * device_maxima, const unsigned int offset, const bool overwrite, cudaStream_t stream = NULL)
{
    int blocksize = 256; 
    int gridsize = (rows + blocksize -1) / blocksize;
    kernelMaxOpt<float><<<gridsize, blocksize, 0, stream>>>(device_results, device_maxima, columns, rows , offset, overwrite);
}
	.file	"tmpxft_003255d4_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2016:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2016:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb, @function
_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb:
.LFB2040:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movb	%r9b, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rax, 120(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12kernelMaxOptIfEvPKT_PS0_mmjb(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb, .-_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb
	.type	_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm, @function
_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm:
.LFB2038:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9kernelMaxIfLj256EEvPKT_PS0_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L7:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm, .-_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm
	.section	.text._Z9kernelMaxIfLj256EEvPKT_PS0_m,"axG",@progbits,_Z9kernelMaxIfLj256EEvPKT_PS0_m,comdat
	.weak	_Z9kernelMaxIfLj256EEvPKT_PS0_m
	.type	_Z9kernelMaxIfLj256EEvPKT_PS0_m, @function
_Z9kernelMaxIfLj256EEvPKT_PS0_m:
.LFB2089:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm
	.cfi_endproc
.LFE2089:
	.size	_Z9kernelMaxIfLj256EEvPKT_PS0_m, .-_Z9kernelMaxIfLj256EEvPKT_PS0_m
	.section	.text._Z12kernelMaxOptIfEvPKT_PS0_mmjb,"axG",@progbits,_Z12kernelMaxOptIfEvPKT_PS0_mmjb,comdat
	.weak	_Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.type	_Z12kernelMaxOptIfEvPKT_PS0_mmjb, @function
_Z12kernelMaxOptIfEvPKT_PS0_mmjb:
.LFB2090:
	.cfi_startproc
	endbr64
	movzbl	%r9b, %r9d
	jmp	_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb
	.cfi_endproc
.LFE2090:
	.size	_Z12kernelMaxOptIfEvPKT_PS0_mmjb, .-_Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.text
	.globl	max_idx_all
	.type	max_idx_all, @function
max_idx_all:
.LFB2010:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%r8, %r9
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	movl	$1, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%esi, %ebx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movl	%edx, 20(%rsp)
	movl	$16777217, %edx
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	salq	$8, %rdx
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z9kernelMaxIfLj256EEvPKT_PS0_mPKfPfm
.L13:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	max_idx_all, .-max_idx_all
	.globl	max_idx_t
	.type	max_idx_t, @function
max_idx_t:
.LFB2013:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	255(%rsi), %eax
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$8, %eax
	movl	%r8d, %r14d
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	movl	$16777217, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	salq	$8, %rdx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	%eax, 8(%rsp)
	movq	96(%rsp), %r9
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%ebx, %ecx
	movl	%ebp, %edx
	movzbl	%r15b, %r9d
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%r14d, %r8d
	popq	%rbp
	.cfi_def_cfa_offset 40
	movq	%r13, %rsi
	movq	%r12, %rdi
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z12kernelMaxOptIfEvPKT_PS0_mmjbPKfPfmmjb
.L16:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2013:
	.size	max_idx_t, .-max_idx_t
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12kernelMaxOptIfEvPKT_PS0_mmjb"
.LC1:
	.string	"_Z9kernelMaxIfLj256EEvPKT_PS0_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12kernelMaxOptIfEvPKT_PS0_mmjb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9kernelMaxIfLj256EEvPKT_PS0_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/**
 * Copyright: Fynn Schröder, 2019
 * Author: Fynn Schröder
 * License: MIT
 */

template<typename T, unsigned int blockSize>
__global__ 
void kernelMax(const T* __restrict__ input, 
        T* __restrict__ per_block_results, 
                const size_t n)
{
    __shared__ float sdata[blockSize];
    __shared__ unsigned int sidx[blockSize];

    T x = -1e38;
    unsigned int idx = UINT_MAX;
    for(unsigned int i=threadIdx.x; i < n; i += blockDim.x) {
        const T val = input[i + blockIdx.x * n];
        if (val > x)
        {
            x = val;
            idx = i;
        }
    }

    sdata[threadIdx.x] = x;
    sidx[threadIdx.x] = idx;
    __syncthreads();

    for (unsigned int s=blockDim.x/2; s>0; s>>=1) 
    {
        if (threadIdx.x < s)
        {
            if (sdata[threadIdx.x + s] > sdata[threadIdx.x])
            {
                sdata[threadIdx.x] = sdata[threadIdx.x + s];
                sidx[threadIdx.x] = sidx[threadIdx.x + s];
            }
        }
        __syncthreads();
    }

    // thread 0 writes the final result
    if(threadIdx.x == 0) {
        per_block_results[blockIdx.x * 2] = sdata[0];
        per_block_results[blockIdx.x * 2 + 1] = __int_as_float(sidx[0]);
    }
}

extern "C" void max_idx_all(const float * device_results, const unsigned int rows, const unsigned int columns, float * device_maxima, hipStream_t stream = NULL)
{
    dim3 blocksize(256); 
    dim3 gridsize(columns);
    kernelMax<float, 256><<<gridsize, blocksize, 0, stream>>>(device_results, device_maxima, rows);
}

template<typename T>
__global__ 
void kernelMaxOpt(const T* __restrict__ input, 
        T* __restrict__ per_block_results, 
                const size_t n, const size_t m, const unsigned int offset, const bool overwrite)
{
    T x = -1e38;
    unsigned int idx = UINT_MAX;

    for (int i = 0; i < n; i += 1)
    {
        if (threadIdx.x + blockIdx.x * blockDim.x < m)
        {
            float val = input[i * m + threadIdx.x + blockIdx.x * blockDim.x];
            if (val > x)
            {
                x = val;
                idx = i;
            }
        }
    }

    if (threadIdx.x + blockIdx.x * blockDim.x < m) {
        if (overwrite || x > per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2]) {
            per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2] = x;
            per_block_results[(blockIdx.x * blockDim.x + threadIdx.x) * 2 + 1] = __int_as_float(idx + offset);
        }
    }
}

extern "C" void max_idx_t(const float * device_results, const unsigned int rows, const unsigned int columns, float * device_maxima, const unsigned int offset, const bool overwrite, hipStream_t stream = NULL)
{
    int blocksize = 256; 
    int gridsize = (rows + blocksize -1) / blocksize;
    kernelMaxOpt<float><<<gridsize, blocksize, 0, stream>>>(device_results, device_maxima, columns, rows , offset, overwrite);
}
	.text
	.file	"kernel.hip"
	.globl	max_idx_all                     # -- Begin function max_idx_all
	.type	max_idx_all,@function
max_idx_all:                            # @max_idx_all
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movq	%r8, %r9
	movq	%rcx, %rbx
	movl	%esi, %ebp
	movq	%rdi, %r14
	movl	%edx, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 32
	movl	%ebp, %edx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m # TAILCALL
.Lfunc_end0:
	.size	max_idx_all, .Lfunc_end0-max_idx_all
	.cfi_endproc
                                        # -- End function
	.section	.text._Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m,"axG",@progbits,_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m,comdat
	.weak	_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m # -- Begin function _Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m
	.type	_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m,@function
_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m: # @_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9kernelMaxIfLj256EEvPKT_PS0_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m, .Lfunc_end1-_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m
	.cfi_endproc
                                        # -- End function
	.text
	.globl	max_idx_t                       # -- Begin function max_idx_t
	.type	max_idx_t,@function
max_idx_t:                              # @max_idx_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movl	%r8d, %ebx
	movq	%rcx, %r14
	movl	%edx, %r13d
	movl	%esi, %r12d
	movq	%rdi, %r15
	movq	64(%rsp), %r9
	leal	255(%r12), %edi
	shrl	$8, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 64
	movl	%r13d, %edx
	movl	%r12d, %ecx
	movzbl	%bpl, %r9d
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %r8d
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb # TAILCALL
.Lfunc_end2:
	.size	max_idx_t, .Lfunc_end2-max_idx_t
	.cfi_endproc
                                        # -- End function
	.section	.text._Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb,"axG",@progbits,_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb,comdat
	.weak	_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb # -- Begin function _Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb
	.type	_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb,@function
_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb: # @_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	11(%rsp), %r8
	movb	%r9b, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12kernelMaxOptIfEvPKT_PS0_mmjb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb, .Lfunc_end3-_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9kernelMaxIfLj256EEvPKT_PS0_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12kernelMaxOptIfEvPKT_PS0_mmjb, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9kernelMaxIfLj256EEvPKT_PS0_m,@object # @_Z9kernelMaxIfLj256EEvPKT_PS0_m
	.section	.rodata._Z9kernelMaxIfLj256EEvPKT_PS0_m,"aG",@progbits,_Z9kernelMaxIfLj256EEvPKT_PS0_m,comdat
	.weak	_Z9kernelMaxIfLj256EEvPKT_PS0_m
	.p2align	3, 0x0
_Z9kernelMaxIfLj256EEvPKT_PS0_m:
	.quad	_Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m
	.size	_Z9kernelMaxIfLj256EEvPKT_PS0_m, 8

	.type	_Z12kernelMaxOptIfEvPKT_PS0_mmjb,@object # @_Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.section	.rodata._Z12kernelMaxOptIfEvPKT_PS0_mmjb,"aG",@progbits,_Z12kernelMaxOptIfEvPKT_PS0_mmjb,comdat
	.weak	_Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.p2align	3, 0x0
_Z12kernelMaxOptIfEvPKT_PS0_mmjb:
	.quad	_Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb
	.size	_Z12kernelMaxOptIfEvPKT_PS0_mmjb, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9kernelMaxIfLj256EEvPKT_PS0_m"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12kernelMaxOptIfEvPKT_PS0_mmjb"
	.size	.L__unnamed_2, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__kernelMaxIfLj256EEvPKT_PS0_m
	.addrsig_sym _Z27__device_stub__kernelMaxOptIfEvPKT_PS0_mmjb
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9kernelMaxIfLj256EEvPKT_PS0_m
	.addrsig_sym _Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z9kernelMaxIfLj256EEvPKT_PS0_m,"axG",@progbits,_Z9kernelMaxIfLj256EEvPKT_PS0_m,comdat
	.protected	_Z9kernelMaxIfLj256EEvPKT_PS0_m ; -- Begin function _Z9kernelMaxIfLj256EEvPKT_PS0_m
	.globl	_Z9kernelMaxIfLj256EEvPKT_PS0_m
	.p2align	8
	.type	_Z9kernelMaxIfLj256EEvPKT_PS0_m,@function
_Z9kernelMaxIfLj256EEvPKT_PS0_m:        ; @_Z9kernelMaxIfLj256EEvPKT_PS0_m
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x10
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr6_sgpr7
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_u64_e64 s[4:5], v[0:1]
	s_xor_b32 s2, exec_lo, s2
; %bb.1:                                ; %.._crit_edge_crit_edge
	s_add_u32 s6, s0, 24
	s_addc_u32 s7, s1, 0
	s_mov_b32 s9, -1
	s_mov_b32 s10, 0xfe967699
; %bb.2:                                ; %Flow41
	s_or_saveexec_b32 s8, s2
	s_load_b64 s[2:3], s[0:1], 0x8
	v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s9
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	s_xor_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x24
	s_mul_i32 s9, s15, s5
	s_mul_hi_u32 s11, s15, s4
	s_mul_i32 s10, s15, s4
	s_add_i32 s11, s11, s9
	v_mov_b32_e32 v4, v1
	s_lshl_b64 s[10:11], s[10:11], 2
	v_dual_mov_b32 v5, 0xfe967699 :: v_dual_mov_b32 v6, -1
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
	v_mov_b32_e32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s9, s6, s10
	s_addc_u32 s10, s7, s11
	s_add_u32 s6, s0, 24
	s_addc_u32 s7, s1, 0
	s_and_b32 s11, s12, 0xffff
	s_mov_b32 s1, 0
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s9, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v5
	v_dual_cndmask_b32 v6, v6, v1 :: v_dual_cndmask_b32 v5, v5, v3
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_cmp_le_u64_e64 s0, s[4:5], v[1:2]
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow40
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
.LBB0_6:                                ; %Flow42
	s_or_b32 exec_lo, exec_lo, s8
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b32 s0, exec_lo
	ds_store_2addr_stride64_b32 v1, v6, v5 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_u16 v2, v[2:3], off offset:12
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u16_e32 1, v2
	s_cbranch_execz .LBB0_12
; %bb.7:                                ; %.lr.ph36.preheader
	v_lshrrev_b16 v3, 1, v2
	v_add_nc_u32_e32 v2, 0x400, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_and_b32_e32 v3, 0xffff, v3
.LBB0_8:                                ; %.lr.ph36
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v0, v3
	s_cbranch_execz .LBB0_11
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	v_lshl_add_u32 v4, v3, 2, v2
	ds_load_b32 v4, v4
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v4, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	v_lshl_add_u32 v5, v3, 2, v1
	ds_load_b32 v5, v5
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v1, v5
.LBB0_11:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_lshrrev_b32_e32 v4, 1, v3
	v_cmp_gt_u32_e32 vcc_lo, 2, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mov_b32_e32 v3, v4
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_8
.LBB0_12:                               ; %Flow39
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_mov_b32_e32 v3, 0
	s_lshl_b32 s0, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s2, s0
	ds_load_2addr_stride64_b32 v[0:1], v3 offset1:4
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v2, v0
	global_store_b64 v3, v[1:2], s[0:1]
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9kernelMaxIfLj256EEvPKT_PS0_m
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z9kernelMaxIfLj256EEvPKT_PS0_m,"axG",@progbits,_Z9kernelMaxIfLj256EEvPKT_PS0_m,comdat
.Lfunc_end0:
	.size	_Z9kernelMaxIfLj256EEvPKT_PS0_m, .Lfunc_end0-_Z9kernelMaxIfLj256EEvPKT_PS0_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 604
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z12kernelMaxOptIfEvPKT_PS0_mmjb,"axG",@progbits,_Z12kernelMaxOptIfEvPKT_PS0_mmjb,comdat
	.protected	_Z12kernelMaxOptIfEvPKT_PS0_mmjb ; -- Begin function _Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.globl	_Z12kernelMaxOptIfEvPKT_PS0_mmjb
	.p2align	8
	.type	_Z12kernelMaxOptIfEvPKT_PS0_mmjb,@function
_Z12kernelMaxOptIfEvPKT_PS0_mmjb:       ; @_Z12kernelMaxOptIfEvPKT_PS0_mmjb
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x8
	s_add_u32 s10, s0, 40
	s_addc_u32 s11, s1, 0
	s_mov_b64 s[12:13], 0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u64 s[4:5], 0
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s14, s[10:11], 0xc
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mov_b32 s17, 0
	v_dual_mov_b32 v4, -1 :: v_dual_lshlrev_b32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s14, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s16, s15, s14
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s16, v0
	s_lshl_b64 s[16:17], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s14, s16, s2
	s_addc_u32 s3, s17, s3
	v_cmp_gt_u64_e64 s2, s[6:7], v[1:2]
	v_add_co_u32 v2, s14, s14, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s3, 0, s14
	v_mov_b32_e32 v1, 0xfe967699
	s_lshl_b64 s[16:17], s[6:7], 2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v5, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v5, v1
	v_cndmask_b32_e64 v4, v4, s12, vcc_lo
	v_cndmask_b32_e32 v1, v1, v5, vcc_lo
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	v_add_co_u32 v2, vcc_lo, v2, s16
	v_cmp_ge_u64_e64 s3, s[12:13], s[4:5]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_2
	s_branch .LBB1_6
.LBB1_5:
	v_dual_mov_b32 v1, 0xfe967699 :: v_dual_mov_b32 v4, -1
.LBB1_6:                                ; %Flow53
	s_load_b32 s2, s[10:11], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[6:7], v[2:3]
	s_cbranch_execz .LBB1_11
; %bb.7:
	s_load_b64 s[0:1], s[0:1], 0x20
	v_lshlrev_b32_e32 v2, 1, v2
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s1, 0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_mov_b32 s1, -1
	s_cbranch_vccnz .LBB1_9
; %bb.8:
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v1, v0
	s_or_not1_b32 s1, vcc_lo, exec_lo
.LBB1_9:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_11
; %bb.10:                               ; %._crit_edge34
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v3, vcc_lo
	v_add_nc_u32_e32 v2, s0, v4
	global_store_b64 v[5:6], v[1:2], off
.LBB1_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12kernelMaxOptIfEvPKT_PS0_mmjb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z12kernelMaxOptIfEvPKT_PS0_mmjb,"axG",@progbits,_Z12kernelMaxOptIfEvPKT_PS0_mmjb,comdat
.Lfunc_end1:
	.size	_Z12kernelMaxOptIfEvPKT_PS0_mmjb, .Lfunc_end1-_Z12kernelMaxOptIfEvPKT_PS0_mmjb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 20
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9kernelMaxIfLj256EEvPKT_PS0_m
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9kernelMaxIfLj256EEvPKT_PS0_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           1
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12kernelMaxOptIfEvPKT_PS0_mmjb
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z12kernelMaxOptIfEvPKT_PS0_mmjb.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
