#include <iostream>
#include <math.h>


// Kernel function to add the elements of two arrays


__global__
void haversine(int n, float *x, float *y)
{


  //int index = threadIdx.x;
  //int stride = blockDim.x;
 // for (int i = index; i < n; i += stride)
  
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  
  float R = 6378.137;
  float toRad = 3.14159/180;
  
  for (int i = index; i < n; i += stride) {
    // y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
    
    float lon1 = x[i];
    float lon2 = x[i];
    float lat1 = y[i];
    float lat2 = y[i];
            
    lon1 = lon1 * toRad;
    lon2 = lon2 * toRad;
    lat1 = lat1 * toRad;
    lat2 = lat2 * toRad;
    float dlon = lon2 - lon1;
    float dlat = lat2 - lat1;
            
    double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
    double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
    x[i] = float(d);
    }
}

int main(void)
{
  int N = pow(2,30);
  std::cout << "In: " << N << std::endl;

  float *x, *y;

  // Allocate Unified Memory – accessible from CPU or GPU
  cudaMallocManaged(&x, N*sizeof(float));
  cudaMallocManaged(&y, N*sizeof(float));

  // initialize x and y arrays on the host
  for (int i = 0; i < N; i++) {
    x[i] = 1.0f;
    y[i] = 2.0f;
  }

  // Run kernel on 1M elements on the GPU
  // int blockSize = 1024;
  // int numBlocks = (N + blockSize - 1) / blockSize;
  // haversine<<<numBlocks, blockSize>>>(N, x, y);
  //add<<<1,1>>>(N, x, y);
  
  int blockSize = 256;
  int numBlocks = (N + blockSize - 1) / blockSize;
  std::cout << numBlocks << std::endl;
  
  for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute 
    haversine<<<numBlocks, blockSize>>>(N, x, y);
  }
  // Wait for GPU to finish before accessing on host
  cudaDeviceSynchronize();

  std::cout << "First: " << x[0] << std::endl;

  // Free memory
  cudaFree(x);
  cudaFree(y);
  
  return 0;
}
	.file	"tmpxft_002b531d_00000000-6_array.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z9haversineiPfS_iPfS_
	.type	_Z31__device_stub__Z9haversineiPfS_iPfS_, @function
_Z31__device_stub__Z9haversineiPfS_iPfS_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9haversineiPfS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z31__device_stub__Z9haversineiPfS_iPfS_, .-_Z31__device_stub__Z9haversineiPfS_iPfS_
	.globl	_Z9haversineiPfS_
	.type	_Z9haversineiPfS_, @function
_Z9haversineiPfS_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9haversineiPfS_iPfS_
	.cfi_endproc
.LFE3662:
	.size	_Z9haversineiPfS_, .-_Z9haversineiPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"In: "
.LC3:
	.string	"First: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	$1, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	_ZSt4cout(%rip), %rbx
	salq	$32, %rbp
	movq	%rbx, %rdi
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1073741824, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rsp, %rdi
	movl	$1, %edx
	movq	%rbp, %rsi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rcx
	movq	8(%rsp), %rdx
	xorl	%eax, %eax
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
.L9:
	movss	%xmm1, (%rcx,%rax)
	movss	%xmm0, (%rdx,%rax)
	addq	$4, %rax
	cmpq	%rbp, %rax
	jne	.L9
	movl	$4194304, %esi
	movq	%rbx, %rdi
	movl	$999, %ebp
	movabsq	$4294967552, %r12
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L11:
	movl	$1025, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	salq	$22, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r12, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rdx
	movq	(%rsp), %rsi
	movl	$1073741824, %edi
	call	_Z31__device_stub__Z9haversineiPfS_iPfS_
.L10:
	decl	%ebp
	jne	.L11
	call	cudaDeviceSynchronize@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%rsp), %rax
	cvtss2sd	(%rax), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z9haversineiPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9haversineiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	1073741824
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>


// Kernel function to add the elements of two arrays


__global__
void haversine(int n, float *x, float *y)
{


  //int index = threadIdx.x;
  //int stride = blockDim.x;
 // for (int i = index; i < n; i += stride)
  
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  
  float R = 6378.137;
  float toRad = 3.14159/180;
  
  for (int i = index; i < n; i += stride) {
    // y[i] = atan(sqrt(x[i])) * sin(sqrt(y[i])) *4;
    
    float lon1 = x[i];
    float lon2 = x[i];
    float lat1 = y[i];
    float lat2 = y[i];
            
    lon1 = lon1 * toRad;
    lon2 = lon2 * toRad;
    lat1 = lat1 * toRad;
    lat2 = lat2 * toRad;
    float dlon = lon2 - lon1;
    float dlat = lat2 - lat1;
            
    double a = pow(sin(dlat / 2), 2) + (cos(lat1) * cos(lat2) * pow(sin(dlon / 2),2));
    double d = 2 * atan2(sqrt(a), sqrt(1 - a)) * R;
    x[i] = float(d);
    }
}

int main(void)
{
  int N = pow(2,30);
  std::cout << "In: " << N << std::endl;

  float *x, *y;

  // Allocate Unified Memory – accessible from CPU or GPU
  hipMallocManaged(&x, N*sizeof(float));
  hipMallocManaged(&y, N*sizeof(float));

  // initialize x and y arrays on the host
  for (int i = 0; i < N; i++) {
    x[i] = 1.0f;
    y[i] = 2.0f;
  }

  // Run kernel on 1M elements on the GPU
  // int blockSize = 1024;
  // int numBlocks = (N + blockSize - 1) / blockSize;
  // haversine<<<numBlocks, blockSize>>>(N, x, y);
  //add<<<1,1>>>(N, x, y);
  
  int blockSize = 256;
  int numBlocks = (N + blockSize - 1) / blockSize;
  std::cout << numBlocks << std::endl;
  
  for (int z = 1; z < 1000; z++) { // Run 1000 calls to function to fill GPU for ~1 minute 
    haversine<<<numBlocks, blockSize>>>(N, x, y);
  }
  // Wait for GPU to finish before accessing on host
  hipDeviceSynchronize();

  std::cout << "First: " << x[0] << std::endl;

  // Free memory
  hipFree(x);
  hipFree(y);
  
  return 0;
}
	.text
	.file	"array.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__haversineiPfS_ # -- Begin function _Z24__device_stub__haversineiPfS_
	.type	_Z24__device_stub__haversineiPfS_,@function
_Z24__device_stub__haversineiPfS_:      # @_Z24__device_stub__haversineiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9haversineiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__haversineiPfS_, .Lfunc_end0-_Z24__device_stub__haversineiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967296, %rbx               # imm = 0x100000000
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$1073741824, %esi               # imm = 0x40000000
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r14), %rax
	xorl	%ecx, %ecx
	movq	(%r15), %rdx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rcx,4)      # imm = 0x3F800000
	movl	$1073741824, (%rdx,%rcx,4)      # imm = 0x40000000
	incq	%rcx
	cmpq	$1073741824, %rcx               # imm = 0x40000000
	jne	.LBB1_1
# %bb.2:
	movl	$_ZSt4cout, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$999, %ebp                      # imm = 0x3E7
	leaq	256(%rbx), %r14
	addq	$4194304, %rbx                  # imm = 0x400000
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$1073741824, %edi               # imm = 0x40000000
	callq	_Z24__device_stub__haversineiPfS_
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	decl	%ebp
	jne	.LBB1_3
# %bb.6:
	callq	hipDeviceSynchronize
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rax
	cvtss2sd	(%rax), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9haversineiPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9haversineiPfS_,@object       # @_Z9haversineiPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z9haversineiPfS_
	.p2align	3, 0x0
_Z9haversineiPfS_:
	.quad	_Z24__device_stub__haversineiPfS_
	.size	_Z9haversineiPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"In: "
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"First: "
	.size	.L.str.1, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9haversineiPfS_"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__haversineiPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9haversineiPfS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9haversineiPfS_       ; -- Begin function _Z9haversineiPfS_
	.globl	_Z9haversineiPfS_
	.p2align	8
	.type	_Z9haversineiPfS_,@function
_Z9haversineiPfS_:                      ; @_Z9haversineiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s33, s[0:1], 0x0
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s18, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s33, v1
	s_cbranch_execz .LBB0_19
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s19, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v0, 0x7f3321d2
	v_mov_b32_e32 v8, 0x4002d97c
	s_mov_b32 s2, 0xbd3237f4
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_mov_b32 s8, 0xb5e68a13
	s_mov_b32 s10, 0x69efb384
	s_mov_b32 s12, 0xaf56de9b
	s_mov_b32 s14, 0xa595c56f
	s_mov_b32 s16, 0xa57d9582
	s_mov_b32 s20, 0x5f08b19f
	s_mov_b32 s24, 0xfc27006a
	s_mov_b32 s26, 0x5711927a
	s_mov_b32 s28, 0xe82d3ff0
	s_mov_b32 s30, 0x6ef28734
	s_mov_b32 s34, 0x6a214619
	s_mov_b32 s36, 0x8427b883
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s18, s19, s18
	s_mov_b32 s38, 0x8b207f05
	s_ashr_i32 s19, s18, 31
	s_mov_b32 s40, 0x57b87036
	s_mov_b32 s42, 0x19378e4f
	s_mov_b32 s44, 0x17e1913c
	s_mov_b32 s46, 0x92376b7d
	s_mov_b32 s48, 0x999952cc
	s_mov_b32 s50, 0x55555523
	s_mov_b32 s52, 0x54442d18
	s_brev_b32 s54, 4
	s_mov_b32 s58, 0
	s_mov_b32 s59, 0x7fffff
	s_mov_b32 s60, 0xb94c1982
	s_mov_b32 s3, 0xbf23e260
	s_mov_b32 s9, 0x3eeba404
	s_mov_b32 s11, 0x3f4b2bb0
	s_mov_b32 s13, 0xbf67952d
	s_mov_b32 s15, 0x3f7d6d43
	s_mov_b32 s17, 0xbf8c6ea4
	s_mov_b32 s21, 0x3f967e29
	s_lshl_b64 s[22:23], s[18:19], 2
	s_mov_b32 s25, 0xbf9e9ae6
	s_mov_b32 s27, 0x3fa2c15b
	s_mov_b32 s29, 0xbfa59976
	s_mov_b32 s31, 0x3fa82d5d
	s_mov_b32 s35, 0xbfaae5ce
	s_mov_b32 s37, 0x3fae1bb4
	s_mov_b32 s39, 0xbfb110e4
	s_mov_b32 s41, 0x3fb3b136
	s_mov_b32 s43, 0xbfb745d1
	s_mov_b32 s45, 0x3fbc71c7
	s_mov_b32 s47, 0xbfc24924
	s_mov_b32 s49, 0x3fc99999
	s_mov_b32 s51, 0xbfd55555
	s_mov_b32 s53, 0x3ff921fb
	s_mov_b32 s55, 0x40b8ea23
	s_mov_b32 s19, 0x37d75334
	s_mov_b32 s61, 0x3e76c4e1
	s_mov_b32 s57, 0x400921fb
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_mov_b32 s1, exec_lo
	global_load_b32 v4, v[6:7], off
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v18, v[6:7], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v9, 0x3c8efa2d, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0x3c8efa2d, v4, -v9
	v_mul_f32_e32 v11, 0.5, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v12, 0x7fffffff, v11
	v_cmpx_ngt_f32_e64 0x48000000, |v11|
	s_xor_b32 s56, exec_lo, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v10, v12, s59, 0x800000
	v_lshrrev_b32_e32 v19, 23, v12
	v_mad_u64_u32 v[13:14], null, 0xfe5163ab, v10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v14
	v_mad_u64_u32 v[14:15], null, 0x3c439041, v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v15
	v_mad_u64_u32 v[15:16], null, 0xdb629599, v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v16
	v_mad_u64_u32 v[16:17], null, 0xf534ddc0, v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v17 :: v_dual_add_nc_u32 v17, 0xffffff88, v19
	v_mad_u64_u32 v[19:20], null, 0xfc2757d1, v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v4, v20
	v_dual_cndmask_b32 v14, v16, v14 :: v_dual_cndmask_b32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, v21, v17
	v_mad_u64_u32 v[20:21], null, 0x4e441529, v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v17
	v_mov_b32_e32 v4, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v22, 0, 0xffffffe0, s0
	v_cndmask_b32_e64 v13, v14, v13, s0
	v_add_nc_u32_e32 v17, v22, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[21:22], null, 0xa2f9836e, v10, v[4:5]
	v_cndmask_b32_e32 v10, v20, v16, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v21, v19, vcc_lo
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v20, v22, v20 :: v_dual_cndmask_b32 v19, v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v21, v10, s0
	v_add_nc_u32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v20, v21, s0
	v_cndmask_b32_e64 v10, v10, v19, s0
	v_cndmask_b32_e64 v19, v19, v14, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v20, 32, v4
	v_cndmask_b32_e64 v17, v17, v16, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, v10, s1
	v_cndmask_b32_e64 v10, v10, v19, s1
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v13, v19, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v21, v17, v16, v20
	v_alignbit_b32 v15, v16, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v10, v13, v20
	v_cndmask_b32_e32 v4, v21, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v15, v16, vcc_lo
	v_cndmask_b32_e32 v10, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v16, v4, 29, 1
	v_alignbit_b32 v15, v4, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v14, v10, 30
	v_alignbit_b32 v10, v10, v13, 30
	v_sub_nc_u32_e32 v17, 0, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v15, v17
	v_xor_b32_e32 v13, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v17
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v14, 31, v19
	v_lshlrev_b32_e32 v21, 23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v13, v14
	v_alignbit_b32 v10, v13, v10, v14
	v_lshrrev_b32_e32 v14, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	v_alignbit_b32 v13, v15, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v14, 31, v14
	v_lshrrev_b32_e32 v15, 9, v15
	v_add_nc_u32_e32 v16, v16, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v17, v13
	v_or_b32_e32 v20, 0.5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v22, 31, v17
	v_alignbit_b32 v10, v13, v10, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v13, v15, v20
	v_add_lshl_u32 v15, v17, v19, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x3fc90fda, v13
	v_sub_nc_u32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3fc90fda, v13, -v17
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, 0x33a22168, v13
	v_or_b32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0x3fc90fda, v10
	v_add_f32_e32 v15, v17, v15
.LBB0_4:                                ; %Flow77
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s56
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v11|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v4
	v_fma_f32 v15, 0xbfc90fda, v4, |v11|
	v_cvt_i32_f32_e32 v16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0xb3a22168, v4
	v_fmac_f32_e32 v15, 0xa7c234c4, v4
; %bb.6:                                ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v4, 0x7fffffff, v9
	v_cmp_ngt_f32_e64 s56, 0x48000000, |v9|
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 23, v4
	v_and_or_b32 v19, v4, s59, 0x800000
	v_add_nc_u32_e32 v20, 0xffffff88, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s56
	s_xor_b32 s62, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[13:14], null, 0xfe5163ab, v19, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v20
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v14
	v_add_nc_u32_e32 v10, v10, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[21:22], null, 0x3c439041, v19, v[4:5]
	v_cmp_lt_u32_e64 s0, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v22
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, 0xdb629599, v19, v[4:5]
	v_add_nc_u32_e32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v10
	v_dual_mov_b32 v4, v23 :: v_dual_cndmask_b32 v13, v22, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, 0xf534ddc0, v19, v[4:5]
	v_mov_b32_e32 v4, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0xfc2757d1, v19, v[4:5]
	v_mov_b32_e32 v4, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0x4e441529, v19, v[4:5]
	v_mov_b32_e32 v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v25, v23, vcc_lo
	v_mad_u64_u32 v[26:27], null, 0xa2f9836e, v19, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v26, v24 :: v_dual_add_nc_u32 v4, v4, v10
	v_dual_cndmask_b32 v25, v27, v25 :: v_dual_cndmask_b32 v24, v24, v22
	v_cndmask_b32_e32 v10, v23, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v23, 32, v4
	v_cndmask_b32_e64 v21, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v25, v17, s0
	v_cndmask_b32_e64 v14, v14, v24, s0
	v_cndmask_b32_e64 v24, v24, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v10, v10, v13, s0
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v21, v21, v14, s1
	v_cndmask_b32_e64 v14, v14, v24, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v24, v10, s1
	v_alignbit_b32 v25, v17, v21, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v21, v14, v23
	v_alignbit_b32 v23, v14, v10, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v25, v17, vcc_lo
	v_dual_cndmask_b32 v13, v22, v21 :: v_dual_cndmask_b32 v14, v23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v17, v4, 29, 1
	v_alignbit_b32 v21, v4, v13, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v13, v13, v14, 30
	v_alignbit_b32 v10, v14, v10, 30
	v_sub_nc_u32_e32 v22, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v21, v21, v22
	v_xor_b32_e32 v13, v13, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v22
	v_clz_i32_u32_e32 v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v23, 32, v23
	v_sub_nc_u32_e32 v14, 31, v23
	v_lshlrev_b32_e32 v25, 23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v21, v13, v14
	v_alignbit_b32 v10, v13, v10, v14
	v_lshrrev_b32_e32 v14, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	v_alignbit_b32 v13, v21, v10, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 31, v14
	v_lshrrev_b32_e32 v21, 9, v21
	v_clz_i32_u32_e32 v22, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, 0.5, v14
	v_min_u32_e32 v22, 32, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, v24, v25
	v_sub_nc_u32_e32 v26, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v13, v10, v26
	v_or_b32_e32 v13, v21, v24
	v_add_lshl_u32 v21, v22, v23, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_mul_f32_e32 v22, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v21
	v_fma_f32 v21, 0x3fc90fda, v13, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fmac_f32_e32 v21, 0x33a22168, v13
	v_add_nc_u32_e32 v13, v17, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v10, v10, v14
	v_fmac_f32_e32 v21, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v10, v22, v21
.LBB0_8:                                ; %Flow76
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s62
	v_mul_f32_e64 v4, 0x3f22f983, |v9|
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v4, v4
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0xbfc90fda, v4, |v9|
	v_cvt_i32_f32_e32 v13, v4
	v_fmac_f32_e32 v10, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0xa7c234c4, v4
; %bb.10:                               ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s0, s56
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s56, exec_lo, s0
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[21:22], null, 0xfe5163ab, v19, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v20
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v22
	v_add_nc_u32_e32 v14, v14, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, 0x3c439041, v19, v[4:5]
	v_cmp_lt_u32_e64 s0, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v23
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[23:24], null, 0xdb629599, v19, v[4:5]
	v_add_nc_u32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v14
	v_dual_mov_b32 v4, v24 :: v_dual_cndmask_b32 v21, v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0xf534ddc0, v19, v[4:5]
	v_mov_b32_e32 v4, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0xfc2757d1, v19, v[4:5]
	v_mov_b32_e32 v4, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, 0x4e441529, v19, v[4:5]
	v_dual_mov_b32 v4, v27 :: v_dual_cndmask_b32 v17, v26, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[27:28], null, 0xa2f9836e, v19, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v19, v27, v25 :: v_dual_add_nc_u32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, v28, v26 :: v_dual_cndmask_b32 v25, v25, v23
	v_cndmask_b32_e32 v14, v24, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v19, v17, s0
	v_cndmask_b32_e64 v19, v20, v19, s0
	v_cndmask_b32_e64 v17, v17, v25, s0
	v_sub_nc_u32_e32 v20, 32, v4
	v_cndmask_b32_e64 v24, v25, v14, s0
	v_cndmask_b32_e64 v14, v14, v21, s0
	v_cndmask_b32_e64 v19, v19, v22, s1
	v_cndmask_b32_e64 v22, v22, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v24, s1
	v_cndmask_b32_e64 v14, v24, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v25, v19, v22, v20
	v_alignbit_b32 v23, v22, v17, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v17, v14, v20
	v_dual_cndmask_b32 v4, v25, v19 :: v_dual_cndmask_b32 v19, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v20, v17, vcc_lo
	v_bfe_u32 v21, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v4, v19, 30
	v_alignbit_b32 v19, v19, v17, 30
	v_alignbit_b32 v14, v17, v14, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 0, v21
	v_xor_b32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, v19, v23
	v_xor_b32_e32 v14, v14, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v22
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v25, 23, v20
	v_sub_nc_u32_e32 v19, 31, v20
	v_alignbit_b32 v22, v22, v17, v19
	v_alignbit_b32 v14, v17, v14, v19
	v_lshrrev_b32_e32 v19, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v22, v14, 9
	v_lshlrev_b32_e32 v19, 31, v19
	v_lshrrev_b32_e32 v22, 9, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v23, v17
	v_or_b32_e32 v24, 0.5, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v23, 32, v23
	v_sub_nc_u32_e32 v24, v24, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, 31, v23
	v_add_lshl_u32 v20, v23, v20, 23
	v_alignbit_b32 v14, v17, v14, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v22, v24
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x3fc90fda, v17
	v_sub_nc_u32_e32 v14, v14, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0x3fc90fda, v17, -v22
	v_add_nc_u32_e32 v14, 0x33000000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, 0x33a22168, v17 :: v_dual_add_nc_u32 v17, v21, v4
                                        ; implicit-def: $vgpr4
	v_or_b32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0x3fc90fda, v14
	v_add_f32_e32 v14, v22, v20
.LBB0_12:                               ; %Flow75
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s56
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	v_fma_f32 v14, 0xbfc90fda, v4, |v9|
	v_cvt_i32_f32_e32 v17, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0xb3a22168, v4
	v_fmac_f32_e32 v14, 0xa7c234c4, v4
; %bb.14:                               ; %_ZL3cosf.exit46
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, 0x3c8efa2d, v18
                                        ; implicit-def: $vgpr20
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0x3c8efa2d, v18, -v4
	v_mul_f32_e32 v18, 0.5, v4
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v19, 0x7fffffff, v18
	v_cmpx_ngt_f32_e64 0x48000000, |v18|
	s_xor_b32 s56, exec_lo, s1
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v25, 23, v19
	v_and_or_b32 v28, v19, s59, 0x800000
	v_add_nc_u32_e32 v26, 0xffffff88, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfe5163ab, v28, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v26
	v_cndmask_b32_e64 v27, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v21 :: v_dual_add_nc_u32 v27, v27, v26
	v_mad_u64_u32 v[21:22], null, 0x3c439041, v28, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v27
	v_cndmask_b32_e64 v29, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v22 :: v_dual_add_nc_u32 v29, v29, v27
	v_mad_u64_u32 v[22:23], null, 0xdb629599, v28, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v29
	v_mov_b32_e32 v4, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v22, v20, vcc_lo
	v_mad_u64_u32 v[23:24], null, 0xf534ddc0, v28, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v24 :: v_dual_cndmask_b32 v21, v23, v21
	v_mad_u64_u32 v[24:25], null, 0xfc2757d1, v28, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v20, v21, v20, s0
	v_mov_b32_e32 v4, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0x4e441529, v28, v[4:5]
	v_mov_b32_e32 v4, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[26:27], null, 0xa2f9836e, v28, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v28, v25, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, v4, v29
	v_dual_cndmask_b32 v26, v26, v24 :: v_dual_cndmask_b32 v25, v27, v25
	v_cndmask_b32_e32 v24, v24, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v27, 32, v4
	v_cndmask_b32_e64 v23, v26, v28, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v25, v26, s0
	v_cndmask_b32_e64 v26, v28, v24, s0
	v_cndmask_b32_e64 v24, v24, v21, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v25, v23, s1
	v_cndmask_b32_e64 v23, v23, v26, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v26, v24, s1
	v_cndmask_b32_e64 v20, v24, v20, s1
	v_alignbit_b32 v28, v25, v23, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v22, v23, v26, v27
	v_dual_cndmask_b32 v4, v28, v25 :: v_dual_cndmask_b32 v21, v22, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v25, v26, v20, v27
	v_bfe_u32 v22, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v4, v21, 30
	v_cndmask_b32_e32 v25, v25, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, 0, v22
	v_alignbit_b32 v21, v21, v25, 30
	v_alignbit_b32 v20, v25, v20, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v23, v23, v24
	v_xor_b32_e32 v21, v21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v20, v24
	v_lshrrev_b32_e32 v24, 29, v4
	v_clz_i32_u32_e32 v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v24, 31, v24
	v_min_u32_e32 v26, 32, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v27, 0.5, v24
	v_sub_nc_u32_e32 v25, 31, v26
	v_lshlrev_b32_e32 v28, 23, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v23, v21, v25
	v_alignbit_b32 v20, v21, v20, v25
	v_sub_nc_u32_e32 v27, v27, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v23, v20, 9
	v_lshrrev_b32_e32 v23, 9, v23
	v_clz_i32_u32_e32 v25, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v25, 32, v25
	v_sub_nc_u32_e32 v29, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v21, v20, v29
	v_or_b32_e32 v21, v23, v27
	v_add_lshl_u32 v23, v25, v26, 23
	v_lshrrev_b32_e32 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, 0x3fc90fda, v21
	v_sub_nc_u32_e32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0x3fc90fda, v21, -v25
	v_add_nc_u32_e32 v20, 0x33000000, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, 0x33a22168, v21
	v_or_b32_e32 v20, v20, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, 0x3fc90fda, v20
	v_lshrrev_b32_e32 v20, 30, v4
	v_add_f32_e32 v4, v25, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v20, v22, v20
.LBB0_16:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s56
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v18|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v20, v4
	v_fma_f32 v4, 0xbfc90fda, v20, |v18|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, 0xb3a22168, v20
	v_fmac_f32_e32 v4, 0xa7c234c4, v20
	v_cvt_i32_f32_e32 v20, v20
; %bb.18:                               ; %_ZL3sinf.exit54
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v21, v15, v15 :: v_dual_and_b32 v22, 1, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v23, v4, v4
	v_lshlrev_b32_e32 v16, 30, v16
	v_xor_b32_e32 v12, v12, v11
	v_fmaak_f32 v25, s19, v21, 0xbab64f3b
	v_fmaak_f32 v24, s60, v21, 0x3c0881c4
	v_dual_fmaak_f32 v27, s19, v23, 0xbab64f3b :: v_dual_and_b32 v28, 1, v20
	v_cmp_eq_u32_e32 vcc_lo, 0, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v25, v21, v25, 0x3d2aabf7 :: v_dual_lshlrev_b32 v20, 30, v20
	v_fmaak_f32 v24, v21, v24, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v27, v23, v27, 0x3d2aabf7
	v_and_b32_e32 v16, 0x80000000, v16
	v_fmaak_f32 v25, v21, v25, 0xbf000004
	v_and_b32_e32 v20, 0x80000000, v20
	v_mul_f32_e32 v24, v21, v24
	v_fmaak_f32 v26, s60, v23, 0x3c0881c4
	v_xor_b32_e32 v19, v19, v18
	v_fma_f32 v21, v21, v25, 1.0
	s_mov_b32 s56, s52
	v_fmac_f32_e32 v15, v15, v24
	v_dual_fmaak_f32 v26, v23, v26, 0xbe2aaa9d :: v_dual_add_nc_u32 v1, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v21, v15 :: v_dual_mul_f32 v26, v23, v26
	v_fmaak_f32 v27, v23, v27, 0xbf000004
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	v_xor3_b32 v12, v12, v16, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v4, v26
	v_fma_f32 v23, v23, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v23, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x1f8
	v_xor3_b32 v4, v19, v20, v4
	v_cndmask_b32_e32 v11, 0x7fc00000, v12, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v18, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	v_frexp_mant_f32_e64 v15, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v15
	v_cndmask_b32_e64 v18, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v15, v15, v18
	v_add_f32_e32 v18, 1.0, v15
	v_frexp_mant_f32_e64 v12, |v11|
	v_add_f32_e32 v22, -1.0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v18
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v12
	v_add_f32_e32 v27, -1.0, v18
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v15, v15, v27 :: v_dual_mul_f32 v24, v22, v20
	v_ldexp_f32 v12, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, v18, v24
	v_add_f32_e32 v21, -1.0, v12
	v_add_f32_e32 v16, 1.0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v24, v18, -v28
	v_rcp_f32_e32 v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v24, v15
	v_add_f32_e32 v15, v28, v18
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v23, v21, v19
	v_add_f32_e32 v25, -1.0, v16
	v_dual_sub_f32 v27, v22, v15 :: v_dual_sub_f32 v28, v15, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, v16, v23
	v_frexp_exp_i32_f32_e32 v30, v4
	v_sub_f32_e32 v22, v22, v27
	v_sub_f32_e32 v12, v12, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v23, v16, -v26
	v_dual_sub_f32 v18, v28, v18 :: v_dual_sub_f32 v15, v22, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v23, v12 :: v_dual_add_f32 v15, v18, v15
	v_dual_add_f32 v12, v26, v16 :: v_dual_add_f32 v15, v27, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v21, v12
	v_mul_f32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v21, v25 :: v_dual_add_f32 v18, v24, v15
	v_sub_f32_e32 v20, v18, v24
	v_sub_f32_e32 v26, v12, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v21, v12
	v_sub_f32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v26, v16
	v_add_f32_e32 v24, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v16, v12
	v_add_f32_e32 v12, v25, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v19, v12
	v_add_f32_e32 v16, v23, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v16, v23
	v_mul_f32_e32 v21, v16, v16
	v_dual_sub_f32 v12, v12, v19 :: v_dual_mul_f32 v19, v18, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, v16, v16, -v21
	v_fma_f32 v23, v18, v18, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v23, v18, v24
	v_add_f32_e32 v22, v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v24, v19, v23
	v_dual_fmaak_f32 v26, s61, v24, 0x3e91f4c4 :: v_dual_sub_f32 v19, v24, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v26, v24, v26, 0x3ecccdef :: v_dual_sub_f32 v19, v23, v19
	v_mul_f32_e32 v28, v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v24, v26, -v28
	v_fmac_f32_e32 v23, v19, v26
	v_dual_fmac_f32 v20, v16, v22 :: v_dual_mul_f32 v31, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v21, v20
	v_fmaak_f32 v25, s61, v22, 0x3e91f4c4
	v_sub_f32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v25, v22, v25, 0x3ecccdef
	v_sub_f32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v22, v25
	v_fma_f32 v21, v22, v25, -v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, v20, v25
	v_frexp_exp_i32_f32_e32 v25, v11
	v_add_f32_e32 v29, v27, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v27, v29, v27
	v_sub_f32_e32 v21, v21, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v21, 0x31739010, v21 :: v_dual_mul_f32 v26, v16, v22
	v_fma_f32 v33, v22, v16, -v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v33, v22, v12
	v_fma_f32 v35, v24, v18, -v31
	v_add_f32_e32 v34, 0x3f2aaaaa, v29
	v_ldexp_f32 v12, v12, 1
	v_fmac_f32_e32 v35, v24, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v27, 0xbf2aaaaa, v34 :: v_dual_add_f32 v32, v28, v23
	v_ldexp_f32 v15, v15, 1
	v_fmac_f32_e32 v35, v19, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v29, v27
	v_ldexp_f32 v18, v18, 1
	v_add_f32_e32 v21, v21, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v27, v31, v35 :: v_dual_sub_f32 v28, v32, v28
	v_sub_f32_e32 v31, v27, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v23, v28
	v_fmac_f32_e32 v33, v20, v16
	v_ldexp_f32 v16, v16, 1
	v_add_f32_e32 v20, 0x31739010, v22
	v_add_f32_e32 v36, 0x3f2aaaaa, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, 0xbf2aaaaa, v36
	v_sub_f32_e32 v22, v32, v23
	v_subrev_co_ci_u32_e32 v23, vcc_lo, 0, v25, vcc_lo
	v_subrev_co_ci_u32_e64 v24, vcc_lo, 0, v30, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v19, v20, v22 :: v_dual_add_f32 v22, v34, v21
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v11|
	v_add_f32_e32 v25, v36, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v30, v36, v25
	v_add_f32_e32 v20, v26, v33
	v_mul_f32_e32 v32, v27, v25
	v_add_f32_e32 v19, v19, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v29, v20, v22
	v_fma_f32 v30, v27, v25, -v32
	v_sub_f32_e32 v26, v20, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v27, v19
	v_cvt_f32_i32_e32 v19, v24
	v_sub_f32_e32 v28, v34, v22
	v_add_f32_e32 v21, v21, v28
	v_fma_f32 v28, v20, v22, -v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v28, v20, v21 :: v_dual_sub_f32 v21, v35, v31
	v_cvt_f32_i32_e32 v20, v23
	v_dual_mul_f32 v23, 0x3f317218, v19 :: v_dual_fmac_f32 v30, v21, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v24, v32, v30
	v_dual_sub_f32 v26, v33, v26 :: v_dual_sub_f32 v31, v24, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v26, v22
	v_add_f32_e32 v21, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v26, v16, v21
	v_dual_sub_f32 v27, v21, v29 :: v_dual_sub_f32 v16, v26, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v21, v16
	v_fma_f32 v21, 0x3f317218, v19, -v23
	v_fmac_f32_e32 v21, 0xb102e308, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v22, 0x3f317218, v20 :: v_dual_sub_f32 v27, v28, v27
	v_add_f32_e32 v19, v23, v21
	v_add_f32_e32 v29, v18, v24
	v_sub_f32_e32 v28, v30, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v25, 0x3f317218, v20, -v22
	v_add_f32_e32 v12, v12, v27
	v_dual_sub_f32 v23, v19, v23 :: v_dual_sub_f32 v18, v29, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v15, v15, v28
	v_fmac_f32_e32 v25, 0xb102e308, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v21, v23 :: v_dual_sub_f32 v18, v24, v18
	v_add_f32_e32 v15, v15, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v29, v15
	v_sub_f32_e32 v29, v20, v29
	v_add_f32_e32 v12, v12, v16
	v_add_f32_e32 v16, v22, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v29 :: v_dual_add_f32 v18, v26, v12
	v_add_f32_e32 v24, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v28, v24, v16
	v_sub_f32_e32 v23, v24, v28
	v_sub_f32_e32 v22, v16, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v16, v23
	v_sub_f32_e32 v22, v25, v22
	v_sub_f32_e32 v25, v18, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v25
	v_add_f32_e32 v23, v22, v12
	v_add_f32_e32 v27, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v27, v19
	v_sub_f32_e32 v25, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v20, v26 :: v_dual_sub_f32 v19, v19, v25
	v_dual_sub_f32 v18, v18, v28 :: v_dual_add_f32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v18, v16
	v_add_f32_e32 v18, v21, v15
	v_dual_sub_f32 v20, v23, v22 :: v_dual_sub_f32 v25, v18, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v18, v19
	v_sub_f32_e32 v18, v18, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v25 :: v_dual_sub_f32 v18, v21, v18
	v_add_f32_e32 v15, v15, v18
	v_add_f32_e32 v16, v23, v16
	v_sub_f32_e32 v23, v23, v20
	v_sub_f32_e32 v12, v12, v20
	v_add_f32_e32 v20, v27, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v22, v23
	v_sub_f32_e32 v21, v20, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v19, v21
	v_and_b32_e32 v21, 1, v13
	v_lshlrev_b32_e32 v13, 30, v13
	v_add_f32_e32 v15, v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v13, 0x80000000, v13
	v_add_f32_e32 v19, v20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v19, v20 :: v_dual_mul_f32 v25, 0, v19
	v_sub_f32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v26, v24, v16 :: v_dual_fmac_f32 v25, 2.0, v15
	v_sub_f32_e32 v23, v26, v24
	v_and_b32_e32 v15, 1, v17
	v_dual_add_f32 v12, v12, v22 :: v_dual_lshlrev_b32 v17, 30, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v16, v23 :: v_dual_and_b32 v17, 0x80000000, v17
	v_add_f32_e32 v12, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v26, v12
	v_sub_f32_e32 v22, v16, v26
	v_add_f32_e32 v23, v16, v16
	v_mul_f32_e32 v24, 0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v12, v22
	v_add_f32_e32 v22, v19, v19
	v_fma_f32 v16, v16, 2.0, -v23
	v_cmp_class_f32_e64 vcc_lo, v23, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v24, 2.0, v12
	v_fma_f32 v19, v19, 2.0, -v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v19, v25 :: v_dual_add_f32 v16, v16, v24
	v_add_f32_e32 v27, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v25, v23, v16 :: v_dual_mul_f32 v12, v14, v14
	v_cndmask_b32_e32 v28, v25, v23, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v22, 0x204
	v_dual_sub_f32 v23, v25, v23 :: v_dual_mul_f32 v18, v10, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v29, s19, v12, 0xbab64f3b
	v_fmaak_f32 v26, s60, v12, 0x3c0881c4
	v_cndmask_b32_e32 v30, v27, v22, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v28
	v_fmaak_f32 v24, s19, v18, 0xbab64f3b
	v_sub_f32_e32 v22, v27, v22
	v_fmaak_f32 v26, v12, v26, 0xbe2aaa9d
	v_fmaak_f32 v29, v12, v29, 0x3d2aabf7
	v_cndmask_b32_e64 v31, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v30
	v_dual_fmaak_f32 v24, v18, v24, 0x3d2aabf7 :: v_dual_sub_f32 v19, v19, v22
	v_sub_f32_e32 v16, v16, v23
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v33, v28, v31
	v_cndmask_b32_e64 v32, 0, 0x37000000, vcc_lo
	v_fmaak_f32 v20, s60, v18, 0x3c0881c4
	v_fmaak_f32 v24, v18, v24, 0xbf000004
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_dual_mul_f32 v35, 0x3fb8aa3b, v33 :: v_dual_mul_f32 v26, v12, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v20, v18, v20, 0xbe2aaa9d
	v_fmaak_f32 v29, v12, v29, 0xbf000004
	v_fma_f32 v37, 0x3fb8aa3b, v33, -v35
	v_rndne_f32_e32 v38, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v20, v18, v20
	v_fma_f32 v18, v18, v24, 1.0
	v_dual_fmac_f32 v14, v14, v26 :: v_dual_fmac_f32 v37, 0x32a5705f, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v35, v35, v38 :: v_dual_fmac_f32 v10, v10, v20
	v_fma_f32 v12, v12, v29, 1.0
	v_add_f32_e32 v26, v35, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v10, v18, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v28|
	v_xor_b32_e32 v10, v13, v10
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v30|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v16, v31, v16 :: v_dual_cndmask_b32 v19, 0, v19
	v_sub_f32_e32 v34, v30, v32
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v33
	v_dual_add_f32 v19, v32, v19 :: v_dual_mul_f32 v36, 0x3fb8aa3b, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0x3fb8aa3b, v34, -v36
	v_rndne_f32_e32 v39, v36
	v_fmac_f32_e32 v20, 0x32a5705f, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v36, v39
	v_cvt_i32_f32_e32 v21, v39
	v_add_f32_e32 v20, v24, v20
	v_exp_f32_e32 v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v18, v20
	v_cvt_i32_f32_e32 v20, v38
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v20, v24, v20
	v_ldexp_f32 v18, v18, v21
	v_cndmask_b32_e32 v20, 0, v20, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v33
	v_cndmask_b32_e32 v20, 0x7f800000, v20, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, 0x7f800000, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_fma_f32 v13, v18, v19, v18
	v_cndmask_b32_e64 v12, -v14, v12, vcc_lo
	v_fma_f32 v14, v20, v16, v20
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v17, v12
	v_cndmask_b32_e32 v14, v14, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v10, v12
	v_cndmask_b32_e64 v12, 0x7f800000, |v14|, s0
	v_cndmask_b32_e32 v13, v13, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x1f8
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
	v_cndmask_b32_e32 v9, 0x7fc00000, v10, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 0x7f800000, |v13|, s0
	v_cndmask_b32_e32 v10, 0, v12, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v4, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v9, v4
	v_cvt_f64_f32_e32 v[9:10], v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], -v[9:10], 1.0
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[9:10]
	v_cmp_gt_f64_e64 s0, 0x10000000, v[11:12]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 8, v4
	v_ldexp_f64 v[9:10], v[9:10], v4
	v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
	v_cndmask_b32_e64 v13, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v13, 8, v13
	v_ldexp_f64 v[11:12], v[11:12], v13
	v_rsq_f64_e32 v[13:14], v[9:10]
	v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x260
	s_delay_alu instid0(VALU_DEP_2)
	v_rsq_f64_e32 v[15:16], v[11:12]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[17:18], v[9:10], v[13:14]
	v_mul_f64 v[13:14], v[13:14], 0.5
	v_mul_f64 v[19:20], v[11:12], v[15:16]
	v_mul_f64 v[15:16], v[15:16], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 0.5
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_fma_f64 v[13:14], v[13:14], v[21:22], v[13:14]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], -v[17:18], v[17:18], v[9:10]
	v_fma_f64 v[15:16], v[15:16], v[23:24], v[15:16]
	v_fma_f64 v[23:24], -v[19:20], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[21:22], v[13:14], v[17:18]
	v_fma_f64 v[19:20], v[23:24], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[17:18], v[17:18], v[9:10]
	v_fma_f64 v[23:24], -v[19:20], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[21:22], v[13:14], v[17:18]
	v_cndmask_b32_e64 v17, 0, 0xffffff80, s0
	v_cmp_class_f64_e64 s0, v[11:12], 0x260
	v_fma_f64 v[15:16], v[23:24], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[13:14], v[13:14], v4
	v_ldexp_f64 v[15:16], v[15:16], v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v10, v14, v10 :: v_dual_cndmask_b32 v9, v13, v9
	v_cmp_class_f64_e64 s1, v[9:10], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v16, v12, s0
	v_cndmask_b32_e64 v11, v15, v11, s0
	v_cmp_eq_f64_e64 s0, 0, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v12
	v_max_f64 v[13:14], |v[11:12]|, |v[9:10]|
	v_min_f64 v[15:16], |v[11:12]|, |v[9:10]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, v[13:14], v[13:14], v[15:16]
	v_div_scale_f64 v[23:24], vcc_lo, v[15:16], v[13:14], v[15:16]
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
	v_cmp_lt_f64_e64 vcc_lo, |v[11:12]|, |v[9:10]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[13:14], v[17:18], v[13:14], v[15:16]
	v_mul_f64 v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], s[8:9], s[2:3]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[12:13]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[16:17]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[34:35]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[38:39]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[42:43]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[46:47]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[50:51]
	v_mul_f64 v[15:16], v[15:16], v[17:18]
	v_and_b32_e32 v18, 0x54442d18, v4
	v_and_b32_e32 v4, 0x400921fb, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_add_f64 v[15:16], -v[13:14], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v14, v16 :: v_dual_cndmask_b32 v13, v13, v15
	v_cmp_gt_i32_e32 vcc_lo, 0, v12
	v_add_f64 v[15:16], -v[13:14], s[56:57]
	v_cmp_class_f64_e64 s56, v[11:12], 0x204
	v_cndmask_b32_e32 v17, 0x54442d18, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v13, v15, vcc_lo
	v_cndmask_b32_e32 v15, 0x3fe921fb, v8, vcc_lo
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	s_and_b32 vcc_lo, s1, s56
	v_cndmask_b32_e64 v13, v13, v18, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v15, 0x7fffffff, v15, v10
	v_cndmask_b32_e64 v4, v14, v4, s0
	v_add_co_u32 v2, s0, v2, s22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v13, v13, v17, vcc_lo
	v_add_co_ci_u32_e64 v3, s0, s23, v3, s0
	v_cndmask_b32_e32 v4, v4, v15, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7ff80000, v4, vcc_lo
	v_cndmask_b32_e32 v9, 0, v13, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s33, v1
	v_bfi_b32 v10, 0x7fffffff, v4, v10
	s_or_b32 s58, vcc_lo, s58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], v[9:10]
	v_mul_f64 v[9:10], v[9:10], s[54:55]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[9:10]
	global_store_b32 v[6:7], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s58
	s_cbranch_execnz .LBB0_2
.LBB0_19:                               ; %Flow79
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9haversineiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 63
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9haversineiPfS_, .Lfunc_end0-_Z9haversineiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6932
; NumSgprs: 65
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 65
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9haversineiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     65
    .sgpr_spill_count: 0
    .symbol:         _Z9haversineiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
