#include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>

#define CUDA_ERROR_CHECK

#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError()    __cudaCheckError( __FILE__, __LINE__ )

inline void __cudaSafeCall( cudaError err, const char *file, const int line ) {
    #ifdef CUDA_ERROR_CHECK
    if ( cudaSuccess != err ) {
        fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n", file, line, cudaGetErrorString( err));
         exit(-1);
                                        }
    #endif
}


inline void __cudaCheckError( const char *file, const int line ) {
    #ifdef CUDA_ERROR_CHECK
    cudaError err = cudaGetLastError();
    if ( cudaSuccess != err ) {
        fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n", file, line, cudaGetErrorString( err ) );
        exit( -1 );
                                            }

        // More careful checking. However, this will affect performance.
        // Comment away if needed.
        err = cudaDeviceSynchronize();
        if( cudaSuccess != err ) {
            fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n", file, line, cudaGetErrorString( err ) );
            exit( -1 );
                                                    }
    #endif
}


__device__ void calc_cov_est(float* cov_arr, float* cov_inv_arr, float* cov_est, int n, int n_threads) {

    int i, j;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int offset = threadID * n;

    for (i = offset; i < offset + n; i++) {
        cov_inv_arr[i] = 1.f / cov_arr[i];
    }

    if (threadID == 0) {
        for (i = 0; i < n; i++) {
            cov_est[i] = 0.f;
        }

        for (i = 0; i < n; i++) {
            for (j = 0; j < n_threads; j++) {
                cov_est[i] += cov_inv_arr[i + n * j];
            }
            cov_est[i] = 1.f / cov_est[i];
            // printf("Covariance estimate for element %d: %f\n", i, cov_est[i]);
        }
    }

    __syncthreads();

}


__device__ void calc_mu_est(float* mu_arr, float* cov_inv_arr, float* mu_inv_arr, float* cov_est, float* mu_est, int n, int n_threads) {

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    
    int offset = threadID * n;
    int i, j;

    for (i = offset; i < offset + n; i++) {
        mu_inv_arr[i] = mu_arr[i] * cov_inv_arr[i];
    }

    if (threadID == 0) {
        for (i = 0; i < n; i++) {
            mu_est[i] = 0.f;
        }

        for (i = 0; i < n; i++) {
            for (j = 0; j < n_threads; j++) {
                mu_est[i] += mu_inv_arr[i + n * j];
            }
        }

        for (i = 0; i < n; i++) {
            mu_est[i] = cov_est[i] * mu_est[i];
        }
    }

    __syncthreads();
}


__device__ void rand_init(curandState *state) {

    // unsigned int seed = (unsigned int) clock64();
    int seed = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    curand_init(seed+threadID, 0, 0, &state[threadID]);
}


__device__ void get_rand_nums(curandState *state, float* rand_num, int* rand_ints, int max_int) {

    float rand_int_num;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    rand_num[threadID] = (float) (curand_uniform(&state[threadID]));
    rand_int_num = (float) (curand_uniform(&state[threadID]));

    rand_ints[threadID] = int(max_int * rand_int_num);
}


__device__ void get_rand_gaussian(curandState *state, float sigma1, float* gaussian_arr1, float sigma2, float* gaussian_arr2) {

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    gaussian_arr1[threadID] = (float) (curand_normal(&state[threadID]) * sigma1);
    gaussian_arr2[threadID] = (float) (curand_normal(&state[threadID]) * sigma2);
}


__device__ float alt_calc_det(float* cov_arr, int n) {

    int i;
    float det = 1.f;

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int initial_idx = n * threadID;

    for (i = initial_idx; i < initial_idx + n; i++) {
        det *= cov_arr[i];
    }

    return det;
}


__device__ float calc_vec_mat_vec_prod(float* cov_arr, float* data, float* mu_arr, int data_idx, int n) {

    int i, j;
    
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int initial_idx = n * threadID;
    float diff;
    float cum_sum = 0.f;

    for (i = initial_idx; i < initial_idx + n; i++) {

        j = i - initial_idx + data_idx;

        diff = data[j] - mu_arr[i];
        cum_sum += diff * diff * 1. / cov_arr[i];
    }

    return cum_sum;
}


__device__ float get_log_det(float* A, int n) {

    float det = alt_calc_det(A, n);

    return log(det);
}


__device__ float get_log_likelihood(float* data, float* mu_arr, float* cov_arr, float cov_det, int data_idx, int n) {
    // Log likelihood, assuming Gaussian errors.
    
    float t1, t2, t3;
    float L;
    float fl_inf = 10000000000000000000;

    t1 = -0.5 * cov_det;
    t2 = -0.5 * calc_vec_mat_vec_prod(cov_arr, data, mu_arr, data_idx, n);
    t3 = -0.5 * n * log(2 * M_PI);

    // printf("Terms: %f, %f, %f\n", t1, t2, t3);

    L = t1 + t2 + t3;

    if (isnan(L)) {
        return -1 * fl_inf;
    } else {
        return L;
    }
}


__device__ float get_total_log_likelihood(float* cov, float* mu, float* data, int n_data_per_thread, int n_data, int n) {
    // Gets the log likelihood for all of the data files, summing the result.

    int data_idx;
    float cov_det = get_log_det(cov, n);

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int data_offset = threadID * n * n_data_per_thread;
    float cum_L = 0.f;

    for (data_idx = data_offset; data_idx < data_offset + n * n_data_per_thread; data_idx+=n) {
       cum_L += get_log_likelihood(data, mu, cov, cov_det, data_idx, n);
    }

    return cum_L;
}


__device__ void generate_random_nums(curandState *state, float* rand_mu, float* rand_cov, float mu_step, float cov_step, float* rand_num, int* rand_ints, int n) {

    int n_params = 2 * n;

    get_rand_nums(state, rand_num, rand_ints, n_params);

    get_rand_gaussian(state, mu_step, rand_mu, cov_step, rand_cov);
}


__device__ void perturb_cov(float* old_cov, float* new_cov, int param_idx, float rand_cov_num, int n) {

    float new_val;

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    int offset = threadID * n;
    int idx = param_idx - n;

    new_val = old_cov[offset + idx] + rand_cov_num;

    if (new_val > 0) {
        new_cov[offset + idx] = new_val;
    }
}


__device__ void perturb_params(float* old_cov, float* old_mu, float* new_cov, float* new_mu, int* rand_ints, float* rand_mu, float* rand_cov, int n) {
    // Perturbs a random parameter from array params from a Gaussian distribution 
    // with a standard deviation of its step-size in array step_size. Returns a new
    // parameter vector params.
    
    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;
    // Pick parameter to perturb
    int param_idx = rand_ints[threadID];
    // printf("Random interger: %d.\n", param_idx);

    if (param_idx < n) {
        new_mu[param_idx + offset] = old_mu[param_idx + offset] + rand_mu[threadID];
    } else {
        perturb_cov(old_cov, new_cov, param_idx, rand_cov[threadID], n);
    }
}


__device__ void mcmc_step(float* curr_L, float* new_cov, float* new_mu, float* old_cov, float* old_mu, int* rand_ints, float* rand_mu, float* rand_cov, float* rand_num, int n, int n_data_per_thread, int n_data, int* take_step, float* data) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;

    float old_L = curr_L[threadID];

    float new_L = get_total_log_likelihood(new_cov, new_mu, data, n_data_per_thread, n_data, n);

    float threshold;

    // Note: might need to restrict elements of cov to keep matrix positive semi-definite
    if (new_L > old_L) {

        take_step[threadID] = 1;
        curr_L[threadID] = new_L;

    } else {

        threshold = exp(new_L - old_L);

        if (rand_num[threadID] < threshold) {
            take_step[threadID] = 1;
            curr_L[threadID] = new_L;
        } else {
            take_step[threadID] = 0;
        }
    }
}


__device__ float calc_l2_norm(float* mu, float* true_mu, int n) {

    int i;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    int offset = n * threadID;

    float diff;
    float cum_sum = 0.;
    float result;

    for (i = offset; i < offset + n; i++) {
        diff = true_mu[i] - mu[i];
        cum_sum += diff * diff;
    }

    result = sqrt(cum_sum);

    return result;
}


__device__ void initialize_cov(float* cov, int n) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;
    float val = 5.0f;

    int i;

    for (i = offset; i < offset + n; i++) {
        cov[i] = val;
    }
}


__device__ void initialize_means(float initial_mean, float* curr_mu, int n) {

    int i;
    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;

    for (i = offset; i < offset + n; i++) {
        curr_mu[i] = initial_mean;
    }
}


__host__ int count_n_data(int n) {

    FILE *input;
    unsigned int i = 0;

    float temp;
   
    // input = fopen("data_10.txt", "r");
    char input_file [50];
    sprintf(input_file, "data_%d.txt", n);
    input = fopen(input_file, "r");

    while ((fscanf(input, "%f", &temp)) != EOF) {
        i++;
    }
        
    fclose(input);

    return i / n;
}

__host__ void read_data(int n_data, int n, float* data) {

    FILE *input;
    unsigned int i = 0;
   
    // input = fopen("data_10.txt", "r");
    char input_file [50];
    sprintf(input_file, "data_%d.txt", n);
    input = fopen(input_file, "r");

    while ((fscanf(input, "%f", &data[i])) != EOF) {
        i++;
    }
        
    fclose(input);
}


__device__ void vec_cpy(float* parent_mat, float* child_mat, int n) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;

    int offset = threadID * n;

    int i;

    for (i = offset; i < offset + n; i++) {
        child_mat[i] = parent_mat[i];
    }
}


__global__ void kernel_rand_nums(curandState* state, float* rand_mu, float* rand_cov, float mu_step, float cov_step, float* rand_num, int* rand_ints, int n) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

}


__global__ void mcmc_shared(int n, int n_data, int n_data_per_thread, int n_threads, int n_steps, int spacing, float mu_step, float cov_step, curandState* state, float* curr_cov, float* new_cov, float* curr_mu, float* new_mu, float* rand_num, int* rand_ints, float* rand_mu, float* rand_cov, float* curr_L, int* take_step, float* data, float* mu_inv_arr, float* cov_inv_arr, float* mu_est, float* cov_est, float* all_mu_est) {

    int step_count = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    extern __shared__ float s_data[];

    float initial_mean = 1.0f;
    int local_take_step;

    int estimation_offset;
    int i;
    int copy_offset = threadID * n * n_data_per_thread;

    for (i = copy_offset; i < copy_offset + n_data_per_thread * n; i++) {
        s_data[i] = data[i];
    }

    // begin code
    initialize_cov(curr_cov, n);
    initialize_means(initial_mean, curr_mu, n);
    rand_init(state);

    curr_L[threadID] = get_total_log_likelihood(curr_cov, curr_mu, s_data, n_data_per_thread, n_data, n);

    vec_cpy(curr_cov, new_cov, n);
    vec_cpy(curr_mu, new_mu, n);

    while (step_count < n_steps) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

        perturb_params(curr_cov, curr_mu, new_cov, new_mu, rand_ints, rand_mu, rand_cov, n);

        mcmc_step(curr_L, new_cov, new_mu, curr_cov, curr_mu, rand_ints, rand_mu, rand_cov, rand_num, n, n_data_per_thread, n_data, take_step, s_data);

        local_take_step = take_step[threadID];

        if (local_take_step == 1) {

            vec_cpy(new_cov, curr_cov, n);
            vec_cpy(new_mu, curr_mu, n);
        } 

        if (step_count % spacing == 0) {
           
            calc_cov_est(curr_cov, cov_inv_arr, cov_est, n, n_threads);

            calc_mu_est(curr_mu, cov_inv_arr, mu_inv_arr, cov_est, mu_est, n, n_threads);

            if (threadID == 0) {
                estimation_offset = step_count / spacing * n;

                // ERROR
                for (i = estimation_offset; i < estimation_offset + n; i++) {
                    all_mu_est[i] = mu_est[i - estimation_offset];
                }
            }

            __syncthreads();

        }

        step_count += 1;
    }
}



__global__ void mcmc(int n, int n_data, int n_data_per_thread, int n_threads, int n_steps, int spacing, float mu_step, float cov_step, curandState* state, float* curr_cov, float* new_cov, float* curr_mu, float* new_mu, float* rand_num, int* rand_ints, float* rand_mu, float* rand_cov, float* curr_L, int* take_step, float* data, float* mu_inv_arr, float* cov_inv_arr, float* mu_est, float* cov_est, float* all_mu_est) {

    int step_count = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    float initial_mean = 1.0f;
    int local_take_step;

    int estimation_offset;
    int i;

    // begin code
    initialize_cov(curr_cov, n);
    initialize_means(initial_mean, curr_mu, n);
    rand_init(state);

    curr_L[threadID] = get_total_log_likelihood(curr_cov, curr_mu, data, n_data_per_thread, n_data, n);

    vec_cpy(curr_cov, new_cov, n);
    vec_cpy(curr_mu, new_mu, n);

    while (step_count < n_steps) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

        perturb_params(curr_cov, curr_mu, new_cov, new_mu, rand_ints, rand_mu, rand_cov, n);

        mcmc_step(curr_L, new_cov, new_mu, curr_cov, curr_mu, rand_ints, rand_mu, rand_cov, rand_num, n, n_data_per_thread, n_data, take_step, data);

        local_take_step = take_step[threadID];

        if (local_take_step == 1) {

            vec_cpy(new_cov, curr_cov, n);
            vec_cpy(new_mu, curr_mu, n);

        } 

        if (step_count % spacing == 0) {
           
            calc_cov_est(curr_cov, cov_inv_arr, cov_est, n, n_threads);

            calc_mu_est(curr_mu, cov_inv_arr, mu_inv_arr, cov_est, mu_est, n, n_threads);

            if (threadID == 0) {
                estimation_offset = step_count / spacing * n;

                // ERROR
                for (i = estimation_offset; i < estimation_offset + n; i++) {
                    all_mu_est[i] = mu_est[i - estimation_offset];
                }
            }

            __syncthreads();

        }

        step_count += 1;
    }
}


void print_usage() {

    printf("Usage: MCMC options are...\n");
    printf("    Number of steps: --n_steps=n_steps\n");
    printf("    Number of dimensions: --n_dim=n_dim\n");
    printf("    Evaluation frequency: --eval_freq=eval_freq\n");
    printf("    Store data in shared memory (requires small datasets): --shared_memory=1\n");
}


int query_flag_idx(char* arg, const char* query_array[]) {

    int unique_idx = 5;
    int i;

    for (i = 0; i < 4; i++) {
        if (arg[unique_idx] == query_array[i][unique_idx]) {
            return i;
        }
    }

    return -1;
}


int* parse_args(int argc, char *argv[]) {

    const char* query_array[4];
    query_array[0] = "--n_steps";
    query_array[1] = "--n_dim";
    query_array[2] = "--eval_freq";
    query_array[3] = "--shared_memory";

    int* arg_vals = (int*)malloc(4 * sizeof(int));

    int default_n_steps = 10000;
    int default_n = 10;
    int default_spacing = 1000;
    int default_shared = 0;

    int i;
    int arg_idx;
    int init_idx;

    for (i = 0; i < 4; i++) {
        arg_vals[i] = -1;
    }

    for (i = 1; i < argc; i++) {
        if (!strcmp(argv[i], "-h") || !strcmp(argv[i], "--help")) {
            print_usage();
            exit(0);
        } else {
            arg_idx = query_flag_idx(argv[i], query_array);

            if (arg_idx != -1) {
                init_idx = strlen(query_array[arg_idx]) + 1;
                argv[i] += init_idx;
                sscanf(argv[i], "%d", &arg_vals[arg_idx]);
            } else {
                print_usage();
                exit(0);
            }
        }
    }

    if (arg_vals[0] == -1) {
        printf("Number of steps not provided. Defaulting to %d steps.\n", default_n_steps);
        arg_vals[0] = default_n_steps;
    }
    if (arg_vals[1] == -1) {
        printf("Number of dimensions not provided. Defaulting to %d dimensions.\n", default_n);
        arg_vals[1] = default_n;
    }
    if (arg_vals[2] == -1) {
        printf("Evaluation frequency not provided. Defaulting to evaluating every %d steps.\n", default_spacing);
        arg_vals[2] = default_spacing;
    }
    if (arg_vals[3] == -1) {
        printf("Shared memory not specified. Defaulting to using global memory.\n");
        arg_vals[3] = default_shared;
    }

    return arg_vals;
}


int main(int argc, char *argv[]) {

    int* arg_vals = parse_args(argc, argv);
    int n_steps = arg_vals[0];
    int n = arg_vals[1];
    int spacing = arg_vals[2];
    int use_shared = arg_vals[3];

    int n_threads = 1024;
    int n_data = count_n_data(n);
    int n_data_per_thread = n_data / n_threads;
    int n_blocks = 1;

    int n_sample_points = n_steps / spacing;
    int i;

    float mu_step = 0.2;
    float cov_step = 0.2;

    FILE* f;

    cudaEvent_t start, stop;
    curandState* state;

    float* rand_num;
    float* rand_mu;
    float* rand_cov;
    int* rand_ints;

    float* curr_mu;
    float* new_mu;
    float* curr_cov;
    float* new_cov;

    float* curr_L;
    int* take_step;

    float* data;

    float* mu_inv;
    float* cov_inv;

    float* mu_est;
    float* cov_est;

    float* all_mu_est;

    float* h_data = (float*)malloc(n * n_data * sizeof(float));
    float* h_cov = (float*)malloc(n * n_threads * n_blocks * sizeof(float));
    float* h_mu = (float*)malloc(n * n_threads * n_blocks * sizeof(float));
    float* h_rand = (float*)malloc(n_threads * n_blocks * sizeof(float));
    
    float* h_mu_est = (float*)malloc(n * n_sample_points * sizeof(float));

    CudaSafeCall(cudaMalloc(&state, n_blocks * n_threads * sizeof(curandState)));

    CudaSafeCall(cudaMalloc((void**)&rand_num, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&rand_mu, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&rand_cov, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&rand_ints, n_blocks * n_threads * sizeof(int)));

    CudaSafeCall(cudaMalloc((void**)&curr_L, n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&take_step, n_threads * n_blocks * sizeof(int)));

    CudaSafeCall(cudaMalloc((void**)&curr_mu, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&new_mu, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&curr_cov, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&new_cov, n * n_threads * n_blocks * sizeof(float)));

    CudaSafeCall(cudaMalloc((void**)&data, n * n_data * sizeof(float)));

    CudaSafeCall(cudaMalloc((void**)&mu_inv, n * n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&cov_inv, n * n_threads * n_blocks * sizeof(float)));

    CudaSafeCall(cudaMalloc((void**)&mu_est, n * sizeof(float)));
    CudaSafeCall(cudaMalloc((void**)&cov_est, n * sizeof(float)));

    CudaSafeCall(cudaMalloc((void**)&all_mu_est, n * n_sample_points * sizeof(float)));

    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // Array for covariance elements held by every thread
    read_data(n_data, n, h_data);

    CudaSafeCall(cudaMemcpy(data, h_data, n * n_data * sizeof(float), cudaMemcpyHostToDevice));

    // kernel_rand_nums<<<1, 1024>>>(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

    //cudaEventRecord(start);
    //mcmc<<<n_blocks, n_threads>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
    //cudaEventRecord(stop);
    //CudaCheckError();

    if (use_shared == 1) {
        cudaEventRecord(start);
        mcmc_shared<<<n_blocks, n_threads, n * n_data * sizeof(float)>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
        cudaEventRecord(stop);
        CudaCheckError();
    } else {
        cudaEventRecord(start);
        mcmc<<<n_blocks, n_threads>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
        cudaEventRecord(stop);
        CudaCheckError();
    }


    CudaSafeCall(cudaMemcpy(h_cov, curr_cov, n * n_threads * sizeof(float), cudaMemcpyDeviceToHost));
    CudaSafeCall(cudaMemcpy(h_mu, curr_mu, n * n_threads * sizeof(float), cudaMemcpyDeviceToHost));

    CudaSafeCall(cudaMemcpy(h_mu_est, all_mu_est, n * n_sample_points * sizeof(float), cudaMemcpyDeviceToHost));
    CudaSafeCall(cudaMemcpy(h_rand, rand_num, n_threads * sizeof(float), cudaMemcpyDeviceToHost));

    cudaEventSynchronize(stop);

//    for (i = 0; i < n * n_threads; i++) {
//        printf("%f ", h_mu[i]);
//    }

    float milliseconds = 0.f;
    cudaEventElapsedTime(&milliseconds, start, stop);

    printf("Code executed in %f ms.\n", milliseconds);

    f = fopen("mu_data.txt", "w");
    for (i = 0; i < n * n_threads; i++) {
        fprintf(f, "%f ", h_mu[i]);
    }
    fclose(f);

    f = fopen("cov_data.txt", "w");
    for (i = 0; i < n * n_threads; i++) {
        fprintf(f, "%f ", h_cov[i]);
    }
    fclose(f);

    f = fopen("rand_data.txt", "w");
    for (i = 0; i < n_threads; i++) {
        fprintf(f, "%f ", h_rand[i]);
    }
    fclose(f);

    f = fopen("mu_evolution.txt", "w");
    for (i = 0; i < n_sample_points * n; i++) {
        fprintf(f, "%f ", h_mu_est[i]);
        // printf("%f ", h_mu_est[i]);
    }
    fclose(f);


    free(h_data);
    free(h_cov);
    free(h_mu);
    free(h_rand);

    cudaFree(state);

    free(h_mu_est);

    cudaFree(mu_inv);
    cudaFree(cov_inv);

    cudaFree(mu_est);
    cudaFree(cov_est);

    cudaFree(all_mu_est);

    cudaFree(rand_num);
    cudaFree(rand_mu);
    cudaFree(rand_cov);
    cudaFree(rand_ints);

    cudaFree(curr_L);
    cudaFree(take_step);

    cudaFree(curr_mu);
    cudaFree(new_mu);
    cudaFree(curr_cov);
    cudaFree(new_cov);

    cudaFree(data);

    return 0;
}

	.file	"tmpxft_00203f3a_00000000-6_mcmc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2269:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2269:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z14__cudaSafeCall9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaSafeCall() failed at %s:%i : %s\n"
	.section	.text._Z14__cudaSafeCall9cudaErrorPKci,"axG",@progbits,_Z14__cudaSafeCall9cudaErrorPKci,comdat
	.weak	_Z14__cudaSafeCall9cudaErrorPKci
	.type	_Z14__cudaSafeCall9cudaErrorPKci, @function
_Z14__cudaSafeCall9cudaErrorPKci:
.LFB2241:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edx, 12(%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	movl	12(%rsp), %r8d
	movq	%rax, %r9
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE2241:
	.size	_Z14__cudaSafeCall9cudaErrorPKci, .-_Z14__cudaSafeCall9cudaErrorPKci
	.section	.rodata._Z16__cudaCheckErrorPKci.str1.1,"aMS",@progbits,1
.LC1:
	.string	"cudaCheckError() failed at %s:%i : %s\n"
.LC2:
	.string	"cudaCheckError() with sync failed at %s:%i : %s\n"
	.section	.text._Z16__cudaCheckErrorPKci,"axG",@progbits,_Z16__cudaCheckErrorPKci,comdat
	.weak	_Z16__cudaCheckErrorPKci
	.type	_Z16__cudaCheckErrorPKci, @function
_Z16__cudaCheckErrorPKci:
.LFB2242:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L9
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	%ebp, %r8d
	movq	%rbx, %rcx
	leaq	.LC1(%rip), %rdx
	movq	%rax, %r9
	jmp	.L12
.L9:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L8
	call	cudaGetErrorString@PLT
	movl	%ebp, %r8d
	movq	%rbx, %rcx
	leaq	.LC2(%rip), %rdx
	movq	%rax, %r9
.L12:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L8:
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2242:
	.size	_Z16__cudaCheckErrorPKci, .-_Z16__cudaCheckErrorPKci
	.text
	.globl	_Z12calc_cov_estPfS_S_ii
	.type	_Z12calc_cov_estPfS_S_ii, @function
_Z12calc_cov_estPfS_S_ii:
.LFB2243:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2243:
	.size	_Z12calc_cov_estPfS_S_ii, .-_Z12calc_cov_estPfS_S_ii
	.globl	_Z11calc_mu_estPfS_S_S_S_ii
	.type	_Z11calc_mu_estPfS_S_S_S_ii, @function
_Z11calc_mu_estPfS_S_S_S_ii:
.LFB2244:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2244:
	.size	_Z11calc_mu_estPfS_S_S_S_ii, .-_Z11calc_mu_estPfS_S_S_S_ii
	.globl	_Z9rand_initP17curandStateXORWOW
	.type	_Z9rand_initP17curandStateXORWOW, @function
_Z9rand_initP17curandStateXORWOW:
.LFB2245:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2245:
	.size	_Z9rand_initP17curandStateXORWOW, .-_Z9rand_initP17curandStateXORWOW
	.globl	_Z13get_rand_numsP17curandStateXORWOWPfPii
	.type	_Z13get_rand_numsP17curandStateXORWOWPfPii, @function
_Z13get_rand_numsP17curandStateXORWOWPfPii:
.LFB2246:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2246:
	.size	_Z13get_rand_numsP17curandStateXORWOWPfPii, .-_Z13get_rand_numsP17curandStateXORWOWPfPii
	.globl	_Z17get_rand_gaussianP17curandStateXORWOWfPffS1_
	.type	_Z17get_rand_gaussianP17curandStateXORWOWfPffS1_, @function
_Z17get_rand_gaussianP17curandStateXORWOWfPffS1_:
.LFB2247:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2247:
	.size	_Z17get_rand_gaussianP17curandStateXORWOWfPffS1_, .-_Z17get_rand_gaussianP17curandStateXORWOWfPffS1_
	.globl	_Z12alt_calc_detPfi
	.type	_Z12alt_calc_detPfi, @function
_Z12alt_calc_detPfi:
.LFB2248:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2248:
	.size	_Z12alt_calc_detPfi, .-_Z12alt_calc_detPfi
	.globl	_Z21calc_vec_mat_vec_prodPfS_S_ii
	.type	_Z21calc_vec_mat_vec_prodPfS_S_ii, @function
_Z21calc_vec_mat_vec_prodPfS_S_ii:
.LFB2249:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2249:
	.size	_Z21calc_vec_mat_vec_prodPfS_S_ii, .-_Z21calc_vec_mat_vec_prodPfS_S_ii
	.globl	_Z11get_log_detPfi
	.type	_Z11get_log_detPfi, @function
_Z11get_log_detPfi:
.LFB2417:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z12alt_calc_detPfi
	.cfi_endproc
.LFE2417:
	.size	_Z11get_log_detPfi, .-_Z11get_log_detPfi
	.globl	_Z18get_log_likelihoodPfS_S_fii
	.type	_Z18get_log_likelihoodPfS_S_fii, @function
_Z18get_log_likelihoodPfS_S_fii:
.LFB2251:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2251:
	.size	_Z18get_log_likelihoodPfS_S_fii, .-_Z18get_log_likelihoodPfS_S_fii
	.globl	_Z24get_total_log_likelihoodPfS_S_iii
	.type	_Z24get_total_log_likelihoodPfS_S_iii, @function
_Z24get_total_log_likelihoodPfS_S_iii:
.LFB2252:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2252:
	.size	_Z24get_total_log_likelihoodPfS_S_iii, .-_Z24get_total_log_likelihoodPfS_S_iii
	.globl	_Z20generate_random_numsP17curandStateXORWOWPfS1_ffS1_Pii
	.type	_Z20generate_random_numsP17curandStateXORWOWPfS1_ffS1_Pii, @function
_Z20generate_random_numsP17curandStateXORWOWPfS1_ffS1_Pii:
.LFB2253:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2253:
	.size	_Z20generate_random_numsP17curandStateXORWOWPfS1_ffS1_Pii, .-_Z20generate_random_numsP17curandStateXORWOWPfS1_ffS1_Pii
	.globl	_Z11perturb_covPfS_ifi
	.type	_Z11perturb_covPfS_ifi, @function
_Z11perturb_covPfS_ifi:
.LFB2254:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2254:
	.size	_Z11perturb_covPfS_ifi, .-_Z11perturb_covPfS_ifi
	.globl	_Z14perturb_paramsPfS_S_S_PiS_S_i
	.type	_Z14perturb_paramsPfS_S_S_PiS_S_i, @function
_Z14perturb_paramsPfS_S_S_PiS_S_i:
.LFB2255:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2255:
	.size	_Z14perturb_paramsPfS_S_S_PiS_S_i, .-_Z14perturb_paramsPfS_S_S_PiS_S_i
	.globl	_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_
	.type	_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_, @function
_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_:
.LFB2256:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2256:
	.size	_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_, .-_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_
	.globl	_Z12calc_l2_normPfS_i
	.type	_Z12calc_l2_normPfS_i, @function
_Z12calc_l2_normPfS_i:
.LFB2257:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2257:
	.size	_Z12calc_l2_normPfS_i, .-_Z12calc_l2_normPfS_i
	.globl	_Z14initialize_covPfi
	.type	_Z14initialize_covPfi, @function
_Z14initialize_covPfi:
.LFB2258:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2258:
	.size	_Z14initialize_covPfi, .-_Z14initialize_covPfi
	.globl	_Z16initialize_meansfPfi
	.type	_Z16initialize_meansfPfi, @function
_Z16initialize_meansfPfi:
.LFB2259:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2259:
	.size	_Z16initialize_meansfPfi, .-_Z16initialize_meansfPfi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"data_%d.txt"
.LC4:
	.string	"r"
.LC5:
	.string	"%f"
	.text
	.globl	_Z12count_n_datai
	.type	_Z12count_n_datai, @function
_Z12count_n_datai:
.LFB2260:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %r8d
	movl	$50, %edx
	movl	$2, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC3(%rip), %rcx
	leaq	.LC5(%rip), %r13
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	6(%rsp), %rbx
	movq	%rbx, %rdi
	call	__sprintf_chk@PLT
	movq	%rbx, %rdi
	leaq	.LC4(%rip), %rsi
	xorl	%ebx, %ebx
	call	fopen@PLT
	movq	%rax, %r12
.L48:
	xorl	%eax, %eax
	movq	%rsp, %rdx
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L52
	incl	%ebx
	jmp	.L48
.L52:
	movq	%r12, %rdi
	call	fclose@PLT
	movl	%ebx, %eax
	xorl	%edx, %edx
	divl	%ebp
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2260:
	.size	_Z12count_n_datai, .-_Z12count_n_datai
	.globl	_Z9read_dataiiPf
	.type	_Z9read_dataiiPf, @function
_Z9read_dataiiPf:
.LFB2261:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%esi, %r8d
	leaq	.LC3(%rip), %rcx
	movl	$2, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC5(%rip), %r13
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdx, %rbp
	movl	$50, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	6(%rsp), %rbx
	movq	%rbx, %rdi
	call	__sprintf_chk@PLT
	movq	%rbx, %rdi
	leaq	.LC4(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rbx
.L54:
	movl	%r12d, %eax
	movq	%r13, %rsi
	movq	%rbx, %rdi
	leaq	0(%rbp,%rax,4), %rdx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	incl	%eax
	je	.L58
	incl	%r12d
	jmp	.L54
.L58:
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2261:
	.size	_Z9read_dataiiPf, .-_Z9read_dataiiPf
	.globl	_Z7vec_cpyPfS_i
	.type	_Z7vec_cpyPfS_i, @function
_Z7vec_cpyPfS_i:
.LFB2262:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2262:
	.size	_Z7vec_cpyPfS_i, .-_Z7vec_cpyPfS_i
	.section	.rodata.str1.1
.LC6:
	.string	"Usage: MCMC options are...\n"
.LC7:
	.string	"    Number of steps: --n_steps=n_steps\n"
.LC8:
	.string	"    Number of dimensions: --n_dim=n_dim\n"
.LC9:
	.string	"    Evaluation frequency: --eval_freq=eval_freq\n"
.LC10:
	.string	"    Store data in shared memory (requires small datasets): --shared_memory=1\n"
	.text
	.globl	_Z11print_usagev
	.type	_Z11print_usagev, @function
_Z11print_usagev:
.LFB2263:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	movl	$2, %edi
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2263:
	.size	_Z11print_usagev, .-_Z11print_usagev
	.globl	_Z14query_flag_idxPcPPKc
	.type	_Z14query_flag_idxPcPPKc, @function
_Z14query_flag_idxPcPPKc:
.LFB2264:
	.cfi_startproc
	endbr64
	movb	5(%rdi), %dl
	xorl	%eax, %eax
.L65:
	movq	(%rsi,%rax,8), %rcx
	cmpb	5(%rcx), %dl
	je	.L63
	incq	%rax
	cmpq	$4, %rax
	jne	.L65
	orl	$-1, %eax
.L63:
	ret
	.cfi_endproc
.LFE2264:
	.size	_Z14query_flag_idxPcPPKc, .-_Z14query_flag_idxPcPPKc
	.section	.rodata.str1.1
.LC11:
	.string	"--n_steps"
.LC12:
	.string	"--n_dim"
.LC13:
	.string	"--eval_freq"
.LC14:
	.string	"--shared_memory"
.LC15:
	.string	"-h"
.LC16:
	.string	"--help"
.LC17:
	.string	"%d"
.LC18:
	.string	"Number of steps not provided. Defaulting to %d steps.\n"
.LC19:
	.string	"Number of dimensions not provided. Defaulting to %d dimensions.\n"
.LC20:
	.string	"Evaluation frequency not provided. Defaulting to evaluating every %d steps.\n"
.LC21:
	.string	"Shared memory not specified. Defaulting to using global memory.\n"
	.text
	.globl	_Z10parse_argsiPPc
	.type	_Z10parse_argsiPPc, @function
_Z10parse_argsiPPc:
.LFB2265:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edi, %r14d
	movl	$16, %edi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$1, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	leaq	.LC11(%rip), %rax
	movq	%rax, 8(%rsp)
	leaq	.LC12(%rip), %rax
	movq	%rax, 16(%rsp)
	leaq	.LC13(%rip), %rax
	movq	%rax, 24(%rsp)
	leaq	.LC14(%rip), %rax
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movq	$-1, (%rax)
	movq	%rax, %rbx
	movq	$-1, 8(%rax)
.L69:
	cmpl	%r12d, %r14d
	jle	.L85
	movq	0(%r13,%r12,8), %rbp
	leaq	.LC15(%rip), %rsi
	movq	%rbp, %rdi
	call	strcmp@PLT
	testl	%eax, %eax
	je	.L70
	leaq	.LC16(%rip), %rsi
	movq	%rbp, %rdi
	call	strcmp@PLT
	testl	%eax, %eax
	jne	.L71
.L70:
	call	_Z11print_usagev
	xorl	%edi, %edi
	call	exit@PLT
.L71:
	leaq	8(%rsp), %rsi
	movq	%rbp, %rdi
	call	_Z14query_flag_idxPcPPKc
	cmpl	$-1, %eax
	je	.L70
	movslq	%eax, %r15
	movq	8(%rsp,%r15,8), %rdi
	call	strlen@PLT
	leaq	(%rbx,%r15,4), %rdx
	leaq	.LC17(%rip), %rsi
	incl	%eax
	cltq
	leaq	0(%rbp,%rax), %rdi
	xorl	%eax, %eax
	movq	%rdi, 0(%r13,%r12,8)
	incq	%r12
	call	__isoc23_sscanf@PLT
	jmp	.L69
.L85:
	cmpl	$-1, (%rbx)
	jne	.L73
	movl	$10000, %edx
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$10000, (%rbx)
.L73:
	cmpl	$-1, 4(%rbx)
	jne	.L74
	movl	$10, %edx
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$10, 4(%rbx)
.L74:
	cmpl	$-1, 8(%rbx)
	jne	.L75
	movl	$1000, %edx
	leaq	.LC20(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1000, 8(%rbx)
.L75:
	cmpl	$-1, 12(%rbx)
	jne	.L68
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	%eax, 12(%rbx)
.L68:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L77
	call	__stack_chk_fail@PLT
.L77:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2265:
	.size	_Z10parse_argsiPPc, .-_Z10parse_argsiPPc
	.globl	_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii
	.type	_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii, @function
_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii:
.LFB2291:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 36(%rsp)
	movss	%xmm1, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L86
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L86:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L88
	call	__stack_chk_fail@PLT
.L88:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2291:
	.size	_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii, .-_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii
	.globl	_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii
	.type	_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii, @function
_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii:
.LFB2292:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_PiiP17curandStateXORWOWPfS1_ffS1_Pii
	.cfi_endproc
.LFE2292:
	.size	_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii, .-_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii
	.globl	_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, @function
_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
.LFB2293:
	.cfi_startproc
	endbr64
	subq	$456, %rsp
	.cfi_def_cfa_offset 464
	movq	464(%rsp), %rax
	movl	%edi, 172(%rsp)
	leaq	192(%rsp), %rdi
	movl	%esi, 168(%rsp)
	leaq	204(%rsp), %rsi
	movq	%rax, 136(%rsp)
	movq	472(%rsp), %rax
	movl	%edx, 164(%rsp)
	leaq	176(%rsp), %rdx
	movq	%rax, 128(%rsp)
	movq	480(%rsp), %rax
	movl	%ecx, 160(%rsp)
	leaq	184(%rsp), %rcx
	movq	%rax, 120(%rsp)
	movq	488(%rsp), %rax
	movl	%r8d, 156(%rsp)
	movq	%rax, 112(%rsp)
	movq	496(%rsp), %rax
	movl	%r9d, 152(%rsp)
	movq	%rax, 104(%rsp)
	movq	504(%rsp), %rax
	movss	%xmm0, 148(%rsp)
	movq	%rax, 96(%rsp)
	movq	512(%rsp), %rax
	movss	%xmm1, 144(%rsp)
	movq	%rax, 88(%rsp)
	movq	520(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	528(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	544(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	568(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	576(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 440(%rsp)
	xorl	%eax, %eax
	leaq	172(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	164(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	156(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	148(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 432(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 192(%rsp)
	movl	$1, 200(%rsp)
	movq	%rax, 204(%rsp)
	movl	$1, 212(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L91
	pushq	184(%rsp)
	.cfi_def_cfa_offset 472
	leaq	_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_(%rip), %rdi
	pushq	184(%rsp)
	.cfi_def_cfa_offset 480
	movq	220(%rsp), %rcx
	movl	228(%rsp), %r8d
	movq	208(%rsp), %rsi
	movl	216(%rsp), %edx
	leaq	256(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 472
	popq	%rdx
	.cfi_def_cfa_offset 464
.L91:
	movq	440(%rsp), %rax
	subq	%fs:40, %rax
	je	.L93
	call	__stack_chk_fail@PLT
.L93:
	addq	$456, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2293:
	.size	_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .-_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, @function
_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
.LFB2294:
	.cfi_startproc
	endbr64
	jmp	_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
.LFE2294:
	.size	_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .-_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, @function
_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
.LFB2295:
	.cfi_startproc
	endbr64
	subq	$456, %rsp
	.cfi_def_cfa_offset 464
	movq	464(%rsp), %rax
	movl	%edi, 172(%rsp)
	leaq	192(%rsp), %rdi
	movl	%esi, 168(%rsp)
	leaq	204(%rsp), %rsi
	movq	%rax, 136(%rsp)
	movq	472(%rsp), %rax
	movl	%edx, 164(%rsp)
	leaq	176(%rsp), %rdx
	movq	%rax, 128(%rsp)
	movq	480(%rsp), %rax
	movl	%ecx, 160(%rsp)
	leaq	184(%rsp), %rcx
	movq	%rax, 120(%rsp)
	movq	488(%rsp), %rax
	movl	%r8d, 156(%rsp)
	movq	%rax, 112(%rsp)
	movq	496(%rsp), %rax
	movl	%r9d, 152(%rsp)
	movq	%rax, 104(%rsp)
	movq	504(%rsp), %rax
	movss	%xmm0, 148(%rsp)
	movq	%rax, 96(%rsp)
	movq	512(%rsp), %rax
	movss	%xmm1, 144(%rsp)
	movq	%rax, 88(%rsp)
	movq	520(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	528(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	544(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	568(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	576(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 440(%rsp)
	xorl	%eax, %eax
	leaq	172(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	164(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	156(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	148(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 432(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 192(%rsp)
	movl	$1, 200(%rsp)
	movq	%rax, 204(%rsp)
	movl	$1, 212(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	pushq	184(%rsp)
	.cfi_def_cfa_offset 472
	leaq	_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_(%rip), %rdi
	pushq	184(%rsp)
	.cfi_def_cfa_offset 480
	movq	220(%rsp), %rcx
	movl	228(%rsp), %r8d
	movq	208(%rsp), %rsi
	movl	216(%rsp), %edx
	leaq	256(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 472
	popq	%rdx
	.cfi_def_cfa_offset 464
.L96:
	movq	440(%rsp), %rax
	subq	%fs:40, %rax
	je	.L98
	call	__stack_chk_fail@PLT
.L98:
	addq	$456, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2295:
	.size	_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .-_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, @function
_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
.LFB2296:
	.cfi_startproc
	endbr64
	jmp	_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
.LFE2296:
	.size	_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .-_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.section	.rodata.str1.1
.LC22:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/MaxwellDeJong/parallel_mcmc/main/mcmc.cu"
.LC25:
	.string	"Code executed in %f ms.\n"
.LC26:
	.string	"w"
.LC27:
	.string	"mu_data.txt"
.LC28:
	.string	"%f "
.LC29:
	.string	"cov_data.txt"
.LC30:
	.string	"rand_data.txt"
.LC31:
	.string	"mu_evolution.txt"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2266:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	call	_Z10parse_argsiPPc
	movslq	4(%rax), %r14
	movl	(%rax), %ecx
	movl	8(%rax), %r13d
	movl	12(%rax), %r12d
	movl	%r14d, %edi
	movl	%ecx, 28(%rsp)
	movl	%r14d, %r15d
	movq	%r14, %rbx
	call	_Z12count_n_datai
	movl	$1024, %ecx
	sall	$10, %r15d
	cltd
	movl	%eax, %ebp
	idivl	%ecx
	movl	%eax, 76(%rsp)
	movl	%r14d, %eax
	imull	%ebp, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rax, 32(%rsp)
	movslq	%r15d, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, 48(%rsp)
	call	malloc@PLT
	movq	%rax, 56(%rsp)
	movl	28(%rsp), %eax
	cltd
	idivl	%r13d
	imull	%r14d, %eax
	movl	%eax, 72(%rsp)
	cltq
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	leaq	104(%rsp), %rdi
	movl	$49152, %esi
	movq	%rax, 64(%rsp)
	call	cudaMalloc@PLT
	movl	$674, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	112(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$676, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	120(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$677, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	128(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$678, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	136(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$679, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	176(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$681, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	184(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movl	$682, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	salq	$2, %r14
	leaq	144(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$684, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	leaq	152(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$685, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	leaq	160(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$686, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	leaq	168(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$687, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	8(%rsp), %rsi
	leaq	192(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$689, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	leaq	200(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$691, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rsi
	leaq	208(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$692, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	216(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movl	$694, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	224(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movl	$695, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	16(%rsp), %rsi
	leaq	232(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$697, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdx
	movl	%ebx, %esi
	movl	%ebp, %edi
	call	_Z9read_dataiiPf
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	192(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC22(%rip), %rsi
	movl	$705, %edx
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	xorl	%esi, %esi
	decl	%r12d
	movq	88(%rsp), %rdi
	jne	.L102
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	movq	8(%rsp), %r8
	movabsq	$4294967297, %rdi
	salq	$10, %rdx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%rdi, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L103
	pushq	%rdx
	.cfi_def_cfa_offset 344
	movl	%r13d, %r9d
	movl	$1024, %ecx
	movl	%ebp, %esi
	pushq	240(%rsp)
	.cfi_def_cfa_offset 352
	movl	%ebx, %edi
	pushq	240(%rsp)
	.cfi_def_cfa_offset 360
	pushq	240(%rsp)
	.cfi_def_cfa_offset 368
	pushq	240(%rsp)
	.cfi_def_cfa_offset 376
	pushq	240(%rsp)
	.cfi_def_cfa_offset 384
	pushq	240(%rsp)
	.cfi_def_cfa_offset 392
	pushq	240(%rsp)
	.cfi_def_cfa_offset 400
	pushq	240(%rsp)
	.cfi_def_cfa_offset 408
	pushq	200(%rsp)
	.cfi_def_cfa_offset 416
	pushq	200(%rsp)
	.cfi_def_cfa_offset 424
	pushq	224(%rsp)
	.cfi_def_cfa_offset 432
	movss	.LC23(%rip), %xmm1
	pushq	208(%rsp)
	.cfi_def_cfa_offset 440
	pushq	256(%rsp)
	.cfi_def_cfa_offset 448
	pushq	256(%rsp)
	.cfi_def_cfa_offset 456
	movaps	%xmm1, %xmm0
	pushq	288(%rsp)
	.cfi_def_cfa_offset 464
	pushq	288(%rsp)
	.cfi_def_cfa_offset 472
	pushq	240(%rsp)
	.cfi_def_cfa_offset 480
	movl	172(%rsp), %r8d
	movl	220(%rsp), %edx
	call	_Z103__device_stub__Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	addq	$144, %rsp
	.cfi_def_cfa_offset 336
.L103:
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$718, %esi
	jmp	.L116
.L102:
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rdx, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%rdi, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L105
	pushq	%rax
	.cfi_def_cfa_offset 344
	movl	%r13d, %r9d
	movl	$1024, %ecx
	movl	%ebp, %esi
	pushq	240(%rsp)
	.cfi_def_cfa_offset 352
	movl	%ebx, %edi
	pushq	240(%rsp)
	.cfi_def_cfa_offset 360
	pushq	240(%rsp)
	.cfi_def_cfa_offset 368
	pushq	240(%rsp)
	.cfi_def_cfa_offset 376
	pushq	240(%rsp)
	.cfi_def_cfa_offset 384
	pushq	240(%rsp)
	.cfi_def_cfa_offset 392
	pushq	240(%rsp)
	.cfi_def_cfa_offset 400
	pushq	240(%rsp)
	.cfi_def_cfa_offset 408
	pushq	200(%rsp)
	.cfi_def_cfa_offset 416
	pushq	200(%rsp)
	.cfi_def_cfa_offset 424
	pushq	224(%rsp)
	.cfi_def_cfa_offset 432
	movss	.LC23(%rip), %xmm1
	pushq	208(%rsp)
	.cfi_def_cfa_offset 440
	pushq	256(%rsp)
	.cfi_def_cfa_offset 448
	pushq	256(%rsp)
	.cfi_def_cfa_offset 456
	movaps	%xmm1, %xmm0
	pushq	288(%rsp)
	.cfi_def_cfa_offset 464
	pushq	288(%rsp)
	.cfi_def_cfa_offset 472
	pushq	240(%rsp)
	.cfi_def_cfa_offset 480
	movl	172(%rsp), %r8d
	movl	220(%rsp), %edx
	call	_Z95__device_stub__Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_iiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	addq	$144, %rsp
	.cfi_def_cfa_offset 336
.L105:
	movq	96(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$723, %esi
.L116:
	leaq	.LC22(%rip), %rdi
	leaq	.LC26(%rip), %rbp
	xorl	%r13d, %r13d
	call	_Z16__cudaCheckErrorPKci
	movq	(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	$2, %ecx
	movq	160(%rsp), %rsi
	leaq	.LC28(%rip), %rbx
	call	cudaMemcpy@PLT
	movl	$727, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	(%rsp), %rdx
	movq	48(%rsp), %rdi
	movl	$2, %ecx
	movq	144(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$728, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	16(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	$2, %ecx
	movq	232(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$730, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	112(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$2, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movl	$731, %edx
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	96(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rsi
	leaq	252(%rsp), %rdi
	movl	$0x00000000, 252(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC25(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	252(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	leaq	.LC27(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L106:
	cmpl	%r13d, %r15d
	jle	.L117
	movq	48(%rsp), %rax
	movq	%rbx, %rdx
	movl	$2, %esi
	movq	%r12, %rdi
	cvtss2sd	(%rax,%r13,4), %xmm0
	movb	$1, %al
	incq	%r13
	call	__fprintf_chk@PLT
	jmp	.L106
.L117:
	movq	%r12, %rdi
	xorl	%r13d, %r13d
	call	fclose@PLT
	movq	%rbp, %rsi
	leaq	.LC29(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L108:
	cmpl	%r13d, %r15d
	jle	.L118
	movq	40(%rsp), %rax
	movq	%rbx, %rdx
	movl	$2, %esi
	movq	%r12, %rdi
	cvtss2sd	(%rax,%r13,4), %xmm0
	movb	$1, %al
	incq	%r13
	call	__fprintf_chk@PLT
	jmp	.L108
.L118:
	movq	%r12, %rdi
	xorl	%r13d, %r13d
	call	fclose@PLT
	movq	%rbp, %rsi
	leaq	.LC30(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L110:
	movq	56(%rsp), %rax
	movq	%rbx, %rdx
	movl	$2, %esi
	movq	%r12, %rdi
	cvtss2sd	(%rax,%r13,4), %xmm0
	movb	$1, %al
	incq	%r13
	call	__fprintf_chk@PLT
	cmpq	$1024, %r13
	jne	.L110
	movq	%r12, %rdi
	xorl	%r12d, %r12d
	call	fclose@PLT
	movq	%rbp, %rsi
	leaq	.LC31(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %rbp
.L111:
	cmpl	%r12d, 72(%rsp)
	jle	.L119
	movq	64(%rsp), %rax
	movq	%rbx, %rdx
	movl	$2, %esi
	movq	%rbp, %rdi
	cvtss2sd	(%rax,%r12,4), %xmm0
	movb	$1, %al
	incq	%r12
	call	__fprintf_chk@PLT
	jmp	.L111
.L119:
	movq	%rbp, %rdi
	call	fclose@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	free@PLT
	movq	48(%rsp), %rdi
	call	free@PLT
	movq	56(%rsp), %rdi
	call	free@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	free@PLT
	movq	200(%rsp), %rdi
	call	cudaFree@PLT
	movq	208(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movq	224(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	192(%rsp), %rdi
	call	cudaFree@PLT
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L113
	call	__stack_chk_fail@PLT
.L113:
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2266:
	.size	main, .-main
	.section	.rodata.str1.1
.LC32:
	.string	"_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_"
.LC33:
	.string	"_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_"
.LC34:
	.string	"_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii"
.LC35:
	.string	"precalc_xorwow_matrix"
.LC36:
	.string	"precalc_xorwow_offset_matrix"
.LC37:
	.string	"mrg32k3aM1"
.LC38:
	.string	"mrg32k3aM2"
.LC39:
	.string	"mrg32k3aM1SubSeq"
.LC40:
	.string	"mrg32k3aM2SubSeq"
.LC41:
	.string	"mrg32k3aM1Seq"
.LC42:
	.string	"mrg32k3aM2Seq"
.LC43:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z4mcmciiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11mcmc_sharediiiiiiffP17curandStateXORWOWPfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16kernel_rand_numsP17curandStateXORWOWPfS1_ffS1_Pii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2298:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC23:
	.long	1045220557
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>

#define CUDA_ERROR_CHECK

#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError()    __cudaCheckError( __FILE__, __LINE__ )

inline void __cudaSafeCall( hipError_t err, const char *file, const int line ) {
    #ifdef CUDA_ERROR_CHECK
    if ( hipSuccess != err ) {
        fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n", file, line, hipGetErrorString( err));
         exit(-1);
                                        }
    #endif
}


inline void __cudaCheckError( const char *file, const int line ) {
    #ifdef CUDA_ERROR_CHECK
    hipError_t err = hipGetLastError();
    if ( hipSuccess != err ) {
        fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n", file, line, hipGetErrorString( err ) );
        exit( -1 );
                                            }

        // More careful checking. However, this will affect performance.
        // Comment away if needed.
        err = hipDeviceSynchronize();
        if( hipSuccess != err ) {
            fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n", file, line, hipGetErrorString( err ) );
            exit( -1 );
                                                    }
    #endif
}


__device__ void calc_cov_est(float* cov_arr, float* cov_inv_arr, float* cov_est, int n, int n_threads) {

    int i, j;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int offset = threadID * n;

    for (i = offset; i < offset + n; i++) {
        cov_inv_arr[i] = 1.f / cov_arr[i];
    }

    if (threadID == 0) {
        for (i = 0; i < n; i++) {
            cov_est[i] = 0.f;
        }

        for (i = 0; i < n; i++) {
            for (j = 0; j < n_threads; j++) {
                cov_est[i] += cov_inv_arr[i + n * j];
            }
            cov_est[i] = 1.f / cov_est[i];
            // printf("Covariance estimate for element %d: %f\n", i, cov_est[i]);
        }
    }

    __syncthreads();

}


__device__ void calc_mu_est(float* mu_arr, float* cov_inv_arr, float* mu_inv_arr, float* cov_est, float* mu_est, int n, int n_threads) {

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    
    int offset = threadID * n;
    int i, j;

    for (i = offset; i < offset + n; i++) {
        mu_inv_arr[i] = mu_arr[i] * cov_inv_arr[i];
    }

    if (threadID == 0) {
        for (i = 0; i < n; i++) {
            mu_est[i] = 0.f;
        }

        for (i = 0; i < n; i++) {
            for (j = 0; j < n_threads; j++) {
                mu_est[i] += mu_inv_arr[i + n * j];
            }
        }

        for (i = 0; i < n; i++) {
            mu_est[i] = cov_est[i] * mu_est[i];
        }
    }

    __syncthreads();
}


__device__ void rand_init(hiprandState *state) {

    // unsigned int seed = (unsigned int) clock64();
    int seed = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    hiprand_init(seed+threadID, 0, 0, &state[threadID]);
}


__device__ void get_rand_nums(hiprandState *state, float* rand_num, int* rand_ints, int max_int) {

    float rand_int_num;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    rand_num[threadID] = (float) (hiprand_uniform(&state[threadID]));
    rand_int_num = (float) (hiprand_uniform(&state[threadID]));

    rand_ints[threadID] = int(max_int * rand_int_num);
}


__device__ void get_rand_gaussian(hiprandState *state, float sigma1, float* gaussian_arr1, float sigma2, float* gaussian_arr2) {

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    gaussian_arr1[threadID] = (float) (hiprand_normal(&state[threadID]) * sigma1);
    gaussian_arr2[threadID] = (float) (hiprand_normal(&state[threadID]) * sigma2);
}


__device__ float alt_calc_det(float* cov_arr, int n) {

    int i;
    float det = 1.f;

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int initial_idx = n * threadID;

    for (i = initial_idx; i < initial_idx + n; i++) {
        det *= cov_arr[i];
    }

    return det;
}


__device__ float calc_vec_mat_vec_prod(float* cov_arr, float* data, float* mu_arr, int data_idx, int n) {

    int i, j;
    
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    int initial_idx = n * threadID;
    float diff;
    float cum_sum = 0.f;

    for (i = initial_idx; i < initial_idx + n; i++) {

        j = i - initial_idx + data_idx;

        diff = data[j] - mu_arr[i];
        cum_sum += diff * diff * 1. / cov_arr[i];
    }

    return cum_sum;
}


__device__ float get_log_det(float* A, int n) {

    float det = alt_calc_det(A, n);

    return log(det);
}


__device__ float get_log_likelihood(float* data, float* mu_arr, float* cov_arr, float cov_det, int data_idx, int n) {
    // Log likelihood, assuming Gaussian errors.
    
    float t1, t2, t3;
    float L;
    float fl_inf = 10000000000000000000;

    t1 = -0.5 * cov_det;
    t2 = -0.5 * calc_vec_mat_vec_prod(cov_arr, data, mu_arr, data_idx, n);
    t3 = -0.5 * n * log(2 * M_PI);

    // printf("Terms: %f, %f, %f\n", t1, t2, t3);

    L = t1 + t2 + t3;

    if (isnan(L)) {
        return -1 * fl_inf;
    } else {
        return L;
    }
}


__device__ float get_total_log_likelihood(float* cov, float* mu, float* data, int n_data_per_thread, int n_data, int n) {
    // Gets the log likelihood for all of the data files, summing the result.

    int data_idx;
    float cov_det = get_log_det(cov, n);

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int data_offset = threadID * n * n_data_per_thread;
    float cum_L = 0.f;

    for (data_idx = data_offset; data_idx < data_offset + n * n_data_per_thread; data_idx+=n) {
       cum_L += get_log_likelihood(data, mu, cov, cov_det, data_idx, n);
    }

    return cum_L;
}


__device__ void generate_random_nums(hiprandState *state, float* rand_mu, float* rand_cov, float mu_step, float cov_step, float* rand_num, int* rand_ints, int n) {

    int n_params = 2 * n;

    get_rand_nums(state, rand_num, rand_ints, n_params);

    get_rand_gaussian(state, mu_step, rand_mu, cov_step, rand_cov);
}


__device__ void perturb_cov(float* old_cov, float* new_cov, int param_idx, float rand_cov_num, int n) {

    float new_val;

    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    int offset = threadID * n;
    int idx = param_idx - n;

    new_val = old_cov[offset + idx] + rand_cov_num;

    if (new_val > 0) {
        new_cov[offset + idx] = new_val;
    }
}


__device__ void perturb_params(float* old_cov, float* old_mu, float* new_cov, float* new_mu, int* rand_ints, float* rand_mu, float* rand_cov, int n) {
    // Perturbs a random parameter from array params from a Gaussian distribution 
    // with a standard deviation of its step-size in array step_size. Returns a new
    // parameter vector params.
    
    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;
    // Pick parameter to perturb
    int param_idx = rand_ints[threadID];
    // printf("Random interger: %d.\n", param_idx);

    if (param_idx < n) {
        new_mu[param_idx + offset] = old_mu[param_idx + offset] + rand_mu[threadID];
    } else {
        perturb_cov(old_cov, new_cov, param_idx, rand_cov[threadID], n);
    }
}


__device__ void mcmc_step(float* curr_L, float* new_cov, float* new_mu, float* old_cov, float* old_mu, int* rand_ints, float* rand_mu, float* rand_cov, float* rand_num, int n, int n_data_per_thread, int n_data, int* take_step, float* data) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;

    float old_L = curr_L[threadID];

    float new_L = get_total_log_likelihood(new_cov, new_mu, data, n_data_per_thread, n_data, n);

    float threshold;

    // Note: might need to restrict elements of cov to keep matrix positive semi-definite
    if (new_L > old_L) {

        take_step[threadID] = 1;
        curr_L[threadID] = new_L;

    } else {

        threshold = exp(new_L - old_L);

        if (rand_num[threadID] < threshold) {
            take_step[threadID] = 1;
            curr_L[threadID] = new_L;
        } else {
            take_step[threadID] = 0;
        }
    }
}


__device__ float calc_l2_norm(float* mu, float* true_mu, int n) {

    int i;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;
    int offset = n * threadID;

    float diff;
    float cum_sum = 0.;
    float result;

    for (i = offset; i < offset + n; i++) {
        diff = true_mu[i] - mu[i];
        cum_sum += diff * diff;
    }

    result = sqrt(cum_sum);

    return result;
}


__device__ void initialize_cov(float* cov, int n) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;
    float val = 5.0f;

    int i;

    for (i = offset; i < offset + n; i++) {
        cov[i] = val;
    }
}


__device__ void initialize_means(float initial_mean, float* curr_mu, int n) {

    int i;
    int threadID = threadIdx.x + blockDim.x * blockIdx.x;
    int offset = threadID * n;

    for (i = offset; i < offset + n; i++) {
        curr_mu[i] = initial_mean;
    }
}


__host__ int count_n_data(int n) {

    FILE *input;
    unsigned int i = 0;

    float temp;
   
    // input = fopen("data_10.txt", "r");
    char input_file [50];
    sprintf(input_file, "data_%d.txt", n);
    input = fopen(input_file, "r");

    while ((fscanf(input, "%f", &temp)) != EOF) {
        i++;
    }
        
    fclose(input);

    return i / n;
}

__host__ void read_data(int n_data, int n, float* data) {

    FILE *input;
    unsigned int i = 0;
   
    // input = fopen("data_10.txt", "r");
    char input_file [50];
    sprintf(input_file, "data_%d.txt", n);
    input = fopen(input_file, "r");

    while ((fscanf(input, "%f", &data[i])) != EOF) {
        i++;
    }
        
    fclose(input);
}


__device__ void vec_cpy(float* parent_mat, float* child_mat, int n) {

    int threadID = threadIdx.x + blockDim.x * blockIdx.x;

    int offset = threadID * n;

    int i;

    for (i = offset; i < offset + n; i++) {
        child_mat[i] = parent_mat[i];
    }
}


__global__ void kernel_rand_nums(hiprandState* state, float* rand_mu, float* rand_cov, float mu_step, float cov_step, float* rand_num, int* rand_ints, int n) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

}


__global__ void mcmc_shared(int n, int n_data, int n_data_per_thread, int n_threads, int n_steps, int spacing, float mu_step, float cov_step, hiprandState* state, float* curr_cov, float* new_cov, float* curr_mu, float* new_mu, float* rand_num, int* rand_ints, float* rand_mu, float* rand_cov, float* curr_L, int* take_step, float* data, float* mu_inv_arr, float* cov_inv_arr, float* mu_est, float* cov_est, float* all_mu_est) {

    int step_count = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    extern __shared__ float s_data[];

    float initial_mean = 1.0f;
    int local_take_step;

    int estimation_offset;
    int i;
    int copy_offset = threadID * n * n_data_per_thread;

    for (i = copy_offset; i < copy_offset + n_data_per_thread * n; i++) {
        s_data[i] = data[i];
    }

    // begin code
    initialize_cov(curr_cov, n);
    initialize_means(initial_mean, curr_mu, n);
    rand_init(state);

    curr_L[threadID] = get_total_log_likelihood(curr_cov, curr_mu, s_data, n_data_per_thread, n_data, n);

    vec_cpy(curr_cov, new_cov, n);
    vec_cpy(curr_mu, new_mu, n);

    while (step_count < n_steps) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

        perturb_params(curr_cov, curr_mu, new_cov, new_mu, rand_ints, rand_mu, rand_cov, n);

        mcmc_step(curr_L, new_cov, new_mu, curr_cov, curr_mu, rand_ints, rand_mu, rand_cov, rand_num, n, n_data_per_thread, n_data, take_step, s_data);

        local_take_step = take_step[threadID];

        if (local_take_step == 1) {

            vec_cpy(new_cov, curr_cov, n);
            vec_cpy(new_mu, curr_mu, n);
        } 

        if (step_count % spacing == 0) {
           
            calc_cov_est(curr_cov, cov_inv_arr, cov_est, n, n_threads);

            calc_mu_est(curr_mu, cov_inv_arr, mu_inv_arr, cov_est, mu_est, n, n_threads);

            if (threadID == 0) {
                estimation_offset = step_count / spacing * n;

                // ERROR
                for (i = estimation_offset; i < estimation_offset + n; i++) {
                    all_mu_est[i] = mu_est[i - estimation_offset];
                }
            }

            __syncthreads();

        }

        step_count += 1;
    }
}



__global__ void mcmc(int n, int n_data, int n_data_per_thread, int n_threads, int n_steps, int spacing, float mu_step, float cov_step, hiprandState* state, float* curr_cov, float* new_cov, float* curr_mu, float* new_mu, float* rand_num, int* rand_ints, float* rand_mu, float* rand_cov, float* curr_L, int* take_step, float* data, float* mu_inv_arr, float* cov_inv_arr, float* mu_est, float* cov_est, float* all_mu_est) {

    int step_count = 0;
    int threadID = threadIdx.x + blockIdx.x * blockDim.x;

    float initial_mean = 1.0f;
    int local_take_step;

    int estimation_offset;
    int i;

    // begin code
    initialize_cov(curr_cov, n);
    initialize_means(initial_mean, curr_mu, n);
    rand_init(state);

    curr_L[threadID] = get_total_log_likelihood(curr_cov, curr_mu, data, n_data_per_thread, n_data, n);

    vec_cpy(curr_cov, new_cov, n);
    vec_cpy(curr_mu, new_mu, n);

    while (step_count < n_steps) {

        generate_random_nums(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

        perturb_params(curr_cov, curr_mu, new_cov, new_mu, rand_ints, rand_mu, rand_cov, n);

        mcmc_step(curr_L, new_cov, new_mu, curr_cov, curr_mu, rand_ints, rand_mu, rand_cov, rand_num, n, n_data_per_thread, n_data, take_step, data);

        local_take_step = take_step[threadID];

        if (local_take_step == 1) {

            vec_cpy(new_cov, curr_cov, n);
            vec_cpy(new_mu, curr_mu, n);

        } 

        if (step_count % spacing == 0) {
           
            calc_cov_est(curr_cov, cov_inv_arr, cov_est, n, n_threads);

            calc_mu_est(curr_mu, cov_inv_arr, mu_inv_arr, cov_est, mu_est, n, n_threads);

            if (threadID == 0) {
                estimation_offset = step_count / spacing * n;

                // ERROR
                for (i = estimation_offset; i < estimation_offset + n; i++) {
                    all_mu_est[i] = mu_est[i - estimation_offset];
                }
            }

            __syncthreads();

        }

        step_count += 1;
    }
}


void print_usage() {

    printf("Usage: MCMC options are...\n");
    printf("    Number of steps: --n_steps=n_steps\n");
    printf("    Number of dimensions: --n_dim=n_dim\n");
    printf("    Evaluation frequency: --eval_freq=eval_freq\n");
    printf("    Store data in shared memory (requires small datasets): --shared_memory=1\n");
}


int query_flag_idx(char* arg, const char* query_array[]) {

    int unique_idx = 5;
    int i;

    for (i = 0; i < 4; i++) {
        if (arg[unique_idx] == query_array[i][unique_idx]) {
            return i;
        }
    }

    return -1;
}


int* parse_args(int argc, char *argv[]) {

    const char* query_array[4];
    query_array[0] = "--n_steps";
    query_array[1] = "--n_dim";
    query_array[2] = "--eval_freq";
    query_array[3] = "--shared_memory";

    int* arg_vals = (int*)malloc(4 * sizeof(int));

    int default_n_steps = 10000;
    int default_n = 10;
    int default_spacing = 1000;
    int default_shared = 0;

    int i;
    int arg_idx;
    int init_idx;

    for (i = 0; i < 4; i++) {
        arg_vals[i] = -1;
    }

    for (i = 1; i < argc; i++) {
        if (!strcmp(argv[i], "-h") || !strcmp(argv[i], "--help")) {
            print_usage();
            exit(0);
        } else {
            arg_idx = query_flag_idx(argv[i], query_array);

            if (arg_idx != -1) {
                init_idx = strlen(query_array[arg_idx]) + 1;
                argv[i] += init_idx;
                sscanf(argv[i], "%d", &arg_vals[arg_idx]);
            } else {
                print_usage();
                exit(0);
            }
        }
    }

    if (arg_vals[0] == -1) {
        printf("Number of steps not provided. Defaulting to %d steps.\n", default_n_steps);
        arg_vals[0] = default_n_steps;
    }
    if (arg_vals[1] == -1) {
        printf("Number of dimensions not provided. Defaulting to %d dimensions.\n", default_n);
        arg_vals[1] = default_n;
    }
    if (arg_vals[2] == -1) {
        printf("Evaluation frequency not provided. Defaulting to evaluating every %d steps.\n", default_spacing);
        arg_vals[2] = default_spacing;
    }
    if (arg_vals[3] == -1) {
        printf("Shared memory not specified. Defaulting to using global memory.\n");
        arg_vals[3] = default_shared;
    }

    return arg_vals;
}


int main(int argc, char *argv[]) {

    int* arg_vals = parse_args(argc, argv);
    int n_steps = arg_vals[0];
    int n = arg_vals[1];
    int spacing = arg_vals[2];
    int use_shared = arg_vals[3];

    int n_threads = 1024;
    int n_data = count_n_data(n);
    int n_data_per_thread = n_data / n_threads;
    int n_blocks = 1;

    int n_sample_points = n_steps / spacing;
    int i;

    float mu_step = 0.2;
    float cov_step = 0.2;

    FILE* f;

    hipEvent_t start, stop;
    hiprandState* state;

    float* rand_num;
    float* rand_mu;
    float* rand_cov;
    int* rand_ints;

    float* curr_mu;
    float* new_mu;
    float* curr_cov;
    float* new_cov;

    float* curr_L;
    int* take_step;

    float* data;

    float* mu_inv;
    float* cov_inv;

    float* mu_est;
    float* cov_est;

    float* all_mu_est;

    float* h_data = (float*)malloc(n * n_data * sizeof(float));
    float* h_cov = (float*)malloc(n * n_threads * n_blocks * sizeof(float));
    float* h_mu = (float*)malloc(n * n_threads * n_blocks * sizeof(float));
    float* h_rand = (float*)malloc(n_threads * n_blocks * sizeof(float));
    
    float* h_mu_est = (float*)malloc(n * n_sample_points * sizeof(float));

    CudaSafeCall(hipMalloc(&state, n_blocks * n_threads * sizeof(hiprandState)));

    CudaSafeCall(hipMalloc((void**)&rand_num, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&rand_mu, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&rand_cov, n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&rand_ints, n_blocks * n_threads * sizeof(int)));

    CudaSafeCall(hipMalloc((void**)&curr_L, n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&take_step, n_threads * n_blocks * sizeof(int)));

    CudaSafeCall(hipMalloc((void**)&curr_mu, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&new_mu, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&curr_cov, n * n_threads * n_blocks * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&new_cov, n * n_threads * n_blocks * sizeof(float)));

    CudaSafeCall(hipMalloc((void**)&data, n * n_data * sizeof(float)));

    CudaSafeCall(hipMalloc((void**)&mu_inv, n * n_blocks * n_threads * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&cov_inv, n * n_threads * n_blocks * sizeof(float)));

    CudaSafeCall(hipMalloc((void**)&mu_est, n * sizeof(float)));
    CudaSafeCall(hipMalloc((void**)&cov_est, n * sizeof(float)));

    CudaSafeCall(hipMalloc((void**)&all_mu_est, n * n_sample_points * sizeof(float)));

    hipEventCreate(&start);
    hipEventCreate(&stop);

    // Array for covariance elements held by every thread
    read_data(n_data, n, h_data);

    CudaSafeCall(hipMemcpy(data, h_data, n * n_data * sizeof(float), hipMemcpyHostToDevice));

    // kernel_rand_nums<<<1, 1024>>>(state, rand_mu, rand_cov, mu_step, cov_step, rand_num, rand_ints, n);

    //cudaEventRecord(start);
    //mcmc<<<n_blocks, n_threads>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
    //cudaEventRecord(stop);
    //CudaCheckError();

    if (use_shared == 1) {
        hipEventRecord(start);
        mcmc_shared<<<n_blocks, n_threads, n * n_data * sizeof(float)>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
        hipEventRecord(stop);
        CudaCheckError();
    } else {
        hipEventRecord(start);
        mcmc<<<n_blocks, n_threads>>>(n, n_data, n_data_per_thread, n_threads, n_steps, spacing, mu_step, cov_step, state, curr_cov, new_cov, curr_mu, new_mu, rand_num, rand_ints, rand_mu, rand_cov, curr_L, take_step, data, mu_inv, cov_inv, mu_est, cov_est, all_mu_est);
        hipEventRecord(stop);
        CudaCheckError();
    }


    CudaSafeCall(hipMemcpy(h_cov, curr_cov, n * n_threads * sizeof(float), hipMemcpyDeviceToHost));
    CudaSafeCall(hipMemcpy(h_mu, curr_mu, n * n_threads * sizeof(float), hipMemcpyDeviceToHost));

    CudaSafeCall(hipMemcpy(h_mu_est, all_mu_est, n * n_sample_points * sizeof(float), hipMemcpyDeviceToHost));
    CudaSafeCall(hipMemcpy(h_rand, rand_num, n_threads * sizeof(float), hipMemcpyDeviceToHost));

    hipEventSynchronize(stop);

//    for (i = 0; i < n * n_threads; i++) {
//        printf("%f ", h_mu[i]);
//    }

    float milliseconds = 0.f;
    hipEventElapsedTime(&milliseconds, start, stop);

    printf("Code executed in %f ms.\n", milliseconds);

    f = fopen("mu_data.txt", "w");
    for (i = 0; i < n * n_threads; i++) {
        fprintf(f, "%f ", h_mu[i]);
    }
    fclose(f);

    f = fopen("cov_data.txt", "w");
    for (i = 0; i < n * n_threads; i++) {
        fprintf(f, "%f ", h_cov[i]);
    }
    fclose(f);

    f = fopen("rand_data.txt", "w");
    for (i = 0; i < n_threads; i++) {
        fprintf(f, "%f ", h_rand[i]);
    }
    fclose(f);

    f = fopen("mu_evolution.txt", "w");
    for (i = 0; i < n_sample_points * n; i++) {
        fprintf(f, "%f ", h_mu_est[i]);
        // printf("%f ", h_mu_est[i]);
    }
    fclose(f);


    free(h_data);
    free(h_cov);
    free(h_mu);
    free(h_rand);

    hipFree(state);

    free(h_mu_est);

    hipFree(mu_inv);
    hipFree(cov_inv);

    hipFree(mu_est);
    hipFree(cov_est);

    hipFree(all_mu_est);

    hipFree(rand_num);
    hipFree(rand_mu);
    hipFree(rand_cov);
    hipFree(rand_ints);

    hipFree(curr_L);
    hipFree(take_step);

    hipFree(curr_mu);
    hipFree(new_mu);
    hipFree(curr_cov);
    hipFree(new_cov);

    hipFree(data);

    return 0;
}

	.text
	.file	"mcmc.hip"
	.globl	_Z12count_n_datai               # -- Begin function _Z12count_n_datai
	.type	_Z12count_n_datai,@function
_Z12count_n_datai:                      # @_Z12count_n_datai
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	leaq	16(%rsp), %r14
	movl	$.L.str, %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	sprintf
	movl	$.L.str.1, %esi
	movq	%r14, %rdi
	callq	fopen
	movq	%rax, %r14
	movl	$-1, %ebp
	leaq	12(%rsp), %r15
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incl	%ebp
	cmpl	$-1, %eax
	jne	.LBB0_1
# %bb.2:
	movq	%r14, %rdi
	callq	fclose
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%ebx
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z12count_n_datai, .Lfunc_end0-_Z12count_n_datai
	.cfi_endproc
                                        # -- End function
	.globl	_Z9read_dataiiPf                # -- Begin function _Z9read_dataiiPf
	.type	_Z9read_dataiiPf,@function
_Z9read_dataiiPf:                       # @_Z9read_dataiiPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %rbx
	movl	%esi, %edx
	movq	%rsp, %r14
	movl	$.L.str, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	sprintf
	movl	$.L.str.1, %esi
	movq	%r14, %rdi
	callq	fopen
	movq	%rax, %r14
	xorl	%ebp, %ebp
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ebp, %eax
	leaq	(%rbx,%rax,4), %rdx
	movl	$.L.str.2, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incl	%ebp
	cmpl	$-1, %eax
	jne	.LBB1_1
# %bb.2:
	movq	%r14, %rdi
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end1:
	.size	_Z9read_dataiiPf, .Lfunc_end1-_Z9read_dataiiPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii # -- Begin function _Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.type	_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii,@function
_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii: # @_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	48(%rsp), %r11
	movq	%rcx, (%r11)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%rcx, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii, .Lfunc_end2-_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_ # -- Begin function _Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@function
_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_: # @_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	movq	%rsp, %r10
	movss	%xmm1, (%r10)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .Lfunc_end3-_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_ # -- Begin function _Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.type	_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@function
_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_: # @_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	movq	%rsp, %r10
	movss	%xmm1, (%r10)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .Lfunc_end4-_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11print_usagev                # -- Begin function _Z11print_usagev
	.type	_Z11print_usagev,@function
_Z11print_usagev:                       # @_Z11print_usagev
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	$.Lstr.4, %edi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end5:
	.size	_Z11print_usagev, .Lfunc_end5-_Z11print_usagev
	.cfi_endproc
                                        # -- End function
	.globl	_Z14query_flag_idxPcPPKc        # -- Begin function _Z14query_flag_idxPcPPKc
	.type	_Z14query_flag_idxPcPPKc,@function
_Z14query_flag_idxPcPPKc:               # @_Z14query_flag_idxPcPPKc
	.cfi_startproc
# %bb.0:
	movb	5(%rdi), %cl
	xorl	%eax, %eax
.LBB6_1:                                # =>This Inner Loop Header: Depth=1
	movq	(%rsi,%rax,8), %rdx
	cmpb	5(%rdx), %cl
	je	.LBB6_4
# %bb.2:                                #   in Loop: Header=BB6_1 Depth=1
	incq	%rax
	cmpq	$4, %rax
	jne	.LBB6_1
# %bb.3:
	movl	$-1, %eax
.LBB6_4:                                # %.split.loop.exit
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end6:
	.size	_Z14query_flag_idxPcPPKc, .Lfunc_end6-_Z14query_flag_idxPcPPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z10parse_argsiPPc              # -- Begin function _Z10parse_argsiPPc
	.type	_Z10parse_argsiPPc,@function
_Z10parse_argsiPPc:                     # @_Z10parse_argsiPPc
	.cfi_startproc
# %bb.0:                                # %.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movl	%edi, %ebp
	movq	$.L.str.8, (%rsp)
	movq	$.L.str.9, 8(%rsp)
	movq	$.L.str.10, 16(%rsp)
	movq	$.L.str.11, 24(%rsp)
	movl	$16, %edi
	callq	malloc
	movq	%rax, %rbx
	pcmpeqd	%xmm0, %xmm0
	movdqu	%xmm0, (%rax)
	cmpl	$2, %ebp
	jl	.LBB7_10
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r13d
	movl	$1, %ebp
.LBB7_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_5 Depth 2
	movq	(%r14,%rbp,8), %r15
	movl	$.L.str.12, %esi
	movq	%r15, %rdi
	callq	strcmp
	testl	%eax, %eax
	je	.LBB7_7
# %bb.3:                                #   in Loop: Header=BB7_2 Depth=1
	movl	$.L.str.13, %esi
	movq	%r15, %rdi
	callq	strcmp
	testl	%eax, %eax
	je	.LBB7_7
# %bb.4:                                #   in Loop: Header=BB7_2 Depth=1
	movb	5(%r15), %al
	xorl	%r12d, %r12d
.LBB7_5:                                #   Parent Loop BB7_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%rsp,%r12,2), %rcx
	cmpb	5(%rcx), %al
	je	.LBB7_8
# %bb.6:                                #   in Loop: Header=BB7_5 Depth=2
	addq	$4, %r12
	cmpq	$16, %r12
	jne	.LBB7_5
	jmp	.LBB7_7
.LBB7_8:                                # %_Z14query_flag_idxPcPPKc.exit
                                        #   in Loop: Header=BB7_2 Depth=1
	movq	(%rsp,%r12,2), %rdi
	callq	strlen
	incl	%eax
	cltq
	addq	%rax, %r15
	movq	%r15, (%r14,%rbp,8)
	addq	%rbx, %r12
	movl	$.L.str.14, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	incq	%rbp
	cmpq	%r13, %rbp
	jne	.LBB7_2
# %bb.9:                                # %._crit_edge
	cmpl	$-1, (%rbx)
	jne	.LBB7_11
.LBB7_10:                               # %._crit_edge.thread
	movl	$.L.str.15, %edi
	movl	$10000, %esi                    # imm = 0x2710
	xorl	%eax, %eax
	callq	printf
	movl	$10000, (%rbx)                  # imm = 0x2710
.LBB7_11:
	cmpl	$-1, 4(%rbx)
	jne	.LBB7_13
# %bb.12:
	movl	$.L.str.16, %edi
	movl	$10, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$10, 4(%rbx)
.LBB7_13:
	cmpl	$-1, 8(%rbx)
	jne	.LBB7_15
# %bb.14:
	movl	$.L.str.17, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	xorl	%eax, %eax
	callq	printf
	movl	$1000, 8(%rbx)                  # imm = 0x3E8
.LBB7_15:
	cmpl	$-1, 12(%rbx)
	jne	.LBB7_17
# %bb.16:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$0, 12(%rbx)
.LBB7_17:
	movq	%rbx, %rax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_7:
	.cfi_def_cfa_offset 96
	callq	_Z11print_usagev
	xorl	%edi, %edi
	callq	exit
.Lfunc_end7:
	.size	_Z10parse_argsiPPc, .Lfunc_end7-_Z10parse_argsiPPc
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI8_0:
	.long	0x3e4ccccd                      # float 0.200000003
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	callq	_Z10parse_argsiPPc
	movl	(%rax), %ebx
	movl	4(%rax), %r14d
	movslq	%r14d, %rbp
	movl	8(%rax), %r15d
	movl	12(%rax), %eax
	movl	%eax, 204(%rsp)                 # 4-byte Spill
	movl	%ebp, %edi
	callq	_Z12count_n_datai
	movl	%eax, %ecx
	leal	1023(%rcx), %eax
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movl	%ebx, 32(%rsp)                  # 4-byte Spill
	movl	%ebx, %eax
	cltd
	movl	%r15d, 28(%rsp)                 # 4-byte Spill
	idivl	%r15d
	movl	%eax, %r15d
	movq	%rcx, 208(%rsp)                 # 8-byte Spill
	movl	%ecx, %eax
	imull	%r14d, %eax
	movslq	%eax, %rdi
	shlq	$2, %rdi
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 224(%rsp)                 # 8-byte Spill
	movq	%rbp, %rbx
	shlq	$12, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r13
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r12
	movl	%r14d, 36(%rsp)                 # 4-byte Spill
	imull	%r14d, %r15d
	movl	%r15d, 200(%rsp)                # 4-byte Spill
	movslq	%r15d, %rdi
	shlq	$2, %rdi
	movq	%rdi, 216(%rsp)                 # 8-byte Spill
	callq	malloc
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	leaq	192(%rsp), %rdi
	movl	$49152, %esi                    # imm = 0xC000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_1
# %bb.2:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit
	leaq	72(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_3
# %bb.4:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit145
	leaq	184(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	movl	36(%rsp), %r15d                 # 4-byte Reload
	movq	224(%rsp), %r14                 # 8-byte Reload
	jne	.LBB8_5
# %bb.6:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit147
	leaq	176(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_7
# %bb.8:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit149
	leaq	168(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_9
# %bb.10:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit151
	leaq	144(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_11
# %bb.12:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit153
	leaq	136(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_13
# %bb.14:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit155
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_15
# %bb.16:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit157
	leaq	160(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_17
# %bb.18:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit159
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_19
# %bb.20:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit161
	leaq	152(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_21
# %bb.22:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit163
	leaq	48(%rsp), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_23
# %bb.24:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit165
	leaq	128(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_25
# %bb.26:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit167
	leaq	120(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_27
# %bb.28:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit169
	shlq	$2, %rbp
	leaq	112(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_29
# %bb.30:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit171
	leaq	104(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_31
# %bb.32:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit173
	leaq	40(%rsp), %rdi
	movq	216(%rsp), %rsi                 # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB8_33
# %bb.34:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit175
	leaq	232(%rsp), %rdi
	callq	hipEventCreate
	leaq	80(%rsp), %rdi
	callq	hipEventCreate
	movl	%r15d, %esi
	movq	%r14, %rdx
	callq	_Z9read_dataiiPf
	movq	48(%rsp), %rdi
	movq	%r14, %rsi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB8_35
# %bb.36:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit177
	sarl	$10, 12(%rsp)                   # 4-byte Folded Spill
	movabsq	$4294967297, %rbp               # imm = 0x100000001
	movq	232(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpl	$1, 204(%rsp)                   # 4-byte Folded Reload
	movq	96(%rsp), %r14                  # 8-byte Reload
	leaq	1023(%rbp), %rdx
	movq	%rbp, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	jne	.LBB8_45
# %bb.37:
	movq	16(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_39
# %bb.38:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	.LCPI8_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %edi
	movq	216(%rsp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	20(%rsp), %edx                  # 4-byte Reload
	movl	$1024, %ecx                     # imm = 0x400
	movl	40(%rsp), %r8d                  # 4-byte Reload
	movl	36(%rsp), %r9d                  # 4-byte Reload
	movaps	%xmm0, %xmm1
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	248(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	256(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	272(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	328(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
.LBB8_39:
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipGetLastError
	testl	%eax, %eax
	movq	88(%rsp), %rbp                  # 8-byte Reload
	jne	.LBB8_40
# %bb.43:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB8_52
# %bb.44:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.29, %esi
	jmp	.LBB8_41
.LBB8_45:
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_47
# %bb.46:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	.LCPI8_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %edi
	movq	216(%rsp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	20(%rsp), %edx                  # 4-byte Reload
	movl	$1024, %ecx                     # imm = 0x400
	movl	40(%rsp), %r8d                  # 4-byte Reload
	movl	36(%rsp), %r9d                  # 4-byte Reload
	movaps	%xmm0, %xmm1
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	248(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	256(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	272(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	328(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
.LBB8_47:
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipGetLastError
	testl	%eax, %eax
	movq	88(%rsp), %rbp                  # 8-byte Reload
	jne	.LBB8_48
# %bb.50:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB8_51
.LBB8_52:                               # %_Z16__cudaCheckErrorPKci.exit
	movq	56(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB8_53
# %bb.54:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit183
	movq	64(%rsp), %rsi
	movq	%r13, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB8_55
# %bb.56:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit185
	movq	40(%rsp), %rsi
	movq	%rbp, %rdi
	movq	216(%rsp), %rdx                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB8_57
# %bb.58:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit187
	movq	72(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB8_59
# %bb.60:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit189
	movl	%r15d, %ebp
	shll	$10, %ebp
	movq	80(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	244(%rsp), %rbx
	movl	$0, (%rbx)
	movq	232(%rsp), %rsi
	movq	80(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.20, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.21, %edi
	movl	$.L.str.22, %esi
	callq	fopen
	movq	%rax, %rbx
	testl	%r15d, %r15d
	jle	.LBB8_63
# %bb.61:                               # %.lr.ph.preheader
	cmpl	$2, %ebp
	movl	$1, %r14d
	cmovgel	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB8_62:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%r15,4), %xmm0
	movl	$.L.str.23, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB8_62
.LBB8_63:                               # %._crit_edge
	movq	%r13, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.24, %edi
	movl	$.L.str.22, %esi
	callq	fopen
	movq	%rax, %rbx
	cmpl	$0, 36(%rsp)                    # 4-byte Folded Reload
	movq	96(%rsp), %r13                  # 8-byte Reload
	jle	.LBB8_66
# %bb.64:                               # %.lr.ph202.preheader
	cmpl	$2, %ebp
	movl	$1, %r14d
	cmovgel	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB8_65:                               # %.lr.ph202
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%r15,4), %xmm0
	movl	$.L.str.23, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB8_65
.LBB8_66:                               # %._crit_edge203
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.25, %edi
	movl	$.L.str.22, %esi
	callq	fopen
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB8_67:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%r14,4), %xmm0
	movl	$.L.str.23, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r14
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB8_67
# %bb.68:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.26, %edi
	movl	$.L.str.22, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	200(%rsp), %eax                 # 4-byte Reload
	testl	%eax, %eax
	movq	16(%rsp), %r13                  # 8-byte Reload
	movq	88(%rsp), %rbp                  # 8-byte Reload
	jle	.LBB8_71
# %bb.69:                               # %.lr.ph207.preheader
	movl	%eax, %r14d
	xorl	%r15d, %r15d
.LBB8_70:                               # %.lr.ph207
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbp,%r15,4), %xmm0
	movl	$.L.str.23, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB8_70
.LBB8_71:                               # %._crit_edge208
	movq	%rbx, %rdi
	callq	fclose
	movq	224(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	96(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	192(%rsp), %rdi
	callq	hipFree
	movq	%rbp, %rdi
	callq	free
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	184(%rsp), %rdi
	callq	hipFree
	movq	176(%rsp), %rdi
	callq	hipFree
	movq	168(%rsp), %rdi
	callq	hipFree
	movq	144(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	160(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	152(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB8_1:
	.cfi_def_cfa_offset 304
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$676, %ecx                      # imm = 0x2A4
	jmp	.LBB8_42
.LBB8_3:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$678, %ecx                      # imm = 0x2A6
	jmp	.LBB8_42
.LBB8_5:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$679, %ecx                      # imm = 0x2A7
	jmp	.LBB8_42
.LBB8_7:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$680, %ecx                      # imm = 0x2A8
	jmp	.LBB8_42
.LBB8_9:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$681, %ecx                      # imm = 0x2A9
	jmp	.LBB8_42
.LBB8_11:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$683, %ecx                      # imm = 0x2AB
	jmp	.LBB8_42
.LBB8_13:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$684, %ecx                      # imm = 0x2AC
	jmp	.LBB8_42
.LBB8_15:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$686, %ecx                      # imm = 0x2AE
	jmp	.LBB8_42
.LBB8_17:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$687, %ecx                      # imm = 0x2AF
	jmp	.LBB8_42
.LBB8_19:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$688, %ecx                      # imm = 0x2B0
	jmp	.LBB8_42
.LBB8_21:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$689, %ecx                      # imm = 0x2B1
	jmp	.LBB8_42
.LBB8_23:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$691, %ecx                      # imm = 0x2B3
	jmp	.LBB8_42
.LBB8_25:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$693, %ecx                      # imm = 0x2B5
	jmp	.LBB8_42
.LBB8_27:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$694, %ecx                      # imm = 0x2B6
	jmp	.LBB8_42
.LBB8_29:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$696, %ecx                      # imm = 0x2B8
	jmp	.LBB8_42
.LBB8_31:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$697, %ecx                      # imm = 0x2B9
	jmp	.LBB8_42
.LBB8_33:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$699, %ecx                      # imm = 0x2BB
	jmp	.LBB8_42
.LBB8_35:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$707, %ecx                      # imm = 0x2C3
	jmp	.LBB8_42
.LBB8_53:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$729, %ecx                      # imm = 0x2D9
	jmp	.LBB8_42
.LBB8_55:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$730, %ecx                      # imm = 0x2DA
	jmp	.LBB8_42
.LBB8_57:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$732, %ecx                      # imm = 0x2DC
	jmp	.LBB8_42
.LBB8_59:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.27, %esi
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$733, %ecx                      # imm = 0x2DD
	jmp	.LBB8_42
.LBB8_40:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.28, %esi
.LBB8_41:
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$720, %ecx                      # imm = 0x2D0
	jmp	.LBB8_42
.LBB8_48:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.28, %esi
	jmp	.LBB8_49
.LBB8_51:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.29, %esi
.LBB8_49:
	movl	$.L.str.19, %edx
	movq	%rbx, %rdi
	movl	$725, %ecx                      # imm = 0x2D5
.LBB8_42:
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end8:
	.size	main, .Lfunc_end8-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"data_%d.txt"
	.size	.L.str, 12

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%f"
	.size	.L.str.2, 3

	.type	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii,@object # @_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.section	.rodata,"a",@progbits
	.globl	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.p2align	3, 0x0
_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii:
	.quad	_Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.size	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii, 8

	.type	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@object # @_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.p2align	3, 0x0
_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
	.quad	_Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.size	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, 8

	.type	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@object # @_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.p2align	3, 0x0
_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_:
	.quad	_Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.size	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, 8

	.type	.L.str.8,@object                # @.str.8
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.8:
	.asciz	"--n_steps"
	.size	.L.str.8, 10

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"--n_dim"
	.size	.L.str.9, 8

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"--eval_freq"
	.size	.L.str.10, 12

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"--shared_memory"
	.size	.L.str.11, 16

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"-h"
	.size	.L.str.12, 3

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"--help"
	.size	.L.str.13, 7

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"%d"
	.size	.L.str.14, 3

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Number of steps not provided. Defaulting to %d steps.\n"
	.size	.L.str.15, 55

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Number of dimensions not provided. Defaulting to %d dimensions.\n"
	.size	.L.str.16, 65

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Evaluation frequency not provided. Defaulting to evaluating every %d steps.\n"
	.size	.L.str.17, 77

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/MaxwellDeJong/parallel_mcmc/main/mcmc.hip"
	.size	.L.str.19, 104

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"Code executed in %f ms.\n"
	.size	.L.str.20, 25

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"mu_data.txt"
	.size	.L.str.21, 12

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"w"
	.size	.L.str.22, 2

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"%f "
	.size	.L.str.23, 4

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"cov_data.txt"
	.size	.L.str.24, 13

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"rand_data.txt"
	.size	.L.str.25, 14

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"mu_evolution.txt"
	.size	.L.str.26, 17

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	"cudaSafeCall() failed at %s:%i : %s\n"
	.size	.L.str.27, 37

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"cudaCheckError() failed at %s:%i : %s\n"
	.size	.L.str.28, 39

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"cudaCheckError() with sync failed at %s:%i : %s\n"
	.size	.L.str.29, 49

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii"
	.size	.L__unnamed_1, 49

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_"
	.size	.L__unnamed_2, 85

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_"
	.size	.L__unnamed_3, 77

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Usage: MCMC options are..."
	.size	.Lstr, 27

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"    Number of steps: --n_steps=n_steps"
	.size	.Lstr.1, 39

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"    Number of dimensions: --n_dim=n_dim"
	.size	.Lstr.2, 40

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"    Evaluation frequency: --eval_freq=eval_freq"
	.size	.Lstr.3, 48

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"    Store data in shared memory (requires small datasets): --shared_memory=1"
	.size	.Lstr.4, 77

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"Shared memory not specified. Defaulting to using global memory."
	.size	.Lstr.5, 64

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.addrsig_sym _Z26__device_stub__mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.addrsig_sym _Z19__device_stub__mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.addrsig_sym _Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.addrsig_sym _Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii
	.type	_Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii,@function
_Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii: ; @_Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_load_b32 s0, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s12, s0
	s_cselect_b32 s0, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, s0
	global_load_u16 v14, v13, s[8:9]
	v_and_b32_e32 v13, 0x3ff, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[21:22], null, s12, v14, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[13:14], null, v21, 48, v[0:1]
	v_ashrrev_i32_e32 v22, 31, v21
	s_clause 0x2
	flat_load_b128 v[15:18], v[13:14] offset:24
	flat_load_b32 v19, v[13:14] offset:40
	flat_load_b32 v23, v[13:14]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_lshrrev_b32_e32 v0, 2, v15
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v1, 4, v19
	v_lshrrev_b32_e32 v20, 2, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v15
	v_lshlrev_b32_e32 v15, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v15, v1
	v_xor_b32_e32 v15, v20, v16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v16, 0xb0f8a, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v20, v1, v0, v19
	v_lshlrev_b32_e32 v0, 1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 4, v20
	v_xor_b32_e32 v0, v0, v1
	v_lshlrev_b32_e32 v1, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v15, v0, v15, v20
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v15, v16
	v_cvt_f32_u32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
	v_mul_f32_e32 v12, v0, v1
	v_lshlrev_b64 v[0:1], 2, v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v12, v12
	v_add_co_u32 v10, vcc_lo, v10, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v1, vcc_lo
	s_clause 0x2
	flat_store_b32 v[13:14], v15 offset:40
	flat_store_b128 v[13:14], v[17:20] offset:24
	flat_store_b32 v[13:14], v16
	flat_store_b32 v[10:11], v12
	flat_load_b32 v10, v[13:14] offset:4
	v_add3_u32 v11, v23, v20, 0x587c5
	v_add_co_u32 v8, vcc_lo, v8, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v11, v11
	v_fmaak_f32 v11, 0x2f800000, v11, 0x2f800000
	flat_store_b32 v[8:9], v11
                                        ; implicit-def: $vgpr8
	s_waitcnt vmcnt(0) lgkmcnt(1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	flat_load_b32 v8, v[13:14] offset:12
.LBB0_2:                                ; %Flow19
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_clause 0x2
	flat_load_b128 v[8:11], v[13:14] offset:24
	flat_load_b32 v17, v[13:14] offset:40
	flat_load_b32 v12, v[13:14]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_lshrrev_b32_e32 v15, 2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v15, v8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v15, 4, v17
	v_lshlrev_b32_e32 v16, 1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v16, v15
	v_xor3_b32 v18, v15, v8, v17
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v8, v12, v18, 0x587c5
	v_add_nc_u32_e32 v12, 0xb0f8a, v12
	v_lshlrev_b32_e32 v19, 4, v18
	v_cvt_f32_u32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, 0x2f800000, v8, 0x2f800000
	v_cmp_gt_f32_e64 s0, 0x800000, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, 1.0, 0x4f800000, s0
	v_mul_f32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, 0x3f317217, v8
	v_fma_f32 v16, 0x3f317217, v8, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v16, v8, 0x3377d1cf, v16
	v_add_f32_e32 v15, v15, v16
	v_cndmask_b32_e64 v16, 0, 0x41b17218, s0
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v15, s0
	v_sub_f32_e32 v8, v8, v16
	v_lshrrev_b32_e32 v16, 2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, -2.0, v8
	v_xor_b32_e32 v9, v16, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, 0x4f800000, v8
	v_cmp_gt_f32_e64 s0, 0xf800000, v8
	v_lshlrev_b32_e32 v16, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v8, v15, s0
	v_xor_b32_e32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v15, v8
	v_xor3_b32 v9, v16, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v21, v9, v12
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v19, -1, v15
	v_add_nc_u32_e32 v16, 1, v15
	v_fma_f32 v20, -v19, v15, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v16, v15, v8
	v_cmp_ge_f32_e64 s1, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v19, s1
	v_cvt_f32_u32_e32 v19, v21
	v_cmp_lt_f32_e64 s1, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v16, s1
	v_fmaak_f32 v16, 0x30c90fdb, v19, 0x30c90fdb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, 0x37800000, v15 :: v_dual_mul_f32 v16, 0.15915494, v16
	v_cndmask_b32_e64 v15, v15, v19, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cos_f32_e32 v19, v16
	v_sin_f32_e32 v20, v16
	v_cmp_class_f32_e64 s0, v8, 0x260
	v_mov_b32_e32 v16, v11
	v_cndmask_b32_e64 v8, v15, v8, s0
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v15, v10 :: v_dual_mul_f32 v10, v8, v19
	v_mul_f32_e32 v8, v8, v20
	s_clause 0x3
	flat_store_b32 v[13:14], v9 offset:40
	flat_store_b32 v[13:14], v12
	flat_store_b128 v[13:14], v[15:18] offset:24
	flat_store_b32 v[13:14], v10 offset:12
.LBB0_4:                                ; %_Z14hiprand_normalI12hiprandStateEfPT_.exit.i
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v2, s0, v2, v0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v6, v8, v6
	v_add_co_ci_u32_e64 v3, s0, v3, v1, s0
                                        ; implicit-def: $sgpr0
	flat_store_b32 v[2:3], v6
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_clause 0x2
	flat_load_b128 v[8:11], v[13:14] offset:24
	flat_load_b32 v17, v[13:14] offset:40
	flat_load_b32 v2, v[13:14]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_lshrrev_b32_e32 v3, 2, v8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v6, 4, v17
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v19, 0xb0f8a, v2
	v_xor_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v8, 1, v3
	v_xor_b32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v18, v6, v3, v17
	v_add3_u32 v3, v2, v18, 0x587c5
	v_lshlrev_b32_e32 v12, 4, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, v3
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x3f317217, v3
	v_fma_f32 v8, 0x3f317217, v3, -v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v3, 0x3377d1cf, v8
	v_add_f32_e32 v6, v6, v8
	v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_sub_f32_e32 v3, v3, v8
	v_lshrrev_b32_e32 v8, 2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, -2.0, v3
	v_mul_f32_e32 v6, 0x4f800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_xor_b32_e32 v6, v8, v9
	v_sqrt_f32_e32 v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v9, 1, v6
	v_xor_b32_e32 v9, v9, v12
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v12, -1, v8
	v_xor3_b32 v6, v9, v6, v18
	v_add_nc_u32_e32 v2, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, -v12, v8, v3
	v_add_nc_u32_e32 v15, v6, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, -v2, v8, v3
	v_cmp_ge_f32_e64 s0, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v9, v15
	v_mov_b32_e32 v15, v10
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cmp_lt_f32_e64 s0, 0, v16
	v_mov_b32_e32 v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v8, v2, s0
	v_fmaak_f32 v8, 0x30c90fdb, v9, 0x30c90fdb
	s_mov_b32 s0, 1
	v_dual_mul_f32 v9, 0x37800000, v2 :: v_dual_mul_f32 v8, 0.15915494, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v9, vcc_lo
	v_cos_f32_e32 v9, v8
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_sin_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v2, v9
	v_mul_f32_e32 v2, v2, v8
	s_clause 0x3
	flat_store_b32 v[13:14], v6 offset:40
	flat_store_b32 v[13:14], v19
	flat_store_b128 v[13:14], v[15:18] offset:24
	flat_store_b32 v[13:14], v3 offset:12
.LBB0_6:                                ; %Flow
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v3, s0
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:
	flat_load_b32 v2, v[13:14] offset:12
	v_mov_b32_e32 v3, 0
.LBB0_8:                                ; %_Z17get_rand_gaussianP12hiprandStatefPffS1_.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v2, v2, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	flat_store_b32 v[13:14], v3 offset:4
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii, .Lfunc_end0-_Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1544
; NumSgprs: 34
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii ; -- Begin function _Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.globl	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
	.p2align	8
	.type	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii,@function
_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii: ; @_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x30
	v_mov_b32_e32 v31, v0
	s_add_u32 s8, s0, 56
	s_mov_b32 s12, s15
	s_addc_u32 s9, s1, 0
	s_mov_b32 s32, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@lo+4
	s_addc_u32 s1, s1, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
	v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
	v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
	v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
	v_mov_b32_e32 v12, s2
	s_swappc_b64 s[30:31], s[0:1]
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii, .Lfunc_end1-_Z16kernel_rand_numsP12hiprandStatePfS1_ffS1_Pii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_ ; -- Begin function _Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.p2align	8
	.type	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@function
_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_: ; @_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
; %bb.0:
	s_mov_b64 s[4:5], s[0:1]
	s_load_b32 s0, s[0:1], 0xb4
	s_clause 0x1
	s_load_b32 s7, s[4:5], 0x0
	s_load_b128 s[16:19], s[4:5], 0x8
	v_mov_b32_e32 v31, v0
	s_mov_b32 s12, s15
	s_clause 0x1
	s_load_b64 s[10:11], s[4:5], 0x18
	s_load_b512 s[36:51], s[4:5], 0x60
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s12, s0, v[31:32]
	s_mul_i32 s0, s16, s7
	v_mul_lo_u32 v24, v0, s7
	v_mul_lo_u32 v12, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v52, s7, v24
	v_mul_lo_u32 v26, v24, s16
	v_mul_lo_u32 v53, v52, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s3, v26, v53
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v27, 31, v26
	v_lshl_add_u32 v3, v12, 2, 0
	v_mov_b32_e32 v4, v26
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[26:27]
	v_add_co_u32 v1, vcc_lo, s42, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s43, v2, vcc_lo
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[1:2], off
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v4, v53
	s_or_b32 s2, s0, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
	v_add_nc_u32_e32 v3, 4, v3
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow412
	s_or_b32 exec_lo, exec_lo, s1
	s_load_b512 s[52:67], s[4:5], 0x20
	s_cmp_lt_i32 s7, 1
	v_ashrrev_i32_e32 v25, 31, v24
	s_cselect_b32 s13, -1, 0
	s_cmp_gt_i32 s7, 0
	s_mov_b32 s2, 0
	s_cselect_b32 s1, -1, 0
	s_and_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB2_9
; %bb.4:                                ; %.lr.ph.i.preheader
	v_lshlrev_b64 v[1:2], 2, v[24:25]
	v_dual_mov_b32 v5, 0x40a00000 :: v_dual_mov_b32 v6, v24
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s54, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s55, v2, vcc_lo
.LBB2_5:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v6
	global_store_b32 v[3:4], v5, off
	v_add_co_u32 v3, s0, v3, 4
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	v_cmp_ge_i32_e32 vcc_lo, v6, v52
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_5
; %bb.6:                                ; %.lr.ph.i117.preheader
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v1, vcc_lo, s58, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s59, v2, vcc_lo
	v_dual_mov_b32 v3, 1.0 :: v_dual_mov_b32 v4, v24
	s_mov_b32 s2, 0
.LBB2_7:                                ; %.lr.ph.i117
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v4
	global_store_b32 v[1:2], v3, off
	v_add_co_u32 v1, s0, v1, 4
	v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
	v_cmp_ge_i32_e32 vcc_lo, v4, v52
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_7
; %bb.8:                                ; %Flow407
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_9:                                ; %_Z16initialize_meansfPfi.exit
	v_xor_b32_e32 v2, 0x2c7f967f, v0
	v_dual_mov_b32 v3, 0x8a5d614f :: v_dual_mov_b32 v10, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v4, 0x493c4aa1, v2
	v_cndmask_b32_e64 v54, 0, 1, s1
	v_mov_b32_e32 v11, v10
	v_cndmask_b32_e32 v9, 0xfa091aa4, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[2:3], null, v0, 48, s[52:53]
	s_mov_b32 s2, 0
	s_and_not1_b32 vcc_lo, exec_lo, s1
	v_add_nc_u32_e32 v7, 0x1f123bb5, v9
	v_xor_b32_e32 v8, 0x5491333, v9
	v_add_nc_u32_e32 v5, 0x75bcd15, v4
	v_xor_b32_e32 v6, 0x159a55e5, v4
	v_add3_u32 v9, v4, v9, 0x64f0c9
	v_dual_mov_b32 v4, 1.0 :: v_dual_add_nc_u32 v13, 0x583f19, v4
	s_clause 0x2
	global_store_b96 v[2:3], v[9:11], off
	global_store_b128 v[2:3], v[5:8], off offset:24
	global_store_b32 v[2:3], v13, off offset:40
	s_cbranch_vccnz .LBB2_13
; %bb.10:                               ; %.lr.ph.i.i.i.preheader
	v_lshlrev_b64 v[2:3], 2, v[24:25]
	v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v5, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s54, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s55, v3, vcc_lo
.LBB2_11:                               ; %.lr.ph.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[2:3], off
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v4, v6
	v_cmp_ge_i32_e64 s0, v5, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_11
; %bb.12:                               ; %Flow404
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_13:                               ; %_Z11get_log_detPfi.exit.i
	v_cvt_f64_i32_e32 v[2:3], s7
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[2:3], v[2:3], -0.5
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB2_21
; %bb.14:                               ; %.lr.ph.i119
	s_mov_b32 s8, 0xc864beb4
	s_mov_b32 s9, 0x3ffd67f1
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[5:6], v[2:3], s[8:9]
	v_lshl_add_u32 v16, v12, 2, 0
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v17, v26
	v_cndmask_b32_e64 v7, 1.0, 0x4f800000, vcc_lo
	s_mov_b32 s2, 0
	s_lshl_b32 s6, s7, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v4, v7
	v_log_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v4
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3f317217, v4, -v7
	v_cvt_f32_f64_e32 v14, v[5:6]
	v_fmamk_f32 v5, v4, 0x3377d1cf, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v7, v5
	v_lshlrev_b64 v[6:7], 2, v[24:25]
	v_cndmask_b32_e64 v4, v4, v5, s0
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v5
	v_mul_f32_e32 v15, -0.5, v4
	v_add_co_u32 v4, vcc_lo, s58, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s59, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s54, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s55, v7, vcc_lo
.LBB2_15:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_17 Depth 2
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	v_mov_b32_e32 v8, 0
	s_cbranch_vccnz .LBB2_19
; %bb.16:                               ; %.lr.ph.i.i20.i
                                        ;   in Loop: Header=BB2_15 Depth=1
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v9, v7
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v11, v5
	v_mov_b32_e32 v10, v4
	v_mov_b32_e32 v19, v16
	v_mov_b32_e32 v20, v24
	s_mov_b32 s8, 0
.LBB2_17:                               ;   Parent Loop BB2_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v21, v[10:11], off
	global_load_b32 v22, v[8:9], off
	ds_load_b32 v23, v19
	v_add_co_u32 v8, s0, v8, 4
	v_add_nc_u32_e32 v19, 4, v19
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_dual_sub_f32 v21, v23, v21 :: v_dual_add_nc_u32 v20, 1, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, v21, v21
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[21:22], v22
	v_cvt_f64_f32_e32 v[27:28], v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[29:30], null, v[21:22], v[21:22], v[27:28]
	v_div_scale_f64 v[36:37], vcc_lo, v[27:28], v[21:22], v[27:28]
	v_rcp_f64_e32 v[32:33], v[29:30]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[34:35], -v[29:30], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33]
	v_fma_f64 v[34:35], -v[29:30], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33]
	v_mul_f64 v[34:35], v[36:37], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], -v[29:30], v[34:35], v[36:37]
	v_div_fmas_f64 v[29:30], v[29:30], v[32:33], v[34:35]
	v_cvt_f64_f32_e32 v[32:33], v18
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v20, v52
	s_or_b32 s8, vcc_lo, s8
	v_div_fixup_f64 v[21:22], v[29:30], v[21:22], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[21:22], v[32:33]
	v_cvt_f32_f64_e32 v18, v[21:22]
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_17
; %bb.18:                               ; %_Z21calc_vec_mat_vec_prodPfS_S_ii.exit.loopexit.i.i
                                        ;   in Loop: Header=BB2_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v8, 0.5, v18
.LBB2_19:                               ; %_Z18get_log_likelihoodPfS_S_fii.exit.i
                                        ;   in Loop: Header=BB2_15 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v15, v8 :: v_dual_add_nc_u32 v17, s7, v17
	v_add_nc_u32_e32 v16, s6, v16
	v_add_f32_e32 v8, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_o_f32_e32 vcc_lo, v8, v8
	v_cndmask_b32_e32 v8, 0xdf0ac723, v8, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v17, v53
	v_add_f32_e32 v13, v13, v8
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_15
; %bb.20:                               ; %Flow401
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_21:                               ; %Flow402
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	v_add_co_u32 v27, s0, s38, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v28, s0, s39, v5, s0
	global_store_b32 v[27:28], v13, off
	s_cbranch_vccnz .LBB2_27
; %bb.22:                               ; %.lr.ph.i120.preheader
	v_lshlrev_b64 v[6:7], 2, v[24:25]
	v_mov_b32_e32 v1, v24
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s54, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s55, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s56, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s57, v7, vcc_lo
.LBB2_23:                               ; %.lr.ph.i120
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v13, v[8:9], off
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v52
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v13, off
	v_add_co_u32 v10, s0, v10, 4
	v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_23
; %bb.24:                               ; %.lr.ph.i121.preheader
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v8, vcc_lo, s58, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s59, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s60, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s61, v7, vcc_lo
	v_mov_b32_e32 v1, v24
	s_mov_b32 s1, 0
.LBB2_25:                               ; %.lr.ph.i121
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v10, v[8:9], off
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v52
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v10, off
	v_add_co_u32 v6, s0, v6, 4
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_25
; %bb.26:                               ; %Flow395
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_27:                               ; %_Z7vec_cpyPfS_i.exit123
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB2_92
; %bb.28:                               ; %.lr.ph153
	s_mov_b32 s0, 0xc864beb4
	s_mov_b32 s1, 0x3ffd67f1
	v_cmp_eq_u32_e64 s6, 0, v0
	v_mul_f64 v[0:1], v[2:3], s[0:1]
	s_xor_b32 s2, s13, -1
	v_add_co_u32 v29, vcc_lo, s64, v4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s16, s2, s6
	s_cmp_gt_i32 s17, 0
	v_add_co_ci_u32_e32 v30, vcc_lo, s65, v5, vcc_lo
	s_cselect_b32 s24, -1, 0
	s_cmp_gt_i32 s7, 0
	v_add_co_u32 v32, vcc_lo, s36, v4
	s_cselect_b32 s25, -1, 0
	s_ashr_i32 s26, s19, 31
	v_add_co_ci_u32_e32 v33, vcc_lo, s37, v5, vcc_lo
	s_add_i32 s0, s19, s26
	v_add_co_u32 v34, vcc_lo, s66, v4
	s_xor_b32 s27, s0, s26
	v_add_co_ci_u32_e32 v35, vcc_lo, s67, v5, vcc_lo
	v_cvt_f32_u32_e32 v2, s27
	v_add_co_u32 v36, vcc_lo, s62, v4
	v_add_co_ci_u32_e32 v37, vcc_lo, s63, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v2, v2
	v_mov_b32_e32 v57, 0
	v_add_co_u32 v38, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v39, vcc_lo, s41, v5, vcc_lo
	s_load_b64 s[14:15], s[4:5], 0xa0
	s_sub_i32 s0, 0, s27
	v_subrev_nc_u32_e32 v55, s7, v24
	v_lshl_add_u32 v56, v12, 2, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mov_b32_e32 v58, 1
	s_mov_b32 s21, 0
	s_lshl_b32 s29, s7, 2
	s_mov_b32 s33, 0
	v_cvt_u32_f32_e32 v6, v2
	v_lshlrev_b64 v[2:3], 2, v[24:25]
	v_cvt_f32_f64_e32 v25, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s1, v6
	v_add_co_u32 v40, vcc_lo, s56, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v41, vcc_lo, s57, v3, vcc_lo
	v_add_co_u32 v42, vcc_lo, s60, v2
	v_add_co_ci_u32_e32 v43, vcc_lo, s61, v3, vcc_lo
	v_add_co_u32 v44, vcc_lo, s54, v2
	v_add_co_ci_u32_e32 v45, vcc_lo, s55, v3, vcc_lo
	v_add_co_u32 v46, vcc_lo, s58, v2
	v_add_co_ci_u32_e32 v47, vcc_lo, s59, v3, vcc_lo
	v_add_co_u32 v48, vcc_lo, s46, v2
	v_add_co_ci_u32_e32 v49, vcc_lo, s47, v3, vcc_lo
	v_add_co_u32 v50, vcc_lo, s44, v2
	s_mul_i32 s0, s0, s1
	v_add_co_ci_u32_e32 v51, vcc_lo, s45, v3, vcc_lo
	s_mul_hi_u32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s28, s1, s0
.LBB2_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_37 Depth 2
                                        ;     Child Loop BB2_41 Depth 2
                                        ;       Child Loop BB2_43 Depth 3
                                        ;     Child Loop BB2_57 Depth 2
                                        ;     Child Loop BB2_59 Depth 2
                                        ;     Child Loop BB2_63 Depth 2
                                        ;     Child Loop BB2_67 Depth 2
                                        ;     Child Loop BB2_69 Depth 2
                                        ;       Child Loop BB2_70 Depth 3
                                        ;     Child Loop BB2_74 Depth 2
                                        ;     Child Loop BB2_78 Depth 2
                                        ;     Child Loop BB2_80 Depth 2
                                        ;       Child Loop BB2_82 Depth 3
                                        ;     Child Loop BB2_85 Depth 2
                                        ;     Child Loop BB2_89 Depth 2
	v_dual_mov_b32 v0, s52 :: v_dual_mov_b32 v1, s53
	v_dual_mov_b32 v2, s66 :: v_dual_mov_b32 v3, s67
	v_dual_mov_b32 v4, s36 :: v_dual_mov_b32 v5, s37
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	v_dual_mov_b32 v8, s62 :: v_dual_mov_b32 v9, s63
	v_dual_mov_b32 v10, s64 :: v_dual_mov_b32 v11, s65
	v_mov_b32_e32 v12, s7
	s_add_u32 s8, s4, 0xa8
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@lo+4
	s_addc_u32 s1, s1, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	global_load_b32 v0, v[29:30], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_le_i32_e64 s7, v0
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB2_33
; %bb.30:                               ;   in Loop: Header=BB2_29 Depth=1
	v_add_nc_u32_e32 v0, v55, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s54, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s55, v1, vcc_lo
	global_load_b32 v4, v[32:33], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 0, v2
	s_cbranch_execz .LBB2_32
; %bb.31:                               ;   in Loop: Header=BB2_29 Depth=1
	v_add_co_u32 v0, vcc_lo, s56, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s57, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_32:                               ; %Flow389
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr0
.LBB2_33:                               ; %Flow391
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_35
; %bb.34:                               ;   in Loop: Header=BB2_29 Depth=1
	v_add_nc_u32_e32 v0, v0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s58, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s59, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s60, v0
	global_load_b32 v4, v[34:35], off
	global_load_b32 v2, v[2:3], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s61, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v4
	global_store_b32 v[0:1], v2, off
.LBB2_35:                               ; %_Z14perturb_paramsPfS_S_S_PiS_S_i.exit
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[27:28], off
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	v_mov_b32_e32 v2, 1.0
	s_cbranch_vccnz .LBB2_39
; %bb.36:                               ; %.lr.ph.i.i.i.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_mov_b32_e32 v0, v40
	v_dual_mov_b32 v2, 1.0 :: v_dual_mov_b32 v1, v41
	v_mov_b32_e32 v3, v24
	s_mov_b32 s1, 0
.LBB2_37:                               ; %.lr.ph.i.i.i.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[0:1], off
	v_add_nc_u32_e32 v3, 1, v3
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v2, v5
	v_cmp_ge_i32_e64 s0, v3, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_37
; %bb.38:                               ; %Flow387
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_39:                               ; %_Z11get_log_detPfi.exit.i.i
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_mov_b32_e32 v5, 0
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB2_47
; %bb.40:                               ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	v_mov_b32_e32 v8, v26
	s_mov_b32 s2, 0
	v_mov_b32_e32 v5, 0
	v_cndmask_b32_e64 v0, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v2, v0
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x3f317217, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, 0x3f317217, v0, -v1
	v_fmac_f32_e32 v2, 0x3377d1cf, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v1, v2
	v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v2
	v_dual_mov_b32 v6, v56 :: v_dual_mul_f32 v7, -0.5, v0
.LBB2_41:                               ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_43 Depth 3
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	v_mov_b32_e32 v0, 0
	s_cbranch_vccnz .LBB2_45
; %bb.42:                               ; %.lr.ph.i.i20.i.i
                                        ;   in Loop: Header=BB2_41 Depth=2
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v0, v40
	v_dual_mov_b32 v1, v41 :: v_dual_mov_b32 v2, v42
	v_dual_mov_b32 v3, v43 :: v_dual_mov_b32 v10, v6
	v_mov_b32_e32 v11, v24
	s_mov_b32 s8, 0
.LBB2_43:                               ;   Parent Loop BB2_29 Depth=1
                                        ;     Parent Loop BB2_41 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v12, v[2:3], off
	global_load_b32 v13, v[0:1], off
	ds_load_b32 v14, v10
	v_add_co_u32 v0, s0, v0, 4
	v_add_nc_u32_e32 v10, 4, v10
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_dual_sub_f32 v12, v14, v12 :: v_dual_add_nc_u32 v11, 1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v12, v12
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v13
	v_cvt_f64_f32_e32 v[14:15], v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], v[14:15]
	v_div_scale_f64 v[22:23], vcc_lo, v[14:15], v[12:13], v[14:15]
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_mul_f64 v[20:21], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[16:17], v[20:21], v[22:23]
	v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_cvt_f64_f32_e32 v[18:19], v9
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v11, v52
	s_or_b32 s8, vcc_lo, s8
	v_div_fixup_f64 v[12:13], v[16:17], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], v[18:19]
	v_cvt_f32_f64_e32 v9, v[12:13]
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_43
; %bb.44:                               ; %_Z21calc_vec_mat_vec_prodPfS_S_ii.exit.loopexit.i.i.i
                                        ;   in Loop: Header=BB2_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v0, 0.5, v9
.LBB2_45:                               ; %_Z18get_log_likelihoodPfS_S_fii.exit.i.i
                                        ;   in Loop: Header=BB2_41 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v0, v7, v0
	v_add_nc_u32_e32 v8, s7, v8
	v_add_nc_u32_e32 v6, s29, v6
	v_add_f32_e32 v0, v0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_cndmask_b32_e32 v0, 0xdf0ac723, v0, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v8, v53
	v_add_f32_e32 v5, v5, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_41
; %bb.46:                               ; %Flow384
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_47:                               ; %Flow385
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e32 v5, v4
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB2_53
; %bb.48:                               ;   in Loop: Header=BB2_29 Depth=1
	global_load_b32 v0, v[36:37], off
	v_sub_f32_e32 v1, v5, v4
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3fb8aa3b, v1
	v_fma_f32 v3, 0x3fb8aa3b, v1, -v2
	v_rndne_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v3, 0x32a5705f, v1 :: v_dual_sub_f32 v2, v2, v4
	v_add_f32_e32 v2, v2, v3
	v_cvt_i32_f32_e32 v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v2, v3
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmpx_nlt_f32_e32 v0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_50
; %bb.49:                               ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b32 s1, -1
	global_store_b32 v[38:39], v57, off
                                        ; implicit-def: $vgpr5
.LBB2_50:                               ; %Flow377
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB2_52
; %bb.51:                               ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_b32 s1, s1, exec_lo
	global_store_b32 v[38:39], v58, off
	global_store_b32 v[27:28], v5, off
.LBB2_52:                               ; %Flow378
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr5
.LBB2_53:                               ; %Flow380
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_55
; %bb.54:                               ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_b32 s1, s1, exec_lo
	global_store_b32 v[38:39], v58, off
	global_store_b32 v[27:28], v5, off
.LBB2_55:                               ; %_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_.exit
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_or_b32 s0, s13, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_60
; %bb.56:                               ; %.lr.ph.i124.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_dual_mov_b32 v0, v44 :: v_dual_mov_b32 v1, v45
	v_dual_mov_b32 v2, v40 :: v_dual_mov_b32 v3, v41
	v_mov_b32_e32 v4, v24
	s_mov_b32 s2, 0
.LBB2_57:                               ; %.lr.ph.i124
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v52
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, s0, v0, 4
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_57
; %bb.58:                               ; %.lr.ph.i127.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v0, v46 :: v_dual_mov_b32 v1, v47
	v_dual_mov_b32 v2, v42 :: v_dual_mov_b32 v3, v43
	v_mov_b32_e32 v4, v24
	s_mov_b32 s2, 0
.LBB2_59:                               ; %.lr.ph.i127
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v52
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, s0, v0, 4
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_59
.LBB2_60:                               ; %Flow375
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_mul_hi_u32 s0, s33, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s27
	s_add_i32 s2, s0, 1
	s_sub_i32 s1, s33, s1
	s_sub_i32 s8, s1, s27
	s_cmp_ge_u32 s1, s27
	s_cselect_b32 s0, s2, s0
	s_cselect_b32 s1, s8, s1
	s_add_i32 s2, s0, 1
	s_cmp_ge_u32 s1, s27
	s_cselect_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s26
	s_sub_i32 s2, s0, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s2, s19
	s_sub_i32 s0, s33, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB2_91
; %bb.61:                               ;   in Loop: Header=BB2_29 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	s_cbranch_vccnz .LBB2_65
; %bb.62:                               ; %.lr.ph.i130.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_dual_mov_b32 v0, v48 :: v_dual_mov_b32 v1, v49
	v_dual_mov_b32 v2, v44 :: v_dual_mov_b32 v3, v45
	v_mov_b32_e32 v4, v24
	s_mov_b32 s1, 0
.LBB2_63:                               ; %.lr.ph.i130
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v6, null, v5, v5, 1.0
	v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v7, 1.0
	v_dual_fmac_f32 v7, v9, v7 :: v_dual_add_nc_u32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e64 s0, v4, v52
	v_mul_f32_e32 v9, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s1, s0, s1
	v_fma_f32 v10, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v7
	v_fma_f32 v6, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v7, v9
	v_div_fixup_f32 v5, v6, v5, 1.0
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_63
; %bb.64:                               ; %Flow369
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_65:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_and_saveexec_b32 s22, s16
	s_cbranch_execz .LBB2_72
; %bb.66:                               ; %.lr.ph38.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b64 s[0:1], s[50:51]
	s_mov_b32 s8, s7
.LBB2_67:                               ; %.lr.ph38.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s8, -1
	global_store_b32 v57, v57, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB2_67
; %bb.68:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b32 s0, 0
.LBB2_69:                               ; %.preheader.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_70 Depth 3
	s_mov_b32 s1, s21
	s_mov_b32 s20, s0
	s_lshl_b64 s[8:9], s[0:1], 2
	s_mov_b32 s1, s17
	s_add_u32 s8, s50, s8
	s_addc_u32 s9, s51, s9
	s_and_not1_b32 vcc_lo, exec_lo, s24
	global_load_b32 v0, v57, s[8:9]
	s_cbranch_vccnz .LBB2_71
.LBB2_70:                               ; %.lr.ph40.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ;     Parent Loop BB2_69 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_lshl_b64 s[30:31], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s46, s30
	s_addc_u32 s31, s47, s31
	s_add_i32 s1, s1, -1
	global_load_b32 v1, v57, s[30:31]
	s_add_i32 s20, s20, s7
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v57, v0, s[8:9]
	s_cbranch_scc1 .LBB2_70
.LBB2_71:                               ; %._crit_edge41.i
                                        ;   in Loop: Header=BB2_69 Depth=2
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v1, null, v0, v0, 1.0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, s7
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v2
	v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
	v_mul_f32_e32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v1, v4, v3
	v_fmac_f32_e32 v4, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v4, v3
	v_div_fmas_f32 v1, v1, v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v0, 1.0
	global_store_b32 v57, v0, s[8:9]
	s_cbranch_scc1 .LBB2_69
.LBB2_72:                               ; %Flow367
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_cmp_ne_u32_e32 vcc_lo, 1, v54
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB2_76
; %bb.73:                               ; %.lr.ph.i131.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	v_dual_mov_b32 v0, v50 :: v_dual_mov_b32 v1, v51
	v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v49
	v_dual_mov_b32 v4, v46 :: v_dual_mov_b32 v5, v47
	v_mov_b32_e32 v6, v24
	s_mov_b32 s1, 0
.LBB2_74:                               ; %.lr.ph.i131
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v7, v[4:5], off
	global_load_b32 v8, v[2:3], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v7, v8
	v_cmp_ge_i32_e32 vcc_lo, v6, v52
	global_store_b32 v[0:1], v7, off
	v_add_co_u32 v0, s0, v0, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_74
; %bb.75:                               ; %Flow362
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_76:                               ; %._crit_edge.i132
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_and_saveexec_b32 s22, s16
	s_cbranch_execz .LBB2_86
; %bb.77:                               ; %.lr.ph46.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b64 s[0:1], s[48:49]
	s_mov_b32 s8, s7
.LBB2_78:                               ; %.lr.ph46.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s8, -1
	global_store_b32 v57, v57, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB2_78
; %bb.79:                               ; %.preheader41.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b32 s0, 0
.LBB2_80:                               ; %.preheader41.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_82 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB2_83
; %bb.81:                               ; %.lr.ph48.i
                                        ;   in Loop: Header=BB2_80 Depth=2
	s_mov_b32 s1, s21
	s_mov_b32 s20, s0
	s_lshl_b64 s[8:9], s[0:1], 2
	s_mov_b32 s1, s17
	s_add_u32 s8, s48, s8
	s_addc_u32 s9, s49, s9
	global_load_b32 v0, v57, s[8:9]
.LBB2_82:                               ;   Parent Loop BB2_29 Depth=1
                                        ;     Parent Loop BB2_80 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_lshl_b64 s[30:31], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s44, s30
	s_addc_u32 s31, s45, s31
	s_add_i32 s1, s1, -1
	global_load_b32 v1, v57, s[30:31]
	s_add_i32 s20, s20, s7
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v57, v0, s[8:9]
	s_cbranch_scc1 .LBB2_82
.LBB2_83:                               ; %._crit_edge49.i
                                        ;   in Loop: Header=BB2_80 Depth=2
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, s7
	s_cbranch_scc1 .LBB2_80
; %bb.84:                               ; %.lr.ph52.i.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mov_b64 s[0:1], s[48:49]
	s_mov_b64 s[8:9], s[50:51]
	s_mov_b32 s20, s7
.LBB2_85:                               ; %.lr.ph52.i
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b32 v0, v57, s[8:9]
	global_load_b32 v1, v57, s[0:1]
	s_add_i32 s20, s20, -1
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v1
	global_store_b32 v57, v0, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s20, 0
	s_cbranch_scc1 .LBB2_85
.LBB2_86:                               ; %Flow361
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s20, s6
	s_cbranch_execz .LBB2_90
; %bb.87:                               ;   in Loop: Header=BB2_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB2_90
; %bb.88:                               ; %.lr.ph150.preheader
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_mul_i32 s0, s2, s7
	s_mov_b64 s[22:23], s[48:49]
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[0:1], 2
	s_add_i32 s1, s0, s7
	s_add_u32 s8, s14, s8
	s_addc_u32 s9, s15, s9
.LBB2_89:                               ; %.lr.ph150
                                        ;   Parent Loop BB2_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v0, v57, s[22:23]
	s_add_i32 s0, s0, 1
	s_waitcnt vmcnt(0)
	global_store_b32 v57, v0, s[8:9]
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s22, s22, 4
	s_addc_u32 s23, s23, 0
	s_cmp_lt_i32 s0, s1
	s_cbranch_scc1 .LBB2_89
.LBB2_90:                               ; %.loopexit
                                        ;   in Loop: Header=BB2_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB2_91:                               ;   in Loop: Header=BB2_29 Depth=1
	s_add_i32 s33, s33, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s33, s18
	s_cbranch_scc1 .LBB2_29
.LBB2_92:                               ; %._crit_edge154
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 424
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 59
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .Lfunc_end2-_Z11mcmc_sharediiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4424
; NumSgprs: 70
; NumVgprs: 59
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 59
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_ ; -- Begin function _Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.globl	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
	.p2align	8
	.type	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_,@function
_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_: ; @_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
; %bb.0:
	s_mov_b64 s[4:5], s[0:1]
	s_load_b32 s0, s[0:1], 0xb4
	s_load_b32 s7, s[4:5], 0x0
	v_mov_b32_e32 v31, v0
	s_mov_b32 s12, s15
	s_load_b512 s[36:51], s[4:5], 0x20
	s_mov_b32 s2, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_cmp_lt_i32 s7, 1
	v_mad_u64_u32 v[0:1], null, s12, s0, v[31:32]
	s_cselect_b32 s13, -1, 0
	s_cmp_gt_i32 s7, 0
	s_cselect_b32 s1, -1, 0
	s_and_b32 vcc_lo, exec_lo, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v24, v0, s7
	v_add_nc_u32_e32 v30, s7, v24
	v_ashrrev_i32_e32 v25, 31, v24
	s_cbranch_vccnz .LBB3_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[24:25]
	v_dual_mov_b32 v5, 0x40a00000 :: v_dual_mov_b32 v6, v24
	v_add_co_u32 v3, vcc_lo, s38, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v2, vcc_lo
.LBB3_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v6
	global_store_b32 v[3:4], v5, off
	v_add_co_u32 v3, s0, v3, 4
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	v_cmp_ge_i32_e32 vcc_lo, v6, v30
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_2
; %bb.3:                                ; %.lr.ph.i107.preheader
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v1, vcc_lo, s42, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s43, v2, vcc_lo
	v_dual_mov_b32 v3, 1.0 :: v_dual_mov_b32 v4, v24
	s_mov_b32 s2, 0
.LBB3_4:                                ; %.lr.ph.i107
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v4
	global_store_b32 v[1:2], v3, off
	v_add_co_u32 v1, s0, v1, 4
	v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
	v_cmp_ge_i32_e32 vcc_lo, v4, v30
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_4
; %bb.5:                                ; %Flow380
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_6:                                ; %_Z16initialize_meansfPfi.exit
	v_xor_b32_e32 v2, 0x2c7f967f, v0
	v_dual_mov_b32 v3, 0x8a5d614f :: v_dual_mov_b32 v10, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v4, 0x493c4aa1, v2
	v_cndmask_b32_e64 v52, 0, 1, s1
	v_mov_b32_e32 v11, v10
	v_cndmask_b32_e32 v9, 0xfa091aa4, v3, vcc_lo
	v_mad_i64_i32 v[2:3], null, v0, 48, s[36:37]
	s_mov_b32 s2, 0
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 0x1f123bb5, v9
	v_xor_b32_e32 v8, 0x5491333, v9
	v_add_nc_u32_e32 v5, 0x75bcd15, v4
	v_xor_b32_e32 v6, 0x159a55e5, v4
	v_add3_u32 v9, v4, v9, 0x64f0c9
	v_add_nc_u32_e32 v12, 0x583f19, v4
	v_mov_b32_e32 v4, 1.0
	s_clause 0x2
	global_store_b96 v[2:3], v[9:11], off
	global_store_b128 v[2:3], v[5:8], off offset:24
	global_store_b32 v[2:3], v12, off offset:40
	s_cbranch_vccnz .LBB3_10
; %bb.7:                                ; %.lr.ph.i.i.i.preheader
	v_lshlrev_b64 v[2:3], 2, v[24:25]
	v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v5, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s38, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s39, v3, vcc_lo
.LBB3_8:                                ; %.lr.ph.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[2:3], off
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v4, v6
	v_cmp_ge_i32_e64 s0, v5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_8
; %bb.9:                                ; %Flow377
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_10:                               ; %_Z11get_log_detPfi.exit.i
	v_cvt_f64_i32_e32 v[2:3], s7
	s_clause 0x2
	s_load_b128 s[16:19], s[4:5], 0x8
	s_load_b64 s[10:11], s[4:5], 0x18
	s_load_b512 s[52:67], s[4:5], 0x60
	v_mov_b32_e32 v12, 0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v53, v24, s16
	v_mul_lo_u32 v54, v30, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s3, v53, v54
	v_mul_f64 v[2:3], v[2:3], -0.5
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB3_18
; %bb.11:                               ; %.lr.ph.i109
	s_mov_b32 s8, 0xc864beb4
	s_mov_b32 s9, 0x3ffd67f1
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f64 v[5:6], v[2:3], s[8:9]
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v15, v53
	s_mov_b32 s2, 0
	v_cndmask_b32_e64 v7, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_log_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v4
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v4|
	v_fma_f32 v8, 0x3f317217, v4, -v7
	v_cvt_f32_f64_e32 v13, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v4, 0x3377d1cf, v8
	v_add_f32_e32 v5, v7, v5
	v_lshlrev_b64 v[6:7], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v5, s0
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v14, -0.5, v4
	v_add_co_u32 v4, vcc_lo, s42, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s43, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s38, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s39, v7, vcc_lo
.LBB3_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_14 Depth 2
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	v_mov_b32_e32 v8, 0
	s_cbranch_vccnz .LBB3_16
; %bb.13:                               ; %.lr.ph.i.i20.i
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v9, v7
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v11, v5
	v_mov_b32_e32 v10, v4
	s_mov_b32 s6, 0
	s_mov_b32 s8, 0
.LBB3_14:                               ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, s8, v15
	s_add_i32 s8, s8, 1
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v17, vcc_lo, s58, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v18, vcc_lo, s59, v18, vcc_lo
	global_load_b32 v19, v[10:11], off
	global_load_b32 v17, v[17:18], off
	global_load_b32 v18, v[8:9], off
	v_add_co_u32 v8, s0, v8, 4
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, v17, v17
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[17:18], v18
	v_cvt_f64_f32_e32 v[19:20], v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[21:22], null, v[17:18], v[17:18], v[19:20]
	v_div_scale_f64 v[32:33], vcc_lo, v[19:20], v[17:18], v[19:20]
	v_rcp_f64_e32 v[26:27], v[21:22]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[21:22], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27]
	v_fma_f64 v[28:29], -v[21:22], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27]
	v_mul_f64 v[28:29], v[32:33], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[21:22], v[28:29], v[32:33]
	v_div_fmas_f64 v[21:22], v[21:22], v[26:27], v[28:29]
	v_cvt_f64_f32_e32 v[26:27], v16
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[16:17], v[21:22], v[17:18], v[19:20]
	v_add_f64 v[16:17], v[16:17], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v16, v[16:17]
	v_add_nc_u32_e32 v17, s8, v24
	v_cmp_ge_i32_e32 vcc_lo, v17, v30
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB3_14
; %bb.15:                               ; %_Z21calc_vec_mat_vec_prodPfS_S_ii.exit.loopexit.i.i
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v8, 0.5, v16
.LBB3_16:                               ; %_Z18get_log_likelihoodPfS_S_fii.exit.i
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v14, v8 :: v_dual_add_nc_u32 v15, s7, v15
	v_add_f32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_o_f32_e32 vcc_lo, v8, v8
	v_cndmask_b32_e32 v8, 0xdf0ac723, v8, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v15, v54
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v12, v12, v8
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_12
; %bb.17:                               ; %Flow374
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_18:                               ; %Flow375
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	v_add_co_u32 v26, s0, s54, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v27, s0, s55, v5, s0
	global_store_b32 v[26:27], v12, off
	s_cbranch_vccnz .LBB3_24
; %bb.19:                               ; %.lr.ph.i110.preheader
	v_lshlrev_b64 v[6:7], 2, v[24:25]
	v_mov_b32_e32 v1, v24
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s38, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s39, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s40, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s41, v7, vcc_lo
.LBB3_20:                               ; %.lr.ph.i110
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v12, v[8:9], off
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v30
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v12, off
	v_add_co_u32 v10, s0, v10, 4
	v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_20
; %bb.21:                               ; %.lr.ph.i111.preheader
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v8, vcc_lo, s42, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s43, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s44, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s45, v7, vcc_lo
	v_mov_b32_e32 v1, v24
	s_mov_b32 s1, 0
.LBB3_22:                               ; %.lr.ph.i111
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v10, v[8:9], off
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v30
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v10, off
	v_add_co_u32 v6, s0, v6, 4
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_22
; %bb.23:                               ; %Flow368
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_24:                               ; %_Z7vec_cpyPfS_i.exit113
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB3_89
; %bb.25:                               ; %.lr.ph139
	v_cmp_eq_u32_e64 s6, 0, v0
	s_xor_b32 s0, s13, -1
	v_add_co_u32 v28, vcc_lo, s48, v4
	v_add_co_ci_u32_e32 v29, vcc_lo, s49, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s16, s0, s6
	s_mov_b32 s0, 0xc864beb4
	s_mov_b32 s1, 0x3ffd67f1
	s_cmp_gt_i32 s17, 0
	v_mul_f64 v[0:1], v[2:3], s[0:1]
	s_cselect_b32 s24, -1, 0
	s_cmp_gt_i32 s7, 0
	v_add_co_u32 v32, vcc_lo, s52, v4
	s_cselect_b32 s25, -1, 0
	s_ashr_i32 s26, s19, 31
	v_add_co_ci_u32_e32 v33, vcc_lo, s53, v5, vcc_lo
	s_add_i32 s0, s19, s26
	v_add_co_u32 v34, vcc_lo, s50, v4
	s_xor_b32 s27, s0, s26
	v_add_co_ci_u32_e32 v35, vcc_lo, s51, v5, vcc_lo
	v_cvt_f32_u32_e32 v2, s27
	v_add_co_u32 v36, vcc_lo, s46, v4
	v_add_co_ci_u32_e32 v37, vcc_lo, s47, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v2, v2
	v_add_co_u32 v38, vcc_lo, s56, v4
	v_add_co_ci_u32_e32 v39, vcc_lo, s57, v5, vcc_lo
	s_load_b64 s[14:15], s[4:5], 0xa0
	s_sub_i32 s1, 0, s27
	v_subrev_nc_u32_e32 v55, s7, v24
	v_mov_b32_e32 v57, 1
	s_mov_b32 s21, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_mov_b32 s29, 0
	v_cvt_f32_f64_e32 v56, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[24:25]
	v_mov_b32_e32 v25, 0
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v41, vcc_lo, s41, v1, vcc_lo
	v_add_co_u32 v42, vcc_lo, s44, v0
	v_add_co_ci_u32_e32 v43, vcc_lo, s45, v1, vcc_lo
	v_add_co_u32 v44, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v45, vcc_lo, s39, v1, vcc_lo
	v_add_co_u32 v46, vcc_lo, s42, v0
	v_readfirstlane_b32 s0, v2
	v_add_co_ci_u32_e32 v47, vcc_lo, s43, v1, vcc_lo
	v_add_co_u32 v48, vcc_lo, s62, v0
	v_add_co_ci_u32_e32 v49, vcc_lo, s63, v1, vcc_lo
	v_add_co_u32 v50, vcc_lo, s60, v0
	s_mul_i32 s1, s1, s0
	v_add_co_ci_u32_e32 v51, vcc_lo, s61, v1, vcc_lo
	s_mul_hi_u32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s28, s0, s1
.LBB3_26:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_34 Depth 2
                                        ;     Child Loop BB3_38 Depth 2
                                        ;       Child Loop BB3_40 Depth 3
                                        ;     Child Loop BB3_54 Depth 2
                                        ;     Child Loop BB3_56 Depth 2
                                        ;     Child Loop BB3_60 Depth 2
                                        ;     Child Loop BB3_64 Depth 2
                                        ;     Child Loop BB3_66 Depth 2
                                        ;       Child Loop BB3_67 Depth 3
                                        ;     Child Loop BB3_71 Depth 2
                                        ;     Child Loop BB3_75 Depth 2
                                        ;     Child Loop BB3_77 Depth 2
                                        ;       Child Loop BB3_79 Depth 3
                                        ;     Child Loop BB3_82 Depth 2
                                        ;     Child Loop BB3_86 Depth 2
	v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
	v_dual_mov_b32 v2, s50 :: v_dual_mov_b32 v3, s51
	v_dual_mov_b32 v4, s52 :: v_dual_mov_b32 v5, s53
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	v_dual_mov_b32 v8, s46 :: v_dual_mov_b32 v9, s47
	v_dual_mov_b32 v10, s48 :: v_dual_mov_b32 v11, s49
	v_mov_b32_e32 v12, s7
	s_add_u32 s8, s4, 0xa8
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@lo+4
	s_addc_u32 s1, s1, _Z20generate_random_numsP12hiprandStatePfS1_ffS1_Pii@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	global_load_b32 v0, v[28:29], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_le_i32_e64 s7, v0
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_30
; %bb.27:                               ;   in Loop: Header=BB3_26 Depth=1
	v_add_nc_u32_e32 v0, v55, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s39, v1, vcc_lo
	global_load_b32 v4, v[32:33], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 0, v2
	s_cbranch_execz .LBB3_29
; %bb.28:                               ;   in Loop: Header=BB3_26 Depth=1
	v_add_co_u32 v0, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s41, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB3_29:                               ; %Flow362
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr0
.LBB3_30:                               ; %Flow364
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB3_32
; %bb.31:                               ;   in Loop: Header=BB3_26 Depth=1
	v_add_nc_u32_e32 v0, v0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s42, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s43, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s44, v0
	global_load_b32 v4, v[34:35], off
	global_load_b32 v2, v[2:3], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s45, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v4
	global_store_b32 v[0:1], v2, off
.LBB3_32:                               ; %_Z14perturb_paramsPfS_S_S_PiS_S_i.exit
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[26:27], off
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	v_mov_b32_e32 v2, 1.0
	s_cbranch_vccnz .LBB3_36
; %bb.33:                               ; %.lr.ph.i.i.i.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_mov_b32_e32 v0, v40
	v_dual_mov_b32 v2, 1.0 :: v_dual_mov_b32 v1, v41
	v_mov_b32_e32 v3, v24
	s_mov_b32 s1, 0
.LBB3_34:                               ; %.lr.ph.i.i.i.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[0:1], off
	v_add_nc_u32_e32 v3, 1, v3
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v2, v5
	v_cmp_ge_i32_e64 s0, v3, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_34
; %bb.35:                               ; %Flow360
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_36:                               ; %_Z11get_log_detPfi.exit.i.i
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_mov_b32_e32 v5, 0
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB3_44
; %bb.37:                               ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	s_mov_b32 s2, 0
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v7, v53
	v_cndmask_b32_e64 v0, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v2, v0
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x3f317217, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, 0x3f317217, v0, -v1
	v_fmac_f32_e32 v2, 0x3377d1cf, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v1, v2
	v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v2
	v_mul_f32_e32 v6, -0.5, v0
.LBB3_38:                               ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_40 Depth 3
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	v_mov_b32_e32 v0, 0
	s_cbranch_vccnz .LBB3_42
; %bb.39:                               ; %.lr.ph.i.i20.i.i
                                        ;   in Loop: Header=BB3_38 Depth=2
	v_mov_b32_e32 v0, v40
	v_dual_mov_b32 v2, v42 :: v_dual_mov_b32 v3, v43
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, v41
	s_mov_b32 s8, 0
	s_mov_b32 s9, 0
.LBB3_40:                               ;   Parent Loop BB3_26 Depth=1
                                        ;     Parent Loop BB3_38 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, s9, v7
	s_add_i32 s9, s9, 1
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s58, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, s59, v10, vcc_lo
	global_load_b32 v11, v[2:3], off
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[0:1], off
	v_add_co_u32 v0, s0, v0, 4
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v9, v9
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[9:10], v10
	v_cvt_f64_f32_e32 v[11:12], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
	v_div_scale_f64 v[19:20], vcc_lo, v[11:12], v[9:10], v[11:12]
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_mul_f64 v[17:18], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
	v_cvt_f64_f32_e32 v[15:16], v8
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[8:9], v[13:14], v[9:10], v[11:12]
	v_add_f64 v[8:9], v[8:9], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v8, v[8:9]
	v_add_nc_u32_e32 v9, s9, v24
	v_cmp_ge_i32_e32 vcc_lo, v9, v30
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB3_40
; %bb.41:                               ; %_Z21calc_vec_mat_vec_prodPfS_S_ii.exit.loopexit.i.i.i
                                        ;   in Loop: Header=BB3_38 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v0, 0.5, v8
.LBB3_42:                               ; %_Z18get_log_likelihoodPfS_S_fii.exit.i.i
                                        ;   in Loop: Header=BB3_38 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v6, v0 :: v_dual_add_nc_u32 v7, s7, v7
	v_add_f32_e32 v0, v0, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_cndmask_b32_e32 v0, 0xdf0ac723, v0, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v7, v54
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v5, v5, v0
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_38
; %bb.43:                               ; %Flow357
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_44:                               ; %Flow358
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e32 v5, v4
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_50
; %bb.45:                               ;   in Loop: Header=BB3_26 Depth=1
	global_load_b32 v0, v[36:37], off
	v_sub_f32_e32 v1, v5, v4
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3fb8aa3b, v1
	v_fma_f32 v3, 0x3fb8aa3b, v1, -v2
	v_rndne_f32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v3, 0x32a5705f, v1 :: v_dual_sub_f32 v2, v2, v4
	v_add_f32_e32 v2, v2, v3
	v_cvt_i32_f32_e32 v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v2, v3
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmpx_nlt_f32_e32 v0, v1
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_47
; %bb.46:                               ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b32 s1, -1
	global_store_b32 v[38:39], v25, off
                                        ; implicit-def: $vgpr5
.LBB3_47:                               ; %Flow350
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_49
; %bb.48:                               ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_b32 s1, s1, exec_lo
	global_store_b32 v[38:39], v57, off
	global_store_b32 v[26:27], v5, off
.LBB3_49:                               ; %Flow351
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr5
.LBB3_50:                               ; %Flow353
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB3_52
; %bb.51:                               ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_b32 s1, s1, exec_lo
	global_store_b32 v[38:39], v57, off
	global_store_b32 v[26:27], v5, off
.LBB3_52:                               ; %_Z9mcmc_stepPfS_S_S_S_PiS_S_S_iiiS0_S_.exit
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_or_b32 s0, s13, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_57
; %bb.53:                               ; %.lr.ph.i114.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_dual_mov_b32 v0, v44 :: v_dual_mov_b32 v1, v45
	v_dual_mov_b32 v2, v40 :: v_dual_mov_b32 v3, v41
	v_mov_b32_e32 v4, v24
	s_mov_b32 s2, 0
.LBB3_54:                               ; %.lr.ph.i114
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v30
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, s0, v0, 4
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_54
; %bb.55:                               ; %.lr.ph.i117.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v0, v46 :: v_dual_mov_b32 v1, v47
	v_dual_mov_b32 v2, v42 :: v_dual_mov_b32 v3, v43
	v_mov_b32_e32 v4, v24
	s_mov_b32 s2, 0
.LBB3_56:                               ; %.lr.ph.i117
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_nc_u32_e32 v4, 1, v4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v4, v30
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, s0, v0, 4
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_56
.LBB3_57:                               ; %Flow348
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_mul_hi_u32 s0, s29, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s27
	s_add_i32 s2, s0, 1
	s_sub_i32 s1, s29, s1
	s_sub_i32 s8, s1, s27
	s_cmp_ge_u32 s1, s27
	s_cselect_b32 s0, s2, s0
	s_cselect_b32 s1, s8, s1
	s_add_i32 s2, s0, 1
	s_cmp_ge_u32 s1, s27
	s_cselect_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s26
	s_sub_i32 s2, s0, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s2, s19
	s_sub_i32 s0, s29, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB3_88
; %bb.58:                               ;   in Loop: Header=BB3_26 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	s_cbranch_vccnz .LBB3_62
; %bb.59:                               ; %.lr.ph.i120.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_dual_mov_b32 v0, v48 :: v_dual_mov_b32 v1, v49
	v_dual_mov_b32 v2, v44 :: v_dual_mov_b32 v3, v45
	v_mov_b32_e32 v4, v24
	s_mov_b32 s1, 0
.LBB3_60:                               ; %.lr.ph.i120
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v6, null, v5, v5, 1.0
	v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v7, 1.0
	v_dual_fmac_f32 v7, v9, v7 :: v_dual_add_nc_u32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e64 s0, v4, v30
	v_mul_f32_e32 v9, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s1, s0, s1
	v_fma_f32 v10, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v7
	v_fma_f32 v6, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v7, v9
	v_div_fixup_f32 v5, v6, v5, 1.0
	global_store_b32 v[0:1], v5, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_60
; %bb.61:                               ; %Flow342
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_62:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_and_saveexec_b32 s22, s16
	s_cbranch_execz .LBB3_69
; %bb.63:                               ; %.lr.ph38.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b64 s[0:1], s[66:67]
	s_mov_b32 s8, s7
.LBB3_64:                               ; %.lr.ph38.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s8, -1
	global_store_b32 v25, v25, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB3_64
; %bb.65:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b32 s0, 0
.LBB3_66:                               ; %.preheader.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_67 Depth 3
	s_mov_b32 s1, s21
	s_mov_b32 s20, s0
	s_lshl_b64 s[8:9], s[0:1], 2
	s_mov_b32 s1, s17
	s_add_u32 s8, s66, s8
	s_addc_u32 s9, s67, s9
	s_and_not1_b32 vcc_lo, exec_lo, s24
	global_load_b32 v0, v25, s[8:9]
	s_cbranch_vccnz .LBB3_68
.LBB3_67:                               ; %.lr.ph40.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ;     Parent Loop BB3_66 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_lshl_b64 s[30:31], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s62, s30
	s_addc_u32 s31, s63, s31
	s_add_i32 s1, s1, -1
	global_load_b32 v1, v25, s[30:31]
	s_add_i32 s20, s20, s7
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v25, v0, s[8:9]
	s_cbranch_scc1 .LBB3_67
.LBB3_68:                               ; %._crit_edge41.i
                                        ;   in Loop: Header=BB3_66 Depth=2
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v1, null, v0, v0, 1.0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, s7
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v2
	v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
	v_mul_f32_e32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v1, v4, v3
	v_fmac_f32_e32 v4, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v4, v3
	v_div_fmas_f32 v1, v1, v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v0, 1.0
	global_store_b32 v25, v0, s[8:9]
	s_cbranch_scc1 .LBB3_66
.LBB3_69:                               ; %Flow340
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_cmp_ne_u32_e32 vcc_lo, 1, v52
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB3_73
; %bb.70:                               ; %.lr.ph.i121.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	v_dual_mov_b32 v0, v50 :: v_dual_mov_b32 v1, v51
	v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v49
	v_dual_mov_b32 v4, v46 :: v_dual_mov_b32 v5, v47
	v_mov_b32_e32 v6, v24
	s_mov_b32 s1, 0
.LBB3_71:                               ; %.lr.ph.i121
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v7, v[4:5], off
	global_load_b32 v8, v[2:3], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v7, v8
	v_cmp_ge_i32_e32 vcc_lo, v6, v30
	global_store_b32 v[0:1], v7, off
	v_add_co_u32 v0, s0, v0, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_71
; %bb.72:                               ; %Flow335
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_73:                               ; %._crit_edge.i122
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_and_saveexec_b32 s22, s16
	s_cbranch_execz .LBB3_83
; %bb.74:                               ; %.lr.ph46.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b64 s[0:1], s[64:65]
	s_mov_b32 s8, s7
.LBB3_75:                               ; %.lr.ph46.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s8, -1
	global_store_b32 v25, v25, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB3_75
; %bb.76:                               ; %.preheader41.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b32 s0, 0
.LBB3_77:                               ; %.preheader41.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_79 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB3_80
; %bb.78:                               ; %.lr.ph48.i
                                        ;   in Loop: Header=BB3_77 Depth=2
	s_mov_b32 s1, s21
	s_mov_b32 s20, s0
	s_lshl_b64 s[8:9], s[0:1], 2
	s_mov_b32 s1, s17
	s_add_u32 s8, s64, s8
	s_addc_u32 s9, s65, s9
	global_load_b32 v0, v25, s[8:9]
.LBB3_79:                               ;   Parent Loop BB3_26 Depth=1
                                        ;     Parent Loop BB3_77 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_lshl_b64 s[30:31], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s30, s60, s30
	s_addc_u32 s31, s61, s31
	s_add_i32 s1, s1, -1
	global_load_b32 v1, v25, s[30:31]
	s_add_i32 s20, s20, s7
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	global_store_b32 v25, v0, s[8:9]
	s_cbranch_scc1 .LBB3_79
.LBB3_80:                               ; %._crit_edge49.i
                                        ;   in Loop: Header=BB3_77 Depth=2
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, s7
	s_cbranch_scc1 .LBB3_77
; %bb.81:                               ; %.lr.ph52.i.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mov_b64 s[0:1], s[64:65]
	s_mov_b64 s[8:9], s[66:67]
	s_mov_b32 s20, s7
.LBB3_82:                               ; %.lr.ph52.i
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b32 v0, v25, s[8:9]
	global_load_b32 v1, v25, s[0:1]
	s_add_i32 s20, s20, -1
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v1
	global_store_b32 v25, v0, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s20, 0
	s_cbranch_scc1 .LBB3_82
.LBB3_83:                               ; %Flow334
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s20, s6
	s_cbranch_execz .LBB3_87
; %bb.84:                               ;   in Loop: Header=BB3_26 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s25
	s_cbranch_vccnz .LBB3_87
; %bb.85:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_mul_i32 s0, s2, s7
	s_mov_b64 s[22:23], s[64:65]
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[0:1], 2
	s_add_i32 s1, s0, s7
	s_add_u32 s8, s14, s8
	s_addc_u32 s9, s15, s9
.LBB3_86:                               ; %.lr.ph
                                        ;   Parent Loop BB3_26 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v0, v25, s[22:23]
	s_add_i32 s0, s0, 1
	s_waitcnt vmcnt(0)
	global_store_b32 v25, v0, s[8:9]
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s22, s22, 4
	s_addc_u32 s23, s23, 0
	s_cmp_lt_i32 s0, s1
	s_cbranch_scc1 .LBB3_86
.LBB3_87:                               ; %.loopexit
                                        ;   in Loop: Header=BB3_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB3_88:                               ;   in Loop: Header=BB3_26 Depth=1
	s_add_i32 s29, s29, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s29, s18
	s_cbranch_scc1 .LBB3_26
.LBB3_89:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 424
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_, .Lfunc_end3-_Z4mcmciiiiiiffP12hiprandStatePfS1_S1_S1_S1_PiS1_S1_S1_S2_S1_S1_S1_S1_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4328
; NumSgprs: 70
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
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...

	.end_amdgpu_metadata
