#include <iostream>
#include <assert.h>
#include <limits.h>
#include <vector>
#include <curand.h>
#include <curand_kernel.h>
#include <algorithm>
using namespace std;
// #define RNG_DEF int& rx
// #define RNG_ARGS rx
// #define MY_RAND_MAX ((1U << 31) - 1)
// Command line arguments that get set below (these give default values)

float sdscale = 1.0; // scale the SDs by this
int N = 1<<20;
int steps = 1000;
int outer = 100;
int thin = 1; // how many outer blocks to skip?
int seed = -1;
int burn = 0;
int QUIET = 0;
int WHICH_GPU = 0;
int FIRST_HALF_DATA = 0;
int EVEN_HALF_DATA = 0;
int SHOW_CONSTANTS = 0;
string in_file_path = "data.txt";
string out_path = "out/";

const unsigned int nBlocks = 10 ;

const unsigned int BLOCK_SIZE = 64;
// const unsigned int HARDARE_MAX_X_BLOCKS = 4096;
// const unsigned int HARDWARE_MAX_THREADS_PER_BLOCK = 1024;
// __device__ __host__ int cuda_rand(RNG_DEF) {
//    //http://rosettacode.org/wiki/Linear_congruential_generator#C
//    return rx = (rx * 1103515245 + 12345) & MY_RAND_MAX;
// }
// __device__ int random_int(int n) {
//      // number in [0,(n-1)]
//     int divisor = MY_RAND_MAX/(n+1);
//     int retval;
//
//     do {
//         retval = cuda_rand(RNG_ARGS) / divisor;
//     } while (retval >= n);
//
//     return retval;
// }
__device__ float density_function(float beta, float cost) {
    // printf("%f-%f\n", beta, cost);
	return exp2f(-beta * cost);
}
__device__ float get_randomNum(unsigned int seed, int maxLimit) {
  /* CUDA's random number library uses curandState_t to keep track of the seed value
     we will store a random state for every thread  */
  curandState_t state;

  /* we have to initialize the state */
  curand_init(seed, /* the seed controls the sequence of random values that are produced */
              0, /* the sequence number is only important with multiple cores */
              0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
              &state);

  /* curand works like rand - except that it takes a state as a parameter */
  return curand(&state) % maxLimit;
 // int res = curand(&state) % maxLimit;
 // printf("%d ", res);
 // return res;
}
void setUpDevices(){
    int deviceCount = 0;
    cudaGetDeviceCount(&deviceCount);
    if(WHICH_GPU <= deviceCount) {
    cudaError_t err = cudaSetDevice(WHICH_GPU);
    if(err != cudaSuccess)
        cout<< "CUDA error:" <<cudaGetErrorString(err)<<endl;
    }
    else {
        cout << "Invalid GPU device " << WHICH_GPU << endl;
        exit(-1);
    }
    int wgpu;
    cudaGetDevice(&wgpu);
    cudaDeviceReset();
}
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y){
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < n; i+=stride)
    y[i] = x[i] + y[i];
}
void debug_add(){
    float *x, *y;

    // Allocate Unified Memory – accessible from CPU or GPU
    cudaMallocManaged(&x, N*sizeof(float));
    cudaMallocManaged(&y, N*sizeof(float));

    // initialize x and y arrays on the host
    for (int i = 0; i < N; i++) {
      x[i] = 1.0f;
      y[i] = 2.0f;
    }

    int numOfBlocks = (N+BLOCK_SIZE-1)/BLOCK_SIZE;
    // Run kernel on 1M elements on the GPU
    add<<<numOfBlocks, BLOCK_SIZE>>>(N, x, y);

    // Wait for GPU to finish before accessing on host
    cudaDeviceSynchronize();

    // Check for errors (all values should be 3.0f)
    float maxError = 0.0f;
    for (int i = 0; i < N; i++)
      maxError = fmax(maxError, fabs(y[i]-3.0f));
    std::cout << "Max error: " << maxError << std::endl;

    // Free memory
    cudaFree(x);
    cudaFree(y);
}
__device__ float cost_function(float * data, int length){
    //dummy cost, just sum up all
    float res = 0;

    for(int i=0; i<length; i++)
        res += data[i];
    // printf("res: %f\n", res);
    return res/1000;
}
__device__
void changeTemparature(float * temparature, unsigned int seed){
    int t1 = get_randomNum(seed, nBlocks);
    int t2=t1;
    while(t2 == t1)
        t2 = get_randomNum(seed + 100, nBlocks);
    float tmp = temparature[t1];
    temparature[t1] = temparature[t2];
    temparature[t2] = tmp;
}
__device__
void ActualHW(int randTimes, int numofObjs, unsigned int seed, int* pickedIdAddr, float*sArray, float * cost, float *temparature){
    // bool hit = false;
    int index = blockIdx.x*blockDim.x + threadIdx.x;
    for(int t=0; t<randTimes; t++){
        if(pickedIdAddr[t] == threadIdx.x){
            if(t % 10 == 0)
                changeTemparature(temparature, seed+index);
            float cost_pri = cost_function(sArray, numofObjs);
            float p0 = density_function(temparature[blockIdx.x], cost_pri);
            float tmpKeep = sArray[threadIdx.x];
            sArray[threadIdx.x] = get_randomNum(seed+index, 1000);

            float cost_post = cost_function(sArray, numofObjs);
            float p = density_function(temparature[blockIdx.x], cost_post);
            float alpha = min(1.0f, p/p0);
            // printf("p/p0: %f\n", p/p0);
            float t =0.8f;
            //change back
            if(alpha>t)
                sArray[threadIdx.x] = tmpKeep;
            else{
                if(sArray[threadIdx.x]>tmpKeep)
                    printf("%f - %f\n", tmpKeep, sArray[threadIdx.x]);
                cost[blockIdx.x] = cost_post;
            }


            // hit = true;
        }
    }
    // return hit;
}
__global__
void simpleHW(int numofObjs, float * gValues, float* gArray,unsigned int seed,int*pickedIdxs, int randTimes){
    //here should be dynamic shared mem
    //__shared__ float sArray[30];
    extern __shared__ float sharedMem[];
    float * sArray = sharedMem;
    float * lastSumUp = (float *) & sArray[nBlocks*numofObjs];
    float * temparature = (float *) & lastSumUp[nBlocks];
    //initialize
    int startIdx = blockIdx.x * numofObjs;
    int idx =  startIdx+ threadIdx.x;

    sArray[idx] = gValues[threadIdx.x];
    temparature[blockIdx.x] = -get_randomNum(seed+blockIdx.x, 100) / 10;
    // printf("temp: %f", temparature[blockIdx.x]);
    lastSumUp[blockIdx.x] = 0;
    for(int i = 0;i<numofObjs; i++)
        lastSumUp[blockIdx.x] += gValues[i];

    int* pickedIdAddr = &pickedIdxs[blockIdx.x * randTimes];

    ActualHW(randTimes, numofObjs, seed, pickedIdAddr, &sArray[startIdx], lastSumUp, temparature);
    __syncthreads();
    gArray[idx] = sArray[idx];
}

void simpleStructure(){
    float *gValues;
    float * gArray;
    int * pickedIdxs;

    int numofObjs = 5;

    int nTimes =20000;

    int totalSize = nBlocks*numofObjs* sizeof(float);

    cudaMallocManaged(&gValues, numofObjs * sizeof(float));
    for(int i=0; i<numofObjs; i++)
        gValues[i] = 1000;
    cudaMallocManaged(&pickedIdxs, nBlocks*nTimes * sizeof(int));
    for(int i=0; i<nBlocks*nTimes; i++)
        pickedIdxs[i] = rand()%numofObjs;
    // for(int i=0; i<nBlocks*nTimes; i++)
    //     cout<<pickedIdxs[i]<<" ";
    // cout<<endl;

    cudaMallocManaged(&gArray, totalSize);
    //dynamic shared mem, <<<nb, nt, sm>>>
    simpleHW<<<nBlocks, numofObjs, totalSize + 2*nBlocks*sizeof(float)>>>(numofObjs, gValues, gArray,time(NULL),pickedIdxs,nTimes);

    // Wait for GPU to finish before accessing on host
    cudaDeviceSynchronize();

    for(int i=0;i<nBlocks;i++){
        for(int j=0; j<numofObjs; j++)
            cout<<gArray[i * numofObjs+ j]<<" ";
        cout<<endl;
    }

    // Free memory
    cudaFree(gValues);
    cudaFree(gArray);
    cudaFree(pickedIdxs);
}
int main(int argc, char** argv){
    setUpDevices();
    // debug_add();
    //setup blockSize
    // int N_BLOCKS = N/BLOCK_SIZE + (N%BLOCK_SIZE == 0? 0:1);
    // assert(N_BLOCKS < HARDARE_MAX_X_BLOCKS); // can have at most this many blocks
    // assert(N/N_BLOCKS <= HARDWARE_MAX_THREADS_PER_BLOCK); // MUST HAVE LESS THREADS PER BLOCK!!
    // setup the output files??
    //Make RNG replicable
    if(seed == -1)
        seed = time(NULL);
    srand(seed);
    simpleStructure();
    // read data and se
    return 0;
}

	.file	"tmpxft_00218e01_00000000-6_mcmc.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4477:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4477:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16density_functionff
	.type	_Z16density_functionff, @function
_Z16density_functionff:
.LFB4466:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4466:
	.size	_Z16density_functionff, .-_Z16density_functionff
	.globl	_Z13get_randomNumji
	.type	_Z13get_randomNumji, @function
_Z13get_randomNumji:
.LFB4467:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4467:
	.size	_Z13get_randomNumji, .-_Z13get_randomNumji
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error:"
.LC1:
	.string	"Invalid GPU device "
	.text
	.globl	_Z12setUpDevicesv
	.type	_Z12setUpDevicesv, @function
_Z12setUpDevicesv:
.LFB4468:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	xorl	%eax, %eax
	movl	%eax, (%rsp)
	call	cudaGetDeviceCount@PLT
	movl	WHICH_GPU(%rip), %edi
	cmpl	(%rsp), %edi
	jg	.L7
	call	cudaSetDevice@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L8
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L8
.L7:
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	WHICH_GPU(%rip), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %edi
	call	exit@PLT
.L8:
	leaq	4(%rsp), %rdi
	call	cudaGetDevice@PLT
	call	cudaDeviceReset@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4468:
	.size	_Z12setUpDevicesv, .-_Z12setUpDevicesv
	.globl	_Z13cost_functionPfi
	.type	_Z13cost_functionPfi, @function
_Z13cost_functionPfi:
.LFB4470:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4470:
	.size	_Z13cost_functionPfi, .-_Z13cost_functionPfi
	.globl	_Z17changeTemparaturePfj
	.type	_Z17changeTemparaturePfj, @function
_Z17changeTemparaturePfj:
.LFB4471:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4471:
	.size	_Z17changeTemparaturePfj, .-_Z17changeTemparaturePfj
	.globl	_Z8ActualHWiijPiPfS0_S0_
	.type	_Z8ActualHWiijPiPfS0_S0_, @function
_Z8ActualHWiijPiPfS0_S0_:
.LFB4472:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4472:
	.size	_Z8ActualHWiijPiPfS0_S0_, .-_Z8ActualHWiijPiPfS0_S0_
	.globl	_Z25__device_stub__Z3addiPfS_iPfS_
	.type	_Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB4499:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z3addiPfS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L21:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4499:
	.size	_Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
	.globl	_Z3addiPfS_
	.type	_Z3addiPfS_, @function
_Z3addiPfS_:
.LFB4500:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z3addiPfS_iPfS_
	.cfi_endproc
.LFE4500:
	.size	_Z3addiPfS_, .-_Z3addiPfS_
	.section	.rodata.str1.1
.LC7:
	.string	"Max error: "
	.text
	.globl	_Z9debug_addv
	.type	_Z9debug_addv, @function
_Z9debug_addv:
.LFB4469:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movslq	N(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	leaq	24(%rsp), %rdi
	movslq	N(%rip), %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	N(%rip), %eax
	xorl	%edx, %edx
	movq	16(%rsp), %rcx
	movq	24(%rsp), %rsi
	movss	.LC3(%rip), %xmm0
	movss	.LC4(%rip), %xmm1
.L27:
	cmpl	%edx, %eax
	jle	.L34
	movss	%xmm0, (%rcx,%rdx,4)
	movss	%xmm1, (%rsi,%rdx,4)
	incq	%rdx
	jmp	.L27
.L34:
	addl	$63, %eax
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$6, %eax
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, 52(%rsp)
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	movq	%rdx, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	N(%rip), %edi
	call	_Z25__device_stub__Z3addiPfS_iPfS_
.L29:
	call	cudaDeviceSynchronize@PLT
	movl	N(%rip), %ebp
	xorl	%ebx, %ebx
	xorps	%xmm0, %xmm0
	movq	24(%rsp), %r12
.L30:
	cmpl	%ebx, %ebp
	jle	.L35
	movss	(%r12,%rbx,4), %xmm1
	subss	.LC5(%rip), %xmm1
	incq	%rbx
	andps	.LC6(%rip), %xmm1
	call	fmaxf@PLT
	jmp	.L30
.L35:
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4469:
	.size	_Z9debug_addv, .-_Z9debug_addv
	.globl	_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii
	.type	_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii, @function
_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii:
.LFB4501:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8simpleHWiPfS_jPii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L36:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4501:
	.size	_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii, .-_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii
	.globl	_Z8simpleHWiPfS_jPii
	.type	_Z8simpleHWiPfS_jPii, @function
_Z8simpleHWiPfS_jPii:
.LFB4502:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii
	.cfi_endproc
.LFE4502:
	.size	_Z8simpleHWiPfS_jPii, .-_Z8simpleHWiPfS_jPii
	.section	.rodata.str1.1
.LC9:
	.string	" "
	.text
	.globl	_Z15simpleStructurev
	.type	_Z15simpleStructurev, @function
_Z15simpleStructurev:
.LFB4473:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %edx
	movl	$20, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	$5, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movq	24(%rsp), %rax
	leaq	40(%rsp), %rdi
	movabsq	$4934256342886645760, %rdx
	movl	$800000, %esi
	movq	%rdx, (%rax)
	movq	%rdx, 8(%rax)
	movl	$1, %edx
	movl	$0x447a0000, 16(%rax)
	call	cudaMallocManaged@PLT
.L42:
	call	rand@PLT
	cltd
	idivl	%ebp
	movq	40(%rsp), %rax
	movl	%edx, (%rax,%rbx)
	addq	$4, %rbx
	cmpq	$800000, %rbx
	jne	.L42
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$200, %esi
	call	cudaMallocManaged@PLT
	movl	$2147483653, %edi
	xorl	%r9d, %r9d
	movabsq	$4294967301, %rdx
	addq	%rdi, %rdi
	movl	$280, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	40(%rsp), %r8
	xorl	%edi, %edi
	movq	%r8, 8(%rsp)
	call	time@PLT
	movq	8(%rsp), %r8
	movq	32(%rsp), %rdx
	movl	$20000, %r9d
	movq	24(%rsp), %rsi
	movl	%eax, %ecx
	movl	$5, %edi
	call	_Z34__device_stub__Z8simpleHWiPfS_jPiiiPfS_jPii
.L43:
	call	cudaDeviceSynchronize@PLT
	xorl	%ebp, %ebp
	leaq	_ZSt4cout(%rip), %r12
.L44:
	xorl	%ebx, %ebx
.L45:
	leaq	0(,%rbx,4), %rax
	movq	%r12, %rdi
	addq	32(%rsp), %rax
	incq	%rbx
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$5, %rbx
	jne	.L45
	movq	%r12, %rdi
	addq	$20, %rbp
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$200, %rbp
	jne	.L44
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4473:
	.size	_Z15simpleStructurev, .-_Z15simpleStructurev
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4474:
	.cfi_startproc
	endbr64
	pushq	%rcx
	.cfi_def_cfa_offset 16
	call	_Z12setUpDevicesv
	cmpl	$-1, seed(%rip)
	jne	.L52
	xorl	%edi, %edi
	call	time@PLT
	movl	%eax, seed(%rip)
.L52:
	movl	seed(%rip), %edi
	call	srand@PLT
	call	_Z15simpleStructurev
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4474:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z8simpleHWiPfS_jPii"
.LC11:
	.string	"_Z3addiPfS_"
.LC12:
	.string	"precalc_xorwow_matrix"
.LC13:
	.string	"precalc_xorwow_offset_matrix"
.LC14:
	.string	"mrg32k3aM1"
.LC15:
	.string	"mrg32k3aM2"
.LC16:
	.string	"mrg32k3aM1SubSeq"
.LC17:
	.string	"mrg32k3aM2SubSeq"
.LC18:
	.string	"mrg32k3aM1Seq"
.LC19:
	.string	"mrg32k3aM2Seq"
.LC20:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4504:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8simpleHWiPfS_jPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3addiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4504:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.1,"aMS",@progbits,1
.LC21:
	.string	"basic_string: construction from null is not valid"
	.section	.text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
	.align 2
	.weak	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
	.type	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4805:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	leaq	16(%rdi), %rax
	movq	%rax, (%rdi)
	testq	%rsi, %rsi
	jne	.L57
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L62
	leaq	.LC21(%rip), %rdi
	call	_ZSt19__throw_logic_errorPKc@PLT
.L57:
	movq	%rdi, %rbx
	movq	%rsi, %rdi
	movq	%rsi, %rbp
	call	strlen@PLT
	movq	%rax, (%rsp)
	leaq	0(%rbp,%rax), %r12
	cmpq	$15, %rax
	jbe	.L59
	movq	%rsp, %rsi
	xorl	%edx, %edx
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
	movq	%rax, (%rbx)
	movq	(%rsp), %rax
	movq	%rax, 16(%rbx)
.L59:
	movq	(%rbx), %rdi
	movq	%r12, %rdx
	movq	%rbp, %rsi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcPKcS7_@PLT
	movq	(%rsp), %rax
	movq	(%rbx), %rdx
	movq	%rax, 8(%rbx)
	movb	$0, (%rdx,%rax)
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L60
.L62:
	call	__stack_chk_fail@PLT
.L60:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4805:
	.size	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
	.weak	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
	.set	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
	.section	.rodata.str1.1
.LC22:
	.string	"data.txt"
.LC23:
	.string	"out/"
	.section	.text.startup
	.type	_GLOBAL__sub_I_sdscale, @function
_GLOBAL__sub_I_sdscale:
.LFB5138:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	_Z12in_file_pathB5cxx11(%rip), %r12
	leaq	.LC22(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%r12, %rdi
	leaq	__dso_handle(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	leaq	7(%rsp), %rbx
	movq	%rbx, %rdx
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
	movq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rdi
	movq	%rbp, %rdx
	movq	%r12, %rsi
	call	__cxa_atexit@PLT
	movq	%rbx, %rdx
	leaq	_Z8out_pathB5cxx11(%rip), %rbx
	leaq	.LC23(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L64
	call	__stack_chk_fail@PLT
.L64:
	movq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	__cxa_atexit@PLT
	.cfi_endproc
.LFE5138:
	.size	_GLOBAL__sub_I_sdscale, .-_GLOBAL__sub_I_sdscale
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_sdscale
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	_Z8out_pathB5cxx11
	.bss
	.align 32
	.type	_Z8out_pathB5cxx11, @object
	.size	_Z8out_pathB5cxx11, 32
_Z8out_pathB5cxx11:
	.zero	32
	.globl	_Z12in_file_pathB5cxx11
	.align 32
	.type	_Z12in_file_pathB5cxx11, @object
	.size	_Z12in_file_pathB5cxx11, 32
_Z12in_file_pathB5cxx11:
	.zero	32
	.globl	SHOW_CONSTANTS
	.align 4
	.type	SHOW_CONSTANTS, @object
	.size	SHOW_CONSTANTS, 4
SHOW_CONSTANTS:
	.zero	4
	.globl	EVEN_HALF_DATA
	.align 4
	.type	EVEN_HALF_DATA, @object
	.size	EVEN_HALF_DATA, 4
EVEN_HALF_DATA:
	.zero	4
	.globl	FIRST_HALF_DATA
	.align 4
	.type	FIRST_HALF_DATA, @object
	.size	FIRST_HALF_DATA, 4
FIRST_HALF_DATA:
	.zero	4
	.globl	WHICH_GPU
	.align 4
	.type	WHICH_GPU, @object
	.size	WHICH_GPU, 4
WHICH_GPU:
	.zero	4
	.globl	QUIET
	.align 4
	.type	QUIET, @object
	.size	QUIET, 4
QUIET:
	.zero	4
	.globl	burn
	.align 4
	.type	burn, @object
	.size	burn, 4
burn:
	.zero	4
	.globl	seed
	.data
	.align 4
	.type	seed, @object
	.size	seed, 4
seed:
	.long	-1
	.globl	thin
	.align 4
	.type	thin, @object
	.size	thin, 4
thin:
	.long	1
	.globl	outer
	.align 4
	.type	outer, @object
	.size	outer, 4
outer:
	.long	100
	.globl	steps
	.align 4
	.type	steps, @object
	.size	steps, 4
steps:
	.long	1000
	.globl	N
	.align 4
	.type	N, @object
	.size	N, 4
N:
	.long	1048576
	.globl	sdscale
	.align 4
	.type	sdscale, @object
	.size	sdscale, 4
sdscale:
	.long	1065353216
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1065353216
	.align 4
.LC4:
	.long	1073741824
	.align 4
.LC5:
	.long	1077936128
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC6:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.hidden	__dso_handle
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
#include <limits.h>
#include <vector>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <algorithm>
using namespace std;
// #define RNG_DEF int& rx
// #define RNG_ARGS rx
// #define MY_RAND_MAX ((1U << 31) - 1)
// Command line arguments that get set below (these give default values)

float sdscale = 1.0; // scale the SDs by this
int N = 1<<20;
int steps = 1000;
int outer = 100;
int thin = 1; // how many outer blocks to skip?
int seed = -1;
int burn = 0;
int QUIET = 0;
int WHICH_GPU = 0;
int FIRST_HALF_DATA = 0;
int EVEN_HALF_DATA = 0;
int SHOW_CONSTANTS = 0;
string in_file_path = "data.txt";
string out_path = "out/";

const unsigned int nBlocks = 10 ;

const unsigned int BLOCK_SIZE = 64;
// const unsigned int HARDARE_MAX_X_BLOCKS = 4096;
// const unsigned int HARDWARE_MAX_THREADS_PER_BLOCK = 1024;
// __device__ __host__ int cuda_rand(RNG_DEF) {
//    //http://rosettacode.org/wiki/Linear_congruential_generator#C
//    return rx = (rx * 1103515245 + 12345) & MY_RAND_MAX;
// }
// __device__ int random_int(int n) {
//      // number in [0,(n-1)]
//     int divisor = MY_RAND_MAX/(n+1);
//     int retval;
//
//     do {
//         retval = cuda_rand(RNG_ARGS) / divisor;
//     } while (retval >= n);
//
//     return retval;
// }
__device__ float density_function(float beta, float cost) {
    // printf("%f-%f\n", beta, cost);
	return exp2f(-beta * cost);
}
__device__ float get_randomNum(unsigned int seed, int maxLimit) {
  /* CUDA's random number library uses curandState_t to keep track of the seed value
     we will store a random state for every thread  */
  hiprandState_t state;

  /* we have to initialize the state */
  hiprand_init(seed, /* the seed controls the sequence of random values that are produced */
              0, /* the sequence number is only important with multiple cores */
              0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
              &state);

  /* curand works like rand - except that it takes a state as a parameter */
  return hiprand(&state) % maxLimit;
 // int res = curand(&state) % maxLimit;
 // printf("%d ", res);
 // return res;
}
void setUpDevices(){
    int deviceCount = 0;
    hipGetDeviceCount(&deviceCount);
    if(WHICH_GPU <= deviceCount) {
    hipError_t err = hipSetDevice(WHICH_GPU);
    if(err != hipSuccess)
        cout<< "CUDA error:" <<hipGetErrorString(err)<<endl;
    }
    else {
        cout << "Invalid GPU device " << WHICH_GPU << endl;
        exit(-1);
    }
    int wgpu;
    hipGetDevice(&wgpu);
    hipDeviceReset();
}
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y){
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < n; i+=stride)
    y[i] = x[i] + y[i];
}
void debug_add(){
    float *x, *y;

    // Allocate Unified Memory – accessible from CPU or GPU
    hipMallocManaged(&x, N*sizeof(float));
    hipMallocManaged(&y, N*sizeof(float));

    // initialize x and y arrays on the host
    for (int i = 0; i < N; i++) {
      x[i] = 1.0f;
      y[i] = 2.0f;
    }

    int numOfBlocks = (N+BLOCK_SIZE-1)/BLOCK_SIZE;
    // Run kernel on 1M elements on the GPU
    add<<<numOfBlocks, BLOCK_SIZE>>>(N, x, y);

    // Wait for GPU to finish before accessing on host
    hipDeviceSynchronize();

    // Check for errors (all values should be 3.0f)
    float maxError = 0.0f;
    for (int i = 0; i < N; i++)
      maxError = fmax(maxError, fabs(y[i]-3.0f));
    std::cout << "Max error: " << maxError << std::endl;

    // Free memory
    hipFree(x);
    hipFree(y);
}
__device__ float cost_function(float * data, int length){
    //dummy cost, just sum up all
    float res = 0;

    for(int i=0; i<length; i++)
        res += data[i];
    // printf("res: %f\n", res);
    return res/1000;
}
__device__
void changeTemparature(float * temparature, unsigned int seed){
    int t1 = get_randomNum(seed, nBlocks);
    int t2=t1;
    while(t2 == t1)
        t2 = get_randomNum(seed + 100, nBlocks);
    float tmp = temparature[t1];
    temparature[t1] = temparature[t2];
    temparature[t2] = tmp;
}
__device__
void ActualHW(int randTimes, int numofObjs, unsigned int seed, int* pickedIdAddr, float*sArray, float * cost, float *temparature){
    // bool hit = false;
    int index = blockIdx.x*blockDim.x + threadIdx.x;
    for(int t=0; t<randTimes; t++){
        if(pickedIdAddr[t] == threadIdx.x){
            if(t % 10 == 0)
                changeTemparature(temparature, seed+index);
            float cost_pri = cost_function(sArray, numofObjs);
            float p0 = density_function(temparature[blockIdx.x], cost_pri);
            float tmpKeep = sArray[threadIdx.x];
            sArray[threadIdx.x] = get_randomNum(seed+index, 1000);

            float cost_post = cost_function(sArray, numofObjs);
            float p = density_function(temparature[blockIdx.x], cost_post);
            float alpha = min(1.0f, p/p0);
            // printf("p/p0: %f\n", p/p0);
            float t =0.8f;
            //change back
            if(alpha>t)
                sArray[threadIdx.x] = tmpKeep;
            else{
                if(sArray[threadIdx.x]>tmpKeep)
                    printf("%f - %f\n", tmpKeep, sArray[threadIdx.x]);
                cost[blockIdx.x] = cost_post;
            }


            // hit = true;
        }
    }
    // return hit;
}
__global__
void simpleHW(int numofObjs, float * gValues, float* gArray,unsigned int seed,int*pickedIdxs, int randTimes){
    //here should be dynamic shared mem
    //__shared__ float sArray[30];
    extern __shared__ float sharedMem[];
    float * sArray = sharedMem;
    float * lastSumUp = (float *) & sArray[nBlocks*numofObjs];
    float * temparature = (float *) & lastSumUp[nBlocks];
    //initialize
    int startIdx = blockIdx.x * numofObjs;
    int idx =  startIdx+ threadIdx.x;

    sArray[idx] = gValues[threadIdx.x];
    temparature[blockIdx.x] = -get_randomNum(seed+blockIdx.x, 100) / 10;
    // printf("temp: %f", temparature[blockIdx.x]);
    lastSumUp[blockIdx.x] = 0;
    for(int i = 0;i<numofObjs; i++)
        lastSumUp[blockIdx.x] += gValues[i];

    int* pickedIdAddr = &pickedIdxs[blockIdx.x * randTimes];

    ActualHW(randTimes, numofObjs, seed, pickedIdAddr, &sArray[startIdx], lastSumUp, temparature);
    __syncthreads();
    gArray[idx] = sArray[idx];
}

void simpleStructure(){
    float *gValues;
    float * gArray;
    int * pickedIdxs;

    int numofObjs = 5;

    int nTimes =20000;

    int totalSize = nBlocks*numofObjs* sizeof(float);

    hipMallocManaged(&gValues, numofObjs * sizeof(float));
    for(int i=0; i<numofObjs; i++)
        gValues[i] = 1000;
    hipMallocManaged(&pickedIdxs, nBlocks*nTimes * sizeof(int));
    for(int i=0; i<nBlocks*nTimes; i++)
        pickedIdxs[i] = rand()%numofObjs;
    // for(int i=0; i<nBlocks*nTimes; i++)
    //     cout<<pickedIdxs[i]<<" ";
    // cout<<endl;

    hipMallocManaged(&gArray, totalSize);
    //dynamic shared mem, <<<nb, nt, sm>>>
    simpleHW<<<nBlocks, numofObjs, totalSize + 2*nBlocks*sizeof(float)>>>(numofObjs, gValues, gArray,time(NULL),pickedIdxs,nTimes);

    // Wait for GPU to finish before accessing on host
    hipDeviceSynchronize();

    for(int i=0;i<nBlocks;i++){
        for(int j=0; j<numofObjs; j++)
            cout<<gArray[i * numofObjs+ j]<<" ";
        cout<<endl;
    }

    // Free memory
    hipFree(gValues);
    hipFree(gArray);
    hipFree(pickedIdxs);
}
int main(int argc, char** argv){
    setUpDevices();
    // debug_add();
    //setup blockSize
    // int N_BLOCKS = N/BLOCK_SIZE + (N%BLOCK_SIZE == 0? 0:1);
    // assert(N_BLOCKS < HARDARE_MAX_X_BLOCKS); // can have at most this many blocks
    // assert(N/N_BLOCKS <= HARDWARE_MAX_THREADS_PER_BLOCK); // MUST HAVE LESS THREADS PER BLOCK!!
    // setup the output files??
    //Make RNG replicable
    if(seed == -1)
        seed = time(NULL);
    srand(seed);
    simpleStructure();
    // read data and se
    return 0;
}

	.text
	.file	"mcmc.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z12setUpDevicesv               # -- Begin function _Z12setUpDevicesv
	.type	_Z12setUpDevicesv,@function
_Z12setUpDevicesv:                      # @_Z12setUpDevicesv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	12(%rsp), %rbx
	movl	$0, (%rbx)
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	movl	WHICH_GPU(%rip), %edi
	cmpl	(%rbx), %edi
	jg	.LBB0_7
# %bb.1:
	callq	hipSetDevice
	testl	%eax, %eax
	je	.LBB0_6
# %bb.2:
	movl	%eax, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB0_3
# %bb.4:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB0_5
.LBB0_3:
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cout(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_5:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB0_6:
	leaq	8(%rsp), %rdi
	callq	hipGetDevice
	callq	hipDeviceReset
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_7:
	.cfi_def_cfa_offset 32
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	WHICH_GPU(%rip), %esi
	movq	%rax, %rdi
	callq	_ZNSolsEi
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z12setUpDevicesv, .Lfunc_end0-_Z12setUpDevicesv
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__addiPfS_     # -- Begin function _Z18__device_stub__addiPfS_
	.type	_Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_:            # @_Z18__device_stub__addiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__addiPfS_, .Lfunc_end1-_Z18__device_stub__addiPfS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9debug_addv
.LCPI2_0:
	.long	0xc0400000                      # float -3
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI2_1:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	_Z9debug_addv
	.type	_Z9debug_addv,@function
_Z9debug_addv:                          # @_Z9debug_addv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movslq	N(%rip), %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	N(%rip), %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	N(%rip), %edi
	testl	%edi, %edi
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph
	movq	16(%rsp), %rax
	movq	8(%rsp), %rcx
	xorl	%edx, %edx
.LBB2_2:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rdx,4)      # imm = 0x3F800000
	movl	$1073741824, (%rcx,%rdx,4)      # imm = 0x40000000
	incq	%rdx
	cmpq	%rdx, %rdi
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	addl	$63, %edi
	shrl	$6, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:
	movl	N(%rip), %edi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z18__device_stub__addiPfS_
.LBB2_5:
	callq	hipDeviceSynchronize
	movl	N(%rip), %eax
	testl	%eax, %eax
	jle	.LBB2_6
# %bb.9:                                # %.lr.ph21
	xorps	%xmm3, %xmm3
	movq	8(%rsp), %rcx
	xorl	%edx, %edx
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	.LCPI2_1(%rip), %xmm2           # xmm2 = [NaN,NaN,NaN,NaN]
	movaps	%xmm3, %xmm1
.LBB2_10:                               # =>This Inner Loop Header: Depth=1
	movss	(%rcx,%rdx,4), %xmm4            # xmm4 = mem[0],zero,zero,zero
	addss	%xmm0, %xmm4
	andps	%xmm2, %xmm4
	cmpunordss	%xmm1, %xmm1
	movaps	%xmm1, %xmm5
	andps	%xmm4, %xmm5
	maxss	%xmm3, %xmm4
	andnps	%xmm4, %xmm1
	orps	%xmm5, %xmm1
	incq	%rdx
	movaps	%xmm1, %xmm3
	cmpq	%rdx, %rax
	jne	.LBB2_10
# %bb.7:                                # %._crit_edge22.loopexit
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	jmp	.LBB2_8
.LBB2_6:
	xorps	%xmm0, %xmm0
.LBB2_8:                                # %._crit_edge22
	movsd	%xmm0, 24(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9debug_addv, .Lfunc_end2-_Z9debug_addv
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__simpleHWiPfS_jPii # -- Begin function _Z23__device_stub__simpleHWiPfS_jPii
	.type	_Z23__device_stub__simpleHWiPfS_jPii,@function
_Z23__device_stub__simpleHWiPfS_jPii:   # @_Z23__device_stub__simpleHWiPfS_jPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8simpleHWiPfS_jPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__simpleHWiPfS_jPii, .Lfunc_end3-_Z23__device_stub__simpleHWiPfS_jPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15simpleStructurev            # -- Begin function _Z15simpleStructurev
	.type	_Z15simpleStructurev,@function
_Z15simpleStructurev:                   # @_Z15simpleStructurev
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	16(%rsp), %rbx
	movl	$20, %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%rbx), %rcx
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1148846080, (%rcx,%rax,4)      # imm = 0x447A0000
	incq	%rax
	cmpq	$5, %rax
	jne	.LBB4_1
# %bb.2:
	movq	%rsp, %rdi
	movl	$800000, %esi                   # imm = 0xC3500
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%ebx, %ebx
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movq	(%rsp), %rcx
	movl	%eax, (%rcx,%rbx,4)
	incq	%rbx
	cmpq	$200000, %rbx                   # imm = 0x30D40
	jne	.LBB4_3
# %bb.4:
	leaq	8(%rsp), %rdi
	movl	$200, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	movabsq	$4294967301, %rdx               # imm = 0x100000005
	leaq	5(%rdx), %rdi
	movl	$280, %r8d                      # imm = 0x118
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	16(%rsp), %rbx
	movq	8(%rsp), %r14
	xorl	%edi, %edi
	callq	time
	movq	(%rsp), %r8
	movl	$5, %edi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	%eax, %ecx
	movl	$20000, %r9d                    # imm = 0x4E20
	callq	_Z23__device_stub__simpleHWiPfS_jPii
.LBB4_6:
	callq	hipDeviceSynchronize
	xorl	%ebx, %ebx
	movl	$_ZSt4cout, %r14d
	xorl	%r15d, %r15d
.LBB4_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_8 Depth 2
	xorl	%r12d, %r12d
.LBB4_8:                                #   Parent Loop BB4_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rsp), %rax
	addq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r12,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r12
	cmpq	$5, %r12
	jne	.LBB4_8
# %bb.9:                                #   in Loop: Header=BB4_7 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r15
	addq	$20, %rbx
	cmpq	$10, %r15
	jne	.LBB4_7
# %bb.10:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z15simpleStructurev, .Lfunc_end4-_Z15simpleStructurev
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z12setUpDevicesv
	movl	seed(%rip), %edi
	cmpl	$-1, %edi
	jne	.LBB5_2
# %bb.1:
	xorl	%edi, %edi
	callq	time
	movq	%rax, %rdi
	movl	%edi, seed(%rip)
.LBB5_2:
                                        # kill: def $edi killed $edi killed $rdi
	callq	srand
	callq	_Z15simpleStructurev
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.section	.text.startup,"ax",@progbits
	.type	_GLOBAL__sub_I_mcmc.hip,@function # -- Begin function _GLOBAL__sub_I_mcmc.hip
_GLOBAL__sub_I_mcmc.hip:                # @_GLOBAL__sub_I_mcmc.hip
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	$_Z12in_file_pathB5cxx11+16, _Z12in_file_pathB5cxx11(%rip)
	movabsq	$8392585648157253988, %rax      # imm = 0x7478742E61746164
	movq	%rax, _Z12in_file_pathB5cxx11+16(%rip)
	movq	$8, _Z12in_file_pathB5cxx11+8(%rip)
	xorl	%ebx, %ebx
	movb	%bl, _Z12in_file_pathB5cxx11+24(%rip)
	movl	$_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
	movl	$_Z12in_file_pathB5cxx11, %esi
	movl	$__dso_handle, %edx
	callq	__cxa_atexit
	movq	$_Z8out_pathB5cxx11+16, _Z8out_pathB5cxx11(%rip)
	movl	$796161391, _Z8out_pathB5cxx11+16(%rip) # imm = 0x2F74756F
	movq	$4, _Z8out_pathB5cxx11+8(%rip)
	movb	%bl, _Z8out_pathB5cxx11+20(%rip)
	movl	$_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
	movl	$_Z8out_pathB5cxx11, %esi
	movl	$__dso_handle, %edx
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	__cxa_atexit                    # TAILCALL
.Lfunc_end6:
	.size	_GLOBAL__sub_I_mcmc.hip, .Lfunc_end6-_GLOBAL__sub_I_mcmc.hip
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addiPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8simpleHWiPfS_jPii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	sdscale,@object                 # @sdscale
	.data
	.globl	sdscale
	.p2align	2, 0x0
sdscale:
	.long	0x3f800000                      # float 1
	.size	sdscale, 4

	.type	N,@object                       # @N
	.globl	N
	.p2align	2, 0x0
N:
	.long	1048576                         # 0x100000
	.size	N, 4

	.type	steps,@object                   # @steps
	.globl	steps
	.p2align	2, 0x0
steps:
	.long	1000                            # 0x3e8
	.size	steps, 4

	.type	outer,@object                   # @outer
	.globl	outer
	.p2align	2, 0x0
outer:
	.long	100                             # 0x64
	.size	outer, 4

	.type	thin,@object                    # @thin
	.globl	thin
	.p2align	2, 0x0
thin:
	.long	1                               # 0x1
	.size	thin, 4

	.type	seed,@object                    # @seed
	.globl	seed
	.p2align	2, 0x0
seed:
	.long	4294967295                      # 0xffffffff
	.size	seed, 4

	.type	burn,@object                    # @burn
	.bss
	.globl	burn
	.p2align	2, 0x0
burn:
	.long	0                               # 0x0
	.size	burn, 4

	.type	QUIET,@object                   # @QUIET
	.globl	QUIET
	.p2align	2, 0x0
QUIET:
	.long	0                               # 0x0
	.size	QUIET, 4

	.type	WHICH_GPU,@object               # @WHICH_GPU
	.globl	WHICH_GPU
	.p2align	2, 0x0
WHICH_GPU:
	.long	0                               # 0x0
	.size	WHICH_GPU, 4

	.type	FIRST_HALF_DATA,@object         # @FIRST_HALF_DATA
	.globl	FIRST_HALF_DATA
	.p2align	2, 0x0
FIRST_HALF_DATA:
	.long	0                               # 0x0
	.size	FIRST_HALF_DATA, 4

	.type	EVEN_HALF_DATA,@object          # @EVEN_HALF_DATA
	.globl	EVEN_HALF_DATA
	.p2align	2, 0x0
EVEN_HALF_DATA:
	.long	0                               # 0x0
	.size	EVEN_HALF_DATA, 4

	.type	SHOW_CONSTANTS,@object          # @SHOW_CONSTANTS
	.globl	SHOW_CONSTANTS
	.p2align	2, 0x0
SHOW_CONSTANTS:
	.long	0                               # 0x0
	.size	SHOW_CONSTANTS, 4

	.type	_Z12in_file_pathB5cxx11,@object # @_Z12in_file_pathB5cxx11
	.globl	_Z12in_file_pathB5cxx11
	.p2align	3, 0x0
_Z12in_file_pathB5cxx11:
	.zero	32
	.size	_Z12in_file_pathB5cxx11, 32

	.hidden	__dso_handle
	.type	_Z8out_pathB5cxx11,@object      # @_Z8out_pathB5cxx11
	.globl	_Z8out_pathB5cxx11
	.p2align	3, 0x0
_Z8out_pathB5cxx11:
	.zero	32
	.size	_Z8out_pathB5cxx11, 32

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"CUDA error:"
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Invalid GPU device "
	.size	.L.str.4, 20

	.type	_Z3addiPfS_,@object             # @_Z3addiPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z3addiPfS_
	.p2align	3, 0x0
_Z3addiPfS_:
	.quad	_Z18__device_stub__addiPfS_
	.size	_Z3addiPfS_, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"Max error: "
	.size	.L.str.5, 12

	.type	_Z8simpleHWiPfS_jPii,@object    # @_Z8simpleHWiPfS_jPii
	.section	.rodata,"a",@progbits
	.globl	_Z8simpleHWiPfS_jPii
	.p2align	3, 0x0
_Z8simpleHWiPfS_jPii:
	.quad	_Z23__device_stub__simpleHWiPfS_jPii
	.size	_Z8simpleHWiPfS_jPii, 8

	.type	.L.str.6,@object                # @.str.6
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.6:
	.asciz	" "
	.size	.L.str.6, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3addiPfS_"
	.size	.L__unnamed_1, 12

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8simpleHWiPfS_jPii"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	_GLOBAL__sub_I_mcmc.hip
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym _Z18__device_stub__addiPfS_
	.addrsig_sym _Z23__device_stub__simpleHWiPfS_jPii
	.addrsig_sym _GLOBAL__sub_I_mcmc.hip
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12in_file_pathB5cxx11
	.addrsig_sym __dso_handle
	.addrsig_sym _Z8out_pathB5cxx11
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z3addiPfS_
	.addrsig_sym _Z8simpleHWiPfS_jPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addiPfS_             ; -- Begin function _Z3addiPfS_
	.globl	_Z3addiPfS_
	.p2align	8
	.type	_Z3addiPfS_,@function
_Z3addiPfS_:                            ; @_Z3addiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s8
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	global_load_b32 v0, v[4:5], off
	global_load_b32 v4, v[6:7], off
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e64 s0, s10, v1
	global_store_b32 v[6:7], v0, off
	s_or_b32 s1, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow21
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8simpleHWiPfS_jPii    ; -- Begin function _Z8simpleHWiPfS_jPii
	.globl	_Z8simpleHWiPfS_jPii
	.p2align	8
	.type	_Z8simpleHWiPfS_jPii,@function
_Z8simpleHWiPfS_jPii:                   ; @_Z8simpleHWiPfS_jPii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s8, s[0:1], 0x18
	v_lshlrev_b32_e32 v1, 2, v0
	s_load_b32 s20, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v2, v1, s[4:5]
	s_add_i32 s2, s15, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, 0x2c7f967f
	s_mul_i32 s2, s2, 0x493c4aa1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s2, 0x75bcd15
	s_add_i32 s10, s2, 0x583f19
	s_lshr_b32 s9, s3, 2
	s_xor_b32 s3, s9, s3
	s_lshl_b32 s9, s10, 4
	s_lshl_b32 s11, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s9, s11
	s_xor_b32 s9, s9, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s9, s3
	s_mul_i32 s9, s15, s20
	s_add_i32 s2, s2, s3
	s_add_i32 s2, s2, 0x8ac7d9dd
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, 0x51eb851f
	s_lshr_b32 s3, s3, 5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mulk_i32 s3, 0x64
	s_sub_i32 s2, s2, s3
	s_mul_i32 s3, s20, 40
	v_cvt_f32_u32_e32 v3, s2
	s_lshl_b32 s2, s15, 2
	s_add_i32 s27, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s21, s27, s2
	v_div_scale_f32 v1, null, 0xc1200000, 0xc1200000, v3
	v_div_scale_f32 v6, vcc_lo, v3, 0xc1200000, v3
	v_add_nc_u32_e32 v34, s9, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v4, v1
	s_cmp_gt_i32 s20, 0
	s_cselect_b32 s22, -1, 0
	s_cmp_lt_i32 s20, 1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v1, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v1, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v5, v6
	v_div_fmas_f32 v4, v1, v4, v5
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v5, s21
	v_lshl_add_u32 v35, v34, 2, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_div_fixup_f32 v3, v4, 0xc1200000, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v35, v2
	ds_store_2addr_b32 v5, v1, v3 offset1:10
	s_cbranch_scc1 .LBB1_4
; %bb.1:                                ; %.lr.ph.preheader
	s_mov_b32 s2, s20
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s3, s[4:5], 0x0
	s_add_i32 s2, s2, -1
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s2, 0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, s3, v1
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ; %._crit_edge
	v_mov_b32_e32 v2, s21
	ds_store_b32 v2, v1
.LBB1_4:
	s_load_b32 s23, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s23, 1
	s_cbranch_scc1 .LBB1_221
; %bb.5:                                ; %.lr.ph.i
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x20
	s_load_b32 s12, s[0:1], 0x3c
	s_mul_i32 s2, s15, s23
	s_mov_b32 s3, 0
	v_mbcnt_lo_u32_b32 v41, -1, 0
	s_lshl_b64 s[10:11], s[2:3], 2
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s24, s4, s10
	s_addc_u32 s25, s5, s11
	s_lshl_b32 s2, s9, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s26, s2, 0
	s_add_u32 s4, s0, 48
	s_addc_u32 s5, s1, 0
	s_and_b32 s0, s12, 0xffff
	v_lshl_add_u32 v39, v0, 2, s26
	s_mul_i32 s15, s15, s0
	s_mov_b32 s2, s3
	v_add3_u32 v1, s15, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, 0x2c7f967f, v1
	v_add_nc_u32_e32 v1, 0x64, v1
	v_mul_lo_u32 v2, 0x493c4aa1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, 0x2c7f967f, v1
	v_mul_lo_u32 v1, 0x493c4aa1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x75bcd15, v2
	v_add_nc_u32_e32 v5, 0x583f19, v2
	v_lshrrev_b32_e32 v4, 2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v4, v3
	v_lshlrev_b32_e32 v4, 4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 1, v3
	v_xor_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor3_b32 v3, v4, v5, v3
	v_add_nc_u32_e32 v4, 0x75bcd15, v1
	v_add_nc_u32_e32 v5, 0x583f19, v1
	v_add3_u32 v2, v2, v3, 0x8ac7d9dd
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v3, 2, v4
	v_mul_hi_u32 v6, 0x10624dd3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v4
	v_lshlrev_b32_e32 v4, 4, v5
	v_lshlrev_b32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 6, v6
	v_xor_b32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_u32_u24_e32 v6, 0x3e8, v6
	v_xor3_b32 v3, v4, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v2, v6
	v_mul_hi_u32 v6, 0xcccccccd, v2
	v_add3_u32 v1, v1, v3, 0x8ac7d9dd
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cvt_f64_u32_e32 v[3:4], v5
	v_cvt_f32_u32_e32 v40, v5
	v_mov_b32_e32 v5, 33
	v_mul_hi_u32 v7, 0xcccccccd, v1
	v_lshrrev_b32_e32 v6, 3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, v6, 10
	v_lshrrev_b32_e32 v7, 3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, v7, 10
	v_sub_nc_u32_e32 v36, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v38, v36, 2, s27
	s_add_i32 s27, s27, 40
	v_sub_nc_u32_e32 v37, v1, v7
	v_mov_b32_e32 v7, 0
.LBB1_6:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
                                        ;     Child Loop BB1_13 Depth 2
                                        ;     Child Loop BB1_16 Depth 2
                                        ;     Child Loop BB1_22 Depth 2
                                        ;     Child Loop BB1_30 Depth 2
                                        ;     Child Loop BB1_36 Depth 2
                                        ;     Child Loop BB1_45 Depth 2
                                        ;     Child Loop BB1_48 Depth 2
                                        ;       Child Loop BB1_51 Depth 3
                                        ;       Child Loop BB1_59 Depth 3
                                        ;       Child Loop BB1_67 Depth 3
                                        ;       Child Loop BB1_75 Depth 3
                                        ;       Child Loop BB1_83 Depth 3
                                        ;       Child Loop BB1_91 Depth 3
                                        ;       Child Loop BB1_99 Depth 3
                                        ;       Child Loop BB1_107 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
                                        ;       Child Loop BB1_121 Depth 3
                                        ;       Child Loop BB1_130 Depth 3
                                        ;     Child Loop BB1_138 Depth 2
                                        ;     Child Loop BB1_146 Depth 2
                                        ;     Child Loop BB1_152 Depth 2
                                        ;     Child Loop BB1_161 Depth 2
                                        ;     Child Loop BB1_166 Depth 2
                                        ;     Child Loop BB1_174 Depth 2
                                        ;     Child Loop BB1_180 Depth 2
                                        ;     Child Loop BB1_189 Depth 2
                                        ;     Child Loop BB1_193 Depth 2
                                        ;     Child Loop BB1_201 Depth 2
                                        ;     Child Loop BB1_207 Depth 2
                                        ;     Child Loop BB1_216 Depth 2
	s_lshl_b64 s[0:1], s[2:3], 2
	s_mov_b32 s28, exec_lo
	s_add_u32 s0, s24, s0
	s_addc_u32 s1, s25, s1
	global_load_b32 v1, v7, s[0:1]
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 v1, v0
	s_cbranch_execz .LBB1_220
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=1
	s_mul_i32 s0, s2, 0xcccccccd
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v1, s0, s0, 1
	v_cmp_lt_u32_e32 vcc_lo, 0x19999999, v1
	s_cbranch_vccnz .LBB1_11
; %bb.8:                                ; %.preheader76.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	v_mov_b32_e32 v2, v36
	s_mov_b32 s0, 0
.LBB1_9:                                ; %.preheader76.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v37
	v_cmp_ne_u32_e32 vcc_lo, v1, v36
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_9
; %bb.10:                               ; %_Z17changeTemparaturePfj.exit.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_lshl_add_u32 v1, v1, 2, s27
	ds_load_b32 v2, v1
	ds_load_b32 v6, v38 offset:40
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v38, v2 offset:40
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v1, v6
.LBB1_11:                               ;   in Loop: Header=BB1_6 Depth=1
	v_mov_b32_e32 v1, 0
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB1_14
; %bb.12:                               ; %.lr.ph.i.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, s20
	s_mov_b32 s1, s26
.LBB1_13:                               ; %.lr.ph.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s1
	s_add_i32 s0, s0, -1
	s_add_i32 s1, s1, 4
	s_cmp_lg_u32 s0, 0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	s_cbranch_scc1 .LBB1_13
.LBB1_14:                               ; %_Z13cost_functionPfi.exit.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	v_mov_b32_e32 v2, s21
	v_mov_b32_e32 v6, 0
	s_and_not1_b32 vcc_lo, exec_lo, s22
	ds_load_b32 v2, v2 offset:40
	ds_load_b32 v42, v39
	ds_store_b32 v39, v40
	s_cbranch_vccnz .LBB1_17
; %bb.15:                               ; %.lr.ph.i34.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, s20
	s_mov_b32 s1, s26
.LBB1_16:                               ; %.lr.ph.i34.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s1
	s_add_i32 s0, s0, -1
	s_add_i32 s1, s1, 4
	s_cmp_lg_u32 s0, 0
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v8
	s_cbranch_scc1 .LBB1_16
.LBB1_17:                               ; %_Z13cost_functionPfi.exit38.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	v_div_scale_f32 v8, null, 0x447a0000, 0x447a0000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, 0x447a0000, 0x447a0000, v6
	v_div_scale_f32 v16, vcc_lo, v1, 0x447a0000, v1
	v_rcp_f32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v9
	v_mov_b32_e32 v20, s21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v8, v12, 1.0
	v_fma_f32 v15, -v9, v13, 1.0
	v_dual_fmac_f32 v12, v14, v12 :: v_dual_fmac_f32 v13, v15, v13
	v_div_scale_f32 v14, s0, v6, 0x447a0000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v16, v12
	v_mul_f32_e32 v17, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v8, v15, v16
	v_fma_f32 v19, -v9, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v18, v12
	ds_load_b32 v18, v20 offset:40
	v_fmac_f32_e32 v17, v19, v13
	v_fma_f32 v8, -v8, v15, v16
	v_fma_f32 v9, -v9, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v8, v8, v12, v15
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v9, v9, v13, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v8, 0x447a0000, v1
	v_div_fixup_f32 v43, v9, 0x447a0000, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v6, v1, -v2
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v8, v43, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v6
	v_cmp_gt_f32_e64 s0, 0xc2fc0000, v8
	v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 0x42800000, s0
	v_fma_f32 v1, v1, -v2, v6
	v_cndmask_b32_e64 v6, 1.0, 0x1f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v2, v43, -v18, v8
	v_cndmask_b32_e64 v8, 1.0, 0x1f800000, s0
	v_exp_f32_e32 v1, v1
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, v1, v6 :: v_dual_mul_f32 v2, v2, v8
	v_div_scale_f32 v6, null, v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v9, vcc_lo, v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v9, v8
	v_fma_f32 v13, -v6, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v8
	v_fma_f32 v6, -v6, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v12
	v_div_fixup_f32 v1, v6, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f32_e32 v1, 1.0, v1
	v_cmp_nlt_f32_e32 vcc_lo, 0x3f4ccccd, v1
	s_cbranch_vccz .LBB1_218
; %bb.18:                               ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s29, exec_lo
	v_cmpx_lt_f32_e32 v42, v40
	s_cbranch_execz .LBB1_217
; %bb.19:                               ;   in Loop: Header=BB1_6 Depth=1
	s_load_b64 s[8:9], s[4:5], 0x50
	v_dual_mov_b32 v6, v41 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_25
; %bb.20:                               ;   in Loop: Header=BB1_6 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[14:15], v7, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v15
	v_and_b32_e32 v1, v1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[12:13], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[14:15]
	s_cbranch_execz .LBB1_24
; %bb.21:                               ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s11, 0
.LBB1_22:                               ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[12:13], v7, s[8:9]
	v_dual_mov_b32 v15, v2 :: v_dual_mov_b32 v14, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[12:13], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[14:15]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_22
; %bb.23:                               ; %Flow426
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_24:                               ; %Flow428
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_25:                               ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b128 v[12:15], v7, s[8:9]
	v_readfirstlane_b32 s10, v1
	v_readfirstlane_b32 s11, v2
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s18, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v13, vcc_lo
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, v7
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_27:                               ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_lshl_b64 s[12:13], s[12:13], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v15, vcc_lo
	s_mov_b32 s16, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s17, s3
	s_mov_b32 s18, s3
	s_mov_b32 s19, s3
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_mov_b32_e32 v6, v7
	v_mov_b32_e32 v8, v7
	v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v17, s19
	v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v16, s18
	s_clause 0x3
	global_store_b128 v[1:2], v[5:8], off
	global_store_b128 v[1:2], v[14:17], off offset:16
	global_store_b128 v[1:2], v[14:17], off offset:32
	global_store_b128 v[1:2], v[14:17], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_35
; %bb.28:                               ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v7, s[8:9] offset:32 glc
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	v_mov_b32_e32 v16, s10
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v6, s11, v9
	v_and_b32_e32 v8, s10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v9, v6
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v6, vcc_lo
	global_store_b64 v[8:9], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v7, v[16:19], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[18:19]
	s_cbranch_execz .LBB1_31
; %bb.29:                               ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s16, 0
.LBB1_30:                               ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
	s_sleep 1
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[14:17], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[16:17]
	v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_30
.LBB1_31:                               ; %Flow424
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[8:9], v7, s[8:9] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v6, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_6 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[6:7], off offset:8
.LBB1_33:                               ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[14:15], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	s_cbranch_vccnz .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_6 Depth=1
	global_load_b32 v6, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[14:15], v[6:7], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_35:                               ; %Flow425
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v6, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB1_36:                               ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_38
; %bb.37:                               ;   in Loop: Header=BB1_36 Depth=2
	global_load_b32 v6, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB1_38:                               ;   in Loop: Header=BB1_36 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_40
; %bb.39:                               ;   in Loop: Header=BB1_36 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_41
.LBB1_40:                               ;   in Loop: Header=BB1_36 Depth=2
	s_mov_b32 s1, -1
.LBB1_41:                               ; %Flow419
                                        ;   in Loop: Header=BB1_36 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_36
; %bb.42:                               ;   in Loop: Header=BB1_6 Depth=1
	global_load_b64 v[12:13], v[1:2], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_46
; %bb.43:                               ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x2
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9] offset:24 glc
	global_load_b64 v[16:17], v7, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_cndmask_b32_e32 v14, v14, v6, vcc_lo
	v_cndmask_b32_e32 v15, v15, v18, vcc_lo
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, v1
	v_mov_b32_e32 v16, v8
	v_and_b32_e32 v2, v15, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, v17, v2, vcc_lo
	v_mov_b32_e32 v17, v9
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v7, v[14:17], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_46
; %bb.44:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, 0
.LBB1_45:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[1:2], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[14:17], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[16:17]
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v16, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_45
.LBB1_46:                               ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB1_133
; %bb.47:                               ;   in Loop: Header=BB1_6 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v13 :: v_dual_and_b32 v44, 2, v12
	v_and_b32_e32 v14, -3, v12
	s_mov_b64 s[12:13], 9
.LBB1_48:                               ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_51 Depth 3
                                        ;       Child Loop BB1_59 Depth 3
                                        ;       Child Loop BB1_67 Depth 3
                                        ;       Child Loop BB1_75 Depth 3
                                        ;       Child Loop BB1_83 Depth 3
                                        ;       Child Loop BB1_91 Depth 3
                                        ;       Child Loop BB1_99 Depth 3
                                        ;       Child Loop BB1_107 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
                                        ;       Child Loop BB1_121 Depth 3
                                        ;       Child Loop BB1_130 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[12:13], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s14, s12, 56
	s_cselect_b32 s15, s13, 0
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB1_53
; %bb.49:                               ;   in Loop: Header=BB1_48 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_52
; %bb.50:                               ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[10:11]
.LBB1_51:                               ; %.preheader31.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v7, s[18:19]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s0, s16
	v_or_b32_e32 v16, v1, v16
	v_or_b32_e32 v17, v2, v17
	s_cbranch_scc1 .LBB1_51
.LBB1_52:                               ; %Flow395
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s30, 0
	s_branch .LBB1_54
.LBB1_53:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr30
.LBB1_54:                               ; %Flow397
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB1_56
; %bb.55:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[16:17], v7, s[10:11]
	s_add_i32 s30, s14, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB1_56:                               ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s30, 7
	s_cbranch_scc1 .LBB1_61
; %bb.57:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s30, 0
	s_cbranch_scc1 .LBB1_60
; %bb.58:                               ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_59:                               ; %.preheader29.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s18
	s_addc_u32 s35, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v7, s[34:35]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s30, s18
	v_or_b32_e32 v18, v1, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v2, v19
	s_cbranch_scc1 .LBB1_59
.LBB1_60:                               ; %Flow390
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_62
.LBB1_61:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $sgpr31
.LBB1_62:                               ; %Flow392
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_64
; %bb.63:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[18:19], v7, s[0:1]
	s_add_i32 s31, s30, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_64:                               ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_69
; %bb.65:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_68
; %bb.66:                               ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_67:                               ; %.preheader27.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s18
	s_addc_u32 s35, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v7, s[34:35]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s31, s18
	v_or_b32_e32 v20, v1, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v2, v21
	s_cbranch_scc1 .LBB1_67
.LBB1_68:                               ; %Flow385
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s30, 0
	s_branch .LBB1_70
.LBB1_69:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr30
.LBB1_70:                               ; %Flow387
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_72
; %bb.71:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[20:21], v7, s[0:1]
	s_add_i32 s30, s31, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_72:                               ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s30, 7
	s_cbranch_scc1 .LBB1_77
; %bb.73:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s30, 0
	s_cbranch_scc1 .LBB1_76
; %bb.74:                               ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_75:                               ; %.preheader25.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s18
	s_addc_u32 s35, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v7, s[34:35]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s30, s18
	v_or_b32_e32 v22, v1, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v2, v23
	s_cbranch_scc1 .LBB1_75
.LBB1_76:                               ; %Flow380
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_78
.LBB1_77:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $sgpr31
.LBB1_78:                               ; %Flow382
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_80
; %bb.79:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[22:23], v7, s[0:1]
	s_add_i32 s31, s30, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_80:                               ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_85
; %bb.81:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_84
; %bb.82:                               ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_83:                               ; %.preheader23.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s18
	s_addc_u32 s35, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v7, s[34:35]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s31, s18
	v_or_b32_e32 v24, v1, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v2, v25
	s_cbranch_scc1 .LBB1_83
.LBB1_84:                               ; %Flow375
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s30, 0
	s_branch .LBB1_86
.LBB1_85:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr30
.LBB1_86:                               ; %Flow377
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_88
; %bb.87:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[24:25], v7, s[0:1]
	s_add_i32 s30, s31, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_88:                               ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s30, 7
	s_cbranch_scc1 .LBB1_93
; %bb.89:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s30, 0
	s_cbranch_scc1 .LBB1_92
; %bb.90:                               ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_91:                               ; %.preheader21.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s18
	s_addc_u32 s35, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v7, s[34:35]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s30, s18
	v_or_b32_e32 v26, v1, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v27, v2, v27
	s_cbranch_scc1 .LBB1_91
.LBB1_92:                               ; %Flow370
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_94
.LBB1_93:                               ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $sgpr31
.LBB1_94:                               ; %Flow372
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_96
; %bb.95:                               ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[26:27], v7, s[0:1]
	s_add_i32 s31, s30, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_96:                               ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_101
; %bb.97:                               ;   in Loop: Header=BB1_48 Depth=2
	v_mov_b32_e32 v28, 0
	v_mov_b32_e32 v29, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_100
; %bb.98:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[0:1]
.LBB1_99:                               ; %.preheader.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v7, s[18:19]
	s_add_i32 s31, s31, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], s16, v[6:7]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s31, 0
	v_or_b32_e32 v28, v1, v28
	v_or_b32_e32 v29, v2, v29
	s_cbranch_scc1 .LBB1_99
.LBB1_100:                              ; %Flow365
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, 0
	s_branch .LBB1_102
.LBB1_101:                              ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s16, -1
.LBB1_102:                              ; %Flow367
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_104
; %bb.103:                              ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[28:29], v7, s[0:1]
.LBB1_104:                              ; %.loopexit.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	v_dual_mov_b32 v6, v41 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_110
; %bb.105:                              ;   in Loop: Header=BB1_48 Depth=2
	global_load_b64 v[32:33], v7, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9]
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v33
	v_and_b32_e32 v1, v1, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v30, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v30, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[30:31], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[30:33], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[32:33]
	s_cbranch_execz .LBB1_109
; %bb.106:                              ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s17, 0
.LBB1_107:                              ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[30:31], v7, s[8:9]
	v_dual_mov_b32 v33, v2 :: v_dual_mov_b32 v32, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v32
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[30:31]
	v_and_b32_e32 v30, v9, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v30, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[30:31], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[30:33], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[32:33]
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB1_107
; %bb.108:                              ; %Flow360
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
.LBB1_109:                              ; %Flow362
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
.LBB1_110:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b128 v[30:33], v7, s[8:9]
	v_readfirstlane_b32 s16, v1
	v_readfirstlane_b32 s17, v2
	s_mov_b32 s33, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s18, v8
	v_readfirstlane_b32 s19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[16:17], s[18:19]
	s_mul_i32 s1, s19, 24
	s_mul_hi_u32 s30, s18, 24
	s_mul_i32 s31, s18, 24
	s_and_saveexec_b32 s34, s0
	s_cbranch_execz .LBB1_112
; %bb.111:                              ;   in Loop: Header=BB1_48 Depth=2
	s_add_i32 s35, s30, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v30, s31
	v_add_co_ci_u32_e32 v2, vcc_lo, s35, v31, vcc_lo
	v_dual_mov_b32 v8, s33 :: v_dual_mov_b32 v9, v7
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_112:                              ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s34
	v_cmp_gt_u64_e64 vcc_lo, s[12:13], 56
	v_or_b32_e32 v1, 0, v15
	v_or_b32_e32 v2, v14, v44
	s_lshl_b64 s[18:19], s[18:19], 12
	s_lshl_b32 s33, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s33, s33, 28
	v_dual_cndmask_b32 v15, v1, v15 :: v_dual_cndmask_b32 v8, v2, v14
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v32, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v33, vcc_lo
	s_and_b32 s33, s33, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v6, v1
	v_and_or_b32 v14, 0xffffff1f, v8, s33
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	s_clause 0x3
	global_store_b128 v[1:2], v[14:17], off
	global_store_b128 v[1:2], v[18:21], off offset:16
	global_store_b128 v[1:2], v[22:25], off offset:32
	global_store_b128 v[1:2], v[26:29], off offset:48
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB1_120
; %bb.113:                              ;   in Loop: Header=BB1_48 Depth=2
	s_clause 0x1
	global_load_b64 v[18:19], v7, s[8:9] offset:32 glc
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s34, v8
	v_readfirstlane_b32 s35, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[34:35], s[34:35], s[16:17]
	s_mul_i32 s19, s35, 24
	s_mul_hi_u32 s33, s34, 24
	s_mul_i32 s34, s34, 24
	s_add_i32 s33, s33, s19
	v_add_co_u32 v8, vcc_lo, v30, s34
	v_add_co_ci_u32_e32 v9, vcc_lo, s33, v31, vcc_lo
	s_mov_b32 s19, exec_lo
	global_store_b64 v[8:9], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v7, v[16:19], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[18:19]
	s_cbranch_execz .LBB1_116
; %bb.114:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s33, 0
.LBB1_115:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
	s_sleep 1
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[14:17], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[16:17]
	v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
	s_or_b32 s33, vcc_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s33
	s_cbranch_execnz .LBB1_115
.LBB1_116:                              ; %Flow358
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	global_load_b64 v[8:9], v7, s[8:9] offset:16
	s_mov_b32 s33, exec_lo
	s_mov_b32 s19, exec_lo
	v_mbcnt_lo_u32_b32 v6, s33, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB1_118
; %bb.117:                              ;   in Loop: Header=BB1_48 Depth=2
	s_bcnt1_i32_b32 s33, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s33
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[6:7], off offset:8
.LBB1_118:                              ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt vmcnt(0)
	global_load_b64 v[14:15], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	s_cbranch_vccnz .LBB1_120
; %bb.119:                              ;   in Loop: Header=BB1_48 Depth=2
	global_load_b32 v6, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s19, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[14:15], v[6:7], off
	s_and_b32 m0, s19, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_120:                              ; %Flow359
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s30, s30, s1
	v_add_co_u32 v6, vcc_lo, v30, s31
	v_add_co_ci_u32_e32 v9, vcc_lo, s30, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB1_121:                              ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_123
; %bb.122:                              ;   in Loop: Header=BB1_121 Depth=3
	global_load_b32 v6, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB1_123:                              ;   in Loop: Header=BB1_121 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_125
; %bb.124:                              ;   in Loop: Header=BB1_121 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_126
.LBB1_125:                              ;   in Loop: Header=BB1_121 Depth=3
	s_mov_b32 s1, -1
.LBB1_126:                              ; %Flow353
                                        ;   in Loop: Header=BB1_121 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_121
; %bb.127:                              ;   in Loop: Header=BB1_48 Depth=2
	global_load_b128 v[14:17], v[1:2], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_131
; %bb.128:                              ;   in Loop: Header=BB1_48 Depth=2
	s_clause 0x2
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9] offset:24 glc
	global_load_b64 v[18:19], v7, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v6, s16
	v_add_co_ci_u32_e32 v17, vcc_lo, s17, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
	v_dual_cndmask_b32 v17, v17, v20 :: v_dual_cndmask_b32 v16, v16, v6
	v_and_b32_e32 v2, v17, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v16, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v6, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v18, v1
	v_mov_b32_e32 v18, v8
	v_add_co_ci_u32_e32 v2, vcc_lo, v19, v2, vcc_lo
	v_mov_b32_e32 v19, v9
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[18:19], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_131
; %bb.129:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_mov_b32 s0, 0
.LBB1_130:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ;     Parent Loop BB1_48 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[1:2], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[18:19]
	v_dual_mov_b32 v19, v9 :: v_dual_mov_b32 v18, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_130
.LBB1_131:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB1_48 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s12, s12, s14
	s_subb_u32 s13, s13, s15
	s_add_u32 s10, s10, s14
	s_addc_u32 s11, s11, s15
	s_cmp_lg_u64 s[12:13], 0
	s_cbranch_scc1 .LBB1_48
; %bb.132:                              ; %Flow398
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB1_134
.LBB1_133:                              ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
.LBB1_134:                              ; %Flow413
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_163
; %bb.135:                              ;   in Loop: Header=BB1_6 Depth=1
	v_dual_mov_b32 v6, v41 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_141
; %bb.136:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b64 v[16:17], v7, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v17
	v_and_b32_e32 v1, v1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v14, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v14, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[14:15], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[14:17], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[16:17]
	s_cbranch_execz .LBB1_140
; %bb.137:                              ; %.preheader3.i.i.i44.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s11, 0
.LBB1_138:                              ; %.preheader3.i.i.i44.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[14:15], v7, s[8:9]
	v_dual_mov_b32 v17, v2 :: v_dual_mov_b32 v16, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[14:15]
	v_and_b32_e32 v14, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v14, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[14:15], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[14:17], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[16:17]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_138
; %bb.139:                              ; %Flow410
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_140:                              ; %Flow412
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_141:                              ; %.loopexit4.i.i.i39.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b128 v[16:19], v7, s[8:9]
	v_readfirstlane_b32 s10, v1
	v_readfirstlane_b32 s11, v2
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB1_143
; %bb.142:                              ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s18, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s15
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v17, vcc_lo
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, v7
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_143:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_lshl_b64 s[12:13], s[12:13], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v18, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v19, vcc_lo
	s_mov_b32 s19, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s16, s3
	s_mov_b32 s17, s3
	s_mov_b32 s18, s3
	v_and_or_b32 v12, 0xffffff1f, v12, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v21, s19
	v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v20, s18
	v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v18, s16
	s_clause 0x3
	global_store_b128 v[1:2], v[12:15], off
	global_store_b128 v[1:2], v[18:21], off offset:16
	global_store_b128 v[1:2], v[18:21], off offset:32
	global_store_b128 v[1:2], v[18:21], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_151
; %bb.144:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v7, s[8:9] offset:32 glc
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	v_dual_mov_b32 v18, s10 :: v_dual_mov_b32 v19, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v8
	v_readfirstlane_b32 s17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v8, vcc_lo, v16, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v17, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[8:9], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[18:21], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[20:21]
	s_cbranch_execz .LBB1_147
; %bb.145:                              ; %.preheader1.i.i.i42.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s16, 0
.LBB1_146:                              ; %.preheader1.i.i.i42.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v7, v[12:15], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_146
.LBB1_147:                              ; %Flow408
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[8:9], v7, s[8:9] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v6, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB1_149
; %bb.148:                              ;   in Loop: Header=BB1_6 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[6:7], off offset:8
.LBB1_149:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB1_151
; %bb.150:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b32 v6, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[6:7], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_151:                              ; %Flow409
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v6, vcc_lo, v16, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB1_152:                              ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_154
; %bb.153:                              ;   in Loop: Header=BB1_152 Depth=2
	global_load_b32 v6, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB1_154:                              ;   in Loop: Header=BB1_152 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_156
; %bb.155:                              ;   in Loop: Header=BB1_152 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_157
.LBB1_156:                              ;   in Loop: Header=BB1_152 Depth=2
	s_mov_b32 s1, -1
.LBB1_157:                              ; %Flow403
                                        ;   in Loop: Header=BB1_152 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_152
; %bb.158:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b128 v[14:17], v[1:2], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_162
; %bb.159:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x2
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9] offset:24 glc
	global_load_b64 v[12:13], v7, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v19, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
	v_dual_cndmask_b32 v17, v17, v18 :: v_dual_mov_b32 v18, v8
	v_cndmask_b32_e32 v16, v16, v6, vcc_lo
	v_and_b32_e32 v2, v17, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v16, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v6, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v12, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, v13, v2, vcc_lo
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[18:19], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_162
; %bb.160:                              ; %.preheader.i.i.i41.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, 0
.LBB1_161:                              ; %.preheader.i.i.i41.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[1:2], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[18:19]
	v_dual_mov_b32 v19, v9 :: v_dual_mov_b32 v18, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_161
.LBB1_162:                              ; %__ockl_hostcall_preview.exit.i.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_163:                              ; %__ockl_printf_append_string_n.exit.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	v_dual_mov_b32 v6, v41 :: v_dual_mov_b32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v6
	v_mov_b32_e32 v2, 0
	v_cmp_eq_u32_e64 s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_169
; %bb.164:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b64 v[18:19], v7, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v19
	v_and_b32_e32 v1, v1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v12, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v12, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	global_load_b64 v[16:17], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[18:19]
	s_cbranch_execz .LBB1_168
; %bb.165:                              ; %.preheader3.i.i.i51.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s11, 0
.LBB1_166:                              ; %.preheader3.i.i.i51.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[12:13], v7, s[8:9]
	v_dual_mov_b32 v19, v2 :: v_dual_mov_b32 v18, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v18
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[2:3]
	v_mov_b32_e32 v2, v8
	global_load_b64 v[16:17], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v7, v[16:19], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[18:19]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_166
; %bb.167:                              ; %Flow346
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_168:                              ; %Flow348
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_169:                              ; %.loopexit4.i.i.i45.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b128 v[18:21], v7, s[8:9]
	v_readfirstlane_b32 s10, v1
	v_readfirstlane_b32 s11, v2
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB1_171
; %bb.170:                              ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s18, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v18, s15
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v19, vcc_lo
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, v7
	global_store_b128 v[1:2], v[8:11], off offset:8
.LBB1_171:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cvt_f64_f32_e32 v[16:17], v42
	s_lshl_b64 s[12:13], s[12:13], 12
	v_lshlrev_b64 v[1:2], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v20, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v21, vcc_lo
	s_mov_b32 s19, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s16, s3
	s_mov_b32 s17, s3
	s_mov_b32 s18, s3
	v_and_or_b32 v14, 0xffffff1f, v14, 32
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_dual_mov_b32 v23, s19 :: v_dual_mov_b32 v22, s18
	v_dual_mov_b32 v21, s17 :: v_dual_mov_b32 v20, s16
	s_clause 0x3
	global_store_b128 v[1:2], v[14:17], off
	global_store_b128 v[1:2], v[20:23], off offset:16
	global_store_b128 v[1:2], v[20:23], off offset:32
	global_store_b128 v[1:2], v[20:23], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_179
; %bb.172:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v7, s[8:9] offset:32 glc
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v8
	v_readfirstlane_b32 s17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v8, vcc_lo, v18, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v19, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[14:17], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB1_175
; %bb.173:                              ; %.preheader1.i.i.i49.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s16, 0
.LBB1_174:                              ; %.preheader1.i.i.i49.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v7, v[12:15], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_174
.LBB1_175:                              ; %Flow344
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[8:9], v7, s[8:9] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v6, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB1_177
; %bb.176:                              ;   in Loop: Header=BB1_6 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[6:7], off offset:8
.LBB1_177:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB1_179
; %bb.178:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b32 v6, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[6:7], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_179:                              ; %Flow345
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v6, vcc_lo, v18, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB1_180:                              ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_182
; %bb.181:                              ;   in Loop: Header=BB1_180 Depth=2
	global_load_b32 v6, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB1_182:                              ;   in Loop: Header=BB1_180 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_184
; %bb.183:                              ;   in Loop: Header=BB1_180 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_185
.LBB1_184:                              ;   in Loop: Header=BB1_180 Depth=2
	s_mov_b32 s1, -1
.LBB1_185:                              ; %Flow339
                                        ;   in Loop: Header=BB1_180 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_180
; %bb.186:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b64 v[1:2], v[1:2], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_190
; %bb.187:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x2
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[16:17], v7, s[8:9] offset:24 glc
	global_load_b64 v[14:15], v7, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_cndmask_b32_e32 v12, v12, v6, vcc_lo
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_and_b32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v13, v9
	v_mul_hi_u32 v9, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v8, v8, 24
	v_add_nc_u32_e32 v6, v9, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v14, v8
	v_mov_b32_e32 v14, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v6, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_190
; %bb.188:                              ; %.preheader.i.i.i48.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, 0
.LBB1_189:                              ; %.preheader.i.i.i48.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_189
.LBB1_190:                              ; %__ockl_printf_append_args.exit.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v6, v41
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v6
	v_cmp_eq_u32_e64 s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_196
; %bb.191:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b64 v[14:15], v7, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v7, s[8:9] offset:40
	global_load_b64 v[12:13], v7, s[8:9]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v15
	v_and_b32_e32 v8, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v16, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v16, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
	global_load_b64 v[12:13], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[14:15]
	s_cbranch_execz .LBB1_195
; %bb.192:                              ; %.preheader3.i.i.i58.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s11, 0
.LBB1_193:                              ; %.preheader3.i.i.i58.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[12:13], v7, s[8:9] offset:40
	global_load_b64 v[16:17], v7, s[8:9]
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, v12, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[16:17]
	v_and_b32_e32 v16, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v16, 24, v[9:10]
	v_mov_b32_e32 v9, v12
	global_load_b64 v[12:13], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[14:15]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_193
; %bb.194:                              ; %Flow332
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_195:                              ; %Flow334
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_196:                              ; %.loopexit4.i.i.i52.i
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[16:17], v7, s[8:9] offset:40
	global_load_b128 v[12:15], v7, s[8:9]
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v16
	v_readfirstlane_b32 s13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB1_198
; %bb.197:                              ;   in Loop: Header=BB1_6 Depth=1
	s_add_i32 s18, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v16, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v17, vcc_lo, s18, v13, vcc_lo
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, v7
	global_store_b128 v[16:17], v[8:11], off offset:8
.LBB1_198:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_lshl_b64 s[12:13], s[12:13], 12
	v_lshlrev_b64 v[8:9], 6, v[6:7]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v14, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v15, vcc_lo
	s_mov_b32 s16, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, v8
	s_mov_b32 s17, s3
	s_mov_b32 s18, s3
	s_mov_b32 s19, s3
	v_and_or_b32 v1, 0xffffff1d, v1, 34
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v9, vcc_lo
	v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
	v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s19
	s_clause 0x3
	global_store_b128 v[8:9], v[1:4], off
	global_store_b128 v[8:9], v[14:17], off offset:16
	global_store_b128 v[8:9], v[14:17], off offset:32
	global_store_b128 v[8:9], v[14:17], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_206
; %bb.199:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v7, s[8:9] offset:32 glc
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	v_dual_mov_b32 v16, s10 :: v_dual_mov_b32 v17, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v1
	v_readfirstlane_b32 s17, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v1, vcc_lo, v12, s16
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v13, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[1:2], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v7, v[16:19], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[18:19]
	s_cbranch_execz .LBB1_202
; %bb.200:                              ; %.preheader1.i.i.i56.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s16, 0
.LBB1_201:                              ; %.preheader1.i.i.i56.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
	s_sleep 1
	global_store_b64 v[1:2], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[14:17], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[16:17]
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v16, v8
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_201
.LBB1_202:                              ; %Flow330
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[1:2], v7, s[8:9] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v6, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB1_204
; %bb.203:                              ;   in Loop: Header=BB1_6 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[6:7], off offset:8
.LBB1_204:                              ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB1_206
; %bb.205:                              ;   in Loop: Header=BB1_6 Depth=1
	global_load_b32 v6, v[1:2], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[6:7], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_206:                              ; %Flow331
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v2, vcc_lo, s14, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB1_207:                              ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_209
; %bb.208:                              ;   in Loop: Header=BB1_207 Depth=2
	global_load_b32 v6, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB1_209:                              ;   in Loop: Header=BB1_207 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_211
; %bb.210:                              ;   in Loop: Header=BB1_207 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_212
.LBB1_211:                              ;   in Loop: Header=BB1_207 Depth=2
	s_mov_b32 s1, -1
.LBB1_212:                              ; %Flow325
                                        ;   in Loop: Header=BB1_207 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_207
; %bb.213:                              ;   in Loop: Header=BB1_6 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_217
; %bb.214:                              ;   in Loop: Header=BB1_6 Depth=1
	s_clause 0x2
	global_load_b64 v[1:2], v7, s[8:9] offset:40
	global_load_b64 v[8:9], v7, s[8:9] offset:24 glc
	global_load_b64 v[14:15], v7, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v16 :: v_dual_cndmask_b32 v12, v12, v6
	v_and_b32_e32 v2, v13, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v6, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v14, v1
	v_mov_b32_e32 v14, v8
	v_add_co_ci_u32_e32 v2, vcc_lo, v15, v2, vcc_lo
	v_mov_b32_e32 v15, v9
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_217
; %bb.215:                              ; %.preheader.i.i.i55.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b32 s0, 0
.LBB1_216:                              ; %.preheader.i.i.i55.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[1:2], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[12:15], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[14:15]
	v_dual_mov_b32 v15, v9 :: v_dual_mov_b32 v14, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_216
.LBB1_217:                              ; %Flow429
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	v_mov_b32_e32 v1, s21
	s_mov_b32 s0, 0
	ds_store_b32 v1, v43
.LBB1_218:                              ; %Flow431
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_220
; %bb.219:                              ;   in Loop: Header=BB1_6 Depth=1
	ds_store_b32 v39, v42
.LBB1_220:                              ; %Flow439
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s28
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, s23
	s_cbranch_scc1 .LBB1_6
.LBB1_221:                              ; %_Z8ActualHWiijPiPfS0_S0_.exit
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v35
	v_ashrrev_i32_e32 v35, 31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[34:35]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8simpleHWiPfS_jPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8simpleHWiPfS_jPii, .Lfunc_end1-_Z8simpleHWiPfS_jPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9692
; NumSgprs: 38
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%f - %f\n"
	.size	.str, 9

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3addiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         128
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8simpleHWiPfS_jPii
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z8simpleHWiPfS_jPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
