#include "includes.h"
/************************* CudaMat ******************************************
*   Copyright (C) 2008-2009 by Rainer Heintzmann                          *
*   heintzmann@gmail.com                                                  *
*                                                                         *
*   This program is free software; you can redistribute it and/or modify  *
*   it under the terms of the GNU General Public License as published by  *
*   the Free Software Foundation; Version 2 of the License.               *
*                                                                         *
*   This program is distributed in the hope that it will be useful,       *
*   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
*   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
*   GNU General Public License for more details.                          *
*                                                                         *
*   You should have received a copy of the GNU General Public License     *
*   along with this program; if not, write to the                         *
*   Free Software Foundation, Inc.,                                       *
*   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')

Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')

Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC  in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/

// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177


#ifndef NAN   // should be part of math.h
#define NAN (0.0/0.0)
#endif

#define ACCU_ARRTYPE double  // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)

//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS  // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS  64

#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))

#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])


__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);

size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz;  // total size of array, has to be chains*length_of_chain
size_t length=N/chains;  // chain length
size_t steps=N/Processes;  // this is how many steps each processor has to do

size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;

//if (id != 0)   return;
//for (id=0;id<Processes;id++)
{
step=steps*id;   // my starting step as the id times the number of steps
nl=step%length;  // current position in chain length
nx=(step/length)%ux;  // current position in unit cell x
ny=(step/(length*ux))%uy;  // current position in unit cell y
nz=(step/(length*ux*uy))%uz;  // current position in unit cell z
i=0;

//if (step/steps != 4 && step/steps != 5) return;

while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx;  // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N)  // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}

c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
}
	.file	"tmpxft_0037e1e2_00000000-6_rotate.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
	.type	_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, @function
_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 40(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 52(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z6rotatePffS_mmmmmmmmm(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm, .-_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
	.globl	_Z6rotatePffS_mmmmmmmmm
	.type	_Z6rotatePffS_mmmmmmmmm, @function
_Z6rotatePffS_mmmmmmmmm:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z6rotatePffS_mmmmmmmmmPffS_mmmmmmmmm
	.cfi_endproc
.LFE2033:
	.size	_Z6rotatePffS_mmmmmmmmm, .-_Z6rotatePffS_mmmmmmmmm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6rotatePffS_mmmmmmmmm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6rotatePffS_mmmmmmmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
*   Copyright (C) 2008-2009 by Rainer Heintzmann                          *
*   heintzmann@gmail.com                                                  *
*                                                                         *
*   This program is free software; you can redistribute it and/or modify  *
*   it under the terms of the GNU General Public License as published by  *
*   the Free Software Foundation; Version 2 of the License.               *
*                                                                         *
*   This program is distributed in the hope that it will be useful,       *
*   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
*   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
*   GNU General Public License for more details.                          *
*                                                                         *
*   You should have received a copy of the GNU General Public License     *
*   along with this program; if not, write to the                         *
*   Free Software Foundation, Inc.,                                       *
*   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
***************************************************************************
* Compile with:
* Windows:
system('"c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin\vcvars32.bat"')
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 9.0\VC\bin')

Window 64 bit:
system('nvcc -c cudaArith.cu -ccbin "c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin" -I"c:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\include" ')

Linux:
* File sudo vi /usr/local/cuda/bin/nvcc.profile
* needs the flag -fPIC  in the include line
system('nvcc -c cudaArith.cu -v -I/usr/local/cuda/include/')
*/

// To suppress the unused variable argument for ARM targets
#pragma diag_suppress 177


#ifndef NAN   // should be part of math.h
#define NAN (0.0/0.0)
#endif

#define ACCU_ARRTYPE double  // Type of the tempory arrays for reduce operations
#define IMUL(a, b) __mul24(a, b)

//#define BLOCKSIZE 512
//#define BLOCKSIZE 512
// below is blocksize for temporary array for reduce operations. Has to be a power of 2 in size
#ifndef CUIMAGE_REDUCE_THREADS  // this can be defined at compile time via the flag NVCCFLAG='-D CUIMAGE_REDUCE_THREADS=512'
#define CUIMAGE_REDUCE_THREADS 512
#endif
// (prop.maxThreadsPerBlock)
// #define CUIMAGE_REDUCE_THREADS 512
// #define CUIMAGE_REDUCE_THREADS 128
//#define CUIMAGE_REDUCE_BLOCKS  64

#define NBLOCKS(N,blockSize) (N/blockSize+(N%blockSize==0?0:1))

#define NBLOCKSL(N,blockSize) 1
// min((N/blockSize+(N%blockSize==0?0:1)),prop.maxGridSize[0])


__global__ void rotate(float*a,float b, float * c, size_t sx,size_t sy,size_t sz, size_t dx, size_t dy, size_t dz, size_t ux, size_t uy, size_t uz)
{
// id of this processor
size_t id=((blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x);

size_t Processes=blockDim.x * gridDim.x;
size_t chains=ux*uy*uz; // total number of independent chains
size_t N=sx*sy*sz;  // total size of array, has to be chains*length_of_chain
size_t length=N/chains;  // chain length
size_t steps=N/Processes;  // this is how many steps each processor has to do

size_t step,nl,nx,ny,nz,x,y,z,i,idd;
float swp, nswp;

//if (id != 0)   return;
//for (id=0;id<Processes;id++)
{
step=steps*id;   // my starting step as the id times the number of steps
nl=step%length;  // current position in chain length
nx=(step/length)%ux;  // current position in unit cell x
ny=(step/(length*ux))%uy;  // current position in unit cell y
nz=(step/(length*ux*uy))%uz;  // current position in unit cell z
i=0;

//if (step/steps != 4 && step/steps != 5) return;

while(nz<uz)
{
while(ny<uy)
{
while (nx<ux)
{
x=(nx+nl*dx)%sx;  // advance by the offset steps along the chain
y=(ny+nl*dy)%sy;
z=(nz+nl*dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps) {
swp=a[idd];
// a[idd]=a[idd]+0.1;
__syncthreads();
}
while (nl<length-1)
{
if (i > steps-1)
goto nextProcessor; // return;
if (step >= N)  // this thread has reached the end of the total data to process
goto nextProcessor; // return;
step++;
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
if (i < steps-1) {
nswp=a[idd];
__syncthreads();
//a[idd]=a[idd]+0.1;
}

c[idd]=swp+0.1; // c[idd]+ny+0.1; // c[idd]+i; // swp+0.1; // c[idd]+(step/steps);
i++; // counts number of writes
if (i > steps-1)
goto nextProcessor; // return;
nl++;
if (i < steps) {
swp=nswp;
}
}
nx++; nl=0;
//if (nx < ux) {
x = (x+dx)%sx; // new position
y = (y+dy)%sy;
z = (z+dz)%sz;
idd=x+sx*y+sx*sy*z;
c[idd]=swp+0.1; // no need to save this value as this is the end of the line
//}
i++;
if (i > steps-1)
goto nextProcessor; // return;
// if (nx <ux) x=(x+1)%sx;
}
ny++;
// if (ny <uy) y=(y+1)%sy;
nx=0;x=0;
}
nz++;
// if (nz <uz) z=(z+1)%sz;
ny=0;y=0;
}
nextProcessor:
nz=0;
}
return;
}
	.text
	.file	"rotate.hip"
	.globl	_Z21__device_stub__rotatePffS_mmmmmmmmm # -- Begin function _Z21__device_stub__rotatePffS_mmmmmmmmm
	.type	_Z21__device_stub__rotatePffS_mmmmmmmmm,@function
_Z21__device_stub__rotatePffS_mmmmmmmmm: # @_Z21__device_stub__rotatePffS_mmmmmmmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movss	%xmm0, (%rdi)
	leaq	64(%rsp), %r10
	movq	%rsi, (%r10)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6rotatePffS_mmmmmmmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__rotatePffS_mmmmmmmmm, .Lfunc_end0-_Z21__device_stub__rotatePffS_mmmmmmmmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6rotatePffS_mmmmmmmmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6rotatePffS_mmmmmmmmm,@object # @_Z6rotatePffS_mmmmmmmmm
	.section	.rodata,"a",@progbits
	.globl	_Z6rotatePffS_mmmmmmmmm
	.p2align	3, 0x0
_Z6rotatePffS_mmmmmmmmm:
	.quad	_Z21__device_stub__rotatePffS_mmmmmmmmm
	.size	_Z6rotatePffS_mmmmmmmmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6rotatePffS_mmmmmmmmm"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__rotatePffS_mmmmmmmmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6rotatePffS_mmmmmmmmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6rotatePffS_mmmmmmmmm ; -- Begin function _Z6rotatePffS_mmmmmmmmm
	.globl	_Z6rotatePffS_mmmmmmmmm
	.p2align	8
	.type	_Z6rotatePffS_mmmmmmmmm,@function
_Z6rotatePffS_mmmmmmmmm:                ; @_Z6rotatePffS_mmmmmmmmm
; %bb.0:
	s_clause 0x3
	s_load_b512 s[16:31], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x50
	s_load_b32 s3, s[0:1], 0x60
	s_load_b32 s8, s[0:1], 0x6c
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr37
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s13, s21, s18
	s_mul_i32 s2, s4, s31
	s_mul_hi_u32 s9, s4, s30
	s_mul_i32 s10, s5, s30
	s_mul_i32 s12, s4, s30
	s_add_i32 s2, s9, s2
	s_mul_i32 s9, s12, s7
	s_mul_hi_u32 s11, s12, s6
	s_add_i32 s2, s2, s10
	s_add_i32 s9, s11, s9
	s_mul_i32 s2, s2, s6
	s_mul_i32 s12, s12, s6
	s_add_i32 s2, s9, s2
	v_cvt_f32_u32_e32 v1, s12
	v_cvt_f32_u32_e32 v2, s2
	s_and_b32 s10, s8, 0xffff
	s_mul_i32 s8, s20, s19
	s_mul_hi_u32 s9, s20, s18
	s_mul_i32 s11, s3, s15
	v_fmac_f32_e32 v1, 0x4f800000, v2
	s_mul_i32 s33, s20, s18
	s_add_i32 s8, s9, s8
	s_add_i32 s11, s11, s14
	s_mul_i32 s9, s33, s23
	v_rcp_f32_e32 v1, v1
	s_mul_hi_u32 s14, s33, s22
	s_add_i32 s34, s8, s13
	s_add_i32 s8, s14, s9
	s_mul_i32 s9, s34, s22
	s_mul_i32 s3, s3, s10
	s_add_i32 s9, s8, s9
	s_sub_u32 s15, 0, s12
	s_subb_u32 s35, 0, s2
	v_cvt_f32_u32_e32 v5, s30
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	v_cvt_f32_u32_e32 v6, s31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_fmac_f32_e32 v5, 0x4f800000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v2, v2
	v_rcp_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s13, v2
	v_cvt_f32_u32_e32 v2, s3
	v_readfirstlane_b32 s14, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_i32 s8, s15, s13
	v_fmac_f32_e64 v2, 0, 0x4f800000
	s_delay_alu instid0(VALU_DEP_2)
	s_mul_hi_u32 s36, s15, s14
	s_mul_i32 s37, s35, s14
	s_add_i32 s8, s36, s8
	s_mul_i32 s38, s15, s14
	s_add_i32 s8, s8, s37
	s_mul_hi_u32 s36, s14, s38
	s_mul_hi_u32 s39, s13, s38
	s_mul_i32 s37, s13, s38
	s_mul_hi_u32 s38, s14, s8
	s_mul_i32 s14, s14, s8
	s_mul_hi_u32 s40, s13, s8
	s_add_u32 s14, s36, s14
	s_addc_u32 s36, 0, s38
	s_add_u32 s14, s14, s37
	s_mul_i32 s8, s13, s8
	s_addc_u32 s14, s36, s39
	s_addc_u32 s36, s40, 0
	s_add_u32 s8, s14, s8
	s_addc_u32 s14, 0, s36
	v_add_co_u32 v1, s8, v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s8, 0
	s_mul_i32 s8, s33, s22
	s_addc_u32 s13, s13, s14
	v_readfirstlane_b32 s36, v1
	s_mul_i32 s14, s15, s13
	v_rcp_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s37, s15, s36
	s_mul_i32 s35, s35, s36
	s_add_i32 s14, s37, s14
	s_mul_i32 s15, s15, s36
	s_add_i32 s14, s14, s35
	s_mul_hi_u32 s37, s13, s15
	s_mul_i32 s38, s13, s15
	s_mul_hi_u32 s15, s36, s15
	s_mul_hi_u32 s39, s36, s14
	s_mul_i32 s36, s36, s14
	s_mul_hi_u32 s35, s13, s14
	s_add_u32 s15, s15, s36
	s_addc_u32 s36, 0, s39
	s_add_u32 s15, s15, s38
	s_mul_i32 s14, s13, s14
	s_addc_u32 s15, s36, s37
	s_addc_u32 s35, s35, 0
	s_add_u32 s14, s15, s14
	s_addc_u32 s15, 0, s35
	v_add_co_u32 v1, s14, v1, s14
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s14, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	s_addc_u32 s13, s13, s15
	v_readfirstlane_b32 s14, v1
	s_mul_i32 s35, s8, s13
	s_mul_hi_u32 s15, s8, s13
	s_mul_hi_u32 s36, s9, s13
	s_mul_i32 s13, s9, s13
	s_mul_hi_u32 s37, s8, s14
	s_mul_hi_u32 s38, s9, s14
	s_mul_i32 s14, s9, s14
	s_add_u32 s35, s37, s35
	s_addc_u32 s15, 0, s15
	s_add_u32 s14, s35, s14
	s_addc_u32 s14, s15, s38
	s_addc_u32 s15, s36, 0
	s_add_u32 s13, s14, s13
	s_addc_u32 s14, 0, s15
	s_mul_hi_u32 s15, s12, s13
	s_mul_i32 s36, s12, s14
	s_mul_i32 s37, s12, s13
	s_add_i32 s15, s15, s36
	v_sub_co_u32 v1, s36, s8, s37
	s_mul_i32 s35, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s15, s15, s35
	v_sub_co_u32 v3, s37, v1, s12
	s_sub_i32 s35, s9, s15
	s_cmp_lg_u32 s36, 0
	s_subb_u32 s35, s35, s2
	s_cmp_lg_u32 s37, 0
	v_readfirstlane_b32 s37, v3
	s_subb_u32 s35, s35, 0
	v_mul_f32_e32 v3, 0x2f800000, v2
	s_cmp_ge_u32 s35, s2
	s_cselect_b32 s38, -1, 0
	s_cmp_ge_u32 s37, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	s_cselect_b32 s37, -1, 0
	s_cmp_eq_u32 s35, s2
	s_cselect_b32 s35, s37, s38
	s_add_u32 s37, s13, 1
	s_addc_u32 s38, s14, 0
	s_add_u32 s39, s13, 2
	s_addc_u32 s40, s14, 0
	s_cmp_lg_u32 s35, 0
	v_fmac_f32_e32 v2, 0xcf800000, v3
	s_cselect_b32 s35, s39, s37
	s_cselect_b32 s37, s40, s38
	s_cmp_lg_u32 s36, 0
	v_readfirstlane_b32 s36, v1
	s_subb_u32 s15, s9, s15
	v_cvt_u32_f32_e32 v1, v3
	s_cmp_ge_u32 s15, s2
	v_cvt_u32_f32_e32 v2, v2
	s_cselect_b32 s38, -1, 0
	s_cmp_ge_u32 s36, s12
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s15, s2
	s_cselect_b32 s2, s12, s38
	v_readfirstlane_b32 s12, v1
	s_cmp_lg_u32 s2, 0
	v_readfirstlane_b32 s2, v2
	s_cselect_b32 s15, s37, s14
	s_cselect_b32 s14, s35, s13
	s_sub_u32 s13, 0, s3
	s_subb_u32 s35, 0, 0
	s_mul_i32 s36, s13, s12
	s_mul_hi_u32 s37, s13, s2
	s_mul_i32 s39, s35, s2
	s_add_i32 s36, s37, s36
	s_mul_i32 s38, s13, s2
	s_add_i32 s36, s36, s39
	s_mul_hi_u32 s37, s2, s38
	s_mul_hi_u32 s39, s2, s36
	s_mul_i32 s2, s2, s36
	s_mul_hi_u32 s40, s12, s38
	s_mul_i32 s38, s12, s38
	s_add_u32 s2, s37, s2
	s_addc_u32 s37, 0, s39
	s_mul_hi_u32 s41, s12, s36
	s_add_u32 s2, s2, s38
	s_mul_i32 s36, s12, s36
	s_addc_u32 s2, s37, s40
	s_addc_u32 s37, s41, 0
	s_add_u32 s2, s2, s36
	s_addc_u32 s36, 0, s37
	v_add_co_u32 v2, s2, v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s2, 0
	v_cvt_f32_u32_e32 v1, s14
	s_addc_u32 s12, s12, s36
	v_readfirstlane_b32 s2, v2
	s_mul_i32 s36, s13, s12
	v_cvt_f32_u32_e32 v3, s15
	s_delay_alu instid0(VALU_DEP_2)
	s_mul_hi_u32 s37, s13, s2
	s_mul_i32 s35, s35, s2
	s_add_i32 s36, s37, s36
	s_mul_i32 s13, s13, s2
	s_add_i32 s36, s36, s35
	s_mul_hi_u32 s37, s12, s13
	s_mul_i32 s38, s12, s13
	s_mul_hi_u32 s13, s2, s13
	s_mul_hi_u32 s39, s2, s36
	s_mul_i32 s2, s2, s36
	s_mul_hi_u32 s35, s12, s36
	s_add_u32 s2, s13, s2
	s_addc_u32 s13, 0, s39
	s_add_u32 s2, s2, s38
	s_mul_i32 s36, s12, s36
	s_addc_u32 s2, s13, s37
	s_addc_u32 s13, s35, 0
	v_fmac_f32_e32 v1, 0x4f800000, v3
	s_add_u32 s2, s2, s36
	s_addc_u32 s13, 0, s13
	v_add_co_u32 v2, s2, v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v1
	s_cmp_lg_u32 s2, 0
	s_addc_u32 s2, s12, s13
	v_readfirstlane_b32 s12, v2
	s_mul_i32 s35, s8, s2
	s_mul_hi_u32 s13, s8, s2
	s_mul_hi_u32 s36, s9, s2
	s_mul_i32 s2, s9, s2
	s_mul_hi_u32 s37, s8, s12
	s_mul_hi_u32 s38, s9, s12
	s_mul_i32 s12, s9, s12
	s_add_u32 s35, s37, s35
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_addc_u32 s13, 0, s13
	s_add_u32 s12, s35, s12
	s_addc_u32 s12, s13, s38
	s_addc_u32 s13, s36, 0
	s_add_u32 s12, s12, s2
	v_mul_f32_e32 v3, 0x2f800000, v1
	s_mul_i32 s36, s3, s12
	s_addc_u32 s13, 0, s13
	s_add_u32 s35, s12, 1
	v_sub_co_u32 v2, s36, s8, s36
	s_mul_hi_u32 s2, s3, s12
	s_addc_u32 s37, s13, 0
	s_mul_i32 s38, s3, s13
	s_add_u32 s39, s12, 2
	v_trunc_f32_e32 v3, v3
	s_addc_u32 s40, s13, 0
	s_add_i32 s2, s2, s38
	s_cmp_lg_u32 s36, 0
	v_sub_co_u32 v4, s36, v2, s3
	s_subb_u32 s38, s9, s2
	s_cmp_lg_u32 s36, 0
	v_fmac_f32_e32 v1, 0xcf800000, v3
	s_subb_u32 s2, s38, 0
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_cmp_eq_u32 s2, 0
	v_cvt_u32_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v1, v1
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_cselect_b32 s3, -1, 0
	s_sub_u32 s36, 0, s14
	s_subb_u32 s38, 0, s15
	v_mul_lo_u32 v7, s36, v3
	v_mul_hi_u32 v8, s36, v1
	v_mul_lo_u32 v6, s38, v1
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cndmask_b32_e64 v4, -1, v4, s2
	v_mov_b32_e32 v10, s39
	v_dual_mov_b32 v12, s40 :: v_dual_add_nc_u32 v7, v8, v7
	v_mul_lo_u32 v8, s36, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v7, 0x5f7ffffc, v5 :: v_dual_add_nc_u32 v6, v7, v6
	v_mul_hi_u32 v5, v1, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v9, v1, v6
	v_mul_hi_u32 v11, v1, v6
	v_mul_hi_u32 v13, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_mul_hi_u32 v14, v3, v6
	v_mul_lo_u32 v6, v3, v6
	v_add_co_u32 v5, vcc_lo, v5, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v5, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v13, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, v1, v5
	v_add_co_ci_u32_e64 v6, s2, v3, v6, s2
	v_cndmask_b32_e64 v1, -1, v2, s3
	v_cndmask_b32_e32 v2, s35, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v9, s36, v8
	v_mul_lo_u32 v10, s36, v6
	v_cndmask_b32_e32 v3, s37, v12, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_mul_lo_u32 v11, s38, v8
	v_mad_u64_u32 v[4:5], null, s11, s10, v[0:1]
	v_mul_f32_e32 v5, 0x2f800000, v7
	v_cndmask_b32_e32 v0, s12, v2, vcc_lo
	v_dual_cndmask_b32 v1, s13, v3 :: v_dual_add_nc_u32 v2, v9, v10
	v_mul_lo_u32 v3, s36, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v9, v5
	v_mad_u64_u32 v[18:19], null, v0, v4, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, v2, v11
	s_sub_u32 s11, 0, s30
	v_fmac_f32_e32 v7, 0xcf800000, v9
	v_cvt_u32_f32_e32 v9, v9
	v_mul_hi_u32 v10, v8, v3
	v_mul_lo_u32 v11, v8, v2
	v_mul_hi_u32 v12, v8, v2
	v_mul_hi_u32 v13, v6, v3
	v_mul_lo_u32 v3, v6, v3
	v_mul_hi_u32 v14, v6, v2
	v_mov_b32_e32 v5, v19
	s_subb_u32 s12, 0, s31
	s_mul_i32 s10, s14, s30
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	v_mul_lo_u32 v12, v6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v14, vcc_lo
	v_mad_u64_u32 v[2:3], null, v1, v4, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v11, vcc_lo
	v_cvt_u32_f32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v19, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v12, v18, v8
	s_mul_i32 s13, s10, s4
	v_mad_u64_u32 v[3:4], null, v18, v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v19, v8, 0
	v_mad_u64_u32 v[7:8], null, v19, v10, 0
	v_mul_hi_u32 v10, s11, v11
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_mul_lo_u32 v12, s12, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v6, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v5, s11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v3, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v4, vcc_lo
	v_mul_lo_u32 v7, s11, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v13, s15, v6
	v_mad_u64_u32 v[3:4], null, s14, v6, 0
	v_mul_lo_u32 v14, s14, v8
	v_add_nc_u32_e32 v5, v10, v5
	v_mul_hi_u32 v10, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v5, v12
	v_sub_co_u32 v3, s2, v18, v3
	v_add3_u32 v4, v4, v14, v13
	v_mul_hi_u32 v12, v9, v7
	v_mul_lo_u32 v14, v11, v5
	v_mul_hi_u32 v13, v11, v5
	v_mul_lo_u32 v7, v9, v7
	v_sub_nc_u32_e32 v15, v19, v4
	v_mul_hi_u32 v16, v9, v5
	v_mul_lo_u32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v15, vcc_lo, s15, v15, s2
	v_add_co_u32 v10, vcc_lo, v10, v14
	v_sub_co_u32 v14, s3, v3, s14
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	v_subrev_co_ci_u32_e64 v15, s3, 0, v15, s3
	v_add_co_u32 v17, s3, v6, 2
	v_add_co_u32 v7, vcc_lo, v10, v7
	v_add_co_ci_u32_e64 v20, s3, 0, v8, s3
	v_cmp_le_u32_e64 s3, s14, v14
	v_add_co_ci_u32_e32 v7, vcc_lo, v13, v12, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v16, vcc_lo
	v_sub_co_ci_u32_e64 v4, vcc_lo, v19, v4, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, -1, s3
	v_cmp_le_u32_e64 s3, s15, v15
	v_add_co_u32 v5, vcc_lo, v7, v5
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v10, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s15, v4
	v_cndmask_b32_e64 v21, 0, -1, s3
	v_add_co_u32 v22, s3, v6, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v23, s3, 0, v8, s3
	v_cmp_eq_u32_e64 s3, s15, v15
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_add_co_u32 v5, vcc_lo, v11, v5
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
	v_cndmask_b32_e64 v14, v21, v14, s3
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	s_mul_i32 s2, s14, s31
	s_mul_hi_u32 s3, s14, s30
	v_mul_lo_u32 v9, s11, v7
	s_add_i32 s3, s3, s2
	s_mul_i32 s2, s15, s30
	v_mul_hi_u32 v11, s11, v5
	s_add_i32 s3, s3, s2
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_eq_u32_e64 s2, s15, v4
	v_cvt_f32_u32_e32 v12, s3
	v_cvt_f32_u32_e32 v13, s10
	v_mul_lo_u32 v15, s12, v5
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	v_add_nc_u32_e32 v9, v11, v9
	v_cndmask_b32_e64 v3, v10, v3, s2
	v_fmac_f32_e32 v13, 0x4f800000, v12
	v_mul_lo_u32 v10, s11, v5
	v_cndmask_b32_e32 v14, v22, v17, vcc_lo
	v_dual_cndmask_b32 v12, v23, v20 :: v_dual_add_nc_u32 v9, v9, v15
	v_cmp_ne_u32_e64 s2, 0, v3
	v_rcp_f32_e32 v11, v13
	s_sub_u32 s11, 0, s10
	s_mul_hi_u32 s12, s10, s4
	v_mul_lo_u32 v3, v5, v9
	v_cndmask_b32_e64 v4, v6, v14, s2
	v_mul_hi_u32 v6, v5, v10
	v_mul_hi_u32 v14, v5, v9
	v_mul_lo_u32 v15, v7, v10
	v_mul_hi_u32 v10, v7, v10
	v_mul_hi_u32 v13, v7, v9
	v_mul_f32_e32 v11, 0x5f7ffffc, v11
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v6, 0x2f800000, v11
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v15
	v_mul_lo_u32 v3, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v6, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v10, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, 0xcf800000, v6
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_cvt_u32_f32_e32 v10, v6
	v_cvt_u32_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, v7, v9, vcc_lo
	v_cndmask_b32_e64 v3, v8, v12, s2
	v_mul_lo_u32 v12, s11, v10
	v_mul_hi_u32 v14, s11, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v4, v9, 0
	v_mul_hi_u32 v15, v4, v13
	s_subb_u32 s2, 0, s3
	v_mad_u64_u32 v[7:8], null, v3, v13, 0
	v_mul_lo_u32 v13, s2, v11
	v_add_nc_u32_e32 v12, v14, v12
	v_mul_lo_u32 v16, s11, v11
	v_add_co_u32 v14, vcc_lo, v15, v5
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v6, vcc_lo
	v_mad_u64_u32 v[5:6], null, v3, v9, 0
	v_add_nc_u32_e32 v9, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, v14, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, v15, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v7, v11, v9
	v_mul_hi_u32 v8, v11, v16
	v_mul_hi_u32 v13, v11, v9
	v_mul_lo_u32 v15, v10, v16
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v6, vcc_lo
	v_mul_hi_u32 v16, v10, v16
	v_mul_hi_u32 v6, v10, v9
	v_mul_lo_u32 v9, v10, v9
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, v15
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v16, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v11, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, s11, v7
	v_mul_lo_u32 v10, s2, v7
	v_mul_lo_u32 v8, s11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v9, v8
	v_mul_lo_u32 v9, s11, v7
	s_sub_u32 s11, 0, s4
	s_subb_u32 s35, 0, s5
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v7, v9
	v_mul_lo_u32 v10, v7, v8
	v_mul_hi_u32 v13, v7, v8
	v_mul_lo_u32 v16, v6, v9
	v_mul_hi_u32 v9, v6, v9
	v_mul_hi_u32 v15, v6, v8
	v_mul_lo_u32 v8, v6, v8
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v9, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v10, vcc_lo, v6, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v15, v18, v13
	v_mad_u64_u32 v[6:7], null, v18, v10, 0
	v_mad_u64_u32 v[8:9], null, v2, v10, 0
	v_mad_u64_u32 v[10:11], null, v2, v13, 0
	v_cvt_f32_u32_e32 v13, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v15, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_cvt_f32_u32_e32 v15, s5
	v_add_co_u32 v6, vcc_lo, v6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v11, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
	v_fmac_f32_e32 v13, 0x4f800000, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v13
	v_mul_lo_u32 v11, s3, v8
	v_mad_u64_u32 v[6:7], null, s10, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v13, s10, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x5f7ffffc, v9
	v_sub_co_u32 v6, s2, v18, v6
	v_add3_u32 v7, v7, v13, v11
	v_mul_f32_e32 v15, 0x2f800000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, v2, v7
	v_trunc_f32_e32 v11, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v13, vcc_lo, s3, v13, s2
	v_sub_co_u32 v15, vcc_lo, v6, s10
	v_fmac_f32_e32 v9, 0xcf800000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	v_cvt_u32_f32_e32 v11, v11
	v_cvt_u32_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v13
	v_mul_lo_u32 v17, s11, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v16, s11, v9
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v15
	v_mul_lo_u32 v21, s35, v9
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s3, v13
	v_add_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v20, v15, vcc_lo
	v_mul_lo_u32 v15, s11, v9
	v_add_nc_u32_e32 v16, v16, v21
	v_add_co_u32 v17, vcc_lo, v8, 2
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v22, v9, v16
	v_mul_hi_u32 v21, v9, v16
	v_mul_hi_u32 v23, v9, v15
	v_add_co_u32 v24, vcc_lo, v8, 1
	v_mul_lo_u32 v26, v11, v15
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v10, vcc_lo
	v_mul_hi_u32 v15, v11, v15
	v_add_co_u32 v22, vcc_lo, v23, v22
	v_mul_hi_u32 v23, v11, v16
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_mul_lo_u32 v16, v11, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v22, v26
	v_add_co_ci_u32_e32 v15, vcc_lo, v21, v15, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v23, vcc_lo
	v_sub_co_ci_u32_e64 v7, vcc_lo, v2, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v15, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v7
	s_mul_i32 s2, s10, s5
	v_cvt_f32_u32_e32 v23, s13
	s_add_i32 s12, s12, s2
	s_mul_i32 s2, s3, s4
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, v15
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, s11, v9
	s_add_i32 s12, s12, s2
	v_mul_lo_u32 v15, s11, v11
	v_cvt_f32_u32_e32 v22, s12
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
	v_cmp_eq_u32_e64 s2, s3, v7
	v_mul_lo_u32 v26, s35, v9
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	v_fmac_f32_e32 v23, 0x4f800000, v22
	v_mul_lo_u32 v7, s11, v9
	v_add_nc_u32_e32 v15, v16, v15
	v_cndmask_b32_e64 v6, v21, v6, s2
	v_cndmask_b32_e32 v13, v24, v17, vcc_lo
	v_rcp_f32_e32 v16, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, v25, v20 :: v_dual_add_nc_u32 v15, v15, v26
	v_cmp_ne_u32_e64 s2, 0, v6
	v_mul_lo_u32 v23, v11, v7
	s_sub_u32 s3, 0, s13
	v_mul_lo_u32 v17, v3, s14
	v_mul_lo_u32 v6, v9, v15
	v_cndmask_b32_e64 v13, v8, v13, s2
	v_mul_hi_u32 v8, v9, v7
	v_mul_hi_u32 v22, v9, v15
	v_mul_f32_e32 v16, 0x5f7ffffc, v16
	v_mul_hi_u32 v7, v11, v7
	v_mul_hi_u32 v21, v11, v15
	v_mul_lo_u32 v24, v4, s15
	s_load_b64 s[10:11], s[0:1], 0x0
	s_mov_b32 s35, 0
	v_add_co_u32 v6, vcc_lo, v8, v6
	v_mul_f32_e32 v8, 0x2f800000, v16
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v6, v23
	v_mul_lo_u32 v6, v11, v15
	v_trunc_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, v22, v7, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v21, vcc_lo
	v_fmac_f32_e32 v16, 0xcf800000, v8
	v_cndmask_b32_e64 v22, v10, v20, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v7, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v15, vcc_lo
	v_cvt_u32_f32_e32 v15, v8
	v_cvt_u32_f32_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, v9, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v10, s3, v15
	v_mul_hi_u32 v20, s3, v16
	s_subb_u32 s2, 0, s12
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, v13, v11, 0
	v_mul_hi_u32 v23, v13, v21
	v_mul_lo_u32 v25, s2, v16
	v_mad_u64_u32 v[8:9], null, v22, v21, 0
	v_add_nc_u32_e32 v10, v20, v10
	v_mul_lo_u32 v20, s3, v16
	v_add_co_u32 v21, vcc_lo, v23, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v10, v25
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v7, vcc_lo
	v_mad_u64_u32 v[6:7], null, v22, v11, 0
	v_add_co_u32 v8, vcc_lo, v21, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v8, v16, v10
	v_mul_hi_u32 v11, v16, v20
	v_add_co_ci_u32_e32 v23, vcc_lo, v23, v9, vcc_lo
	v_mul_hi_u32 v9, v16, v10
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v7, vcc_lo
	v_mul_lo_u32 v7, v15, v20
	v_mul_hi_u32 v20, v15, v20
	v_add_co_u32 v8, vcc_lo, v11, v8
	v_mul_hi_u32 v11, v15, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_mul_lo_u32 v10, v15, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v20, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	v_mad_u64_u32 v[7:8], null, v4, s14, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v5, vcc_lo, v12, v5
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v16, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, v15, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v15, s31, v5
	v_mul_lo_u32 v11, s30, v11
	v_mad_u64_u32 v[9:10], null, s30, v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v5, s3, v14
	v_mul_hi_u32 v16, s3, v12
	v_add3_u32 v8, v8, v24, v17
	v_sub_co_u32 v20, vcc_lo, v18, v7
	v_add3_u32 v11, v10, v11, v15
	v_mul_lo_u32 v10, s2, v12
	v_sub_co_u32 v15, s0, v4, v9
	v_add_nc_u32_e32 v5, v16, v5
	v_sub_co_ci_u32_e32 v21, vcc_lo, v19, v8, vcc_lo
	v_mul_lo_u32 v8, s3, v12
	v_sub_nc_u32_e32 v7, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v5, v10
	v_sub_co_u32 v17, s1, v15, s30
	s_sub_u32 s2, 0, s6
	v_subrev_co_ci_u32_e64 v16, vcc_lo, s31, v7, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v7, v12, v5
	v_mul_hi_u32 v9, v12, v8
	v_mul_hi_u32 v4, v12, v5
	v_mul_lo_u32 v10, v14, v8
	v_subrev_co_ci_u32_e64 v24, vcc_lo, 0, v16, s1
	v_mul_hi_u32 v8, v14, v8
	v_mul_hi_u32 v26, v14, v5
	v_mul_lo_u32 v5, v14, v5
	v_add_co_u32 v7, vcc_lo, v9, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_cvt_f32_u32_e32 v9, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, v7, v10
	v_cvt_f32_u32_e32 v7, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v7, 0x4f800000, v9
	v_add_co_u32 v4, vcc_lo, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v8, vcc_lo
	v_rcp_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v12, v4
	v_add_co_ci_u32_e32 v12, vcc_lo, v14, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s31, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v14, v18, v9
	v_mad_u64_u32 v[4:5], null, v18, v12, 0
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s30, v17
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, 0x5f7ffffc, v7
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s31, v24
	v_mul_f32_e32 v28, 0x2f800000, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v27, v8, v10, vcc_lo
	v_mad_u64_u32 v[7:8], null, v2, v9, 0
	v_mad_u64_u32 v[9:10], null, v2, v12, 0
	v_trunc_f32_e32 v12, v28
	v_add_co_u32 v4, vcc_lo, v14, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, 0xcf800000, v12
	v_add_co_u32 v4, vcc_lo, v4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo
	v_cvt_u32_f32_e32 v7, v26
	v_cvt_u32_f32_e32 v8, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v4, v9
	v_mul_hi_u32 v12, s2, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v14, s2, v8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v16, vcc_lo, s31, v16, s1
	s_subb_u32 s1, 0, s7
	v_mul_lo_u32 v26, s12, v9
	v_mul_lo_u32 v29, s1, v7
	v_add_nc_u32_e32 v12, v12, v14
	v_mul_lo_u32 v28, s13, v10
	v_mad_u64_u32 v[4:5], null, s13, v9, 0
	v_mul_lo_u32 v30, s2, v7
	v_sub_co_u32 v14, vcc_lo, v17, s30
	v_add_nc_u32_e32 v12, v12, v29
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v6, vcc_lo, v23, v6
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v25, vcc_lo
	v_add3_u32 v5, v5, v28, v26
	v_mul_lo_u32 v25, v7, v12
	v_mul_hi_u32 v26, v7, v30
	v_mul_hi_u32 v28, v7, v12
	v_sub_co_ci_u32_e64 v11, vcc_lo, v3, v11, s0
	v_sub_nc_u32_e32 v3, v2, v5
	v_mul_hi_u32 v31, v8, v12
	v_sub_co_u32 v32, s0, v18, v4
	v_add_co_u32 v25, vcc_lo, v26, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v28, vcc_lo
	v_mul_lo_u32 v28, v8, v30
	v_mul_hi_u32 v30, v8, v30
	v_subrev_co_ci_u32_e64 v3, vcc_lo, s12, v3, s0
	v_mul_lo_u32 v12, v8, v12
	v_mul_lo_u32 v29, s5, v6
	v_mul_lo_u32 v23, s4, v23
	s_add_u32 s14, s14, -1
	v_add_co_u32 v4, vcc_lo, v25, v28
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v30, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v31, vcc_lo
	v_sub_co_u32 v26, vcc_lo, v32, s13
	v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v4, v12
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s12, v28
	s_addc_u32 s15, s15, -1
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v26
	v_mad_u64_u32 v[3:4], null, s4, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s2, v8
	v_mul_hi_u32 v26, s2, v7
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s12, v28
	v_cndmask_b32_e32 v12, v12, v25, vcc_lo
	v_mul_lo_u32 v25, s1, v7
	v_add_co_u32 v28, vcc_lo, v9, 2
	v_add_co_ci_u32_e32 v30, vcc_lo, 0, v10, vcc_lo
	v_add_nc_u32_e32 v6, v26, v6
	v_add_co_u32 v31, vcc_lo, v9, 1
	v_mul_lo_u32 v26, s2, v7
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v10, vcc_lo
	v_sub_co_ci_u32_e64 v2, vcc_lo, v2, v5, s0
	v_add_nc_u32_e32 v6, v6, v25
	v_cmp_ne_u32_e64 s0, 0, v12
	v_cmp_eq_u32_e64 s2, s31, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s12, v2
	v_mul_hi_u32 v25, v7, v26
	v_mul_lo_u32 v12, v7, v6
	v_cndmask_b32_e64 v5, v31, v28, s0
	v_mul_hi_u32 v31, v7, v6
	v_cndmask_b32_e64 v28, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v32
	v_mul_lo_u32 v34, v8, v26
	v_mul_hi_u32 v26, v8, v26
	v_cndmask_b32_e64 v32, 0, -1, vcc_lo
	v_add_co_u32 v12, vcc_lo, v25, v12
	v_mul_hi_u32 v25, v8, v6
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v12, v34
	v_mul_lo_u32 v6, v8, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, v31, v26, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s12, v2
	s_mov_b32 s12, 0x9999999a
	s_mov_b32 s13, 0x3fb99999
	v_cndmask_b32_e32 v2, v28, v32, vcc_lo
	v_add_co_u32 v6, vcc_lo, v12, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_add_co_u32 v2, s1, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v8, s1, v8, v12, s1
	v_cndmask_b32_e32 v25, v9, v5, vcc_lo
	v_cndmask_b32_e64 v6, v33, v30, s0
	v_add3_u32 v12, v4, v23, v29
	v_sub_co_u32 v13, s0, v13, v3
	v_mad_u64_u32 v[4:5], null, v25, v8, 0
	v_mul_hi_u32 v23, v25, v2
	v_cndmask_b32_e32 v10, v10, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s30, v15
	v_sub_nc_u32_e32 v28, v22, v12
	v_cmp_le_u32_e64 s1, s31, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[6:7], null, v10, v2, 0
	v_cndmask_b32_e64 v26, 0, -1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v23, v4
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
	v_mad_u64_u32 v[4:5], null, v10, v8, 0
	v_subrev_co_ci_u32_e64 v8, vcc_lo, s5, v28, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v2, v6
	v_add_co_ci_u32_e32 v2, vcc_lo, v23, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
	v_sub_co_u32 v5, vcc_lo, v13, s4
	v_cndmask_b32_e64 v9, 0, -1, s1
	v_subrev_co_ci_u32_e64 v6, s1, 0, v8, vcc_lo
	v_add_co_u32 v4, s1, v2, v4
	v_add_co_ci_u32_e64 v2, s1, 0, v3, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s1, s5, v6
	v_mul_lo_u32 v28, s7, v4
	v_subrev_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v29, s6, v2
	v_cndmask_b32_e64 v7, 0, -1, s1
	v_cmp_le_u32_e64 s1, s4, v5
	v_mad_u64_u32 v[2:3], null, s6, v4, 0
	v_cndmask_b32_e64 v9, v9, v26, s2
	v_cmp_eq_u32_e64 s2, s5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, 0, -1, s1
	v_cmp_ne_u32_e64 s1, 0, v27
	v_add3_u32 v3, v3, v29, v28
	v_cndmask_b32_e64 v7, v7, v23, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v24, v16, s1
	v_sub_co_u32 v16, vcc_lo, v5, s4
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_sub_co_u32 v2, s2, v25, v2
	v_cndmask_b32_e32 v9, v11, v4, vcc_lo
	v_sub_nc_u32_e32 v11, v10, v3
	v_cndmask_b32_e64 v4, v17, v14, s1
	v_cmp_ne_u32_e64 s1, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v7, s3, s7, v11, s2
	v_sub_co_ci_u32_e64 v11, s0, v22, v12, s0
	v_cndmask_b32_e64 v6, v6, v8, s1
	v_sub_co_u32 v8, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v12, s3, 0, v7, s0
	v_cmp_le_u32_e64 s3, s5, v11
	v_sub_co_ci_u32_e64 v3, s2, v10, v3, s2
	v_subrev_co_ci_u32_e64 v7, s0, s7, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, -1, s3
	v_cmp_le_u32_e64 s3, s4, v13
	v_cmp_le_u32_e64 s0, s7, v3
	v_cmp_eq_u32_e64 s2, s7, v12
	v_cndmask_b32_e64 v5, v5, v16, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, 0, -1, s3
	v_cmp_le_u32_e64 s3, s7, v12
	v_cndmask_b32_e64 v22, 0, -1, s3
	v_cmp_le_u32_e64 s3, s6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, -1, s3
	v_cmp_eq_u32_e64 s3, s5, v11
	v_cndmask_b32_e64 v10, v22, v23, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v14, v17, s3
	v_cndmask_b32_e64 v17, 0, -1, s0
	v_cmp_le_u32_e64 s0, s6, v2
	v_cmp_ne_u32_e64 s1, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, 0, -1, s0
	v_sub_co_u32 v23, s0, v8, s6
	v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
	v_cmp_eq_u32_e64 s0, s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v17, v22, s0
	v_cmp_ne_u32_e64 s0, 0, v10
	v_cmp_ne_u32_e64 s2, 0, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v12, v7, s0
	v_cndmask_b32_e64 v12, v8, v23, s0
	v_cndmask_b32_e32 v8, v15, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, -1
	v_mov_b32_e32 v22, 0
	v_cndmask_b32_e64 v7, v11, v6, s1
	v_cndmask_b32_e64 v6, v13, v5, s1
	v_cndmask_b32_e64 v3, v3, v10, s2
	v_cndmask_b32_e64 v2, v2, v12, s2
	v_mov_b32_e32 v23, 0
	v_add_co_ci_u32_e32 v5, vcc_lo, -1, v1, vcc_lo
.LBB0_1:                                ; %.preheader145
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
                                        ;       Child Loop BB0_3 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	v_dual_mov_b32 v38, v36 :: v_dual_mov_b32 v39, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v25, v23 :: v_dual_mov_b32 v24, v22
	v_dual_mov_b32 v27, v21 :: v_dual_mov_b32 v26, v20
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	s_mov_b32 s37, 0
                                        ; implicit-def: $sgpr36
                                        ; implicit-def: $sgpr38
.LBB0_2:                                ; %.preheader
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_3 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v10, v30 :: v_dual_mov_b32 v11, v31
	v_dual_mov_b32 v12, v26 :: v_dual_mov_b32 v13, v27
	v_dual_mov_b32 v14, v24 :: v_dual_mov_b32 v15, v25
	v_dual_mov_b32 v32, v39 :: v_dual_mov_b32 v33, v38
	s_mov_b32 s39, 0
                                        ; implicit-def: $sgpr42
                                        ; implicit-def: $sgpr40
                                        ; implicit-def: $sgpr43
                                        ; implicit-def: $sgpr44
                                        ; implicit-def: $sgpr41
.LBB0_3:                                ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	s_or_b32 s41, s41, exec_lo
	s_and_not1_b32 s44, s44, exec_lo
	s_or_b32 s43, s43, exec_lo
	s_mov_b32 s45, exec_lo
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $vgpr18_vgpr19
	v_cmpx_gt_u64_e64 s[30:31], v[8:9]
	s_cbranch_execz .LBB0_19
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=3
	v_cvt_f32_u32_e32 v16, s18
	v_cvt_f32_u32_e32 v17, s19
	v_cvt_f32_u32_e32 v26, s22
	v_cvt_f32_u32_e32 v28, s23
	s_sub_u32 s0, 0, s18
	v_cvt_f32_u32_e32 v20, s20
	v_fmac_f32_e32 v16, 0x4f800000, v17
	v_cvt_f32_u32_e32 v21, s21
	v_fmac_f32_e32 v26, 0x4f800000, v28
	s_subb_u32 s1, 0, s19
	v_mul_lo_u32 v22, v12, s25
	v_rcp_f32_e32 v16, v16
	v_fmac_f32_e32 v20, 0x4f800000, v21
	v_rcp_f32_e32 v26, v26
	v_mul_lo_u32 v23, v13, s24
	s_sub_u32 s2, 0, s20
	s_subb_u32 s3, 0, s21
	s_sub_u32 s46, 0, s22
	v_mul_lo_u32 v38, v12, s29
	v_mul_lo_u32 v34, v12, s27
	v_mul_lo_u32 v35, v13, s26
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v18, 0x5f7ffffc, v16 :: v_dual_mul_f32 v39, 0x5f7ffffc, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, 0x2f800000, v18
	v_trunc_f32_e32 v19, v16
	v_mad_u64_u32 v[16:17], null, v12, s24, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, 0xcf800000, v19
	v_cvt_u32_f32_e32 v27, v19
	v_add3_u32 v17, v23, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v30, v18
	v_mul_lo_u32 v24, s0, v27
	v_mad_u64_u32 v[18:19], null, v12, s26, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v25, s0, v30
	v_mul_lo_u32 v21, s1, v30
	v_mul_lo_u32 v28, s0, v30
	v_add3_u32 v19, v35, v19, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, v25, v24
	v_rcp_f32_e32 v25, v20
	v_mul_hi_u32 v29, v30, v28
	v_mul_hi_u32 v26, v27, v28
	v_mul_lo_u32 v28, v27, v28
	v_add_nc_u32_e32 v24, v24, v21
	v_mad_u64_u32 v[20:21], null, v12, s28, v[2:3]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v31, v30, v24
	v_mul_hi_u32 v36, v30, v24
	v_mul_hi_u32 v37, v27, v24
	v_mul_lo_u32 v24, v27, v24
	v_mul_f32_e32 v25, 0x5f7ffffc, v25
	v_add_co_u32 v29, vcc_lo, v29, v31
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, v29, v28
	v_add_co_ci_u32_e32 v26, vcc_lo, v31, v26, vcc_lo
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v37, vcc_lo
	v_mul_f32_e32 v29, 0x2f800000, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v26, v24
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v28, v29
	v_add_co_u32 v24, vcc_lo, v30, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v29, vcc_lo, v27, v26, vcc_lo
	v_fmac_f32_e32 v25, 0xcf800000, v28
	v_mul_f32_e32 v26, 0x2f800000, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v31, s0, v24
	v_mul_lo_u32 v40, s0, v29
	v_cvt_u32_f32_e32 v36, v28
	v_cvt_u32_f32_e32 v37, v25
	v_trunc_f32_e32 v25, v26
	v_mul_lo_u32 v26, s1, v24
	s_subb_u32 s1, 0, s23
	v_mul_lo_u32 v28, s2, v36
	v_mul_hi_u32 v41, s2, v37
	v_add_nc_u32_e32 v31, v31, v40
	v_mul_lo_u32 v40, s0, v24
	v_fmac_f32_e32 v39, 0xcf800000, v25
	v_mul_lo_u32 v22, s2, v37
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v23, v31, v26
	v_cvt_u32_f32_e32 v26, v25
	v_add_nc_u32_e32 v28, v41, v28
	v_mul_lo_u32 v25, s3, v37
	v_mul_hi_u32 v31, v24, v40
	v_mul_lo_u32 v41, v24, v23
	v_mul_hi_u32 v43, v24, v23
	v_mul_hi_u32 v45, v29, v40
	v_mul_lo_u32 v40, v29, v40
	v_mul_hi_u32 v46, v29, v23
	v_mul_lo_u32 v23, v29, v23
	v_mul_hi_u32 v42, v37, v22
	v_mul_hi_u32 v44, v36, v22
	v_add_co_u32 v31, vcc_lo, v31, v41
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v43, vcc_lo
	v_add_nc_u32_e32 v25, v28, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v31, vcc_lo, v31, v40
	v_add_co_ci_u32_e32 v31, vcc_lo, v41, v45, vcc_lo
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v46, vcc_lo
	v_mul_lo_u32 v41, v36, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v31, v23
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v40, vcc_lo
	v_mul_lo_u32 v43, v37, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v28, vcc_lo, v24, v22
	v_add_co_ci_u32_e32 v31, vcc_lo, v29, v23, vcc_lo
	v_mul_hi_u32 v40, v37, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v45, v16, v28
	v_mul_hi_u32 v46, v36, v25
	v_mad_u64_u32 v[22:23], null, v16, v31, 0
	v_mul_lo_u32 v47, v36, v25
	v_mad_u64_u32 v[24:25], null, v17, v28, 0
	v_mad_u64_u32 v[28:29], null, v17, v31, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, v45, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_add_co_u32 v31, vcc_lo, v42, v43
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v40, vcc_lo
	v_add_co_u32 v22, vcc_lo, v22, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v22, vcc_lo, v23, v25, vcc_lo
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v29, vcc_lo
	v_add_co_u32 v24, vcc_lo, v31, v41
	v_add_co_ci_u32_e32 v24, vcc_lo, v40, v44, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v46, vcc_lo
	v_cvt_u32_f32_e32 v31, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v24, v47
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	v_mul_lo_u32 v29, s46, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v37, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, v36, v25, vcc_lo
	v_mul_hi_u32 v39, s46, v31
	v_mul_lo_u32 v40, v13, s28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v41, s2, v24
	v_mul_lo_u32 v42, s2, v25
	v_mul_lo_u32 v43, s1, v31
	v_mul_lo_u32 v44, s46, v31
	v_mul_lo_u32 v34, s2, v24
	v_add_nc_u32_e32 v29, v39, v29
	v_mul_lo_u32 v39, s3, v24
	v_add3_u32 v38, v40, v21, v38
	v_add_nc_u32_e32 v21, v41, v42
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v29, v29, v43
	v_mul_hi_u32 v35, v31, v44
	v_mul_hi_u32 v40, v26, v44
	v_mul_hi_u32 v43, v24, v34
	v_add_nc_u32_e32 v21, v21, v39
	v_mul_lo_u32 v39, v26, v44
	v_mul_hi_u32 v41, v31, v29
	v_mul_lo_u32 v42, v31, v29
	v_mul_hi_u32 v45, v26, v29
	v_mul_lo_u32 v44, v24, v21
	v_mul_hi_u32 v46, v24, v21
	v_mul_lo_u32 v47, v26, v29
	v_mul_hi_u32 v29, v25, v34
	v_mul_lo_u32 v34, v25, v34
	v_mul_hi_u32 v48, v25, v21
	v_mul_lo_u32 v21, v25, v21
	v_add_co_u32 v43, vcc_lo, v43, v44
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v34, vcc_lo, v43, v34
	v_add_co_ci_u32_e32 v29, vcc_lo, v44, v29, vcc_lo
	v_add_co_ci_u32_e32 v34, vcc_lo, 0, v48, vcc_lo
	v_add_co_u32 v42, vcc_lo, v35, v42
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, v29, v21
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v34, vcc_lo
	v_add_co_u32 v28, vcc_lo, v22, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v34, s0, v24, v21
	v_add_co_ci_u32_e64 v25, s0, v25, v29, s0
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v44, v18, v34
	v_mad_u64_u32 v[21:22], null, v18, v25, 0
	v_mul_lo_u32 v43, s19, v28
	v_mad_u64_u32 v[23:24], null, s18, v28, 0
	v_mul_lo_u32 v46, s18, v29
	v_mad_u64_u32 v[28:29], null, v19, v34, 0
	v_add_co_u32 v21, vcc_lo, v44, v21
	v_mad_u64_u32 v[34:35], null, v19, v25, 0
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v21, v28
	v_add3_u32 v24, v24, v46, v43
	v_add_co_ci_u32_e32 v21, vcc_lo, v22, v29, vcc_lo
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v25, vcc_lo, v42, v39
	v_add_co_ci_u32_e32 v25, vcc_lo, v41, v40, vcc_lo
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v45, vcc_lo
	v_sub_nc_u32_e32 v29, v17, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v25, vcc_lo, v25, v47
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
	v_sub_co_u32 v35, vcc_lo, v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v16, s0, s19, v29, vcc_lo
	v_add_co_u32 v23, s0, v31, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v25, s0, v26, v28, s0
	v_sub_co_ci_u32_e32 v40, vcc_lo, v17, v24, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v35
	v_sub_co_u32 v39, s0, v35, s18
	v_mul_hi_u32 v17, s46, v23
	v_mul_lo_u32 v24, s46, v25
	v_cndmask_b32_e64 v41, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v42, vcc_lo, 0, v16, s0
	v_cmp_le_u32_e32 vcc_lo, s18, v39
	v_mul_lo_u32 v28, s1, v23
	v_mul_lo_u32 v43, s46, v23
	v_cmp_eq_u32_e64 s2, s19, v40
	v_add_nc_u32_e32 v17, v17, v24
	v_cndmask_b32_e64 v29, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v24, vcc_lo, s19, v16, s0
	v_cmp_le_u32_e32 vcc_lo, s19, v40
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v16, v17, v28
	v_mul_hi_u32 v17, v23, v43
	v_mul_hi_u32 v47, v25, v43
	v_mul_lo_u32 v43, v25, v43
	v_cndmask_b32_e64 v44, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v42
	v_mul_hi_u32 v45, v23, v16
	v_mul_hi_u32 v48, v25, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v41, v44, v41, s2
	v_cndmask_b32_e64 v28, 0, -1, vcc_lo
	v_add_co_u32 v21, vcc_lo, v21, v34
	v_mul_lo_u32 v34, v23, v16
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_mul_lo_u32 v46, s21, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v22, s20, v22
	v_add_co_u32 v17, vcc_lo, v17, v34
	v_add_co_ci_u32_e32 v34, vcc_lo, 0, v45, vcc_lo
	v_mul_lo_u32 v45, v25, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v17, v43
	v_add_co_ci_u32_e32 v34, vcc_lo, v34, v47, vcc_lo
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	v_mad_u64_u32 v[16:17], null, s20, v21, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v34, v45
	v_add_co_ci_u32_e32 v34, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v23, v21
	v_add_co_ci_u32_e32 v25, vcc_lo, v25, v34, vcc_lo
	v_sub_co_u32 v34, vcc_lo, v39, s18
	v_add3_u32 v46, v17, v22, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v17, v20, v43
	v_mad_u64_u32 v[21:22], null, v20, v25, 0
	v_subrev_co_ci_u32_e32 v45, vcc_lo, 0, v24, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s19, v42
	v_mad_u64_u32 v[23:24], null, v38, v43, 0
	v_sub_nc_u32_e32 v48, v19, v46
	v_sub_co_u32 v18, s0, v18, v16
	v_cndmask_b32_e32 v47, v28, v29, vcc_lo
	v_add_co_u32 v17, vcc_lo, v17, v21
	v_mad_u64_u32 v[28:29], null, v38, v25, 0
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v22, vcc_lo
	v_subrev_co_ci_u32_e64 v22, vcc_lo, s21, v48, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v17, v23
	v_add_co_ci_u32_e32 v16, vcc_lo, v21, v24, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v29, vcc_lo
	v_sub_co_u32 v21, vcc_lo, v18, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v24, s1, 0, v22, vcc_lo
	v_add_co_u32 v23, s1, v16, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v16, s1, 0, v17, s1
	v_cmp_le_u32_e64 s1, s21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v29, s23, v23
	v_cmp_eq_u32_e64 s2, s21, v24
	v_mul_lo_u32 v43, s22, v16
	v_mad_u64_u32 v[16:17], null, s22, v23, 0
	v_cndmask_b32_e64 v25, 0, -1, s1
	v_cmp_le_u32_e64 s1, s20, v21
	v_subrev_co_ci_u32_e32 v22, vcc_lo, s21, v22, vcc_lo
	v_sub_co_ci_u32_e64 v19, s0, v19, v46, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, 0, -1, s1
	v_cmp_ne_u32_e64 s1, 0, v47
	v_add3_u32 v17, v17, v43, v29
	v_cndmask_b32_e64 v25, v25, v28, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v39, v34, s1
	v_sub_nc_u32_e32 v34, v38, v17
	v_sub_co_u32 v28, vcc_lo, v21, s20
	v_cndmask_b32_e64 v23, v42, v45, s1
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_cmp_ne_u32_e64 s1, 0, v25
	v_sub_co_u32 v16, s2, v20, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v20, s3, s23, v34, s2
	v_cndmask_b32_e64 v24, v24, v22, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v22, s0, v16, s22
	v_subrev_co_ci_u32_e64 v25, s3, 0, v20, s0
	v_cmp_le_u32_e64 s3, s21, v19
	v_cmp_ne_u32_e32 vcc_lo, 0, v41
	v_sub_co_ci_u32_e64 v17, s2, v38, v17, s2
	v_subrev_co_ci_u32_e64 v20, s0, s23, v20, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v34, 0, -1, s3
	v_cmp_le_u32_e64 s3, s20, v18
	v_cndmask_b32_e32 v23, v40, v23, vcc_lo
	v_cmp_le_u32_e64 s0, s23, v17
	v_cmp_eq_u32_e64 s2, s23, v25
	v_cndmask_b32_e64 v21, v21, v28, s1
	v_cndmask_b32_e64 v39, 0, -1, s3
	v_cmp_le_u32_e64 s3, s23, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v40, 0, -1, s3
	v_cmp_le_u32_e64 s3, s22, v22
	v_cndmask_b32_e64 v41, 0, -1, s3
	v_cmp_eq_u32_e64 s3, s21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v38, v40, v41, s2
	v_cndmask_b32_e64 v34, v34, v39, s3
	v_cndmask_b32_e64 v39, 0, -1, s0
	v_cmp_le_u32_e64 s0, s22, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s1, 0, v34
	v_mov_b32_e32 v34, v32
	v_cndmask_b32_e64 v40, 0, -1, s0
	v_sub_co_u32 v41, s0, v22, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v20, s0, 0, v20, s0
	v_cmp_eq_u32_e64 s0, s23, v17
	v_cndmask_b32_e64 v39, v39, v40, s0
	v_cmp_ne_u32_e64 s0, 0, v38
	v_cndmask_b32_e64 v40, v19, v24, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s2, 0, v39
	v_cndmask_b32_e64 v20, v25, v20, s0
	v_cndmask_b32_e64 v25, v22, v41, s0
	v_cndmask_b32_e32 v22, v35, v29, vcc_lo
	v_cndmask_b32_e64 v41, v18, v21, s1
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e64 v38, v17, v20, s2
	v_cndmask_b32_e64 v39, v16, v25, s2
	v_cmpx_lt_u64_e64 v[14:15], v[0:1]
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=3
	v_mul_lo_u32 v20, v40, s18
	v_mul_lo_u32 v21, v41, s19
	v_mad_u64_u32 v[16:17], null, v41, s18, 0
	v_mul_lo_u32 v24, v38, s33
	v_mul_lo_u32 v25, v39, s34
	v_mad_u64_u32 v[18:19], null, v39, s33, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v17, v17, v21, v20
	v_lshlrev_b64 v[20:21], 2, v[22:23]
	v_add3_u32 v19, v19, v25, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v20, vcc_lo, s10, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v21, vcc_lo, s11, v21, vcc_lo
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v16, vcc_lo, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, v21, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, v16, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, v17, v19, vcc_lo
	global_load_b32 v34, v[16:17], off
	s_waitcnt vmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_6:                                ;   in Loop: Header=BB0_3 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v19, v15
	v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v35, v33 :: v_dual_mov_b32 v18, v14
	s_mov_b32 s3, -1
	s_mov_b32 s2, -1
	s_mov_b32 s49, -1
	s_mov_b32 s46, exec_lo
                                        ; implicit-def: $sgpr47
	v_cmpx_gt_u64_e64 s[14:15], v[12:13]
	s_cbranch_execz .LBB0_16
; %bb.7:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=3
	v_mov_b32_e32 v19, v15
	v_mov_b32_e32 v21, v13
	v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v16, v10
	v_dual_mov_b32 v35, v33 :: v_dual_mov_b32 v18, v14
	v_mov_b32_e32 v20, v12
	s_mov_b32 s49, 0
	s_mov_b32 s47, 0
                                        ; implicit-def: $sgpr48
                                        ; implicit-def: $sgpr50
                                        ; implicit-def: $sgpr51
                                        ; implicit-def: $sgpr52
.LBB0_8:                                ; %.lr.ph
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ;       Parent Loop BB0_3 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e32 vcc_lo, v[18:19], v[4:5]
	v_cmp_gt_u64_e64 s0, s[8:9], v[16:17]
	s_or_b32 s52, s52, exec_lo
	s_or_b32 s51, s51, exec_lo
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s53, s0
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=4
	s_sub_u32 s0, 0, s18
	s_subb_u32 s1, 0, s19
	v_mul_hi_u32 v24, s0, v30
	v_mul_lo_u32 v25, s0, v27
	v_mul_lo_u32 v28, s1, v30
	s_sub_u32 s2, 0, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v45, s2, v37
	v_add_nc_u32_e32 v24, v24, v25
	v_mul_lo_u32 v25, s0, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v48, v37, v45
	v_add_nc_u32_e32 v24, v24, v28
	v_mul_hi_u32 v50, v36, v45
	v_mul_lo_u32 v45, v36, v45
	v_mul_hi_u32 v28, v30, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v29, v30, v24
	v_mul_hi_u32 v42, v30, v24
	v_mul_hi_u32 v43, v27, v25
	v_mul_lo_u32 v25, v27, v25
	v_mul_hi_u32 v44, v27, v24
	v_mul_lo_u32 v24, v27, v24
	v_add_co_u32 v28, vcc_lo, v28, v29
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, v28, v25
	v_add_co_ci_u32_e32 v25, vcc_lo, v29, v43, vcc_lo
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v44, vcc_lo
	v_mul_lo_u32 v44, s2, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v25, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, v30, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, v27, v25, vcc_lo
	v_add_co_u32 v42, vcc_lo, v22, s24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v28, s0, v24
	v_mul_lo_u32 v29, s0, v25
	v_mul_lo_u32 v22, s1, v24
	v_add_co_ci_u32_e32 v43, vcc_lo, s25, v23, vcc_lo
	v_mul_hi_u32 v23, s2, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, v28, v29
	v_mul_lo_u32 v29, s0, v24
	s_subb_u32 s0, 0, s21
	s_sub_u32 s54, 0, s22
	v_add_nc_u32_e32 v23, v23, v44
	v_add_nc_u32_e32 v22, v28, v22
	v_mul_lo_u32 v28, s0, v37
	v_mul_hi_u32 v46, s54, v31
	s_subb_u32 s55, 0, s23
	v_mul_hi_u32 v44, v24, v29
	v_mul_lo_u32 v47, v24, v22
	v_mul_hi_u32 v49, v24, v22
	v_mul_hi_u32 v51, v25, v29
	v_mul_lo_u32 v29, v25, v29
	v_mul_hi_u32 v52, v25, v22
	v_mul_lo_u32 v22, v25, v22
	v_add_nc_u32_e32 v28, v23, v28
	v_add_co_u32 v44, vcc_lo, v44, v47
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v49, v37, v28
	v_add_co_u32 v29, vcc_lo, v44, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v29, vcc_lo, v47, v51, vcc_lo
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v52, vcc_lo
	v_mul_lo_u32 v51, v37, v28
	v_add_co_u32 v22, vcc_lo, v29, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v44, vcc_lo
	v_mul_hi_u32 v53, v36, v28
	v_add_co_u32 v44, vcc_lo, v24, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v47, vcc_lo, v25, v29, vcc_lo
	v_mul_lo_u32 v54, v36, v28
	v_mul_hi_u32 v52, v42, v44
	v_mad_u64_u32 v[24:25], null, v43, v44, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, v42, v47, 0
	v_mad_u64_u32 v[28:29], null, v43, v47, 0
	v_add_co_u32 v22, vcc_lo, v52, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_add_co_u32 v44, vcc_lo, v48, v51
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v49, vcc_lo
	v_add_co_u32 v22, vcc_lo, v22, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v22, vcc_lo, v23, v25, vcc_lo
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v29, vcc_lo
	v_add_co_u32 v24, vcc_lo, v44, v45
	v_add_co_ci_u32_e32 v24, vcc_lo, v47, v50, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v53, vcc_lo
	v_mul_lo_u32 v29, s54, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v24, v54
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	v_mul_lo_u32 v45, s55, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v37, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, v36, v25, vcc_lo
	v_add_nc_u32_e32 v29, v46, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v46, s2, v24
	v_add_co_u32 v48, vcc_lo, v41, s26
	v_mul_lo_u32 v47, s2, v25
	v_add_co_ci_u32_e32 v49, vcc_lo, s27, v40, vcc_lo
	v_mul_lo_u32 v40, s0, v24
	v_add_co_u32 v28, vcc_lo, v22, v28
	v_mul_lo_u32 v44, s54, v31
	v_add_nc_u32_e32 v45, v29, v45
	v_add_nc_u32_e32 v46, v46, v47
	v_mul_lo_u32 v47, s2, v24
	v_mul_lo_u32 v52, s19, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v51, v31, v45
	v_add_nc_u32_e32 v40, v46, v40
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v23, vcc_lo
	v_mad_u64_u32 v[22:23], null, s18, v28, 0
	v_mul_hi_u32 v53, v24, v47
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v54, v24, v40
	v_mul_hi_u32 v28, v24, v40
	v_mul_hi_u32 v55, v25, v47
	v_mul_lo_u32 v47, v25, v47
	v_mul_hi_u32 v56, v25, v40
	v_mul_lo_u32 v40, v25, v40
	v_mul_lo_u32 v46, s18, v46
	v_mul_hi_u32 v29, v31, v44
	v_add_co_u32 v53, vcc_lo, v53, v54
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
	v_mul_hi_u32 v41, v31, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v47, vcc_lo, v53, v47
	v_add_co_ci_u32_e32 v28, vcc_lo, v28, v55, vcc_lo
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v56, vcc_lo
	v_add3_u32 v46, v23, v46, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v28, vcc_lo, v28, v40
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v47, vcc_lo
	v_sub_co_u32 v42, s0, v42, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v47, vcc_lo, v24, v28
	v_add_co_ci_u32_e32 v25, vcc_lo, v25, v40, vcc_lo
	v_sub_nc_u32_e32 v28, v43, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v54, v48, v47
	v_add_co_u32 v51, vcc_lo, v29, v51
	v_mad_u64_u32 v[23:24], null, v48, v25, 0
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v41, vcc_lo
	v_subrev_co_ci_u32_e64 v22, vcc_lo, s19, v28, s0
	v_mad_u64_u32 v[28:29], null, v49, v47, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v23, vcc_lo, v54, v23
	v_mad_u64_u32 v[40:41], null, v49, v25, 0
	v_mul_hi_u32 v50, v26, v44
	v_mul_lo_u32 v44, v26, v44
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
	v_sub_co_u32 v47, s1, v42, s18
	s_delay_alu instid0(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v25, vcc_lo, 0, v22, s1
	v_add_co_u32 v23, vcc_lo, v23, v28
	v_mul_hi_u32 v53, v26, v45
	v_add_co_ci_u32_e32 v23, vcc_lo, v24, v29, vcc_lo
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v41, vcc_lo
	v_add_co_u32 v28, vcc_lo, v51, v44
	v_mul_lo_u32 v28, v26, v45
	v_add_co_ci_u32_e32 v29, vcc_lo, v52, v50, vcc_lo
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v53, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v25
	v_cndmask_b32_e64 v44, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v28, vcc_lo, v29, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v41, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v47
	v_cndmask_b32_e64 v41, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v28, vcc_lo, v31, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, v26, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s19, v25
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v45, s54, v28
	v_mul_lo_u32 v51, s55, v28
	v_cndmask_b32_e32 v41, v44, v41, vcc_lo
	v_subrev_co_ci_u32_e64 v22, vcc_lo, s19, v22, s1
	v_mul_lo_u32 v44, s54, v29
	v_sub_co_u32 v50, vcc_lo, v47, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_sub_co_ci_u32_e64 v43, vcc_lo, v43, v46, s0
	v_cmp_ne_u32_e64 s0, 0, v41
	v_add_nc_u32_e32 v44, v45, v44
	v_cmp_le_u32_e32 vcc_lo, s19, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v41, v25, v22, s0
	v_mul_lo_u32 v22, s54, v28
	v_add_nc_u32_e32 v44, v44, v51
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_add_co_u32 v40, vcc_lo, v23, v40
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v24, v28, v44
	v_mul_hi_u32 v45, v28, v22
	v_cmp_le_u32_e32 vcc_lo, s18, v42
	v_mul_hi_u32 v52, v28, v44
	v_mul_lo_u32 v53, s20, v23
	v_mul_lo_u32 v23, v29, v22
	v_mul_hi_u32 v22, v29, v22
	v_cndmask_b32_e64 v46, 0, -1, vcc_lo
	v_mul_lo_u32 v51, s21, v40
	v_add_co_u32 v24, vcc_lo, v45, v24
	v_mul_hi_u32 v45, v29, v44
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v23, vcc_lo, v24, v23
	v_mul_lo_u32 v24, v29, v44
	v_add_co_ci_u32_e32 v44, vcc_lo, v52, v22, vcc_lo
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v45, vcc_lo
	v_mad_u64_u32 v[22:23], null, s20, v40, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v44, v24
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v39, vcc_lo, v39, s28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v28, s1, v28, v24
	v_add_co_ci_u32_e64 v40, s1, v29, v40, s1
	v_cmp_eq_u32_e64 s1, s19, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v44, v39, v28
	v_add_co_ci_u32_e32 v38, vcc_lo, s29, v38, vcc_lo
	v_add3_u32 v45, v23, v53, v51
	v_cndmask_b32_e64 v29, v25, v46, s1
	v_mad_u64_u32 v[24:25], null, v39, v40, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s1, 0, v29
	v_add_co_u32 v44, vcc_lo, v44, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v25, vcc_lo
	v_mad_u64_u32 v[24:25], null, v38, v28, 0
	v_cndmask_b32_e64 v23, v43, v41, s1
	v_sub_nc_u32_e32 v43, v49, v45
	v_mad_u64_u32 v[28:29], null, v38, v40, 0
	v_cndmask_b32_e64 v41, v47, v50, s0
	v_sub_co_u32 v47, s0, v48, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v40, vcc_lo, s21, v43, s0
	v_add_co_u32 v22, vcc_lo, v44, v24
	v_add_co_ci_u32_e32 v22, vcc_lo, v46, v25, vcc_lo
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v29, vcc_lo
	v_sub_co_u32 v29, vcc_lo, v47, s20
	v_subrev_co_ci_u32_e64 v43, s2, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v22, s2, v22, v28
	v_add_co_ci_u32_e64 v24, s2, 0, v24, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s2, s21, v43
	v_mul_lo_u32 v46, s23, v22
	v_subrev_co_ci_u32_e32 v40, vcc_lo, s21, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v48, s22, v24
	v_mad_u64_u32 v[24:25], null, s22, v22, 0
	v_cndmask_b32_e64 v28, 0, -1, s2
	v_cmp_le_u32_e64 s2, s20, v29
	v_cndmask_b32_e64 v22, v42, v41, s1
	v_sub_co_ci_u32_e64 v41, vcc_lo, v49, v45, s0
	v_cmp_eq_u32_e64 s1, s21, v43
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v44, 0, -1, s2
	v_add3_u32 v25, v25, v48, v46
	v_sub_co_u32 v42, vcc_lo, v29, s20
	v_subrev_co_ci_u32_e32 v40, vcc_lo, 0, v40, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v41
	v_cndmask_b32_e64 v28, v28, v44, s1
	v_sub_nc_u32_e32 v44, v38, v25
	v_cmp_eq_u32_e64 s2, s21, v41
	v_cndmask_b32_e64 v45, 0, -1, vcc_lo
	v_sub_co_u32 v39, vcc_lo, v39, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e64 v24, s0, s23, v44, vcc_lo
	v_cmp_le_u32_e64 s0, s20, v47
	v_sub_co_ci_u32_e32 v38, vcc_lo, v38, v25, vcc_lo
	v_cndmask_b32_e64 v44, 0, -1, s0
	v_sub_co_u32 v46, s0, v39, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v48, s1, 0, v24, s0
	v_cmp_ne_u32_e64 s1, 0, v28
	v_subrev_co_ci_u32_e64 v24, s0, s23, v24, s0
	v_cmp_eq_u32_e64 s0, s23, v38
	v_cndmask_b32_e64 v28, v43, v40, s1
	v_cndmask_b32_e64 v40, v45, v44, s2
	v_cmp_le_u32_e64 s2, s23, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v43, 0, -1, s2
	v_cmp_le_u32_e64 s2, s22, v46
	v_cndmask_b32_e64 v44, 0, -1, s2
	v_cmp_ne_u32_e64 s2, 0, v40
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v40, v41, v28, s2
	v_cndmask_b32_e64 v28, v29, v42, s1
	v_sub_co_u32 v42, vcc_lo, v46, s22
	v_subrev_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v38
	v_cmp_eq_u32_e64 s1, s23, v48
	v_cndmask_b32_e64 v41, v47, v28, s2
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v43, v44, s1
	v_mul_lo_u32 v44, v40, s18
	v_cndmask_b32_e64 v43, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v29, v25, v43, s0
	v_cndmask_b32_e32 v28, v48, v24, vcc_lo
	v_mad_u64_u32 v[24:25], null, v41, s18, v[22:23]
	v_mul_lo_u32 v43, v41, s19
	v_cndmask_b32_e32 v42, v46, v42, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v29
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v38, v38, v28 :: v_dual_cndmask_b32 v39, v39, v42
	v_add3_u32 v25, v44, v25, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[28:29], null, v39, s33, v[24:25]
	v_mul_lo_u32 v24, v39, s34
	v_mul_lo_u32 v25, v38, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v29, v25, v29, v24
	v_lshlrev_b64 v[24:25], 2, v[28:29]
	v_cmpx_lt_u64_e64 v[18:19], v[4:5]
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v28, vcc_lo, s10, v24
	v_add_co_ci_u32_e32 v29, vcc_lo, s11, v25, vcc_lo
	global_load_b32 v35, v[28:29], off
	s_waitcnt vmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_11:                               ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f64_f32_e32 v[28:29], v34
	v_add_co_u32 v18, vcc_lo, v18, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v24, vcc_lo, s16, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s17, v25, vcc_lo
	s_mov_b32 s0, -1
	s_mov_b32 s1, -1
	s_mov_b32 s2, exec_lo
	v_add_f64 v[28:29], v[28:29], s[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v28, v[28:29]
	global_store_b32 v[24:25], v28, off
	v_cmpx_le_u64_e64 v[18:19], v[4:5]
; %bb.12:                               ;   in Loop: Header=BB0_8 Depth=4
	v_add_co_u32 v20, vcc_lo, v20, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_cmp_lt_u64_e32 vcc_lo, v[18:19], v[0:1]
	v_add_co_u32 v16, s0, v16, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s0, 0, v17, s0
	s_xor_b32 s1, exec_lo, -1
	v_cndmask_b32_e32 v34, v34, v35, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[14:15], v[20:21]
	s_or_not1_b32 s0, vcc_lo, exec_lo
; %bb.13:                               ; %Flow337
                                        ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s52, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_and_not1_b32 s51, s51, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s52, s2, s1
	s_or_b32 s51, s51, s0
.LBB0_14:                               ; %Flow
                                        ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s53
	s_xor_b32 s0, s52, -1
	s_and_b32 s1, exec_lo, s51
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s47, s1, s47
	s_and_not1_b32 s1, s50, exec_lo
	s_and_b32 s2, s49, exec_lo
	s_and_not1_b32 s48, s48, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s50, s1, s2
	s_or_b32 s48, s48, s0
	s_and_not1_b32 exec_lo, exec_lo, s47
	s_cbranch_execnz .LBB0_8
; %bb.15:                               ; %loop.exit.guard335
                                        ;   in Loop: Header=BB0_3 Depth=3
	s_or_b32 exec_lo, exec_lo, s47
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s49, s50, exec_lo
	s_and_b32 s47, s50, exec_lo
	s_or_not1_b32 s2, s48, exec_lo
.LBB0_16:                               ; %Flow339
                                        ;   in Loop: Header=BB0_3 Depth=3
	s_or_b32 exec_lo, exec_lo, s46
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr0_sgpr1
	s_and_saveexec_b32 s46, s2
	s_cbranch_execz .LBB0_18
; %bb.17:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=3
	s_sub_u32 s0, 0, s18
	s_subb_u32 s1, 0, s19
	v_mul_hi_u32 v20, s0, v30
	v_mul_lo_u32 v21, s0, v27
	v_mul_lo_u32 v24, s1, v30
	s_sub_u32 s2, 0, s20
	s_subb_u32 s3, 0, s21
	s_sub_u32 s48, 0, s22
	s_subb_u32 s50, 0, s23
	v_mul_hi_u32 v43, s48, v31
	v_mul_lo_u32 v44, s48, v26
	v_add_nc_u32_e32 v20, v20, v21
	v_mul_lo_u32 v21, s0, v30
	s_and_not1_b32 s49, s49, exec_lo
	s_and_not1_b32 s47, s47, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, v20, v24
	v_mul_hi_u32 v24, v30, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v25, v30, v20
	v_mul_hi_u32 v28, v30, v20
	v_mul_hi_u32 v29, v27, v21
	v_mul_lo_u32 v21, v27, v21
	v_mul_hi_u32 v42, v27, v20
	v_mul_lo_u32 v20, v27, v20
	v_add_co_u32 v24, vcc_lo, v24, v25
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, v24, v21
	v_add_co_ci_u32_e32 v21, vcc_lo, v25, v29, vcc_lo
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v42, vcc_lo
	v_mul_lo_u32 v29, s2, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v21, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v24, vcc_lo
	v_mul_lo_u32 v42, s3, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v30, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, v27, v21, vcc_lo
	v_add_co_u32 v27, vcc_lo, v22, s24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v24, s0, v20
	v_mul_lo_u32 v25, s0, v21
	v_add_co_ci_u32_e32 v28, vcc_lo, s25, v23, vcc_lo
	v_mul_lo_u32 v23, s1, v20
	v_mul_hi_u32 v22, s2, v37
	v_mul_lo_u32 v30, s2, v37
	v_add_nc_u32_e32 v24, v24, v25
	v_mul_lo_u32 v25, s0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v22, v22, v29
	v_add_nc_u32_e32 v23, v24, v23
	v_mul_hi_u32 v45, v37, v30
	v_mul_hi_u32 v47, v36, v30
	v_mul_hi_u32 v24, v20, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v29, v20, v23
	v_mul_hi_u32 v46, v20, v23
	v_mul_hi_u32 v48, v21, v25
	v_mul_lo_u32 v25, v21, v25
	v_mul_hi_u32 v49, v21, v23
	v_mul_lo_u32 v23, v21, v23
	v_add_nc_u32_e32 v22, v22, v42
	v_add_co_u32 v24, vcc_lo, v24, v29
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v46, v37, v22
	v_add_co_u32 v24, vcc_lo, v24, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v24, vcc_lo, v29, v48, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v49, vcc_lo
	v_mul_lo_u32 v29, v36, v30
	v_add_co_u32 v23, vcc_lo, v24, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v25, vcc_lo
	v_mul_hi_u32 v42, v37, v22
	v_add_co_u32 v25, vcc_lo, v20, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, v21, v24, vcc_lo
	v_mul_hi_u32 v49, v36, v22
	v_mul_hi_u32 v48, v27, v25
	v_mul_lo_u32 v50, v36, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, v27, v30, 0
	v_mad_u64_u32 v[22:23], null, v28, v25, 0
	v_mad_u64_u32 v[24:25], null, v28, v30, 0
	v_add_co_u32 v20, vcc_lo, v48, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v30, vcc_lo, v45, v46
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v42, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v20, vcc_lo, v21, v23, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v25, vcc_lo
	v_add_co_u32 v22, vcc_lo, v30, v29
	v_add_co_ci_u32_e32 v22, vcc_lo, v42, v47, vcc_lo
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v49, vcc_lo
	v_mul_lo_u32 v29, s50, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v22, v50
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_mul_lo_u32 v25, s48, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v37, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, v36, v23, vcc_lo
	v_add_co_u32 v30, vcc_lo, v41, s26
	v_add_nc_u32_e32 v37, v43, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v41, s2, v22
	v_mul_lo_u32 v42, s2, v23
	v_add_co_ci_u32_e32 v36, vcc_lo, s27, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v29, v37, v29
	v_mul_lo_u32 v37, s3, v22
	v_add_co_u32 v24, vcc_lo, v20, v24
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v21, vcc_lo
	v_add_nc_u32_e32 v41, v41, v42
	v_mul_lo_u32 v42, s2, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v44, s19, v24
	v_mad_u64_u32 v[20:21], null, s18, v24, 0
	v_add_nc_u32_e32 v37, v41, v37
	v_mul_lo_u32 v24, s18, v43
	v_mul_hi_u32 v40, v31, v25
	v_mul_hi_u32 v41, v26, v25
	v_mul_lo_u32 v43, v26, v25
	v_mul_hi_u32 v25, v22, v42
	v_mul_lo_u32 v46, v22, v37
	v_mul_hi_u32 v48, v22, v37
	v_sub_co_u32 v27, s0, v27, v20
	v_add3_u32 v44, v21, v24, v44
	v_mul_lo_u32 v24, v23, v42
	v_mul_hi_u32 v21, v23, v42
	v_mul_hi_u32 v42, v23, v37
	v_add_co_u32 v25, vcc_lo, v25, v46
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v48, vcc_lo
	v_mul_lo_u32 v37, v23, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, v25, v24
	v_add_co_ci_u32_e32 v21, vcc_lo, v46, v21, vcc_lo
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v42, vcc_lo
	v_sub_nc_u32_e32 v25, v28, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v21, v37
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v37, vcc_lo, s19, v25, s0
	v_add_co_u32 v25, vcc_lo, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, v23, v24, vcc_lo
	v_sub_co_u32 v46, s1, v27, s18
	v_mul_hi_u32 v49, v30, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[20:21], null, v30, v42, 0
	v_subrev_co_ci_u32_e64 v48, vcc_lo, 0, v37, s1
	v_cmp_le_u32_e32 vcc_lo, s18, v46
	v_mad_u64_u32 v[22:23], null, v36, v25, 0
	v_mad_u64_u32 v[24:25], null, v36, v42, 0
	v_cndmask_b32_e64 v50, 0, -1, vcc_lo
	v_add_co_u32 v20, vcc_lo, v49, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v48
	v_mul_lo_u32 v47, v31, v29
	v_mul_hi_u32 v45, v31, v29
	v_cndmask_b32_e64 v42, 0, -1, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, v22
	v_add_co_ci_u32_e32 v20, vcc_lo, v21, v23, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v25, vcc_lo
	v_add_co_u32 v22, vcc_lo, v40, v47
	v_mul_hi_u32 v23, v26, v29
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v22, v43
	v_mul_lo_u32 v22, v26, v29
	v_add_co_ci_u32_e32 v25, vcc_lo, v25, v41, vcc_lo
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s19, v48
	v_cndmask_b32_e32 v29, v42, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, v25, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	v_subrev_co_ci_u32_e64 v25, vcc_lo, s19, v37, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v31, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, v26, v23, vcc_lo
	v_sub_co_u32 v26, vcc_lo, v46, s18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	v_mul_lo_u32 v31, s48, v23
	v_mul_hi_u32 v37, s48, v22
	v_cmp_ne_u32_e64 s1, 0, v29
	v_add_co_u32 v24, vcc_lo, v20, v24
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v48, v25, s1
	v_mul_lo_u32 v25, s50, v22
	v_add_nc_u32_e32 v21, v37, v31
	v_mul_lo_u32 v37, s48, v22
	v_sub_co_ci_u32_e64 v28, vcc_lo, v28, v44, s0
	v_mul_lo_u32 v31, s21, v24
	v_mul_lo_u32 v40, s20, v20
	v_cndmask_b32_e64 v26, v46, v26, s1
	v_add_nc_u32_e32 v25, v21, v25
	v_mad_u64_u32 v[20:21], null, s20, v24, 0
	v_cmp_le_u32_e32 vcc_lo, s19, v28
	v_mul_hi_u32 v42, v22, v37
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v41, v22, v25
	v_mul_hi_u32 v44, v22, v25
	v_cndmask_b32_e64 v24, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v27
	v_add3_u32 v31, v21, v40, v31
	v_mul_lo_u32 v40, v23, v37
	v_mul_hi_u32 v37, v23, v37
	v_mul_hi_u32 v21, v23, v25
	v_cndmask_b32_e64 v43, 0, -1, vcc_lo
	v_add_co_u32 v41, vcc_lo, v42, v41
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v44, vcc_lo
	v_mul_lo_u32 v25, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, v41, v40
	v_sub_nc_u32_e32 v44, v36, v31
	v_add_co_ci_u32_e32 v37, vcc_lo, v42, v37, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_sub_co_u32 v30, s0, v30, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v40, vcc_lo, s21, v44, s0
	v_add_co_u32 v20, vcc_lo, v37, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v37, vcc_lo, v39, s28
	v_add_co_u32 v25, s2, v22, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v39, s2, v23, v21, s2
	v_sub_co_u32 v41, s2, v30, s20
	v_add_co_ci_u32_e32 v38, vcc_lo, s29, v38, vcc_lo
	v_subrev_co_ci_u32_e64 v42, s3, 0, v40, s2
	v_cmp_eq_u32_e32 vcc_lo, s19, v28
	v_mad_u64_u32 v[20:21], null, v37, v39, 0
	v_mul_hi_u32 v44, v37, v25
	v_mad_u64_u32 v[22:23], null, v38, v25, 0
	v_cndmask_b32_e32 v43, v24, v43, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v42
	v_mad_u64_u32 v[24:25], null, v38, v39, 0
	v_cndmask_b32_e64 v45, 0, -1, vcc_lo
	v_add_co_u32 v20, vcc_lo, v44, v20
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v20, v22
	v_add_co_ci_u32_e32 v22, vcc_lo, v39, v23, vcc_lo
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v25, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v41
	v_cvt_f64_f32_e32 v[20:21], v34
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_add_co_u32 v24, vcc_lo, v22, v24
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v23, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s21, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v39, s22, v22
	v_mad_u64_u32 v[22:23], null, s22, v24, 0
	v_cndmask_b32_e32 v25, v45, v25, vcc_lo
	v_sub_co_ci_u32_e64 v31, vcc_lo, v36, v31, s0
	v_mul_lo_u32 v36, s23, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s21, v31
	v_cmp_eq_u32_e64 s0, s21, v31
	v_cndmask_b32_e64 v24, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v30
	v_add3_u32 v23, v23, v39, v36
	v_cndmask_b32_e64 v44, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v40, vcc_lo, s21, v40, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v39, v38, v23
	v_sub_co_u32 v45, vcc_lo, v41, s20
	v_cndmask_b32_e64 v24, v24, v44, s0
	v_sub_co_u32 v37, s0, v37, v22
	v_subrev_co_ci_u32_e32 v36, vcc_lo, 0, v40, vcc_lo
	v_subrev_co_ci_u32_e64 v22, s1, s23, v39, s0
	v_cmp_ne_u32_e32 vcc_lo, 0, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v39, s1, v37, s22
	v_subrev_co_ci_u32_e64 v40, s2, 0, v22, s1
	v_cndmask_b32_e32 v25, v41, v45, vcc_lo
	v_cmp_ne_u32_e64 s2, 0, v24
	v_add_f64 v[20:21], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, v30, v25, s2
	v_sub_co_ci_u32_e64 v25, s0, v38, v23, s0
	v_cmp_le_u32_e64 s0, s23, v40
	v_cndmask_b32_e64 v23, 0, -1, s0
	v_cmp_le_u32_e64 s0, s22, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, 0, -1, s0
	v_cmp_le_u32_e64 s0, s23, v25
	v_cndmask_b32_e64 v38, 0, -1, s0
	v_cmp_le_u32_e64 s0, s22, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v41, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s23, v40
	v_cndmask_b32_e64 v23, v23, v30, s0
	v_subrev_co_ci_u32_e64 v22, s0, s23, v22, s1
	v_cmp_eq_u32_e64 s0, s23, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v38, v41, s0
	v_sub_co_u32 v38, s0, v39, s22
	v_subrev_co_ci_u32_e64 v22, s0, 0, v22, s0
	v_cmp_ne_u32_e64 s0, 0, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e64 s1, 0, v30
	v_cndmask_b32_e32 v23, v42, v36, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v43
	v_cndmask_b32_e64 v30, v40, v22, s0
	v_cndmask_b32_e64 v36, v39, v38, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v23, s2
	v_dual_cndmask_b32 v23, v28, v29 :: v_dual_cndmask_b32 v22, v27, v26
	v_cndmask_b32_e64 v25, v25, v30, s1
	v_cvt_f32_f64_e32 v30, v[20:21]
	v_cndmask_b32_e64 v26, v37, v36, s1
	v_mul_lo_u32 v27, v31, s18
	v_mul_lo_u32 v28, v24, s19
	v_mad_u64_u32 v[20:21], null, v24, s18, 0
	v_mul_lo_u32 v29, v25, s33
	v_mul_lo_u32 v31, v26, s34
	v_mad_u64_u32 v[24:25], null, v26, s33, 0
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_add_co_u32 v8, vcc_lo, v8, 1
	v_add3_u32 v21, v21, v28, v27
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_add3_u32 v25, v25, v31, v29
	v_add_co_u32 v26, vcc_lo, s16, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v23, vcc_lo
	v_add_co_u32 v28, vcc_lo, v18, 1
	v_lshlrev_b64 v[22:23], 2, v[24:25]
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v18, vcc_lo, v26, v20
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u64_e32 vcc_lo, v[28:29], v[4:5]
	v_add_co_u32 v18, s0, v18, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s0, v19, v23, s0
	s_mov_b64 s[0:1], 0
	s_or_not1_b32 s3, vcc_lo, exec_lo
	global_store_b32 v[18:19], v30, off
.LBB0_18:                               ; %Flow340
                                        ;   in Loop: Header=BB0_3 Depth=3
	s_or_b32 exec_lo, exec_lo, s46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s41, exec_lo
	s_and_b32 s41, s49, exec_lo
	v_dual_mov_b32 v36, v33 :: v_dual_mov_b32 v37, v32
	v_dual_mov_b32 v23, v15 :: v_dual_mov_b32 v22, v14
	v_dual_mov_b32 v21, v13 :: v_dual_mov_b32 v20, v12
	v_dual_mov_b32 v19, v11 :: v_dual_mov_b32 v18, v10
	s_or_b32 s41, s2, s41
	s_and_not1_b32 s2, s44, exec_lo
	s_and_b32 s44, s47, exec_lo
	s_and_not1_b32 s43, s43, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s44, s2, s44
	s_or_b32 s43, s43, s3
.LBB0_19:                               ; %Flow338
                                        ;   in Loop: Header=BB0_3 Depth=3
	s_or_b32 exec_lo, exec_lo, s45
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s43
	v_dual_mov_b32 v38, v33 :: v_dual_mov_b32 v39, v32
	v_dual_mov_b32 v25, v15 :: v_dual_mov_b32 v24, v14
	v_dual_mov_b32 v27, v13 :: v_dual_mov_b32 v26, v12
	v_dual_mov_b32 v31, v11 :: v_dual_mov_b32 v30, v10
	s_or_b32 s39, s2, s39
	v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
	v_dual_mov_b32 v10, v16 :: v_dual_mov_b32 v11, v17
	v_dual_mov_b32 v14, v28 :: v_dual_mov_b32 v15, v29
	v_dual_mov_b32 v32, v34 :: v_dual_mov_b32 v33, v35
	s_and_not1_b32 s0, s40, exec_lo
	s_and_b32 s1, s41, exec_lo
	s_and_not1_b32 s2, s42, exec_lo
	s_and_b32 s3, s44, exec_lo
	s_or_b32 s40, s0, s1
	s_or_b32 s42, s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s39
	s_cbranch_execnz .LBB0_3
; %bb.20:                               ; %loop.exit.guard328
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s39
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s38, exec_lo
	s_and_b32 s1, s42, exec_lo
	s_mov_b32 s2, -1
	s_or_b32 s38, s0, s1
                                        ; implicit-def: $sgpr0_sgpr1
	s_and_saveexec_b32 s3, s40
	s_xor_b32 s3, exec_lo, s3
; %bb.21:                               ;   in Loop: Header=BB0_2 Depth=2
	v_add_co_u32 v6, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_dual_mov_b32 v18, v30 :: v_dual_mov_b32 v19, v31
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[6:7]
	v_dual_mov_b32 v22, v24 :: v_dual_mov_b32 v23, v25
	v_dual_mov_b32 v37, v39 :: v_dual_mov_b32 v36, v38
	s_mov_b64 s[0:1], 0
	s_or_b32 s38, s38, exec_lo
	s_or_not1_b32 s2, vcc_lo, exec_lo
; %bb.22:                               ; %Flow342
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
	s_or_b32 s37, s2, s37
	s_and_not1_b32 s0, s36, exec_lo
	s_and_b32 s1, s38, exec_lo
	s_or_b32 s36, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s37
	s_cbranch_execnz .LBB0_2
; %bb.23:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s37
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr0_sgpr1
	s_and_saveexec_b32 s3, s36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.24:                               ;   in Loop: Header=BB0_1 Depth=1
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u64_e32 vcc_lo, s[6:7], v[2:3]
	s_or_not1_b32 s2, vcc_lo, exec_lo
; %bb.25:                               ; %Flow344
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
	s_and_b32 s0, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s35, s0, s35
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_and_not1_b32 exec_lo, exec_lo, s35
	s_cbranch_execnz .LBB0_1
; %bb.26:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6rotatePffS_mmmmmmmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 57
		.amdhsa_next_free_sgpr 56
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6rotatePffS_mmmmmmmmm, .Lfunc_end0-_Z6rotatePffS_mmmmmmmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13484
; NumSgprs: 58
; NumVgprs: 57
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 58
; NumVGPRsForWavesPerEU: 57
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6rotatePffS_mmmmmmmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     58
    .sgpr_spill_count: 0
    .symbol:         _Z6rotatePffS_mmmmmmmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     57
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
