#include "includes.h"

// ERROR CHECKING MACROS //////////////////////////////////////////////////////

__global__ void expPVPath(const int noPaths, const float gr, const int nYears, const float meanP, const float timeStep, const float rrr, float current, float reversion, float jumpProb, const float* brownian, const float* jumpSize, const float* jump, float* result) {

// Get the global index for the matrix
unsigned int idx = blockIdx.x*blockDim.x+threadIdx.x;

if (idx < noPaths) {
// Simulate a forward path
float value = 0;
float curr = current;

for (int ii = 0; ii < nYears; ii++) {
float jumped = (jump[idx+ii] < jumpProb)? 1.0f : 0.0f;

curr += reversion*(meanP - curr)*timeStep + curr*brownian[idx+ii] +
(exp(jumpSize[idx+ii]) - 1)*curr*jumped;
value += pow(1 + gr,ii)*curr/pow((1 + rrr),ii);
}

result[idx] = value;
}
}
	.file	"tmpxft_00331e95_00000000-6_expPVPath.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf
	.type	_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf, @function
_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 68(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 72(%rsp)
	movss	%xmm1, 64(%rsp)
	movss	%xmm2, 60(%rsp)
	movss	%xmm3, 56(%rsp)
	movss	%xmm4, 52(%rsp)
	movss	%xmm5, 48(%rsp)
	movss	%xmm6, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z9expPVPathififfffffPKfS0_S0_Pf(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf, .-_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf
	.globl	_Z9expPVPathififfffffPKfS0_S0_Pf
	.type	_Z9expPVPathififfffffPKfS0_S0_Pf, @function
_Z9expPVPathififfffffPKfS0_S0_Pf:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z9expPVPathififfffffPKfS0_S0_PfififfffffPKfS0_S0_Pf
	.cfi_endproc
.LFE2033:
	.size	_Z9expPVPathififfffffPKfS0_S0_Pf, .-_Z9expPVPathififfffffPKfS0_S0_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9expPVPathififfffffPKfS0_S0_Pf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9expPVPathififfffffPKfS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

// ERROR CHECKING MACROS //////////////////////////////////////////////////////

__global__ void expPVPath(const int noPaths, const float gr, const int nYears, const float meanP, const float timeStep, const float rrr, float current, float reversion, float jumpProb, const float* brownian, const float* jumpSize, const float* jump, float* result) {

// Get the global index for the matrix
unsigned int idx = blockIdx.x*blockDim.x+threadIdx.x;

if (idx < noPaths) {
// Simulate a forward path
float value = 0;
float curr = current;

for (int ii = 0; ii < nYears; ii++) {
float jumped = (jump[idx+ii] < jumpProb)? 1.0f : 0.0f;

curr += reversion*(meanP - curr)*timeStep + curr*brownian[idx+ii] +
(exp(jumpSize[idx+ii]) - 1)*curr*jumped;
value += pow(1 + gr,ii)*curr/pow((1 + rrr),ii);
}

result[idx] = value;
}
}
	.text
	.file	"expPVPath.hip"
	.globl	_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf # -- Begin function _Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf
	.type	_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf,@function
_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf: # @_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	44(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movss	%xmm0, (%rdi)
	leaq	36(%rsp), %r10
	movl	%esi, (%r10)
	leaq	32(%rsp), %rsi
	movss	%xmm1, (%rsi)
	leaq	28(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	24(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	20(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	16(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	12(%rsp), %r13
	movss	%xmm6, (%r13)
	leaq	88(%rsp), %rbp
	movq	%rdx, (%rbp)
	leaq	80(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	72(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	64(%rsp), %r8
	movq	%r9, (%r8)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%r15, 48(%rbx)
	movq	%r12, 56(%rbx)
	movq	%r13, 64(%rbx)
	movq	%rbp, 72(%rbx)
	movq	%rdx, 80(%rbx)
	movq	%rcx, 88(%rbx)
	movq	%r8, 96(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9expPVPathififfffffPKfS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$248, %rsp
	.cfi_adjust_cfa_offset -248
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf, .Lfunc_end0-_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9expPVPathififfffffPKfS0_S0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9expPVPathififfffffPKfS0_S0_Pf,@object # @_Z9expPVPathififfffffPKfS0_S0_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z9expPVPathififfffffPKfS0_S0_Pf
	.p2align	3, 0x0
_Z9expPVPathififfffffPKfS0_S0_Pf:
	.quad	_Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf
	.size	_Z9expPVPathififfffffPKfS0_S0_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9expPVPathififfffffPKfS0_S0_Pf"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__expPVPathififfffffPKfS0_S0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9expPVPathififfffffPKfS0_S0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9expPVPathififfffffPKfS0_S0_Pf ; -- Begin function _Z9expPVPathififfffffPKfS0_S0_Pf
	.globl	_Z9expPVPathififfffffPKfS0_S0_Pf
	.p2align	8
	.type	_Z9expPVPathififfffffPKfS0_S0_Pf,@function
_Z9expPVPathififfffffPKfS0_S0_Pf:       ; @_Z9expPVPathififfffffPKfS0_S0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b256 s[16:23], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s16, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x28
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_add_f32_e64 v4, s17, 1.0
	v_add_f32_e64 v5, s21, 1.0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, s22
	v_mov_b32_e32 v0, 0
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0x3e76c4e1
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, s19, v6 :: v_dual_add_nc_u32 v2, s13, v1
	s_cmp_eq_u32 s13, 0
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_cndmask_b32_e64 v9, v4, 1.0, s0
	s_and_b32 s1, s13, 0x7fff0000
	s_and_b32 s2, s13, 0xffff
	v_cndmask_b32_e64 v12, v5, 1.0, s0
	s_bitcmp0_b32 s13, 0
	v_cvt_f32_i32_e32 v16, s1
	s_cselect_b32 s1, -1, 0
	v_frexp_mant_f32_e64 v18, |v9|
	v_frexp_exp_i32_f32_e32 v19, v9
	v_cndmask_b32_e64 v2, v9, 1.0, s1
	v_cmp_class_f32_e64 s15, v9, 0x204
	v_cmp_eq_f32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v9, v9, 0, s1
	v_frexp_mant_f32_e64 v21, |v12|
	v_frexp_exp_i32_f32_e32 v22, v12
	v_cndmask_b32_e64 v23, v12, 1.0, s1
	v_cmp_class_f32_e64 s16, v12, 0x204
	v_cmp_eq_f32_e64 s0, 0, v12
	v_cndmask_b32_e64 v25, v12, 0, s1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, s1, s8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s1, s9, v11, s1
	v_add_co_u32 v14, s1, s4, v10
	v_add_co_ci_u32_e64 v15, s1, s5, v11, s1
	v_add_co_u32 v10, s1, s6, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s1, s7, v11, s1
	v_cvt_f32_i32_e32 v17, s2
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v18
	v_mul_f32_e32 v7, s23, v7
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v21
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[14:15], off
	global_load_b32 v10, v[10:11], off
	v_add_f32_e32 v20, v16, v17
	v_cndmask_b32_e64 v26, 0, 1, s1
	v_subrev_co_ci_u32_e64 v14, s1, 0, v19, s1
	v_cndmask_b32_e64 v27, 0, 1, s2
	v_cndmask_b32_e64 v8, 0x7f800000, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ldexp_f32 v11, v18, v26
	v_sub_f32_e32 v16, v16, v20
	v_cvt_f32_i32_e32 v14, v14
	v_cndmask_b32_e64 v24, 0x7f800000, 0, s0
	v_bfi_b32 v8, 0x7fffffff, v8, v9
	v_add_f32_e32 v19, 1.0, v11
	v_dual_add_f32 v15, v16, v17 :: v_dual_add_f32 v18, -1.0, v11
	v_ldexp_f32 v16, v21, v27
	v_subrev_co_ci_u32_e64 v17, s1, 0, v22, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v27, v19
	v_dual_add_f32 v26, -1.0, v19 :: v_dual_add_f32 v21, -1.0, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v17
	v_add_f32_e32 v22, 1.0, v16
	v_bfi_b32 v9, 0x7fffffff, v24, v25
	s_or_b32 vcc_lo, vcc_lo, s15
	s_add_i32 s13, s13, 1
	v_mul_f32_e32 v31, 0x3f317218, v17
	s_waitcnt_depctr 0xfff
	v_dual_add_f32 v29, -1.0, v22 :: v_dual_mul_f32 v32, v18, v27
	v_mul_f32_e32 v28, 0x3f317218, v14
	v_rcp_f32_e32 v30, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v26 :: v_dual_sub_f32 v16, v16, v29
	v_fma_f32 v29, 0x3f317218, v17, -v31
	v_fmac_f32_e32 v29, 0xb102e308, v17
	v_mul_f32_e32 v17, v19, v32
	v_fma_f32 v26, 0x3f317218, v14, -v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v35, v31, v29
	v_fma_f32 v19, v32, v19, -v17
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v26, 0xb102e308, v14
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v14, v21, v30 :: v_dual_sub_f32 v31, v35, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v19, v32, v11 :: v_dual_mul_f32 v34, v22, v14
	v_fma_f32 v22, v14, v22, -v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v33, v28, v26 :: v_dual_fmac_f32 v22, v14, v16
	v_sub_f32_e32 v28, v33, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v16, v29, v31 :: v_dual_sub_f32 v11, v26, v28
	v_add_f32_e32 v28, v34, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v34, v28, v34
	v_add_f32_e32 v26, v17, v19
	v_sub_f32_e32 v17, v26, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v17, v19
	v_sub_f32_e32 v31, v21, v28
	v_sub_f32_e32 v19, v21, v31
	v_sub_f32_e32 v21, v34, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v19, v28
	v_sub_f32_e32 v29, v18, v26
	v_sub_f32_e32 v18, v18, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v18, v26
	v_add_f32_e32 v17, v17, v18
	v_add_f32_e32 v18, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v17, v29, v17 :: v_dual_add_f32 v18, v31, v18
	v_mul_f32_e32 v18, v30, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v14, v18
	v_dual_mul_f32 v17, v27, v17 :: v_dual_sub_f32 v14, v21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v32, v17 :: v_dual_sub_f32 v14, v18, v14
	v_sub_f32_e32 v22, v19, v32
	v_mul_f32_e32 v26, v19, v19
	v_ldexp_f32 v29, v21, 1
	v_ldexp_f32 v27, v19, 1
	v_add_f32_e32 v32, v14, v14
	v_sub_f32_e32 v17, v17, v22
	v_fma_f32 v22, v19, v19, -v26
	v_ldexp_f32 v34, v14, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v17, v17
	v_fmac_f32_e32 v22, v19, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v26, v22
	v_dual_mul_f32 v28, v21, v21 :: v_dual_mul_f32 v37, v19, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, v21, v21, -v28
	v_sub_f32_e32 v26, v30, v26
	v_fma_f32 v40, v30, v19, -v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v21, v32
	v_add_f32_e32 v32, v28, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmaak_f32 v38, s14, v32, 0x3e91f4c4
	v_dual_mul_f32 v39, v21, v32 :: v_dual_sub_f32 v22, v22, v26
	v_fmac_f32_e32 v40, v30, v17
	v_ldexp_f32 v31, v17, 1
	v_fmaak_f32 v26, v32, v38, 0x3ecccdef
	v_sub_f32_e32 v28, v32, v28
	v_fma_f32 v38, v32, v21, -v39
	v_fmac_f32_e32 v40, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v18, v28
	v_fmac_f32_e32 v38, v32, v14
	v_mul_f32_e32 v14, v32, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v28, v37, v40
	v_fmac_f32_e32 v38, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v32, v26, -v14
	v_dual_fmac_f32 v21, v18, v26 :: v_dual_sub_f32 v18, v28, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v32, v14, v21
	v_dual_sub_f32 v14, v32, v14 :: v_dual_add_f32 v37, 0x3f2aaaaa, v32
	v_fmaak_f32 v36, s14, v30, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v21, v14 :: v_dual_add_f32 v21, 0xbf2aaaaa, v37
	v_fmaak_f32 v36, v30, v36, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, 0x31739010, v14 :: v_dual_sub_f32 v21, v32, v21
	v_mul_f32_e32 v17, v30, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v21
	v_fma_f32 v19, v30, v36, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v37, v14
	v_fmac_f32_e32 v19, v22, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v26, v17, v19
	v_dual_sub_f32 v17, v26, v17 :: v_dual_add_f32 v36, 0x3f2aaaaa, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v19, v17
	v_add_f32_e32 v19, 0xbf2aaaaa, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, 0x31739010, v17
	v_sub_f32_e32 v19, v26, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v17, v19
	v_add_f32_e32 v19, v36, v17
	v_sub_f32_e32 v18, v40, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v26, v36, v19
	v_mul_f32_e32 v32, v28, v19
	v_sub_f32_e32 v36, v37, v21
	v_add_f32_e32 v17, v17, v26
	v_add_f32_e32 v22, v39, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v26, v28, v19, -v32
	v_add_f32_e32 v14, v14, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v37, v22, v21
	v_fmac_f32_e32 v26, v28, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v36, v22, v21, -v37
	v_fmac_f32_e32 v26, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v36, v22, v14
	v_add_f32_e32 v14, v32, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v18, v27, v14 :: v_dual_sub_f32 v19, v14, v32
	v_sub_f32_e32 v30, v22, v39
	v_sub_f32_e32 v27, v18, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v26, v19
	v_sub_f32_e32 v14, v14, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v31, v19
	v_add_f32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v18, v14
	v_sub_f32_e32 v30, v38, v30
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v13, v6, v13 :: v_dual_sub_f32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v36, v30, v21 :: v_dual_fmac_f32 v13, s20, v7
	v_dual_sub_f32 v14, v14, v18 :: v_dual_add_f32 v17, v37, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v29, v17
	v_sub_f32_e32 v22, v17, v37
	v_sub_f32_e32 v26, v21, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v36, v22
	v_sub_f32_e32 v17, v17, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v34, v22
	v_dual_add_f32 v26, v33, v19 :: v_dual_add_f32 v17, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v28, v26, v33
	v_dual_add_f32 v22, v21, v17 :: v_dual_sub_f32 v19, v19, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v35, v22
	v_dual_sub_f32 v21, v22, v21 :: v_dual_sub_f32 v18, v27, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v17, v21
	v_dual_sub_f32 v21, v26, v28 :: v_dual_add_f32 v28, v11, v14
	v_sub_f32_e32 v29, v27, v18
	v_sub_f32_e32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v16, v17
	v_dual_sub_f32 v21, v33, v21 :: v_dual_sub_f32 v30, v28, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v29, v35, v29
	v_sub_f32_e32 v31, v22, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v19, v21
	v_dual_sub_f32 v21, v28, v30 :: v_dual_add_f32 v18, v18, v29
	v_sub_f32_e32 v14, v14, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v29, v22, v31
	v_add_f32_e32 v19, v28, v19
	v_sub_f32_e32 v17, v17, v31
	v_dual_sub_f32 v11, v11, v21 :: v_dual_add_f32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v16, v29 :: v_dual_add_f32 v21, v26, v19
	v_dual_add_f32 v11, v14, v11 :: v_dual_add_f32 v14, v27, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v16, v17, v16
	v_dual_sub_f32 v17, v21, v26 :: v_dual_sub_f32 v22, v14, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v19, v17 :: v_dual_sub_f32 v18, v18, v22
	v_dual_add_f32 v11, v11, v17 :: v_dual_add_f32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v17, v21, v11 :: v_dual_add_f32 v18, v14, v16
	v_sub_f32_e32 v19, v17, v21
	v_mul_f32_e32 v21, v20, v17
	v_mul_f32_e32 v22, v15, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v18, v14
	v_dual_mul_f32 v26, v20, v18 :: v_dual_sub_f32 v11, v11, v19
	v_mul_f32_e32 v15, v15, v18
	v_fma_f32 v17, v20, v17, -v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v16, v14
	v_fma_f32 v16, v20, v18, -v26
	v_fmac_f32_e32 v22, v20, v11
	v_cmp_class_f32_e64 s1, v21, 0x204
	v_cmp_class_f32_e64 s2, v26, 0x204
	v_fmac_f32_e32 v15, v20, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v17, v22 :: v_dual_add_f32 v14, v16, v15
	v_dual_add_f32 v15, v21, v11 :: v_dual_add_f32 v16, v26, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v17, v15, v21
	v_cndmask_b32_e64 v15, v15, v21, s1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v21, 0x3fb8aa3b, v10
	v_sub_f32_e32 v18, v16, v26
	v_cndmask_b32_e64 v16, v16, v26, s2
	v_sub_f32_e32 v11, v11, v17
	v_cmp_eq_f32_e64 s2, 0x42b17218, v15
	v_cmp_neq_f32_e64 s1, 0x7f800000, |v15|
	v_sub_f32_e32 v14, v14, v18
	v_cmp_eq_f32_e64 s3, 0x42b17218, v16
	v_fma_f32 v27, 0x3fb8aa3b, v10, -v21
	v_cndmask_b32_e64 v17, 0, 0x37000000, s2
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v16|
	v_cndmask_b32_e64 v11, 0, v11, s1
	v_cndmask_b32_e64 v18, 0, 0x37000000, s3
	v_cmp_gt_f32_e64 s1, s12, v12
	v_sub_f32_e32 v15, v15, v17
	v_cndmask_b32_e64 v14, 0, v14, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v11, v17, v11 :: v_dual_sub_f32 v16, v16, v18
	v_rndne_f32_e32 v28, v21
	v_dual_mul_f32 v19, 0x3fb8aa3b, v15 :: v_dual_add_f32 v14, v18, v14
	v_cndmask_b32_e64 v12, 0, 1.0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	v_fmac_f32_e32 v27, 0x32a5705f, v10
	v_fma_f32 v18, 0x3fb8aa3b, v15, -v19
	v_rndne_f32_e32 v20, v19
	v_sub_f32_e32 v21, v21, v28
	v_fma_f32 v22, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v26, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v18, 0x32a5705f, v15 :: v_dual_sub_f32 v19, v19, v20
	v_cvt_i32_f32_e32 v20, v20
	v_dual_fmac_f32 v22, 0x32a5705f, v16 :: v_dual_sub_f32 v17, v17, v26
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v18, v19, v18 :: v_dual_add_f32 v19, v21, v27
	v_cvt_i32_f32_e32 v21, v28
	v_add_f32_e32 v17, v17, v22
	v_cvt_i32_f32_e32 v26, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_exp_f32_e32 v18, v18
	v_exp_f32_e32 v19, v19
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v16
	v_exp_f32_e32 v17, v17
	v_ldexp_f32 v18, v18, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v19, v19, v21
	v_ldexp_f32 v17, v17, v26
	v_cndmask_b32_e64 v18, 0, v18, s1
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, 0, v19, s1
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v15
	v_cndmask_b32_e64 v15, 0, v17, s2
	v_cndmask_b32_e64 v17, 0x7f800000, v18, s1
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v17, v11, v17
	v_cndmask_b32_e64 v10, 0x7f800000, v19, s1
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, -1.0, v10
	v_cndmask_b32_e64 v15, 0x7f800000, v15, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v6, v10
	v_fma_f32 v7, v15, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v17, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v15
	v_fmac_f32_e32 v13, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v11, v2
	v_cndmask_b32_e64 v7, v7, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v6, v13
	v_cndmask_b32_e32 v2, v2, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_bfi_b32 v7, 0x7fffffff, v7, v23
	s_or_b32 vcc_lo, s0, s16
	s_cmp_eq_u32 s18, s13
	v_dual_mul_f32 v2, v2, v6 :: v_dual_cndmask_b32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v8, null, v7, v7, v2
	v_div_scale_f32 v11, vcc_lo, v2, v7, v2
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_mul_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v10, v11
	v_fmac_f32_e32 v10, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v10, v11
	v_div_fmas_f32 v8, v8, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v8, v7, v2
	v_add_f32_e32 v0, v0, v2
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
.LBB0_5:                                ; %Flow80
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9expPVPathififfffffPKfS0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9expPVPathififfffffPKfS0_S0_Pf, .Lfunc_end0-_Z9expPVPathififfffffPKfS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2552
; NumSgprs: 26
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9expPVPathififfffffPKfS0_S0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z9expPVPathififfffffPKfS0_S0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
