#include <cuda.h>
#include <stdio.h>
#include <stdint.h> 


#define WIDTH 512
#define HEIGHT 512
#define ITERS 512

#define N (WIDTH*HEIGHT)

#define max_size   4
#define max_colors 16

#define xmax  1.2f
#define xmin -2.0f
#define ymax  1.2f
#define ymin -1.2f

#define deltaP ((xmax - xmin)/512)
#define deltaQ ((ymax - ymin)/512) 


extern "C" __global__ void mandelGen(uint8_t* output0)
{
    extern __shared__ uint8_t sbase[];
    uint32_t tid = threadIdx.x;
    float v0;
    float v1;
    uint32_t v2;
    float t3;
    float t4;
    uint32_t t5;
    
    if (blockIdx.x < 512U) {
        v0 = 0.0F;
        v1 = 0.0F;
        v2 = 1U;
        while (v0 * v0 + v1 * v1 < 4.0F && v2 < 512U) {
            t3 = v0;
            t4 = v1;
            t5 = v2;
            v0 = t3 * t3 - t4 * t4 + (-0.7931140065193176F + (float) tid *
                                      1.3693165965378284e-4F);
            v1 = 2.0F * t3 * t4 + (0.1409740000963211F -
                                   (float) blockIdx.x *
                                   2.0146874885540456e-4F);
            v2 = t5 + 1U;
        }
        output0[blockIdx.x * 512U + tid] = (uint8_t) v2 % 16U * 16U;
    }
}


__global__ void kernel(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-2.0f+(((float)threadIdx.x)*6.25e-3f)));
        v2 = (((2.0f*t6)*t5)+(1.2f-(((float)blockIdx.x)*4.6875e-3f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}

__global__ void plate1(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.69106f+(((float)threadIdx.x)*3.008172e-7f)));
        v2 = (((2.0f*t6)*t5)+(0.387228f-(((float)blockIdx.x)*2.4418114e-7f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}

__global__ void plate2(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.793114f+(((float)threadIdx.x)*1.3693166e-4f)));
        v2 = (((2.0f*t6)*t5)+(0.140974f-(((float)blockIdx.x)*2.0146875e-4f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}
__global__ void plate3(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.745464f+(((float)threadIdx.x)*1.4854595e-7f)));
        v2 = (((2.0f*t6)*t5)+(0.11303f-(((float)blockIdx.x)*1.23051e-7f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}


__global__ void mandel(uint8_t *out) { 
  
  int bid = blockIdx.x; 
  int tid = threadIdx.x; 

  float x = 0.0, y = 0.0, xsq = 0.0, ysq = 0.0;
  int color = 1; 

  while (color < ITERS && (xsq + ysq) < max_size) {

    xsq = x*x;
    ysq = y*y;
    y = 2*x*y+(ymax - blockIdx.x*deltaQ);
    x = xsq - ysq + (xmin + threadIdx.x * deltaP);
    color ++;
  }
  
  
  out[bid* 512 + tid] = (color % 8) * 32; // % max_colors;

  } 

/* ------------------------------------------------------------------------
   MAIN
   --------------------------------------------------------------------- */
int main(void) {
  
   
  uint8_t *r; 

  uint8_t *dr; 
  
  r = (uint8_t*)malloc(sizeof(uint8_t) * N);
  
  cudaMalloc((void**)&dr,N*sizeof(uint8_t));

  cudaMemset(dr,0,N*sizeof(uint8_t));
  
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start,0);

  //mandel<<<HEIGHT,WIDTH,0>>>(dr);
  //kernel<<<HEIGHT,WIDTH,0>>>(dr);	
  //plate1<<<HEIGHT,WIDTH,0>>>(dr);	
  //plate2<<<HEIGHT,WIDTH,0>>>(dr);	  		
  //plate3<<<HEIGHT,WIDTH,0>>>(dr);	  		

  mandelGen<<<HEIGHT,WIDTH,0>>>(dr);	  		

  cudaEventRecord(stop,0);
  cudaEventSynchronize(stop);
  float elapsedTime;
  cudaEventElapsedTime(&elapsedTime, start, stop);

  // std::cout << std::endl;

  cudaMemcpy(r,dr,N*sizeof(uint8_t),cudaMemcpyDeviceToHost);
  //cudaMemcpy(m,dm,64*sizeof(float),cudaMemcpyDeviceToHost);


  for (int i = 0; i < N; i ++) { 
    printf("%d ",r[i]);
  }

    
  printf("Elapsed time: %f\n", elapsedTime);


  FILE *file; 
  file = fopen("image.out","w");
  fwrite(r,sizeof(uint8_t),N,file);
  fclose(file);
  

  return 0;
}



	.file	"tmpxft_00298ed7_00000000-6_mandel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z9mandelGenPhPh
	.type	_Z28__device_stub__Z9mandelGenPhPh, @function
_Z28__device_stub__Z9mandelGenPhPh:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	mandelGen(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z9mandelGenPhPh, .-_Z28__device_stub__Z9mandelGenPhPh
	.globl	mandelGen
	.type	mandelGen, @function
mandelGen:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z9mandelGenPhPh
	.cfi_endproc
.LFE2053:
	.size	mandelGen, .-mandelGen
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"Elapsed time: %f\n"
.LC2:
	.string	"w"
.LC3:
	.string	"image.out"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$262144, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$262144, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$262144, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rdi
	call	_Z28__device_stub__Z9mandelGenPhPh
.L9:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebp, %ebp
	leaq	.LC0(%rip), %r12
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
.L10:
	movzbl	(%rbx,%rbp), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$262144, %rbp
	jne	.L10
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	44(%rsp), %xmm0
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	leaq	.LC3(%rip), %rdi
	call	fopen@PLT
	movq	%rbx, %rdi
	movl	$262144, %edx
	movl	$1, %esi
	movq	%rax, %rbp
	movq	%rax, %rcx
	call	fwrite@PLT
	movq	%rbp, %rdi
	call	fclose@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z25__device_stub__Z6kernelPhPh
	.type	_Z25__device_stub__Z6kernelPhPh, @function
_Z25__device_stub__Z6kernelPhPh:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6kernelPh(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L14:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z25__device_stub__Z6kernelPhPh, .-_Z25__device_stub__Z6kernelPhPh
	.globl	_Z6kernelPh
	.type	_Z6kernelPh, @function
_Z6kernelPh:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6kernelPhPh
	.cfi_endproc
.LFE2055:
	.size	_Z6kernelPh, .-_Z6kernelPh
	.globl	_Z25__device_stub__Z6plate1PhPh
	.type	_Z25__device_stub__Z6plate1PhPh, @function
_Z25__device_stub__Z6plate1PhPh:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6plate1Ph(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L19:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z25__device_stub__Z6plate1PhPh, .-_Z25__device_stub__Z6plate1PhPh
	.globl	_Z6plate1Ph
	.type	_Z6plate1Ph, @function
_Z6plate1Ph:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6plate1PhPh
	.cfi_endproc
.LFE2057:
	.size	_Z6plate1Ph, .-_Z6plate1Ph
	.globl	_Z25__device_stub__Z6plate2PhPh
	.type	_Z25__device_stub__Z6plate2PhPh, @function
_Z25__device_stub__Z6plate2PhPh:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6plate2Ph(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L24:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z25__device_stub__Z6plate2PhPh, .-_Z25__device_stub__Z6plate2PhPh
	.globl	_Z6plate2Ph
	.type	_Z6plate2Ph, @function
_Z6plate2Ph:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6plate2PhPh
	.cfi_endproc
.LFE2059:
	.size	_Z6plate2Ph, .-_Z6plate2Ph
	.globl	_Z25__device_stub__Z6plate3PhPh
	.type	_Z25__device_stub__Z6plate3PhPh, @function
_Z25__device_stub__Z6plate3PhPh:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6plate3Ph(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L29:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z25__device_stub__Z6plate3PhPh, .-_Z25__device_stub__Z6plate3PhPh
	.globl	_Z6plate3Ph
	.type	_Z6plate3Ph, @function
_Z6plate3Ph:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6plate3PhPh
	.cfi_endproc
.LFE2061:
	.size	_Z6plate3Ph, .-_Z6plate3Ph
	.globl	_Z25__device_stub__Z6mandelPhPh
	.type	_Z25__device_stub__Z6mandelPhPh, @function
_Z25__device_stub__Z6mandelPhPh:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6mandelPh(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L34:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z25__device_stub__Z6mandelPhPh, .-_Z25__device_stub__Z6mandelPhPh
	.globl	_Z6mandelPh
	.type	_Z6mandelPh, @function
_Z6mandelPh:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6mandelPhPh
	.cfi_endproc
.LFE2063:
	.size	_Z6mandelPh, .-_Z6mandelPh
	.section	.rodata.str1.1
.LC4:
	.string	"_Z6mandelPh"
.LC5:
	.string	"_Z6plate3Ph"
.LC6:
	.string	"_Z6plate2Ph"
.LC7:
	.string	"_Z6plate1Ph"
.LC8:
	.string	"_Z6kernelPh"
.LC9:
	.string	"mandelGen"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6mandelPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6plate3Ph(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6plate2Ph(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6plate1Ph(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6kernelPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	mandelGen(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2065:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdint.h> 


#define WIDTH 512
#define HEIGHT 512
#define ITERS 512

#define N (WIDTH*HEIGHT)

#define max_size   4
#define max_colors 16

#define xmax  1.2f
#define xmin -2.0f
#define ymax  1.2f
#define ymin -1.2f

#define deltaP ((xmax - xmin)/512)
#define deltaQ ((ymax - ymin)/512) 


extern "C" __global__ void mandelGen(uint8_t* output0)
{
    extern __shared__ uint8_t sbase[];
    uint32_t tid = threadIdx.x;
    float v0;
    float v1;
    uint32_t v2;
    float t3;
    float t4;
    uint32_t t5;
    
    if (blockIdx.x < 512U) {
        v0 = 0.0F;
        v1 = 0.0F;
        v2 = 1U;
        while (v0 * v0 + v1 * v1 < 4.0F && v2 < 512U) {
            t3 = v0;
            t4 = v1;
            t5 = v2;
            v0 = t3 * t3 - t4 * t4 + (-0.7931140065193176F + (float) tid *
                                      1.3693165965378284e-4F);
            v1 = 2.0F * t3 * t4 + (0.1409740000963211F -
                                   (float) blockIdx.x *
                                   2.0146874885540456e-4F);
            v2 = t5 + 1U;
        }
        output0[blockIdx.x * 512U + tid] = (uint8_t) v2 % 16U * 16U;
    }
}


__global__ void kernel(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-2.0f+(((float)threadIdx.x)*6.25e-3f)));
        v2 = (((2.0f*t6)*t5)+(1.2f-(((float)blockIdx.x)*4.6875e-3f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}

__global__ void plate1(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.69106f+(((float)threadIdx.x)*3.008172e-7f)));
        v2 = (((2.0f*t6)*t5)+(0.387228f-(((float)blockIdx.x)*2.4418114e-7f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}

__global__ void plate2(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.793114f+(((float)threadIdx.x)*1.3693166e-4f)));
        v2 = (((2.0f*t6)*t5)+(0.140974f-(((float)blockIdx.x)*2.0146875e-4f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}
__global__ void plate3(uint8_t* output0){
  
    float v3;
    float v2;
    uint32_t v1;
    v3 = 0.0f;
    v2 = 0.0f;
    v1 = 1;
    while (((((v3*v3)+(v2*v2))<4.0f)&&(v1<512))){
      
        float t6;
        float t5;
        uint32_t t4;
        t6 = v3;
        t5 = v2;
        t4 = v1;
        v3 = (((t6*t6)-(t5*t5))+(-0.745464f+(((float)threadIdx.x)*1.4854595e-7f)));
        v2 = (((2.0f*t6)*t5)+(0.11303f-(((float)blockIdx.x)*1.23051e-7f)));
        v1 = (t4+1);
        
    }
    output0[((blockIdx.x*512)+threadIdx.x)] = ((((uint8_t)v1)%16)*16);
    
  
}


__global__ void mandel(uint8_t *out) { 
  
  int bid = blockIdx.x; 
  int tid = threadIdx.x; 

  float x = 0.0, y = 0.0, xsq = 0.0, ysq = 0.0;
  int color = 1; 

  while (color < ITERS && (xsq + ysq) < max_size) {

    xsq = x*x;
    ysq = y*y;
    y = 2*x*y+(ymax - blockIdx.x*deltaQ);
    x = xsq - ysq + (xmin + threadIdx.x * deltaP);
    color ++;
  }
  
  
  out[bid* 512 + tid] = (color % 8) * 32; // % max_colors;

  } 

/* ------------------------------------------------------------------------
   MAIN
   --------------------------------------------------------------------- */
int main(void) {
  
   
  uint8_t *r; 

  uint8_t *dr; 
  
  r = (uint8_t*)malloc(sizeof(uint8_t) * N);
  
  hipMalloc((void**)&dr,N*sizeof(uint8_t));

  hipMemset(dr,0,N*sizeof(uint8_t));
  
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start,0);

  //mandel<<<HEIGHT,WIDTH,0>>>(dr);
  //kernel<<<HEIGHT,WIDTH,0>>>(dr);	
  //plate1<<<HEIGHT,WIDTH,0>>>(dr);	
  //plate2<<<HEIGHT,WIDTH,0>>>(dr);	  		
  //plate3<<<HEIGHT,WIDTH,0>>>(dr);	  		

  mandelGen<<<HEIGHT,WIDTH,0>>>(dr);	  		

  hipEventRecord(stop,0);
  hipEventSynchronize(stop);
  float elapsedTime;
  hipEventElapsedTime(&elapsedTime, start, stop);

  // std::cout << std::endl;

  hipMemcpy(r,dr,N*sizeof(uint8_t),hipMemcpyDeviceToHost);
  //cudaMemcpy(m,dm,64*sizeof(float),cudaMemcpyDeviceToHost);


  for (int i = 0; i < N; i ++) { 
    printf("%d ",r[i]);
  }

    
  printf("Elapsed time: %f\n", elapsedTime);


  FILE *file; 
  file = fopen("image.out","w");
  fwrite(r,sizeof(uint8_t),N,file);
  fclose(file);
  

  return 0;
}



	.text
	.file	"mandel.hip"
	.globl	__device_stub__mandelGen        # -- Begin function __device_stub__mandelGen
	.type	__device_stub__mandelGen,@function
__device_stub__mandelGen:               # @__device_stub__mandelGen
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$mandelGen, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__mandelGen, .Lfunc_end0-__device_stub__mandelGen
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__kernelPh     # -- Begin function _Z21__device_stub__kernelPh
	.type	_Z21__device_stub__kernelPh,@function
_Z21__device_stub__kernelPh:            # @_Z21__device_stub__kernelPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__kernelPh, .Lfunc_end1-_Z21__device_stub__kernelPh
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__plate1Ph     # -- Begin function _Z21__device_stub__plate1Ph
	.type	_Z21__device_stub__plate1Ph,@function
_Z21__device_stub__plate1Ph:            # @_Z21__device_stub__plate1Ph
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6plate1Ph, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__plate1Ph, .Lfunc_end2-_Z21__device_stub__plate1Ph
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__plate2Ph     # -- Begin function _Z21__device_stub__plate2Ph
	.type	_Z21__device_stub__plate2Ph,@function
_Z21__device_stub__plate2Ph:            # @_Z21__device_stub__plate2Ph
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6plate2Ph, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z21__device_stub__plate2Ph, .Lfunc_end3-_Z21__device_stub__plate2Ph
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__plate3Ph     # -- Begin function _Z21__device_stub__plate3Ph
	.type	_Z21__device_stub__plate3Ph,@function
_Z21__device_stub__plate3Ph:            # @_Z21__device_stub__plate3Ph
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6plate3Ph, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z21__device_stub__plate3Ph, .Lfunc_end4-_Z21__device_stub__plate3Ph
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__mandelPh     # -- Begin function _Z21__device_stub__mandelPh
	.type	_Z21__device_stub__mandelPh,@function
_Z21__device_stub__mandelPh:            # @_Z21__device_stub__mandelPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6mandelPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z21__device_stub__mandelPh, .Lfunc_end5-_Z21__device_stub__mandelPh
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %rbx
	leaq	24(%rsp), %r14
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	xorl	%esi, %esi
	callq	hipMemset
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	24(%rsp), %rdi
	callq	__device_stub__mandelGen
.LBB6_2:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	20(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	24(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
.LBB6_3:                                # =>This Inner Loop Header: Depth=1
	movzbl	(%rbx,%r14), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$262144, %r14                   # imm = 0x40000
	jne	.LBB6_3
# %bb.4:
	cvtss2sd	20(%rsp), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	movl	$1, %esi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%rbx, %rdi
	movq	%rax, %rcx
	callq	fwrite
	movq	%r14, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$mandelGen, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPh, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6plate1Ph, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6plate2Ph, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6plate3Ph, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6mandelPh, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	mandelGen,@object               # @mandelGen
	.section	.rodata,"a",@progbits
	.globl	mandelGen
	.p2align	3, 0x0
mandelGen:
	.quad	__device_stub__mandelGen
	.size	mandelGen, 8

	.type	_Z6kernelPh,@object             # @_Z6kernelPh
	.globl	_Z6kernelPh
	.p2align	3, 0x0
_Z6kernelPh:
	.quad	_Z21__device_stub__kernelPh
	.size	_Z6kernelPh, 8

	.type	_Z6plate1Ph,@object             # @_Z6plate1Ph
	.globl	_Z6plate1Ph
	.p2align	3, 0x0
_Z6plate1Ph:
	.quad	_Z21__device_stub__plate1Ph
	.size	_Z6plate1Ph, 8

	.type	_Z6plate2Ph,@object             # @_Z6plate2Ph
	.globl	_Z6plate2Ph
	.p2align	3, 0x0
_Z6plate2Ph:
	.quad	_Z21__device_stub__plate2Ph
	.size	_Z6plate2Ph, 8

	.type	_Z6plate3Ph,@object             # @_Z6plate3Ph
	.globl	_Z6plate3Ph
	.p2align	3, 0x0
_Z6plate3Ph:
	.quad	_Z21__device_stub__plate3Ph
	.size	_Z6plate3Ph, 8

	.type	_Z6mandelPh,@object             # @_Z6mandelPh
	.globl	_Z6mandelPh
	.p2align	3, 0x0
_Z6mandelPh:
	.quad	_Z21__device_stub__mandelPh
	.size	_Z6mandelPh, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Elapsed time: %f\n"
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"image.out"
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"mandelGen"
	.size	.L__unnamed_1, 10

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6kernelPh"
	.size	.L__unnamed_2, 12

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6plate1Ph"
	.size	.L__unnamed_3, 12

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z6plate2Ph"
	.size	.L__unnamed_4, 12

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z6plate3Ph"
	.size	.L__unnamed_5, 12

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z6mandelPh"
	.size	.L__unnamed_6, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__mandelGen
	.addrsig_sym _Z21__device_stub__kernelPh
	.addrsig_sym _Z21__device_stub__plate1Ph
	.addrsig_sym _Z21__device_stub__plate2Ph
	.addrsig_sym _Z21__device_stub__plate3Ph
	.addrsig_sym _Z21__device_stub__mandelPh
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym mandelGen
	.addrsig_sym _Z6kernelPh
	.addrsig_sym _Z6plate1Ph
	.addrsig_sym _Z6plate2Ph
	.addrsig_sym _Z6plate3Ph
	.addrsig_sym _Z6mandelPh
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	mandelGen               ; -- Begin function mandelGen
	.globl	mandelGen
	.p2align	8
	.type	mandelGen,@function
mandelGen:                              ; @mandelGen
; %bb.0:
	s_cmpk_gt_u32 s15, 0x1ff
	s_cbranch_scc1 .LBB0_4
; %bb.1:                                ; %.preheader
	v_cvt_f32_u32_e32 v1, v0
	v_cvt_f32_u32_e32 v2, s15
	s_mov_b32 s2, 0x390f9550
	s_mov_b32 s3, 0xb953415b
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	v_dual_fmaak_f32 v1, s2, v1, 0xbf4b0985 :: v_dual_mov_b32 v4, 0
	v_dual_fmaak_f32 v2, s3, v2, 0x3e105b7d :: v_dual_mov_b32 v5, 0
	s_mov_b32 s3, 1
	s_mov_b32 s2, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_add_f32 v5, v6, v6
	s_add_i32 s4, s3, 1
	s_cmpk_gt_u32 s3, 0x1fe
	v_dual_mov_b32 v7, s4 :: v_dual_add_f32 v6, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v3, v5, v2
	s_cselect_b32 s3, -1, 0
	v_mul_f32_e32 v4, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v3, v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
	v_mul_f32_e32 v5, v3, v3
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
; %bb.3:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b16 v1, 4, v7
	v_lshl_add_u32 v0, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v0, v1, s[0:1]
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel mandelGen
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	mandelGen, .Lfunc_end0-mandelGen
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6kernelPh             ; -- Begin function _Z6kernelPh
	.globl	_Z6kernelPh
	.p2align	8
	.type	_Z6kernelPh,@function
_Z6kernelPh:                            ; @_Z6kernelPh
; %bb.0:
	v_dual_mov_b32 v2, -2.0 :: v_dual_mov_b32 v5, 0
	v_cvt_f32_u32_e32 v1, s15
	v_cvt_f32_u32_e32 v3, v0
	s_mov_b32 s2, 0xbb99999a
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, 0 :: v_dual_fmaak_f32 v1, s2, v1, 0x3f99999a
	v_dual_fmamk_f32 v2, v3, 0x3bcccccd, v2 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s3, 1
	s_mov_b32 s2, 0
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_add_f32 v5, v6, v6
	s_add_i32 s4, s3, 1
	s_cmpk_gt_u32 s3, 0x1fe
	v_dual_mov_b32 v7, s4 :: v_dual_add_f32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v3, v5, v1
	s_cselect_b32 s3, -1, 0
	v_mul_f32_e32 v4, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v3, v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
	v_mul_f32_e32 v5, v3, v3
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b16 v1, 4, v7
	v_lshl_add_u32 v0, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6kernelPh, .Lfunc_end1-_Z6kernelPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6plate1Ph             ; -- Begin function _Z6plate1Ph
	.globl	_Z6plate1Ph
	.p2align	8
	.type	_Z6plate1Ph,@function
_Z6plate1Ph:                            ; @_Z6plate1Ph
; %bb.0:
	v_cvt_f32_u32_e32 v1, s15
	v_cvt_f32_u32_e32 v2, v0
	s_mov_b32 s2, 0x34a18000
	s_mov_b32 s3, 0xb4831800
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	v_dual_fmaak_f32 v1, s3, v1, 0x3ec642c0 :: v_dual_mov_b32 v6, 0
	v_dual_fmaak_f32 v2, s2, v2, 0xbf30e94f :: v_dual_mov_b32 v3, 0
	s_mov_b32 s3, 1
	s_mov_b32 s2, 0
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_add_f32 v5, v6, v6
	s_add_i32 s4, s3, 1
	s_cmpk_gt_u32 s3, 0x1fe
	v_dual_mov_b32 v7, s4 :: v_dual_add_f32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v3, v5, v1
	s_cselect_b32 s3, -1, 0
	v_mul_f32_e32 v4, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v3, v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
	v_mul_f32_e32 v5, v3, v3
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b16 v1, 4, v7
	v_lshl_add_u32 v0, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6plate1Ph
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6plate1Ph, .Lfunc_end2-_Z6plate1Ph
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6plate2Ph             ; -- Begin function _Z6plate2Ph
	.globl	_Z6plate2Ph
	.p2align	8
	.type	_Z6plate2Ph,@function
_Z6plate2Ph:                            ; @_Z6plate2Ph
; %bb.0:
	v_cvt_f32_u32_e32 v1, s15
	v_cvt_f32_u32_e32 v2, v0
	s_mov_b32 s2, 0x390f9550
	s_mov_b32 s3, 0xb953415b
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	v_dual_fmaak_f32 v1, s3, v1, 0x3e105b7d :: v_dual_mov_b32 v6, 0
	v_dual_fmaak_f32 v2, s2, v2, 0xbf4b0985 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s3, 1
	s_mov_b32 s2, 0
.LBB3_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_add_f32 v5, v6, v6
	s_add_i32 s4, s3, 1
	s_cmpk_gt_u32 s3, 0x1fe
	v_dual_mov_b32 v7, s4 :: v_dual_add_f32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v3, v5, v1
	s_cselect_b32 s3, -1, 0
	v_mul_f32_e32 v4, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v3, v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
	v_mul_f32_e32 v5, v3, v3
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b16 v1, 4, v7
	v_lshl_add_u32 v0, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6plate2Ph
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z6plate2Ph, .Lfunc_end3-_Z6plate2Ph
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6plate3Ph             ; -- Begin function _Z6plate3Ph
	.globl	_Z6plate3Ph
	.p2align	8
	.type	_Z6plate3Ph,@function
_Z6plate3Ph:                            ; @_Z6plate3Ph
; %bb.0:
	v_cvt_f32_u32_e32 v1, s15
	v_cvt_f32_u32_e32 v2, v0
	s_mov_b32 s2, 0x341f8000
	s_mov_b32 s3, 0xb4042000
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	v_dual_fmaak_f32 v1, s3, v1, 0x3de77c46 :: v_dual_mov_b32 v6, 0
	v_dual_fmaak_f32 v2, s2, v2, 0xbf3ed6bb :: v_dual_mov_b32 v3, 0
	s_mov_b32 s3, 1
	s_mov_b32 s2, 0
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_add_f32 v5, v6, v6
	s_add_i32 s4, s3, 1
	s_cmpk_gt_u32 s3, 0x1fe
	v_dual_mov_b32 v7, s4 :: v_dual_add_f32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v3, v5, v1
	s_cselect_b32 s3, -1, 0
	v_mul_f32_e32 v4, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v3, v3, v4
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
	v_mul_f32_e32 v5, v3, v3
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b16 v1, 4, v7
	v_lshl_add_u32 v0, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	global_store_b8 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6plate3Ph
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z6plate3Ph, .Lfunc_end4-_Z6plate3Ph
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6mandelPh             ; -- Begin function _Z6mandelPh
	.globl	_Z6mandelPh
	.p2align	8
	.type	_Z6mandelPh,@function
_Z6mandelPh:                            ; @_Z6mandelPh
; %bb.0:
	v_cvt_f32_u32_e32 v2, s15
	v_cvt_f32_u32_e32 v4, v0
	s_mov_b32 s2, 0xbb99999a
	v_mov_b32_e32 v3, -2.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v1, 0 :: v_dual_fmaak_f32 v2, s2, v2, 0x3f99999a
	s_mov_b32 s2, 0
	s_mov_b32 s3, 1
	v_dual_fmamk_f32 v3, v4, 0x3bcccccd, v3 :: v_dual_mov_b32 v4, 0
.LBB5_1:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s4, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v6, v1, v1 :: v_dual_mov_b32 v5, s4
	s_cmpk_gt_u32 s3, 0x1fe
	s_cselect_b32 s3, -1, 0
	v_fma_f32 v7, v4, v4, -v6
	v_fmac_f32_e32 v6, v4, v4
	v_add_f32_e32 v4, v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ngt_f32_e32 vcc_lo, 4.0, v6
	v_add_f32_e32 v6, v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v4, v1, v2
	s_or_b32 s3, s3, vcc_lo
	v_mov_b32_e32 v4, v6
	s_and_b32 s3, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s3, s2
	s_mov_b32 s3, s4
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB5_1
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 9, v0
	v_lshlrev_b16 v2, 5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b8 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6mandelPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z6mandelPh, .Lfunc_end5-_Z6mandelPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           mandelGen
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         mandelGen.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPh
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6plate1Ph
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6plate1Ph.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6plate2Ph
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6plate2Ph.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6plate3Ph
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6plate3Ph.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6mandelPh
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6mandelPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
