//
// Created by yevhen on 8/1/21.
//

#include "iostream"
#include "cassert"
#include "../mmul.cuh"

__global__ void mmul_bl(const int* a, const size_t Arows, const size_t Acols,
                        const int* b, const size_t Bcols,
                        int* c, const size_t ID) {
    // get thread ids
    const unsigned int row = (blockIdx.y * blockDim.y) + threadIdx.y;
    const unsigned int col = (blockIdx.x * blockDim.x) + threadIdx.x;

    // check boundaries
    if((row < Arows) && (col < Bcols)) {
        c[row * Bcols + col] = 0;
        for(size_t k = 0; k < ID; ++k) {
            c[row * Bcols + col] += a[row*Acols + k] * b[k*Bcols + col];
        }
    }
}

void verify_results_mm_bl(const int* a, const size_t Arows, const size_t Acols,
                    const int* b, const size_t Bcols,
                    const int* c, const size_t ID) {
    for(size_t row = 0; row < Arows; ++row){
        for(size_t col = 0; col < Bcols; ++col) {
            int tmp = 0;
            for(size_t k = 0; k < ID; ++k) {
                tmp += a[row*Acols + k] * b[k*Bcols + col];
            }
            assert(c[row*Bcols + col] == tmp);
        }
    }
}


void mmul_baseline() {
    // matrix size
    // A[1024][512] * B[512, 256] -> C[1024][256]
    const int AROWS = 1024;
    const int ACOLS = 512;
    constexpr size_t ASIZE = AROWS * ACOLS;

    const int BROWS = ACOLS;
    const int BCOLS = 256;
    constexpr size_t BSIZE = BROWS * BCOLS;

    const int CROWS = AROWS;
    const int CCOLS = BCOLS;
    constexpr size_t CSIZE = CROWS * CCOLS;

    // the same as const size_t INNER_DIMENSION = BROWS
    const size_t INNER_DIMENSION = ACOLS;

    constexpr size_t ABYTES = sizeof(int) * ASIZE;
    constexpr size_t BBYTES = sizeof(int) * BSIZE;
    constexpr size_t CBYTES = sizeof(int) * CSIZE;

    // allocate device mem
    int *a = (int*) malloc(ABYTES);
    int *b = (int*) malloc(BBYTES);
    int *c = (int*) malloc(CBYTES);

    // populate arrays
    for(size_t i = 0; i < ASIZE; ++i) a[i] = rand() % 100;
    for(size_t i = 0; i < BSIZE; ++i) b[i] = rand() % 100;

    // allocate device mem
    int *d_a, *d_b, *d_c;
    cudaMalloc(&d_a, ABYTES);
    cudaMalloc(&d_b, BBYTES);
    cudaMalloc(&d_c, CBYTES);

    // copy arrays to device
    cudaMemcpy(d_a, a, ABYTES, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, b, BBYTES, cudaMemcpyHostToDevice);

    // num threads per dimension: sqrt(1024) -> 32
    // because of 2 dimensions
    const int THREADS_PER_BLOCK = 32;
    // num blocks
    // let's try to calc each scalar product on own thread
    //    C[1024][256] -> 1024*256 = 262144 threads
    const int NUM_BLOCKS = int(ceil(sqrt(1.0 * CSIZE / THREADS_PER_BLOCK)));

    const dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
    const dim3 blocks(NUM_BLOCKS, NUM_BLOCKS);

    // call matrix multiplication func
    mmul_bl<<<blocks, threads>>>(d_a, AROWS, ACOLS,
                                 d_b, BCOLS,
                                 d_c, INNER_DIMENSION);

    // get results back to CPU
    cudaMemcpy(c, d_c, CBYTES, cudaMemcpyDeviceToHost);

    // verify results
    verify_results_mm_bl(a, AROWS, ACOLS,
                   b, BCOLS,
                   c, INNER_DIMENSION);

    // free cuda mem
    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);

    // free allocated mem
    free(a);
    free(b);
    free(c);

    std::cout << "MMUL_BASELINE COMPLETED" << std::endl;
}
	.file	"tmpxft_00263f94_00000000-6_mmul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z20verify_results_mm_blPKimmS0_mS0_m
	.type	_Z20verify_results_mm_blPKimmS0_mS0_m, @function
_Z20verify_results_mm_blPKimmS0_mS0_m:
.LFB3635:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z20verify_results_mm_blPKimmS0_mS0_m, .-_Z20verify_results_mm_blPKimmS0_mS0_m
	.globl	_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim
	.type	_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim, @function
_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7mmul_blPKimmS0_mPim(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L3:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim, .-_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim
	.globl	_Z7mmul_blPKimmS0_mPim
	.type	_Z7mmul_blPKimmS0_mPim, @function
_Z7mmul_blPKimmS0_mPim:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim
	.cfi_endproc
.LFE3662:
	.size	_Z7mmul_blPKimmS0_mPim, .-_Z7mmul_blPKimmS0_mPim
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"MMUL_BASELINE COMPLETED"
	.text
	.globl	_Z13mmul_baselinev
	.type	_Z13mmul_baselinev, @function
_Z13mmul_baselinev:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$2097152, %edi
	movl	$100, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$524288, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$1048576, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r12
.L10:
	call	rand@PLT
	cltd
	idivl	%r14d
	movl	%edx, 0(%rbp,%r13,4)
	incq	%r13
	cmpq	$524288, %r13
	jne	.L10
	xorl	%r13d, %r13d
	movl	$100, %r14d
.L11:
	call	rand@PLT
	cltd
	idivl	%r14d
	movl	%edx, (%rbx,%r13,4)
	incq	%r13
	cmpq	$131072, %r13
	jne	.L11
	leaq	8(%rsp), %rdi
	movl	$2097152, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$524288, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$2097152, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$524288, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movabsq	$390842024027, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	$512, %edx
	movl	$256, %r8d
	movl	$1024, %esi
	pushq	$512
	.cfi_def_cfa_offset 128
	movq	40(%rsp), %r9
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdi
	call	_Z36__device_stub__Z7mmul_blPKimmS0_mPimPKimmS0_mPim
	popq	%rdx
	.cfi_def_cfa_offset 120
	popq	%rcx
	.cfi_def_cfa_offset 112
.L12:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$1048576, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC0(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z13mmul_baselinev, .-_Z13mmul_baselinev
	.section	.rodata.str1.1
.LC1:
	.string	"_Z7mmul_blPKimmS0_mPim"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7mmul_blPKimmS0_mPim(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//
// Created by yevhen on 8/1/21.
//


#include <hip/hip_runtime.h>
#include "iostream"
#include "cassert"
#include "../mmul.cuh"

__global__ void mmul_bl(const int* a, const size_t Arows, const size_t Acols,
                        const int* b, const size_t Bcols,
                        int* c, const size_t ID) {
    // get thread ids
    const unsigned int row = (blockIdx.y * blockDim.y) + threadIdx.y;
    const unsigned int col = (blockIdx.x * blockDim.x) + threadIdx.x;

    // check boundaries
    if((row < Arows) && (col < Bcols)) {
        c[row * Bcols + col] = 0;
        for(size_t k = 0; k < ID; ++k) {
            c[row * Bcols + col] += a[row*Acols + k] * b[k*Bcols + col];
        }
    }
}

void verify_results_mm_bl(const int* a, const size_t Arows, const size_t Acols,
                    const int* b, const size_t Bcols,
                    const int* c, const size_t ID) {
    for(size_t row = 0; row < Arows; ++row){
        for(size_t col = 0; col < Bcols; ++col) {
            int tmp = 0;
            for(size_t k = 0; k < ID; ++k) {
                tmp += a[row*Acols + k] * b[k*Bcols + col];
            }
            assert(c[row*Bcols + col] == tmp);
        }
    }
}


void mmul_baseline() {
    // matrix size
    // A[1024][512] * B[512, 256] -> C[1024][256]
    const int AROWS = 1024;
    const int ACOLS = 512;
    constexpr size_t ASIZE = AROWS * ACOLS;

    const int BROWS = ACOLS;
    const int BCOLS = 256;
    constexpr size_t BSIZE = BROWS * BCOLS;

    const int CROWS = AROWS;
    const int CCOLS = BCOLS;
    constexpr size_t CSIZE = CROWS * CCOLS;

    // the same as const size_t INNER_DIMENSION = BROWS
    const size_t INNER_DIMENSION = ACOLS;

    constexpr size_t ABYTES = sizeof(int) * ASIZE;
    constexpr size_t BBYTES = sizeof(int) * BSIZE;
    constexpr size_t CBYTES = sizeof(int) * CSIZE;

    // allocate device mem
    int *a = (int*) malloc(ABYTES);
    int *b = (int*) malloc(BBYTES);
    int *c = (int*) malloc(CBYTES);

    // populate arrays
    for(size_t i = 0; i < ASIZE; ++i) a[i] = rand() % 100;
    for(size_t i = 0; i < BSIZE; ++i) b[i] = rand() % 100;

    // allocate device mem
    int *d_a, *d_b, *d_c;
    hipMalloc(&d_a, ABYTES);
    hipMalloc(&d_b, BBYTES);
    hipMalloc(&d_c, CBYTES);

    // copy arrays to device
    hipMemcpy(d_a, a, ABYTES, hipMemcpyHostToDevice);
    hipMemcpy(d_b, b, BBYTES, hipMemcpyHostToDevice);

    // num threads per dimension: sqrt(1024) -> 32
    // because of 2 dimensions
    const int THREADS_PER_BLOCK = 32;
    // num blocks
    // let's try to calc each scalar product on own thread
    //    C[1024][256] -> 1024*256 = 262144 threads
    const int NUM_BLOCKS = int(ceil(sqrt(1.0 * CSIZE / THREADS_PER_BLOCK)));

    const dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
    const dim3 blocks(NUM_BLOCKS, NUM_BLOCKS);

    // call matrix multiplication func
    mmul_bl<<<blocks, threads>>>(d_a, AROWS, ACOLS,
                                 d_b, BCOLS,
                                 d_c, INNER_DIMENSION);

    // get results back to CPU
    hipMemcpy(c, d_c, CBYTES, hipMemcpyDeviceToHost);

    // verify results
    verify_results_mm_bl(a, AROWS, ACOLS,
                   b, BCOLS,
                   c, INNER_DIMENSION);

    // free cuda mem
    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);

    // free allocated mem
    free(a);
    free(b);
    free(c);

    std::cout << "MMUL_BASELINE COMPLETED" << std::endl;
}
	.text
	.file	"mmul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__mmul_blPKimmS0_mPim # -- Begin function _Z22__device_stub__mmul_blPKimmS0_mPim
	.type	_Z22__device_stub__mmul_blPKimmS0_mPim,@function
_Z22__device_stub__mmul_blPKimmS0_mPim: # @_Z22__device_stub__mmul_blPKimmS0_mPim
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7mmul_blPKimmS0_mPim, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__mmul_blPKimmS0_mPim, .Lfunc_end0-_Z22__device_stub__mmul_blPKimmS0_mPim
	.cfi_endproc
                                        # -- End function
	.globl	_Z20verify_results_mm_blPKimmS0_mS0_m # -- Begin function _Z20verify_results_mm_blPKimmS0_mS0_m
	.type	_Z20verify_results_mm_blPKimmS0_mS0_m,@function
_Z20verify_results_mm_blPKimmS0_mS0_m:  # @_Z20verify_results_mm_blPKimmS0_mS0_m
	.cfi_startproc
# %bb.0:                                # %._crit_edge24
	retq
.Lfunc_end1:
	.size	_Z20verify_results_mm_blPKimmS0_mS0_m, .Lfunc_end1-_Z20verify_results_mm_blPKimmS0_mS0_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z13mmul_baselinev              # -- Begin function _Z13mmul_baselinev
	.type	_Z13mmul_baselinev,@function
_Z13mmul_baselinev:                     # @_Z13mmul_baselinev
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$2097152, %edi                  # imm = 0x200000
	callq	malloc
	movq	%rax, %rbx
	movl	$524288, %edi                   # imm = 0x80000
	callq	malloc
	movq	%rax, %r14
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, %r15
	xorl	%r12d, %r12d
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r12,4)
	incq	%r12
	cmpq	$524288, %r12                   # imm = 0x80000
	jne	.LBB2_1
# %bb.2:                                # %.preheader.preheader
	xorl	%r12d, %r12d
.LBB2_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%r12,4)
	incq	%r12
	cmpq	$131072, %r12                   # imm = 0x20000
	jne	.LBB2_3
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$2097152, %esi                  # imm = 0x200000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$524288, %esi                   # imm = 0x80000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$2097152, %edx                  # imm = 0x200000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$524288, %edx                   # imm = 0x80000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$390842024027, %rdi             # imm = 0x5B0000005B
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r9
	movq	$512, (%rsp)                    # imm = 0x200
	movl	$1024, %esi                     # imm = 0x400
	movl	$512, %edx                      # imm = 0x200
	movl	$256, %r8d                      # imm = 0x100
	callq	_Z22__device_stub__mmul_blPKimmS0_mPim
.LBB2_6:
	movq	8(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$23, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z13mmul_baselinev, .Lfunc_end2-_Z13mmul_baselinev
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7mmul_blPKimmS0_mPim, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7mmul_blPKimmS0_mPim,@object  # @_Z7mmul_blPKimmS0_mPim
	.section	.rodata,"a",@progbits
	.globl	_Z7mmul_blPKimmS0_mPim
	.p2align	3, 0x0
_Z7mmul_blPKimmS0_mPim:
	.quad	_Z22__device_stub__mmul_blPKimmS0_mPim
	.size	_Z7mmul_blPKimmS0_mPim, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"MMUL_BASELINE COMPLETED"
	.size	.L.str, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7mmul_blPKimmS0_mPim"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__mmul_blPKimmS0_mPim
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7mmul_blPKimmS0_mPim
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7mmul_blPKimmS0_mPim  ; -- Begin function _Z7mmul_blPKimmS0_mPim
	.globl	_Z7mmul_blPKimmS0_mPim
	.p2align	8
	.type	_Z7mmul_blPKimmS0_mPim,@function
_Z7mmul_blPKimmS0_mPim:                 ; @_Z7mmul_blPKimmS0_mPim
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b256 s[16:23], s[0:1], 0x0
	v_bfe_u32 v4, v0, 10, 10
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s4, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[4:5]
	v_mov_b32_e32 v2, v3
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[18:19], v[1:2]
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_load_b32 s8, s[2:3], 0xc
	s_load_b256 s[0:7], s[0:1], 0x20
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s8, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v4
	v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[2:3]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.2:
	v_mad_u64_u32 v[4:5], null, v1, s0, 0
	s_cmp_eq_u64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v5
	v_mad_u64_u32 v[5:6], null, v1, s1, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[4:5]
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v0, 0
	global_store_b32 v[2:3], v0, off
	s_cbranch_scc1 .LBB0_5
; %bb.3:                                ; %.lr.ph
	v_mad_u64_u32 v[6:7], null, v1, s20, 0
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v1, s21, v[7:8]
	v_mov_b32_e32 v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v1, v[6:7], off
	global_load_b32 v10, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	s_add_u32 s4, s4, -1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_addc_u32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u64 s[4:5], 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v10, v1, v[0:1]
	v_mov_b32_e32 v0, v8
	global_store_b32 v[2:3], v8, off
	s_cbranch_scc1 .LBB0_4
.LBB0_5:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7mmul_blPKimmS0_mPim
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7mmul_blPKimmS0_mPim, .Lfunc_end0-_Z7mmul_blPKimmS0_mPim
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7mmul_blPKimmS0_mPim
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z7mmul_blPKimmS0_mPim.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
