// Vector addition: r = a + b.

#include <stdio.h>
#include <iostream>
#include <iomanip>

using std::cout;
using std::cerr;
using std::endl;

// Handle CUDA errors

void handle_error(cudaError_t err, const char *file, int line) {
	if (err != cudaSuccess) {
		cout << cudaGetErrorString(err) << " in " << file << " at line " << line
				<< endl;
		exit(EXIT_FAILURE);
	}
}

#define CHECK(err) (handle_error(err, __FILE__, __LINE__))

// This will output the proper error string when calling cudaGetLastError

void __handle_last_cuda_error(const char *errorMessage, const char *file,
		const int line) {
	cudaError_t err = cudaGetLastError();

	if (err != cudaSuccess) {
		cout << cudaGetErrorString(err) << " in " << file << " at line " << line
				<< endl;
		exit(EXIT_FAILURE);
	}
}

#define handle_last_cuda_error(msg) __handle_last_cuda_error(msg, __FILE__, __LINE__)

void vector_add_cpu(int n, int* a, int* b, int* r) {
	for (int i = 0; i < n; i++)
		r[i] = a[i] + b[i];
}

__global__
void vector_add_kernel(int n, int const *a, int const *b, int *r) {
	int i = threadIdx.x + blockDim.x * blockIdx.x;

	if (i < n) {
		r[i] = a[i] + b[i];
	}
}

void vector_add_gpu(int n, int const *a, int const *b, int *r) {
	// Launch the Vector Add CUDA Kernel
	int TPB = 256; // Threads per block.
	int BPG = (n + TPB - 1) / TPB; // Blocks per grid
	cout << "CUDA kernel launch with " << BPG << " blocks of " << TPB
			<< " threads" << endl;
	vector_add_kernel<<<BPG, TPB>>>(n, a, b, r);
	CHECK(cudaGetLastError());
}

/**
 * Host main routine
 */
int main(void) {
	// Print the vector length to be used, and compute its size
	int numElements = 50000;
	size_t size = numElements * sizeof(int);
	cout << "[Vector addition of " << numElements << " elements]" << endl;

	int *h_a = (int *) malloc(size);
	int *h_b = (int *) malloc(size);
	int *h_r = (int *) malloc(size);
	int *r = (int *) malloc(size);

	// Verify that allocations succeeded
	if (h_a == NULL || h_b == NULL || h_r == NULL || r == NULL) {
		cerr << "Failed to allocate host vectors!" << endl;
		exit(EXIT_FAILURE);
	}

	// Initialize the host input vectors
	for (int i = 0; i < numElements; ++i) {
		h_a[i] = rand();
		h_b[i] = rand();
	}

	cout << "Copy input data from the host memory to the CUDA device" << endl;
	int *d_a = nullptr;
	CHECK(cudaMalloc(&d_a, size));

	int *d_b = nullptr;
	CHECK(cudaMalloc(&d_b, size));

	int *d_r = nullptr;
	CHECK(cudaMalloc(&d_r, size));

	CHECK(cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice));
	CHECK(cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice));

	// Launch the Vector Add CUDA Kernel
	vector_add_gpu(numElements, d_a, d_b, d_r);

	cout << "Copy output data from the CUDA device to the host memory" << endl;
	CHECK(cudaMemcpy(h_r, d_r, size, cudaMemcpyDeviceToHost));

	// Verify that the result vector is correct
	vector_add_cpu(numElements, h_a, h_b, r);

	for (int i = 0; i < numElements; ++i) {
		if (h_r[i] != r[i]) {
			cerr << "Result verification failed at element " << i << "!"
					<< endl;
			exit(EXIT_FAILURE);
		}
	}

	cout << "Test PASSED" << endl;

	// Free device global memory
	CHECK(cudaFree(d_a));
	CHECK(cudaFree(d_b));
	CHECK(cudaFree(d_r));

	// Free host memory
	free(h_a);
	free(h_b);
	free(h_r);
	free(r);

	cout << "Done" << endl;
	return 0;
}


	.file	"tmpxft_00201fc6_00000000-6_vect_add_cuda.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3922:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3922:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4592:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4592:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" in "
.LC1:
	.string	" at line "
	.text
	.globl	_Z12handle_error9cudaErrorPKci
	.type	_Z12handle_error9cudaErrorPKci, @function
_Z12handle_error9cudaErrorPKci:
.LFB3915:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L3
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edx, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L3:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3915:
	.size	_Z12handle_error9cudaErrorPKci, .-_Z12handle_error9cudaErrorPKci
	.globl	_Z24__handle_last_cuda_errorPKcS0_i
	.type	_Z24__handle_last_cuda_errorPKcS0_i, @function
_Z24__handle_last_cuda_errorPKcS0_i:
.LFB3916:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 32
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L9
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L9:
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3916:
	.size	_Z24__handle_last_cuda_errorPKcS0_i, .-_Z24__handle_last_cuda_errorPKcS0_i
	.globl	_Z14vector_add_cpuiPiS_S_
	.type	_Z14vector_add_cpuiPiS_S_, @function
_Z14vector_add_cpuiPiS_S_:
.LFB3917:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L13:
	cmpl	%eax, %edi
	jle	.L15
	movl	(%rdx,%rax,4), %r8d
	addl	(%rsi,%rax,4), %r8d
	movl	%r8d, (%rcx,%rax,4)
	incq	%rax
	jmp	.L13
.L15:
	ret
	.cfi_endproc
.LFE3917:
	.size	_Z14vector_add_cpuiPiS_S_, .-_Z14vector_add_cpuiPiS_S_
	.globl	_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi
	.type	_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi, @function
_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi:
.LFB3944:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17vector_add_kerneliPKiS0_Pi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3944:
	.size	_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi, .-_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi
	.globl	_Z17vector_add_kerneliPKiS0_Pi
	.type	_Z17vector_add_kerneliPKiS0_Pi, @function
_Z17vector_add_kerneliPKiS0_Pi:
.LFB3945:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi
	.cfi_endproc
.LFE3945:
	.size	_Z17vector_add_kerneliPKiS0_Pi, .-_Z17vector_add_kerneliPKiS0_Pi
	.section	.rodata.str1.1
.LC2:
	.string	"CUDA kernel launch with "
.LC3:
	.string	" blocks of "
.LC4:
	.string	" threads"
.LC5:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/sergei-romanenko/openacc-samples/main/vect_add_cuda/src/vect_add_cuda.cu"
	.text
	.globl	_Z14vector_add_gpuiPKiS0_Pi
	.type	_Z14vector_add_gpuiPKiS0_Pi, @function
_Z14vector_add_gpuiPKiS0_Pi:
.LFB3918:
	.cfi_startproc
	endbr64
	leal	255(%rdi), %eax
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rcx, %r14
	movl	$256, %ecx
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	cltd
	idivl	%ecx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edi, %ebp
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rsi, %r12
	leaq	.LC2(%rip), %rsi
	movl	%eax, %ebx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$256, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	%ebx, 8(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	salq	$8, %rdx
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	%r14, %rcx
	movq	%r13, %rdx
	movq	%r12, %rsi
	movl	%ebp, %edi
	call	_Z44__device_stub__Z17vector_add_kerneliPKiS0_PiiPKiS0_Pi
.L22:
	call	cudaGetLastError@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	movl	$59, %edx
	leaq	.LC5(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 40
	movl	%eax, %edi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z12handle_error9cudaErrorPKci
	.cfi_endproc
.LFE3918:
	.size	_Z14vector_add_gpuiPKiS0_Pi, .-_Z14vector_add_gpuiPKiS0_Pi
	.section	.rodata.str1.1
.LC6:
	.string	"[Vector addition of "
.LC7:
	.string	" elements]"
.LC8:
	.string	"Failed to allocate host vectors!"
.LC9:
	.string	"Copy input data from the host memory to the CUDA device"
.LC10:
	.string	"Copy output data from the CUDA device to the host memory"
.LC11:
	.string	"Result verification failed at element "
.LC12:
	.string	"!"
.LC13:
	.string	"Test PASSED"
.LC14:
	.string	"Done"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3919:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	_ZSt4cout(%rip), %r15
	leaq	.LC6(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r15, %rdi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$50000, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$200000, %edi
	call	malloc@PLT
	movl	$200000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$200000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$200000, %edi
	movq	%rax, %r14
	call	malloc@PLT
	testq	%r12, %r12
	je	.L25
	testq	%rbp, %rbp
	je	.L25
	testq	%r14, %r14
	je	.L25
	movq	%rax, %r13
	xorl	%ebx, %ebx
	testq	%rax, %rax
	jne	.L26
.L25:
	leaq	.LC8(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	jmp	.L37
.L26:
	call	rand@PLT
	movl	%eax, (%r12,%rbx)
	call	rand@PLT
	movl	%eax, 0(%rbp,%rbx)
	addq	$4, %rbx
	cmpq	$200000, %rbx
	jne	.L26
	leaq	.LC9(%rip), %rsi
	movq	%r15, %rdi
	xorl	%ebx, %ebx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	xorl	%eax, %eax
	movq	%rsp, %rdi
	movl	$200000, %esi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movl	$90, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	xorl	%edx, %edx
	leaq	8(%rsp), %rdi
	movl	$200000, %esi
	movq	%rdx, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$93, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	xorl	%ecx, %ecx
	leaq	16(%rsp), %rdi
	movl	$200000, %esi
	movq	%rcx, 16(%rsp)
	call	cudaMalloc@PLT
	movl	$96, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$200000, %edx
	call	cudaMemcpy@PLT
	movl	$98, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$200000, %edx
	call	cudaMemcpy@PLT
	movl	$99, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movl	$50000, %edi
	movq	(%rsp), %rsi
	call	_Z14vector_add_gpuiPKiS0_Pi
	leaq	.LC10(%rip), %rsi
	movq	%r15, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$200000, %edx
	call	cudaMemcpy@PLT
	movl	$105, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	%r13, %rcx
	movq	%rbp, %rdx
	movq	%r12, %rsi
	movl	$50000, %edi
	call	_Z14vector_add_cpuiPiS_S_
.L29:
	movl	0(%r13,%rbx,4), %eax
	cmpl	%eax, (%r14,%rbx,4)
	je	.L28
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
.L37:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L28:
	incq	%rbx
	cmpq	$50000, %rbx
	jne	.L29
	leaq	.LC13(%rip), %rsi
	movq	%r15, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movl	$121, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	$122, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movl	$123, %edx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z12handle_error9cudaErrorPKci
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	leaq	.LC14(%rip), %rsi
	movq	%r15, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3919:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z17vector_add_kerneliPKiS0_Pi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3947:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17vector_add_kerneliPKiS0_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3947:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Vector addition: r = a + b.


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <iomanip>

using std::cout;
using std::cerr;
using std::endl;

// Handle CUDA errors

void handle_error(hipError_t err, const char *file, int line) {
	if (err != hipSuccess) {
		cout << hipGetErrorString(err) << " in " << file << " at line " << line
				<< endl;
		exit(EXIT_FAILURE);
	}
}

#define CHECK(err) (handle_error(err, __FILE__, __LINE__))

// This will output the proper error string when calling cudaGetLastError

void __handle_last_cuda_error(const char *errorMessage, const char *file,
		const int line) {
	hipError_t err = hipGetLastError();

	if (err != hipSuccess) {
		cout << hipGetErrorString(err) << " in " << file << " at line " << line
				<< endl;
		exit(EXIT_FAILURE);
	}
}

#define handle_last_cuda_error(msg) __handle_last_cuda_error(msg, __FILE__, __LINE__)

void vector_add_cpu(int n, int* a, int* b, int* r) {
	for (int i = 0; i < n; i++)
		r[i] = a[i] + b[i];
}

__global__
void vector_add_kernel(int n, int const *a, int const *b, int *r) {
	int i = threadIdx.x + blockDim.x * blockIdx.x;

	if (i < n) {
		r[i] = a[i] + b[i];
	}
}

void vector_add_gpu(int n, int const *a, int const *b, int *r) {
	// Launch the Vector Add CUDA Kernel
	int TPB = 256; // Threads per block.
	int BPG = (n + TPB - 1) / TPB; // Blocks per grid
	cout << "CUDA kernel launch with " << BPG << " blocks of " << TPB
			<< " threads" << endl;
	vector_add_kernel<<<BPG, TPB>>>(n, a, b, r);
	CHECK(hipGetLastError());
}

/**
 * Host main routine
 */
int main(void) {
	// Print the vector length to be used, and compute its size
	int numElements = 50000;
	size_t size = numElements * sizeof(int);
	cout << "[Vector addition of " << numElements << " elements]" << endl;

	int *h_a = (int *) malloc(size);
	int *h_b = (int *) malloc(size);
	int *h_r = (int *) malloc(size);
	int *r = (int *) malloc(size);

	// Verify that allocations succeeded
	if (h_a == NULL || h_b == NULL || h_r == NULL || r == NULL) {
		cerr << "Failed to allocate host vectors!" << endl;
		exit(EXIT_FAILURE);
	}

	// Initialize the host input vectors
	for (int i = 0; i < numElements; ++i) {
		h_a[i] = rand();
		h_b[i] = rand();
	}

	cout << "Copy input data from the host memory to the CUDA device" << endl;
	int *d_a = nullptr;
	CHECK(hipMalloc(&d_a, size));

	int *d_b = nullptr;
	CHECK(hipMalloc(&d_b, size));

	int *d_r = nullptr;
	CHECK(hipMalloc(&d_r, size));

	CHECK(hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice));
	CHECK(hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice));

	// Launch the Vector Add CUDA Kernel
	vector_add_gpu(numElements, d_a, d_b, d_r);

	cout << "Copy output data from the CUDA device to the host memory" << endl;
	CHECK(hipMemcpy(h_r, d_r, size, hipMemcpyDeviceToHost));

	// Verify that the result vector is correct
	vector_add_cpu(numElements, h_a, h_b, r);

	for (int i = 0; i < numElements; ++i) {
		if (h_r[i] != r[i]) {
			cerr << "Result verification failed at element " << i << "!"
					<< endl;
			exit(EXIT_FAILURE);
		}
	}

	cout << "Test PASSED" << endl;

	// Free device global memory
	CHECK(hipFree(d_a));
	CHECK(hipFree(d_b));
	CHECK(hipFree(d_r));

	// Free host memory
	free(h_a);
	free(h_b);
	free(h_r);
	free(r);

	cout << "Done" << endl;
	return 0;
}


	.text
	.file	"vect_add_cuda.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z12handle_error10hipError_tPKci # -- Begin function _Z12handle_error10hipError_tPKci
	.type	_Z12handle_error10hipError_tPKci,@function
_Z12handle_error10hipError_tPKci:       # @_Z12handle_error10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB0_2
# %bb.1:
	retq
.LBB0_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	callq	hipGetErrorString
	movl	$_ZSt4cout, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z12handle_error10hipError_tPKci, .Lfunc_end0-_Z12handle_error10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__handle_last_cuda_errorPKcS0_i # -- Begin function _Z24__handle_last_cuda_errorPKcS0_i
	.type	_Z24__handle_last_cuda_errorPKcS0_i,@function
_Z24__handle_last_cuda_errorPKcS0_i:    # @_Z24__handle_last_cuda_errorPKcS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 32
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cout, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z24__handle_last_cuda_errorPKcS0_i, .Lfunc_end1-_Z24__handle_last_cuda_errorPKcS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z14vector_add_cpuiPiS_S_       # -- Begin function _Z14vector_add_cpuiPiS_S_
	.type	_Z14vector_add_cpuiPiS_S_,@function
_Z14vector_add_cpuiPiS_S_:              # @_Z14vector_add_cpuiPiS_S_
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edi, %eax
	xorl	%edi, %edi
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rdx,%rdi,4), %r8d
	addl	(%rsi,%rdi,4), %r8d
	movl	%r8d, (%rcx,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %rax
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z14vector_add_cpuiPiS_S_, .Lfunc_end2-_Z14vector_add_cpuiPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__vector_add_kerneliPKiS0_Pi # -- Begin function _Z32__device_stub__vector_add_kerneliPKiS0_Pi
	.type	_Z32__device_stub__vector_add_kerneliPKiS0_Pi,@function
_Z32__device_stub__vector_add_kerneliPKiS0_Pi: # @_Z32__device_stub__vector_add_kerneliPKiS0_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17vector_add_kerneliPKiS0_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z32__device_stub__vector_add_kerneliPKiS0_Pi, .Lfunc_end3-_Z32__device_stub__vector_add_kerneliPKiS0_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z14vector_add_gpuiPKiS0_Pi     # -- Begin function _Z14vector_add_gpuiPKiS0_Pi
	.type	_Z14vector_add_gpuiPKiS0_Pi,@function
_Z14vector_add_gpuiPKiS0_Pi:            # @_Z14vector_add_gpuiPKiS0_Pi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movl	%edi, %r12d
	leal	255(%r12), %eax
	leal	510(%r12), %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$8, %r13d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.3, %esi
	movl	$11, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbp, %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.4, %esi
	movl	$8, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbp), %rax
	movq	-24(%rax), %rdi
	addq	%rbp, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbp, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	btsq	$32, %r13
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movl	%r12d, %edi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	_Z32__device_stub__vector_add_kerneliPKiS0_Pi
.LBB4_2:
	callq	hipGetLastError
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$61, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z12handle_error10hipError_tPKci # TAILCALL
.Lfunc_end4:
	.size	_Z14vector_add_gpuiPKiS0_Pi, .Lfunc_end4-_Z14vector_add_gpuiPKiS0_Pi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$50000, %esi                    # imm = 0xC350
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.7, %esi
	movl	$10, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$200000, %edi                   # imm = 0x30D40
	callq	malloc
	movq	%rax, %rbx
	movl	$200000, %edi                   # imm = 0x30D40
	callq	malloc
	movq	%rax, %r14
	movl	$200000, %edi                   # imm = 0x30D40
	callq	malloc
	movq	%rax, %r15
	movl	$200000, %edi                   # imm = 0x30D40
	callq	malloc
	testq	%rbx, %rbx
	je	.LBB5_11
# %bb.1:
	testq	%r14, %r14
	je	.LBB5_11
# %bb.2:
	testq	%r15, %r15
	je	.LBB5_11
# %bb.3:
	movq	%rax, %r12
	testq	%rax, %rax
	je	.LBB5_11
# %bb.4:                                # %.preheader.preheader
	xorl	%r13d, %r13d
.LBB5_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movl	%eax, (%rbx,%r13,4)
	callq	rand
	movl	%eax, (%r14,%r13,4)
	incq	%r13
	cmpq	$50000, %r13                    # imm = 0xC350
	jne	.LBB5_5
# %bb.6:
	movl	$_ZSt4cout, %r13d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$55, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%ebp, %ebp
	leaq	8(%rsp), %rdi
	movq	%rbp, (%rdi)
	movl	$200000, %esi                   # imm = 0x30D40
	callq	hipMalloc
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$92, %edx
	callq	_Z12handle_error10hipError_tPKci
	leaq	16(%rsp), %r13
	movq	%rbp, (%r13)
	movl	$200000, %esi                   # imm = 0x30D40
	movq	%r13, %rdi
	callq	hipMalloc
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$95, %edx
	callq	_Z12handle_error10hipError_tPKci
	movq	%rsp, %rdi
	movq	%rbp, (%rdi)
	movl	$200000, %esi                   # imm = 0x30D40
	callq	hipMalloc
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$98, %edx
	callq	_Z12handle_error10hipError_tPKci
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$200000, %edx                   # imm = 0x30D40
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$100, %edx
	callq	_Z12handle_error10hipError_tPKci
	movq	(%r13), %rdi
	movl	$200000, %edx                   # imm = 0x30D40
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$101, %edx
	callq	_Z12handle_error10hipError_tPKci
	leaq	8(%rsp), %rax
	movq	(%rax), %rsi
	movq	(%r13), %rdx
	movq	%rsp, %rax
	movq	(%rax), %rcx
	movl	$50000, %edi                    # imm = 0xC350
	callq	_Z14vector_add_gpuiPKiS0_Pi
	movl	$_ZSt4cout, %edi
	movl	$.L.str.10, %esi
	movl	$56, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cout, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rsp, %rax
	movq	(%rax), %rsi
	movl	$200000, %edx                   # imm = 0x30D40
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$107, %edx
	callq	_Z12handle_error10hipError_tPKci
.LBB5_7:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rbp,4), %eax
	addl	(%rbx,%rbp,4), %eax
	movl	%eax, (%r12,%rbp,4)
	incq	%rbp
	cmpq	$50000, %rbp                    # imm = 0xC350
	jne	.LBB5_7
# %bb.8:                                # %_Z14vector_add_cpuiPiS_S_.exit.preheader.preheader
	xorl	%r13d, %r13d
.LBB5_9:                                # %_Z14vector_add_cpuiPiS_S_.exit.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r13,4), %eax
	cmpl	(%r12,%r13,4), %eax
	jne	.LBB5_10
# %bb.13:                               # %_Z14vector_add_cpuiPiS_S_.exit
                                        #   in Loop: Header=BB5_9 Depth=1
	incq	%r13
	cmpq	$50000, %r13                    # imm = 0xC350
	jne	.LBB5_9
# %bb.14:
	movl	$_ZSt4cout, %r13d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$123, %edx
	callq	_Z12handle_error10hipError_tPKci
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$124, %edx
	callq	_Z12handle_error10hipError_tPKci
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$125, %edx
	callq	_Z12handle_error10hipError_tPKci
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_10:
	.cfi_def_cfa_offset 80
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.11, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movl	$.L.str.12, %esi
	movq	%rax, %rdi
.LBB5_12:
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.LBB5_11:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.8, %esi
	jmp	.LBB5_12
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17vector_add_kerneliPKiS0_Pi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" in "
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" at line "
	.size	.L.str.1, 10

	.type	_Z17vector_add_kerneliPKiS0_Pi,@object # @_Z17vector_add_kerneliPKiS0_Pi
	.section	.rodata,"a",@progbits
	.globl	_Z17vector_add_kerneliPKiS0_Pi
	.p2align	3, 0x0
_Z17vector_add_kerneliPKiS0_Pi:
	.quad	_Z32__device_stub__vector_add_kerneliPKiS0_Pi
	.size	_Z17vector_add_kerneliPKiS0_Pi, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"CUDA kernel launch with "
	.size	.L.str.2, 25

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" blocks of "
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	" threads"
	.size	.L.str.4, 9

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/sergei-romanenko/openacc-samples/main/vect_add_cuda/src/vect_add_cuda.hip"
	.size	.L.str.5, 136

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"[Vector addition of "
	.size	.L.str.6, 21

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	" elements]"
	.size	.L.str.7, 11

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate host vectors!"
	.size	.L.str.8, 33

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Copy input data from the host memory to the CUDA device"
	.size	.L.str.9, 56

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Copy output data from the CUDA device to the host memory"
	.size	.L.str.10, 57

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Result verification failed at element "
	.size	.L.str.11, 39

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"!"
	.size	.L.str.12, 2

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Test PASSED"
	.size	.L.str.13, 12

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Done"
	.size	.L.str.14, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17vector_add_kerneliPKiS0_Pi"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__vector_add_kerneliPKiS0_Pi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z17vector_add_kerneliPKiS0_Pi
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17vector_add_kerneliPKiS0_Pi ; -- Begin function _Z17vector_add_kerneliPKiS0_Pi
	.globl	_Z17vector_add_kerneliPKiS0_Pi
	.p2align	8
	.type	_Z17vector_add_kerneliPKiS0_Pi,@function
_Z17vector_add_kerneliPKiS0_Pi:         ; @_Z17vector_add_kerneliPKiS0_Pi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17vector_add_kerneliPKiS0_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17vector_add_kerneliPKiS0_Pi, .Lfunc_end0-_Z17vector_add_kerneliPKiS0_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17vector_add_kerneliPKiS0_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17vector_add_kerneliPKiS0_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
