#include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];

// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;

int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {

output >>= 1;
int memPos =  yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;

// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();

int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();

if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();

memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
}
	.file	"tmpxft_002a6a6a_00000000-6_Find3DMinMax.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
	.type	_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, @function
_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii, .-_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
	.globl	_Z12Find3DMinMaxPiPfS0_S0_iii
	.type	_Z12Find3DMinMaxPiPfS0_S0_iii, @function
_Z12Find3DMinMaxPiPfS0_S0_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z12Find3DMinMaxPiPfS0_S0_iiiPiPfS0_S0_iii
	.cfi_endproc
.LFE2033:
	.size	_Z12Find3DMinMaxPiPfS0_S0_iii, .-_Z12Find3DMinMaxPiPfS0_S0_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12Find3DMinMaxPiPfS0_S0_iii"
.LC1:
	.string	"d_Threshold"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12Find3DMinMaxPiPfS0_S0_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL11d_Threshold(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL11d_Threshold
	.comm	_ZL11d_Threshold,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Find3DMinMax(int *d_Result, float *d_Data1, float *d_Data2, float *d_Data3, int width, int pitch, int height)
{
// Data cache
__shared__ float data1[3*(MINMAX_W + 2)];
__shared__ float data2[3*(MINMAX_W + 2)];
__shared__ float data3[3*(MINMAX_W + 2)];
__shared__ float ymin1[(MINMAX_W + 2)];
__shared__ float ymin2[(MINMAX_W + 2)];
__shared__ float ymin3[(MINMAX_W + 2)];
__shared__ float ymax1[(MINMAX_W + 2)];
__shared__ float ymax2[(MINMAX_W + 2)];
__shared__ float ymax3[(MINMAX_W + 2)];

// Current tile and apron limits, relative to row start
const int tx = threadIdx.x;
const int xStart = blockIdx.x*MINMAX_W;
const int xEnd = xStart + MINMAX_W - 1;
const int xReadPos = xStart + tx - WARP_SIZE;
const int xWritePos = xStart + tx;
const int xEndClamped = min(xEnd, width - 1);
int memWid = MINMAX_W + 2;

int memPos0 = (tx - WARP_SIZE + 1);
int memPos1 = (tx - WARP_SIZE + 1);
int yq = 0;
unsigned int output = 0;
for (int y=0;y<32+2;y++) {

output >>= 1;
int memPos =  yq*memWid + (tx - WARP_SIZE + 1);
int yp = 32*blockIdx.y + y - 1;
yp = max(yp, 0);
yp = min(yp, height-1);
int readStart = yp*pitch;

// Set the entire data cache contents
if (tx>=(WARP_SIZE-1)) {
if (xReadPos<0) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else if (xReadPos>=width) {
data1[memPos] = 0;
data2[memPos] = 0;
data3[memPos] = 0;
} else {
data1[memPos] = d_Data1[readStart + xReadPos];
data2[memPos] = d_Data2[readStart + xReadPos];
data3[memPos] = d_Data3[readStart + xReadPos];
}
}
__syncthreads();

int memPos2 = yq*memWid + tx;
if (y>1) {
if (tx<memWid) {
float min1 = fminf(fminf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float min2 = fminf(fminf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float min3 = fminf(fminf(data3[memPos0], data3[memPos1]), data3[memPos2]);
float max1 = fmaxf(fmaxf(data1[memPos0], data1[memPos1]), data1[memPos2]);
float max2 = fmaxf(fmaxf(data2[memPos0], data2[memPos1]), data2[memPos2]);
float max3 = fmaxf(fmaxf(data3[memPos0], data3[memPos1]), data3[memPos2]);
ymin1[tx] = min1;
ymin2[tx] = fminf(fminf(min1, min2), min3);
ymin3[tx] = min3;
ymax1[tx] = max1;
ymax2[tx] = fmaxf(fmaxf(max1, max2), max3);
ymax3[tx] = max3;
}
}
__syncthreads();

if (y>1) {
if (tx<MINMAX_W) {
if (xWritePos<=xEndClamped) {
float minv = fminf(fminf(fminf(fminf(fminf(ymin2[tx], ymin2[tx+2]), ymin1[tx+1]), ymin3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
minv = fminf(minv, d_Threshold[1]);
float maxv = fmaxf(fmaxf(fmaxf(fmaxf(fmaxf(ymax2[tx], ymax2[tx+2]), ymax1[tx+1]), ymax3[tx+1]), data2[memPos0+1]), data2[memPos2+1]);
maxv = fmaxf(maxv, d_Threshold[0]);
if (data2[memPos1+1]<minv || data2[memPos1+1]>maxv)
output |= 0x80000000;
}
}
}
__syncthreads();

memPos0 = memPos1;
memPos1 = memPos2;
yq = (yq<2 ? yq+1 : 0);
}
if (tx<MINMAX_W && xWritePos<width) {
int writeStart = blockIdx.y*pitch + xWritePos;
d_Result[writeStart] = output;
}
}
	.text
	.file	"Find3DMinMax.hip"
	.globl	_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii # -- Begin function _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
	.type	_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii,@function
_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii: # @_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12Find3DMinMaxPiPfS0_S0_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12Find3DMinMaxPiPfS0_S0_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$d_Threshold, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_Threshold,@object             # @d_Threshold
	.local	d_Threshold
	.comm	d_Threshold,8,4
	.type	_Z12Find3DMinMaxPiPfS0_S0_iii,@object # @_Z12Find3DMinMaxPiPfS0_S0_iii
	.section	.rodata,"a",@progbits
	.globl	_Z12Find3DMinMaxPiPfS0_S0_iii
	.p2align	3, 0x0
_Z12Find3DMinMaxPiPfS0_S0_iii:
	.quad	_Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
	.size	_Z12Find3DMinMaxPiPfS0_S0_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12Find3DMinMaxPiPfS0_S0_iii"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"d_Threshold"
	.size	.L__unnamed_2, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__Find3DMinMaxPiPfS0_S0_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_Threshold
	.addrsig_sym _Z12Find3DMinMaxPiPfS0_S0_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12Find3DMinMaxPiPfS0_S0_iii ; -- Begin function _Z12Find3DMinMaxPiPfS0_S0_iii
	.globl	_Z12Find3DMinMaxPiPfS0_S0_iii
	.p2align	8
	.type	_Z12Find3DMinMaxPiPfS0_S0_iii,@function
_Z12Find3DMinMaxPiPfS0_S0_iii:          ; @_Z12Find3DMinMaxPiPfS0_S0_iii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b256 s[16:23], s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_Threshold@rel32@lo+4
	s_addc_u32 s3, s3, d_Threshold@rel32@hi+12
	s_mul_i32 s0, s14, 0x7e
	s_load_b64 s[12:13], s[2:3], 0x0
	v_add_nc_u32_e32 v1, s0, v0
	s_add_i32 s4, s0, 0x7d
	v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v2, -15, v0
	v_lshlrev_b32_e32 v6, 2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, -16, v1
	s_lshl_b32 s5, s15, 5
	v_mov_b32_e32 v12, v2
	v_cmp_lt_u32_e32 vcc_lo, 14, v0
	v_cmp_gt_u32_e64 s1, 0x80, v0
	v_cmp_gt_u32_e64 s0, 0x7e, v0
	v_mov_b32_e32 v13, v2
	v_add_nc_u32_e32 v3, 0x1800, v6
	v_add_nc_u32_e32 v4, 0x1a00, v6
	v_add_nc_u32_e32 v5, 0x1c00, v6
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s8, -1
	s_add_i32 s7, s10, -1
	s_min_i32 s4, s4, s3
	s_add_u32 s10, s18, 0xffffffc0
	s_addc_u32 s11, s19, -1
	v_cmp_le_i32_e64 s3, s8, v7
	v_add_nc_u32_e32 v7, 0x1200, v6
	v_add_nc_u32_e32 v8, 0x1400, v6
	v_add_nc_u32_e32 v9, 0x1600, v6
	s_add_u32 s14, s20, 0xffffffc0
	v_mov_b32_e32 v6, 0
	v_cmp_lt_i32_e64 s2, 15, v1
	v_cmp_ge_i32_e64 s4, s4, v1
	v_ashrrev_i32_e32 v10, 31, v1
	s_addc_u32 s18, s21, -1
	s_add_u32 s19, s22, 0xffffffc0
	s_addc_u32 s20, s23, -1
	s_add_i32 s21, s5, -1
	s_mov_b32 s22, 0
	s_mov_b32 s23, 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_lshl_b32 s6, s22, 7
	s_and_saveexec_b32 s24, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v14, s6, v2
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s5
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $sgpr5
	s_and_saveexec_b32 s26, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshlrev_b32_e32 v15, 2, v14
	s_mov_b32 s5, 0
	ds_store_2addr_stride64_b32 v15, v11, v11 offset1:6
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_saveexec_b32 s26, s26
	v_mov_b32_e32 v15, s5
	s_xor_b32 exec_lo, exec_lo, s26
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s5, s21, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_max_i32 s5, s5, 0
	s_min_i32 s5, s5, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s9
	s_ashr_i32 s27, s5, 31
	v_add_co_u32 v15, s5, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s5, s27, v10, s5
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s5, s10, v15
	v_add_co_ci_u32_e64 v18, s5, s11, v16, s5
	v_add_co_u32 v19, s5, s14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, s5, s18, v16, s5
	v_add_co_u32 v15, s5, s19, v15
	v_add_co_ci_u32_e64 v16, s5, s20, v16, s5
	global_load_b32 v17, v[17:18], off
	global_load_b32 v18, v[19:20], off
	global_load_b32 v15, v[15:16], off
	v_lshlrev_b32_e32 v16, 2, v14
	s_waitcnt vmcnt(1)
	ds_store_2addr_stride64_b32 v16, v17, v18 offset1:6
.LBB0_7:                                ; %Flow174
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
.LBB0_8:                                ; %Flow175
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_saveexec_b32 s5, s25
	v_lshlrev_b32_e32 v14, 2, v14
	s_xor_b32 exec_lo, exec_lo, s5
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_1 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	ds_store_2addr_stride64_b32 v14, v11, v11 offset1:6
.LBB0_10:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	ds_store_b32 v14, v15 offset:3072
.LBB0_11:                               ; %Flow176
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	v_add_nc_u32_e32 v14, s6, v0
	s_cmp_gt_u32 s23, 1
	v_lshlrev_b32_e32 v13, 2, v13
	v_lshlrev_b32_e32 v16, 2, v12
	s_cselect_b32 s5, -1, 0
	v_lshlrev_b32_e32 v15, 2, v14
	s_and_b32 s24, s1, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s6, s24
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_1 Depth=1
	ds_load_2addr_stride64_b32 v[17:18], v13 offset1:6
	ds_load_2addr_stride64_b32 v[19:20], v16 offset1:6
	ds_load_2addr_stride64_b32 v[21:22], v15 offset1:6
	ds_load_b32 v23, v13 offset:3072
	ds_load_b32 v24, v16 offset:3072
	ds_load_b32 v25, v15 offset:3072
	s_waitcnt lgkmcnt(3)
	v_min3_f32 v26, v17, v19, v21
	v_min3_f32 v27, v18, v20, v22
	v_max3_f32 v17, v17, v19, v21
	s_waitcnt lgkmcnt(0)
	v_min3_f32 v28, v23, v24, v25
	v_max3_f32 v18, v18, v20, v22
	v_max3_f32 v19, v23, v24, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_f32 v20, v26, v27, v28
	v_max3_f32 v18, v17, v18, v19
	ds_store_b32 v3, v26
	ds_store_b32 v4, v20
	ds_store_b32 v5, v28
	ds_store_b32 v7, v17
	ds_store_b32 v8, v18
	ds_store_b32 v9, v19
.LBB0_13:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_lshrrev_b32_e32 v6, 1, v6
	s_and_b32 s5, s0, s5
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, s4
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s24, s5
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_1 Depth=1
	ds_load_2addr_b32 v[17:18], v4 offset1:2
	ds_load_b32 v21, v3 offset:4
	ds_load_2addr_b32 v[19:20], v8 offset1:2
	ds_load_b32 v22, v7 offset:4
	ds_load_b32 v23, v5 offset:4
	ds_load_b32 v16, v16 offset:1540
	ds_load_b32 v13, v13 offset:1540
	ds_load_b32 v24, v9 offset:4
	ds_load_b32 v15, v15 offset:1540
	s_waitcnt lgkmcnt(7)
	v_min3_f32 v17, v17, v18, v21
	s_waitcnt lgkmcnt(5)
	v_max3_f32 v18, v19, v20, v22
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min3_f32 v17, v17, v23, v13
	s_waitcnt lgkmcnt(1)
	v_max3_f32 v13, v18, v24, v13
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_f32 v17, v17, v15, s13
	v_max3_f32 v13, v13, v15, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s5, v16, v17
	v_cmp_gt_f32_e64 s6, v16, v13
	v_or_b32_e32 v13, 0x80000000, v6
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s5, s5, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v6, v6, v13, s5
.LBB0_15:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_add_i32 s5, s22, 1
	s_cmp_lt_i32 s22, 2
	s_cselect_b32 s22, s5, 0
	s_add_i32 s23, s23, 1
	s_barrier
	s_cmp_eq_u32 s23, 34
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v13, v12 :: v_dual_mov_b32 v12, v14
	s_branch .LBB0_1
.LBB0_17:
	v_cmp_gt_i32_e32 vcc_lo, s8, v1
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_mad_u64_u32 v[2:3], null, s15, s9, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12Find3DMinMaxPiPfS0_S0_iii
		.amdhsa_group_segment_fixed_size 7680
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12Find3DMinMaxPiPfS0_S0_iii, .Lfunc_end0-_Z12Find3DMinMaxPiPfS0_S0_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1152
; NumSgprs: 30
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 7680 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_Threshold             ; @d_Threshold
	.type	d_Threshold,@object
	.section	.bss,"aw",@nobits
	.globl	d_Threshold
	.p2align	2, 0x0
d_Threshold:
	.zero	8
	.size	d_Threshold, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_Threshold
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 7680
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12Find3DMinMaxPiPfS0_S0_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z12Find3DMinMaxPiPfS0_S0_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
