#include "cuda.h"
#include "stdio.h"
#include "stdlib.h"

// for cuda profiler
#include "cuda_profiler_api.h"

#define M_s 1.f // Solar mass
#define G 39.5f// Gravitational constant Solar mass, AU

// single precision CUDA function to be called on GPU
__device__ float potential_thingy(float x, float y) {
    return G * M_s * x / powf((powf(x, 2) + powf(y, 2)), 1.5f);
}

// euler method for velocity component
__global__ void euler_integration_vx(float *x_out, float *y_out, float *vx_out, int n, int steps, int current_step, float dt) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    while (tid < n){
        vx_out[n*current_step+tid] = vx_out[(n*current_step-n)+tid] - potential_thingy(x_out[(n*current_step-n)+tid], y_out[(n*current_step-n)+tid]) * dt;
        tid += gridDim.x * blockDim.x;
    }
}

// euler method for position component
__global__ void euler_integration_x(float *x_out, float *vx_out, int n, int steps, int current_step, float dt) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    while (tid < n){
        x_out[n*current_step+tid] = x_out[(n*current_step-n)+tid] + vx_out[n*current_step+tid] * dt;
        tid += gridDim.x * blockDim.x;
    }
}

extern "C" int integrate_euler_cuda(float *x, float *y, float *vx, float *vy, float *x_out, float *y_out, float *vx_out,
                                    float *vy_out, int n, int steps, float dt) {
    // dev_** variables for variables on CUDA device
    float *dev_x_out, *dev_y_out, *dev_vx_out, *dev_vy_out;

    // streams related constants and things
    const int nStreams = 4;

    // stream for kernel
    cudaStream_t stream[nStreams];
    for (int i = 0; i < nStreams; ++i)
        cudaStreamCreate(&stream[i]);

    // allocate the memory on the GPU (VRAM)
    // cudaMalloc docs: http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_gc63ffd93e344b939d6399199d8b12fef.html
    cudaMalloc((void**)&dev_x_out, steps * n * sizeof(float));
    cudaMalloc((void**)&dev_y_out, steps * n * sizeof(float));
    cudaMalloc((void**)&dev_vx_out, steps * n * sizeof(float));
    cudaMalloc((void**)&dev_vy_out, steps * n * sizeof(float));

    // map the arrays x, y, vx, vy to the corresponding GPU array
    // cudaMemcpy docs: http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g48efa06b81cc031b2aa6fdc2e9930741.html
    cudaMemcpy(&dev_x_out[0], &x[0], n * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(&dev_y_out[0], &y[0], n * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(&dev_vx_out[0], &vx[0], n * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(&dev_vy_out[0], &vy[0], n * sizeof(float), cudaMemcpyHostToDevice);

    // loop time, because time steps cannot be paralleled
    int cstep = 1;  // keep track of the time in integration
    while (cstep < steps){
        // integrate velocity first in 2 concurrent kernel
        euler_integration_vx<<<128, 128, 0, stream[0]>>>(dev_x_out, dev_y_out, dev_vx_out, n, steps, cstep, dt);
        euler_integration_vx<<<128, 128, 0, stream[1]>>>(dev_y_out, dev_x_out, dev_vy_out, n, steps, cstep, dt);
        // as soon as any kernel finished computation, send the data back to CPU host
        cudaMemcpyAsync(&vx_out[cstep*n], &dev_vx_out[cstep*n], n * sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
        cudaMemcpyAsync(&vy_out[cstep*n], &dev_vy_out[cstep*n], n * sizeof(float), cudaMemcpyDeviceToHost, stream[1]);
        // as soon as above finished, start corresponding position computation
        euler_integration_x<<<128, 128, 0, stream[2]>>>(dev_x_out, dev_vx_out, n, steps, cstep, dt);
        euler_integration_x<<<128, 128, 0, stream[3]>>>(dev_y_out, dev_vy_out, n, steps, cstep, dt);
        // as soon as any kernel finished computation, send the data back to CPU host
        cudaMemcpyAsync(&x_out[cstep*n], &dev_x_out[cstep*n], n * sizeof(float), cudaMemcpyDeviceToHost, stream[2]);
        cudaMemcpyAsync(&y_out[cstep*n], &dev_y_out[cstep*n], n * sizeof(float), cudaMemcpyDeviceToHost, stream[3]);
        // make sure above all finished to start next time step because next time step depends on this step
        cudaDeviceSynchronize();
        cstep += 1;
    }

    // free the memory allocated on the GPU after integration, if really galpy, need to take care memory for real
    cudaFree(dev_x_out);
    cudaFree(dev_y_out);
    cudaFree(dev_vx_out);
    cudaFree(dev_vy_out);

    return 0;
}
	.file	"tmpxft_0039b40a_00000000-6_CUDAOrbits.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16potential_thingyff
	.type	_Z16potential_thingyff, @function
_Z16potential_thingyff:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z16potential_thingyff, .-_Z16potential_thingyff
	.globl	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif
	.type	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif, @function
_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20euler_integration_vxPfS_S_iiif(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif, .-_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif
	.globl	_Z20euler_integration_vxPfS_S_iiif
	.type	_Z20euler_integration_vxPfS_S_iiif, @function
_Z20euler_integration_vxPfS_S_iiif:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif
	.cfi_endproc
.LFE2054:
	.size	_Z20euler_integration_vxPfS_S_iiif, .-_Z20euler_integration_vxPfS_S_iiif
	.globl	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif
	.type	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif, @function
_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z19euler_integration_xPfS_iiif(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L10:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif, .-_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif
	.globl	_Z19euler_integration_xPfS_iiif
	.type	_Z19euler_integration_xPfS_iiif, @function
_Z19euler_integration_xPfS_iiif:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif
	.cfi_endproc
.LFE2056:
	.size	_Z19euler_integration_xPfS_iiif, .-_Z19euler_integration_xPfS_iiif
	.globl	integrate_euler_cuda
	.type	integrate_euler_cuda, @function
integrate_euler_cuda:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%r9, 32(%rsp)
	movq	%rsi, 24(%rsp)
	movq	216(%rsp), %r15
	movq	%rdi, 16(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rax, 40(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	cudaStreamCreate@PLT
	leaq	112(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	120(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	128(%rsp), %rdi
	call	cudaStreamCreate@PLT
	movl	232(%rsp), %ebx
	leaq	48(%rsp), %rdi
	imull	224(%rsp), %ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	72(%rsp), %rdi
	movl	$33554433, %ebx
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movslq	224(%rsp), %rax
	salq	$7, %rbx
	leaq	0(,%rax,4), %r13
	movq	%r13, %rdx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	56(%rsp), %rdi
	movq	%r13, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	movl	$1, %r12d
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movq	%rbp, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%r13, %rbp
	call	cudaMemcpy@PLT
.L16:
	cmpl	232(%rsp), %r12d
	jge	.L24
	movq	104(%rsp), %r9
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rbx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movss	12(%rsp), %xmm0
	movl	232(%rsp), %r8d
	movl	%r12d, %r9d
	movl	224(%rsp), %ecx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif
.L17:
	movq	112(%rsp), %r9
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rbx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movss	12(%rsp), %xmm0
	movl	232(%rsp), %r8d
	movl	%r12d, %r9d
	movl	224(%rsp), %ecx
	movq	72(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z48__device_stub__Z20euler_integration_vxPfS_S_iiifPfS_S_iiif
.L18:
	movq	64(%rsp), %rsi
	movq	40(%rsp), %rax
	movl	$2, %ecx
	movq	%r13, %rdx
	movq	104(%rsp), %r8
	addq	%rbp, %rsi
	leaq	(%rax,%rbp), %rdi
	call	cudaMemcpyAsync@PLT
	movq	72(%rsp), %rsi
	movq	112(%rsp), %r8
	movq	%r13, %rdx
	leaq	(%r15,%rbp), %rdi
	movl	$2, %ecx
	addq	%rbp, %rsi
	call	cudaMemcpyAsync@PLT
	movq	120(%rsp), %r9
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rbx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movss	12(%rsp), %xmm0
	movl	232(%rsp), %ecx
	movl	%r12d, %r8d
	movl	224(%rsp), %edx
	movq	64(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif
.L19:
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movq	128(%rsp), %r9
	movl	$1, %esi
	movq	%rbx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rbx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movss	12(%rsp), %xmm0
	movl	232(%rsp), %ecx
	movl	%r12d, %r8d
	movl	224(%rsp), %edx
	movq	72(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z45__device_stub__Z19euler_integration_xPfS_iiifPfS_iiif
.L20:
	movq	48(%rsp), %rsi
	movq	120(%rsp), %r8
	movq	%r13, %rdx
	incl	%r12d
	leaq	(%r14,%rbp), %rdi
	movl	$2, %ecx
	addq	%rbp, %rsi
	call	cudaMemcpyAsync@PLT
	movq	56(%rsp), %rsi
	movq	32(%rsp), %rax
	movq	%r13, %rdx
	movq	128(%rsp), %r8
	movl	$2, %ecx
	addq	%rbp, %rsi
	leaq	(%rax,%rbp), %rdi
	addq	%r13, %rbp
	call	cudaMemcpyAsync@PLT
	call	cudaDeviceSynchronize@PLT
	jmp	.L16
.L24:
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	integrate_euler_cuda, .-integrate_euler_cuda
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19euler_integration_xPfS_iiif"
.LC1:
	.string	"_Z20euler_integration_vxPfS_S_iiif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19euler_integration_xPfS_iiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20euler_integration_vxPfS_S_iiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"
#include "stdio.h"
#include "stdlib.h"

// for cuda profiler
#include "hip/hip_runtime_api.h"

#define M_s 1.f // Solar mass
#define G 39.5f// Gravitational constant Solar mass, AU

// single precision CUDA function to be called on GPU
__device__ float potential_thingy(float x, float y) {
    return G * M_s * x / powf((powf(x, 2) + powf(y, 2)), 1.5f);
}

// euler method for velocity component
__global__ void euler_integration_vx(float *x_out, float *y_out, float *vx_out, int n, int steps, int current_step, float dt) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    while (tid < n){
        vx_out[n*current_step+tid] = vx_out[(n*current_step-n)+tid] - potential_thingy(x_out[(n*current_step-n)+tid], y_out[(n*current_step-n)+tid]) * dt;
        tid += gridDim.x * blockDim.x;
    }
}

// euler method for position component
__global__ void euler_integration_x(float *x_out, float *vx_out, int n, int steps, int current_step, float dt) {
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    while (tid < n){
        x_out[n*current_step+tid] = x_out[(n*current_step-n)+tid] + vx_out[n*current_step+tid] * dt;
        tid += gridDim.x * blockDim.x;
    }
}

extern "C" int integrate_euler_cuda(float *x, float *y, float *vx, float *vy, float *x_out, float *y_out, float *vx_out,
                                    float *vy_out, int n, int steps, float dt) {
    // dev_** variables for variables on CUDA device
    float *dev_x_out, *dev_y_out, *dev_vx_out, *dev_vy_out;

    // streams related constants and things
    const int nStreams = 4;

    // stream for kernel
    hipStream_t stream[nStreams];
    for (int i = 0; i < nStreams; ++i)
        hipStreamCreate(&stream[i]);

    // allocate the memory on the GPU (VRAM)
    // cudaMalloc docs: http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_gc63ffd93e344b939d6399199d8b12fef.html
    hipMalloc((void**)&dev_x_out, steps * n * sizeof(float));
    hipMalloc((void**)&dev_y_out, steps * n * sizeof(float));
    hipMalloc((void**)&dev_vx_out, steps * n * sizeof(float));
    hipMalloc((void**)&dev_vy_out, steps * n * sizeof(float));

    // map the arrays x, y, vx, vy to the corresponding GPU array
    // cudaMemcpy docs: http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g48efa06b81cc031b2aa6fdc2e9930741.html
    hipMemcpy(&dev_x_out[0], &x[0], n * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(&dev_y_out[0], &y[0], n * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(&dev_vx_out[0], &vx[0], n * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(&dev_vy_out[0], &vy[0], n * sizeof(float), hipMemcpyHostToDevice);

    // loop time, because time steps cannot be paralleled
    int cstep = 1;  // keep track of the time in integration
    while (cstep < steps){
        // integrate velocity first in 2 concurrent kernel
        euler_integration_vx<<<128, 128, 0, stream[0]>>>(dev_x_out, dev_y_out, dev_vx_out, n, steps, cstep, dt);
        euler_integration_vx<<<128, 128, 0, stream[1]>>>(dev_y_out, dev_x_out, dev_vy_out, n, steps, cstep, dt);
        // as soon as any kernel finished computation, send the data back to CPU host
        hipMemcpyAsync(&vx_out[cstep*n], &dev_vx_out[cstep*n], n * sizeof(float), hipMemcpyDeviceToHost, stream[0]);
        hipMemcpyAsync(&vy_out[cstep*n], &dev_vy_out[cstep*n], n * sizeof(float), hipMemcpyDeviceToHost, stream[1]);
        // as soon as above finished, start corresponding position computation
        euler_integration_x<<<128, 128, 0, stream[2]>>>(dev_x_out, dev_vx_out, n, steps, cstep, dt);
        euler_integration_x<<<128, 128, 0, stream[3]>>>(dev_y_out, dev_vy_out, n, steps, cstep, dt);
        // as soon as any kernel finished computation, send the data back to CPU host
        hipMemcpyAsync(&x_out[cstep*n], &dev_x_out[cstep*n], n * sizeof(float), hipMemcpyDeviceToHost, stream[2]);
        hipMemcpyAsync(&y_out[cstep*n], &dev_y_out[cstep*n], n * sizeof(float), hipMemcpyDeviceToHost, stream[3]);
        // make sure above all finished to start next time step because next time step depends on this step
        hipDeviceSynchronize();
        cstep += 1;
    }

    // free the memory allocated on the GPU after integration, if really galpy, need to take care memory for real
    hipFree(dev_x_out);
    hipFree(dev_y_out);
    hipFree(dev_vx_out);
    hipFree(dev_vy_out);

    return 0;
}
	.text
	.file	"CUDAOrbits.hip"
	.globl	_Z35__device_stub__euler_integration_vxPfS_S_iiif # -- Begin function _Z35__device_stub__euler_integration_vxPfS_S_iiif
	.type	_Z35__device_stub__euler_integration_vxPfS_S_iiif,@function
_Z35__device_stub__euler_integration_vxPfS_S_iiif: # @_Z35__device_stub__euler_integration_vxPfS_S_iiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20euler_integration_vxPfS_S_iiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__euler_integration_vxPfS_S_iiif, .Lfunc_end0-_Z35__device_stub__euler_integration_vxPfS_S_iiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__euler_integration_xPfS_iiif # -- Begin function _Z34__device_stub__euler_integration_xPfS_iiif
	.type	_Z34__device_stub__euler_integration_xPfS_iiif,@function
_Z34__device_stub__euler_integration_xPfS_iiif: # @_Z34__device_stub__euler_integration_xPfS_iiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movss	%xmm0, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19euler_integration_xPfS_iiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__euler_integration_xPfS_iiif, .Lfunc_end1-_Z34__device_stub__euler_integration_xPfS_iiif
	.cfi_endproc
                                        # -- End function
	.globl	integrate_euler_cuda            # -- Begin function integrate_euler_cuda
	.type	integrate_euler_cuda,@function
integrate_euler_cuda:                   # @integrate_euler_cuda
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 112(%rsp)                  # 8-byte Spill
	movq	%r8, %r14
	movq	%rcx, 104(%rsp)                 # 8-byte Spill
	movq	%rdx, 96(%rsp)                  # 8-byte Spill
	movq	%rsi, 88(%rsp)                  # 8-byte Spill
	movq	%rdi, 80(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rsp,%rbx), %rdi
	addq	$48, %rdi
	callq	hipStreamCreate
	addq	$8, %rbx
	cmpq	$32, %rbx
	jne	.LBB2_1
# %bb.2:
	movl	200(%rsp), %r15d
	movl	%r15d, %eax
	movl	192(%rsp), %ebx
	imull	%ebx, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	%ebx, %rbx
	shlq	$2, %rbx
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	88(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	200(%rsp), %eax
	cmpl	$2, %eax
	jl	.LBB2_13
# %bb.3:                                # %.lr.ph
	movabsq	$4294967424, %r13               # imm = 0x100000080
	movl	200(%rsp), %eax
	movl	%eax, %r15d
	movl	$1, %ebp
	movq	%rbx, %r12
.LBB2_4:                                # =>This Inner Loop Header: Depth=1
	movq	48(%rsp), %r9
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_4 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	192(%rsp), %ecx
	movl	200(%rsp), %r8d
                                        # kill: def $r8d killed $r8d killed $r8
	movl	%ebp, %r9d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z35__device_stub__euler_integration_vxPfS_S_iiif
.LBB2_6:                                #   in Loop: Header=BB2_4 Depth=1
	movq	56(%rsp), %r9
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:                                #   in Loop: Header=BB2_4 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	192(%rsp), %ecx
	movl	200(%rsp), %r8d
                                        # kill: def $r8d killed $r8d killed $r8
	movl	%ebp, %r9d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z35__device_stub__euler_integration_vxPfS_S_iiif
.LBB2_8:                                #   in Loop: Header=BB2_4 Depth=1
	movq	176(%rsp), %rax
	leaq	(%rax,%r12), %rdi
	movq	40(%rsp), %rsi
	addq	%r12, %rsi
	movq	48(%rsp), %r8
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	184(%rsp), %rax
	leaq	(%rax,%r12), %rdi
	movq	16(%rsp), %rsi
	addq	%r12, %rsi
	movq	56(%rsp), %r8
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	64(%rsp), %r9
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:                                #   in Loop: Header=BB2_4 Depth=1
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movl	192(%rsp), %edx
	movl	200(%rsp), %ecx
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%ebp, %r8d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z34__device_stub__euler_integration_xPfS_iiif
.LBB2_10:                               #   in Loop: Header=BB2_4 Depth=1
	movq	72(%rsp), %r9
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.11:                               #   in Loop: Header=BB2_4 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	192(%rsp), %edx
	movl	200(%rsp), %ecx
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%ebp, %r8d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z34__device_stub__euler_integration_xPfS_iiif
.LBB2_12:                               #   in Loop: Header=BB2_4 Depth=1
	leaq	(%r14,%r12), %rdi
	movq	32(%rsp), %rsi
	addq	%r12, %rsi
	movq	64(%rsp), %r8
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	112(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r12), %rdi
	movq	24(%rsp), %rsi
	addq	%r12, %rsi
	movq	72(%rsp), %r8
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	callq	hipDeviceSynchronize
	incq	%rbp
	addq	%rbx, %r12
	cmpq	%rbp, %r15
	jne	.LBB2_4
.LBB2_13:                               # %._crit_edge
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	integrate_euler_cuda, .Lfunc_end2-integrate_euler_cuda
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20euler_integration_vxPfS_S_iiif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19euler_integration_xPfS_iiif, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20euler_integration_vxPfS_S_iiif,@object # @_Z20euler_integration_vxPfS_S_iiif
	.section	.rodata,"a",@progbits
	.globl	_Z20euler_integration_vxPfS_S_iiif
	.p2align	3, 0x0
_Z20euler_integration_vxPfS_S_iiif:
	.quad	_Z35__device_stub__euler_integration_vxPfS_S_iiif
	.size	_Z20euler_integration_vxPfS_S_iiif, 8

	.type	_Z19euler_integration_xPfS_iiif,@object # @_Z19euler_integration_xPfS_iiif
	.globl	_Z19euler_integration_xPfS_iiif
	.p2align	3, 0x0
_Z19euler_integration_xPfS_iiif:
	.quad	_Z34__device_stub__euler_integration_xPfS_iiif
	.size	_Z19euler_integration_xPfS_iiif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20euler_integration_vxPfS_S_iiif"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19euler_integration_xPfS_iiif"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__euler_integration_vxPfS_S_iiif
	.addrsig_sym _Z34__device_stub__euler_integration_xPfS_iiif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20euler_integration_vxPfS_S_iiif
	.addrsig_sym _Z19euler_integration_xPfS_iiif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20euler_integration_vxPfS_S_iiif ; -- Begin function _Z20euler_integration_vxPfS_S_iiif
	.globl	_Z20euler_integration_vxPfS_S_iiif
	.p2align	8
	.type	_Z20euler_integration_vxPfS_S_iiif,@function
_Z20euler_integration_vxPfS_S_iiif:     ; @_Z20euler_integration_vxPfS_S_iiif
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b32 s12, s[0:1], 0x18
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[4:5], s[0:1], 0x20
	s_load_b32 s15, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	s_mov_b32 s13, 0
	s_mov_b32 s17, 0x3e76c4e1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s4, s12
	s_mul_i32 s15, s15, s16
	s_sub_i32 s16, s14, s12
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s16, v1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[6:7], off
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(2)
	v_frexp_mant_f32_e64 v5, |v2|
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	s_waitcnt vmcnt(1)
	v_frexp_mant_f32_e64 v9, |v3|
	v_frexp_exp_i32_f32_e32 v6, v2
	v_cmp_eq_f32_e64 s0, 1.0, v3
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v4, 2.0, 1.0, vcc_lo
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v9
	v_frexp_exp_i32_f32_e32 v10, v3
	v_cndmask_b32_e64 v8, 2.0, 1.0, s0
	v_cndmask_b32_e64 v12, 0, 1, s1
	v_subrev_co_ci_u32_e64 v6, s1, 0, v6, s1
	v_cndmask_b32_e64 v15, 0, 1, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v17, 0.5, v8
	v_ldexp_f32 v5, v5, v12
	v_mul_f32_e32 v14, 0.5, v4
	v_trunc_f32_e32 v13, v4
	v_ldexp_f32 v9, v9, v15
	v_trunc_f32_e32 v16, v8
	v_add_f32_e32 v15, -1.0, v5
	v_trunc_f32_e32 v12, v14
	v_subrev_co_ci_u32_e64 v10, s2, 0, v10, s2
	v_cvt_f32_i32_e32 v6, v6
	v_cmp_eq_f32_e64 s1, v13, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_neq_f32_e64 s3, v12, v14
	v_add_f32_e32 v14, 1.0, v9
	v_cmp_eq_f32_e64 s2, v16, v8
	v_trunc_f32_e32 v13, v17
	v_cvt_f32_i32_e32 v10, v10
	v_cmp_eq_f32_e32 vcc_lo, 0, v2
	v_add_f32_e32 v20, -1.0, v14
	v_add_f32_e32 v16, 1.0, v5
	v_add_f32_e32 v12, -1.0, v9
	v_cmp_neq_f32_e64 s4, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v22, 0x3f317218, v10 :: v_dual_sub_f32 v9, v9, v20
	v_rcp_f32_e32 v17, v16
	s_and_b32 s3, s1, s3
	v_cndmask_b32_e64 v7, 0x7f800000, 0, vcc_lo
	v_dual_add_f32 v13, -1.0, v16 :: v_dual_mul_f32 v18, 0x3f317218, v6
	v_cndmask_b32_e64 v24, 0, v2, s3
	v_fma_f32 v20, 0x3f317218, v10, -v22
	v_cmp_eq_f32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v5, v5, v13
	v_fma_f32 v13, 0x3f317218, v6, -v18
	v_bfi_b32 v7, 0x7fffffff, v7, v24
	v_fmac_f32_e32 v20, 0xb102e308, v10
	v_mul_f32_e32 v24, v15, v17
	s_and_b32 s4, s2, s4
	v_cndmask_b32_e64 v11, 0x7f800000, 0, s0
	v_cndmask_b32_e64 v25, 0, v3, s4
	v_fmac_f32_e32 v13, 0xb102e308, v6
	v_rcp_f32_e32 v21, v14
	v_mul_f32_e32 v10, v16, v24
	v_cndmask_b32_e64 v23, 1.0, v3, s4
	v_bfi_b32 v11, 0x7fffffff, v11, v25
	v_add_f32_e32 v25, v18, v13
	v_cndmask_b32_e64 v19, 1.0, v2, s3
	v_fma_f32 v16, v24, v16, -v10
	v_cmp_class_f32_e64 s18, v2, 0x204
	v_cmp_class_f32_e64 s19, v3, 0x204
	v_sub_f32_e32 v18, v25, v18
	v_mul_f32_e32 v6, v12, v21
	v_fmac_f32_e32 v16, v24, v5
	s_or_b32 vcc_lo, vcc_lo, s18
	s_or_b32 s0, s0, s19
	v_sub_f32_e32 v5, v13, v18
	v_mul_f32_e32 v26, v14, v6
	v_add_f32_e32 v13, v10, v16
	v_add_f32_e32 v27, v22, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v6, v14, -v26
	v_sub_f32_e32 v10, v13, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v27, v22
	v_fmac_f32_e32 v14, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v16 :: v_dual_sub_f32 v9, v20, v22
	v_sub_f32_e32 v20, v15, v13
	v_sub_f32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v15, v13
	v_add_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v20, v10
	v_mul_f32_e32 v10, v17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v24, v10
	v_dual_add_f32 v18, v26, v14 :: v_dual_sub_f32 v15, v13, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v22, v12, v18
	v_sub_f32_e32 v26, v18, v26
	v_mul_f32_e32 v16, v13, v13
	v_ldexp_f32 v17, v13, 1
	v_sub_f32_e32 v10, v10, v15
	v_sub_f32_e32 v12, v12, v22
	v_sub_f32_e32 v14, v26, v14
	v_fma_f32 v15, v13, v13, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v18
	v_add_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v22, v12
	v_ldexp_f32 v22, v10, 1
	v_dual_mul_f32 v12, v21, v12 :: v_dual_add_f32 v21, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v6, v12 :: v_dual_fmac_f32 v15, v13, v21
	v_sub_f32_e32 v6, v14, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v18, v14, v14 :: v_dual_add_f32 v21, v16, v15
	v_ldexp_f32 v20, v14, 1
	v_sub_f32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v12, v14, v14, -v18
	v_mul_f32_e32 v29, v13, v21
	v_sub_f32_e32 v16, v21, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v24, v6, v6
	v_ldexp_f32 v26, v6, 1
	v_fmaak_f32 v28, s17, v21, 0x3e91f4c4
	v_fma_f32 v32, v21, v13, -v29
	v_sub_f32_e32 v15, v15, v16
	v_fmac_f32_e32 v12, v14, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v28, v21, v28, 0x3ecccdef
	v_fmac_f32_e32 v32, v21, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v18, v12
	v_mul_f32_e32 v10, v21, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v32, v15, v13
	v_fmaak_f32 v30, s17, v24, 0x3e91f4c4
	v_dual_mul_f32 v31, v14, v24 :: v_dual_sub_f32 v18, v24, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v21, v28, -v10
	v_fmaak_f32 v16, v24, v30, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, v24, v14, -v31
	v_dual_sub_f32 v12, v12, v18 :: v_dual_fmac_f32 v13, v15, v28
	v_add_f32_e32 v18, v29, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v30, v24, v6
	v_mul_f32_e32 v6, v24, v16
	v_fmac_f32_e32 v30, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v24, v16, -v6
	v_dual_add_f32 v15, v31, v30 :: v_dual_fmac_f32 v14, v12, v16
	v_add_f32_e32 v16, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v18, v29 :: v_dual_sub_f32 v21, v15, v31
	v_add_f32_e32 v24, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v16, v10
	v_add_f32_e32 v28, 0x3f2aaaaa, v16
	v_dual_sub_f32 v12, v32, v12 :: v_dual_sub_f32 v21, v30, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v24, v6 :: v_dual_add_f32 v29, 0x3f2aaaaa, v24
	v_dual_sub_f32 v10, v13, v10 :: v_dual_add_f32 v13, 0xbf2aaaaa, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v14, v6
	v_add_f32_e32 v14, 0xbf2aaaaa, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v10, 0x31739010, v10 :: v_dual_sub_f32 v13, v16, v13
	v_add_f32_e32 v6, 0x31739010, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v24, v14
	v_add_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v6, v14
	v_add_f32_e32 v13, v28, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v29, v6
	v_sub_f32_e32 v16, v28, v13
	v_mul_f32_e32 v24, v18, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v28, v29, v14
	v_dual_mul_f32 v29, v15, v14 :: v_dual_add_f32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v18, v13, -v24
	v_add_f32_e32 v6, v6, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, v15, v14, -v29
	v_fmac_f32_e32 v16, v18, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v15, v6
	v_fmac_f32_e32 v16, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v21, v14
	v_add_f32_e32 v6, v24, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v29, v28
	v_dual_add_f32 v12, v17, v6 :: v_dual_sub_f32 v13, v6, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v20, v10 :: v_dual_sub_f32 v15, v10, v29
	v_sub_f32_e32 v17, v12, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v16, v13 :: v_dual_sub_f32 v16, v14, v20
	v_dual_sub_f32 v15, v28, v15 :: v_dual_sub_f32 v6, v6, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v22, v13
	v_sub_f32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v15, v26, v15 :: v_dual_add_f32 v6, v13, v6
	v_add_f32_e32 v10, v15, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v12, v6
	v_dual_add_f32 v15, v14, v10 :: v_dual_add_f32 v16, v25, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v13, v12 :: v_dual_add_f32 v17, v27, v15
	v_sub_f32_e32 v14, v15, v14
	v_sub_f32_e32 v18, v16, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v6, v12
	v_sub_f32_e32 v12, v17, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v14
	v_sub_f32_e32 v14, v16, v18
	v_sub_f32_e32 v13, v13, v18
	v_add_f32_e32 v18, v5, v6
	v_sub_f32_e32 v20, v17, v12
	v_dual_sub_f32 v12, v15, v12 :: v_dual_add_f32 v15, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v14, v25, v14 :: v_dual_sub_f32 v21, v18, v5
	v_sub_f32_e32 v20, v27, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v22, v15, v9 :: v_dual_add_f32 v13, v13, v14
	v_sub_f32_e32 v14, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v12, v12, v20
	v_sub_f32_e32 v6, v6, v21
	v_dual_sub_f32 v20, v15, v22 :: v_dual_add_f32 v13, v18, v13
	v_sub_f32_e32 v10, v10, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v12, v15, v12 :: v_dual_sub_f32 v5, v5, v14
	v_dual_sub_f32 v9, v9, v20 :: v_dual_add_f32 v14, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v17, v12
	v_add_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v10, v9
	v_dual_sub_f32 v9, v14, v16 :: v_dual_sub_f32 v10, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v13, v9 :: v_dual_sub_f32 v10, v12, v10
	v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v14, v5 :: v_dual_add_f32 v10, v15, v6
	v_dual_sub_f32 v12, v9, v14 :: v_dual_mul_f32 v13, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v10, v15 :: v_dual_mul_f32 v15, v8, v10
	v_sub_f32_e32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v4, v9, -v13
	v_sub_f32_e32 v6, v6, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v10, v8, v10, -v15
	v_cmp_class_f32_e64 s4, v13, 0x204
	v_cmp_class_f32_e64 s3, v15, 0x204
	v_fmac_f32_e32 v9, v4, v5
	v_fmac_f32_e32 v10, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v13, v9 :: v_dual_add_f32 v5, v15, v10
	v_sub_f32_e32 v6, v4, v13
	v_cndmask_b32_e64 v4, v4, v13, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v5, v15
	v_cndmask_b32_e64 v5, v5, v15, s3
	v_sub_f32_e32 v6, v9, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e64 s3, 0x42b17218, v4
	v_sub_f32_e32 v8, v10, v8
	v_cmp_neq_f32_e64 s4, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0, 0x37000000, s3
	v_cmp_eq_f32_e64 s3, 0x42b17218, v5
	v_cndmask_b32_e64 v6, 0, v6, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v4, v4, v9
	v_cndmask_b32_e64 v10, 0, 0x37000000, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v5|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v9, v6
	v_dual_mul_f32 v12, 0x3fb8aa3b, v4 :: v_dual_sub_f32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0, v8, s3
	v_cmp_ngt_f32_e64 s4, 0xc2ce8ed0, v4
	v_fma_f32 v9, 0x3fb8aa3b, v4, -v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v13, 0x3fb8aa3b, v5 :: v_dual_add_f32 v8, v10, v8
	v_rndne_f32_e32 v10, v12
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v5
	v_fmac_f32_e32 v9, 0x32a5705f, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v14, 0x3fb8aa3b, v5, -v13
	v_rndne_f32_e32 v15, v13
	v_sub_f32_e32 v12, v12, v10
	v_cvt_i32_f32_e32 v10, v10
	v_dual_fmac_f32 v14, 0x32a5705f, v5 :: v_dual_sub_f32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v12, v9 :: v_dual_add_f32 v12, v13, v14
	v_exp_f32_e32 v9, v9
	v_cvt_i32_f32_e32 v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v12, v12
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v9, v10
	v_ldexp_f32 v10, v12, v13
	v_cndmask_b32_e64 v9, 0, v9, s4
	v_cmp_nlt_f32_e64 s4, 0x42b17218, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0, v10, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v5
	v_cndmask_b32_e64 v4, 0x7f800000, v9, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 0x7f800000, v10, s3
	v_fma_f32 v6, v4, v6, v4
	v_cmp_eq_f32_e64 s4, 0x7f800000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v8, v5, v8, v5
	v_cmp_eq_f32_e64 s3, 0x7f800000, v5
	v_cndmask_b32_e64 v4, v6, v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v8, v5, s3
	v_bfi_b32 v4, 0x7fffffff, v4, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v5, 0x7fffffff, v5, v23
	v_cndmask_b32_e64 v6, 0x7fc00000, v4, s1
	v_cmp_gt_f32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0x7fc00000, v5, s2
	v_cmp_gt_f32_e64 s2, 0, v2
	v_cndmask_b32_e64 v5, v5, v8, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v6, s2
	v_cndmask_b32_e64 v5, v5, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	v_cmp_o_f32_e64 s0, v2, v2
	v_cndmask_b32_e64 v3, 0x7fc00000, v4, s0
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_frexp_mant_f32_e64 v4, |v3|
	v_frexp_exp_i32_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v4, v4, v6
	v_cvt_f32_i32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 1.0, v4
	v_dual_add_f32 v7, -1.0, v4 :: v_dual_mul_f32 v10, 0x3f317218, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	v_add_f32_e32 v9, -1.0, v6
	v_sub_f32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3f317218, v5, -v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v7, v8
	v_fmac_f32_e32 v9, 0xb102e308, v5
	v_mul_f32_e32 v5, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v11, v6, -v5
	v_fmac_f32_e32 v6, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	v_dual_sub_f32 v12, v7, v4 :: v_dual_sub_f32 v5, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v12
	v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v4
	v_add_f32_e32 v4, v12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v8, v4
	v_add_f32_e32 v5, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v5, v11
	v_mul_f32_e32 v7, v5, v5
	v_ldexp_f32 v8, v5, 1
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v5, v5, -v7
	v_add_f32_e32 v11, v4, v4
	v_ldexp_f32 v12, v4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v5, v11
	v_add_f32_e32 v11, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v13, s17, v11, 0x3e91f4c4
	v_sub_f32_e32 v7, v11, v7
	v_dual_mul_f32 v14, v5, v11 :: v_dual_fmaak_f32 v13, v11, v13, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v7
	v_fma_f32 v7, v11, v5, -v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v11, v13
	v_fmac_f32_e32 v7, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v11, v13, -v15
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v6, v13
	v_dual_add_f32 v5, v14, v7 :: v_dual_add_f32 v6, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v5, v14
	v_dual_sub_f32 v13, v6, v15 :: v_dual_add_f32 v14, 0x3f2aaaaa, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v7, v7, v11 :: v_dual_sub_f32 v4, v4, v13
	v_add_f32_e32 v11, 0xbf2aaaaa, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, 0x31739010, v4
	v_sub_f32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v6
	v_add_f32_e32 v6, v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v14, v6
	v_dual_mul_f32 v13, v5, v6 :: v_dual_add_f32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v5, v6, -v13
	v_fmac_f32_e32 v11, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v7, v6
	v_add_f32_e32 v4, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v8, v4
	v_dual_sub_f32 v6, v4, v13 :: v_dual_sub_f32 v7, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v11, v6
	v_sub_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v12, v6 :: v_dual_add_f32 v7, v10, v9
	v_add_f32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v7, v10
	v_add_f32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v9, v6 :: v_dual_add_f32 v9, v7, v8
	v_dual_sub_f32 v5, v8, v5 :: v_dual_sub_f32 v10, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v9, v10
	v_sub_f32_e32 v8, v8, v10
	v_dual_add_f32 v10, v6, v4 :: v_dual_sub_f32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v10, v6
	v_dual_add_f32 v5, v8, v5 :: v_dual_sub_f32 v8, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v5, v10, v5
	v_dual_sub_f32 v6, v6, v8 :: v_dual_add_f32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v6
	v_sub_f32_e32 v8, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v8
	v_add_f32_e32 v4, v4, v5
	v_cndmask_b32_e64 v5, 0x3fc00000, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v4
	v_dual_sub_f32 v7, v6, v7 :: v_dual_mul_f32 v8, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v7
	v_fma_f32 v6, v5, v6, -v8
	v_cmp_class_f32_e64 vcc_lo, v8, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v5, v4
	v_add_f32_e32 v4, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v4, v8, vcc_lo
	v_sub_f32_e32 v4, v4, v8
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v6, v4
	v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
	v_sub_f32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_trunc_f32_e32 v7, v5
	v_mul_f32_e32 v11, 0x3fb8aa3b, v10
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v9, v4
	v_fma_f32 v12, 0x3fb8aa3b, v10, -v11
	v_rndne_f32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
	v_cvt_i32_f32_e32 v8, v13
	v_add_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v11, v8
	v_mul_f32_e32 v8, 0.5, v5
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v11, v8
	v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v11, v8
	v_fma_f32 v4, v6, v4, v6
	v_cmp_eq_f32_e64 s1, 0x7f800000, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v5, 1.0, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v6, s1
	v_cmp_eq_f32_e64 s1, 0, v3
	v_cndmask_b32_e64 v6, 0, v3, s0
	v_cmp_class_f32_e64 s0, v3, 0x204
	v_bfi_b32 v4, 0x7fffffff, v4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
	v_cndmask_b32_e32 v7, 0x7fc00000, v4, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v5, 0x7fffffff, v5, v6
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	v_mul_f32_e32 v5, 0xc21e0000, v2
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v4, v4, v5
	v_div_scale_f32 v7, vcc_lo, v5, v4, v5
	v_rcp_f32_e32 v6, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v3, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v2, v6
	v_mul_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v3, v8, v7
	v_fmac_f32_e32 v8, v2, v6
	v_add_nc_u32_e32 v2, s14, v1
	v_add_nc_u32_e32 v1, s15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, -v3, v8, v7
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e64 s0, s12, v1
	v_div_fmas_f32 v6, v7, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_or_b32 s13, s0, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v4, v6, v4, v5
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, s5, v4
	global_store_b32 v[2:3], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20euler_integration_vxPfS_S_iiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20euler_integration_vxPfS_S_iiif, .Lfunc_end0-_Z20euler_integration_vxPfS_S_iiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3568
; NumSgprs: 22
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19euler_integration_xPfS_iiif ; -- Begin function _Z19euler_integration_xPfS_iiif
	.globl	_Z19euler_integration_xPfS_iiif
	.p2align	8
	.type	_Z19euler_integration_xPfS_iiif,@function
_Z19euler_integration_xPfS_iiif:        ; @_Z19euler_integration_xPfS_iiif
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x10
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s2, 0xffff
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s10, s[4:5], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s8
	s_mul_i32 s2, s10, s9
	s_sub_i32 s9, s1, s8
	s_mov_b32 s10, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s9, v1
	v_add_nc_u32_e32 v4, s1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v0, v[2:3], off
	global_load_b32 v6, v[6:7], off
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v2, s0, s4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s5, v5, s0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, s3, v6
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	global_store_b32 v[2:3], v0, off
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19euler_integration_xPfS_iiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19euler_integration_xPfS_iiif, .Lfunc_end1-_Z19euler_integration_xPfS_iiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20euler_integration_vxPfS_S_iiif
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z20euler_integration_vxPfS_S_iiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19euler_integration_xPfS_iiif
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19euler_integration_xPfS_iiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
