#include <cuda_runtime_api.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define TILE_WIDTH 16

__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
    int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
    int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
    int sum = 0; // initialize the sum

    if( col < k && row < m) // check to make sure that the thread needs to compute
    {
        for(int i = 0; i < n; i++)
        {
            sum += a[row * n + i] * b[i * k + col];
        }
        c[row * k + col] = sum;
    }
}

__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{

    // shared memory for tiling
    __shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
    __shared__ int Nds [TILE_WIDTH][TILE_WIDTH];

    int bx = blockIdx.x;  int by = blockIdx.y;
    int tx = threadIdx.x; int ty = threadIdx.y;

    // recall that TILE_WIDTH = blockDim
    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    int pval = 0;

    // this loop is iterating through cols of M and rows of N
    // recall that n is the shared inner dimension, that's why we're using it
    // to define our loop size
    for (int ph = 0; ph < n / TILE_WIDTH; ph++){
        // boundary check for shared Mds
        if (row < k && ph * TILE_WIDTH + tx < m){
            // saving tile from M
            /* indexing thought exercise:
             * "row * k" gets us to our desired row in M
             * adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
             * adding "tx" moves us to the desired location within the tile
             * */
            Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
        }
        // boundary check
        if (ph*TILE_WIDTH + ty < k && col < m){
            // saving tile from N
            /* indexing thought exercise:
             * "ph * TILE_WIDTH" moves the tile "down" to the desired location
             * adding "ty" gets us to the desired location within the tile
             * multiplying by "k" does the magic (remember row major order)
             * adding col moves the tile to the desired column*/
            Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
        }

        __syncthreads();  // execution barrier

        for (int j = 0; j < TILE_WIDTH; j++){
            // performing part of inner product
            pval += Mds[ty][j] * Nds[j][tx];
        }

        __syncthreads();
    }
    if (row < k && col < m){
        d_P[row * k + col] = pval;
    }
}

int main(int argc, char const *argv[])
{
    int m, n, k; // init matrix dimensions
    printf("---------------------------------------------\n");
    printf("We will be multiplying two matrices\n");
    printf("The first will be of size m x n\n");
    printf("The second will be of size n x k\n");
    printf("I will have you choose these dimensions!\n");
    printf("---------------------------------------------\n\n");
    printf("Input m:\n");
    scanf("%d", &m);
    printf("\nInput n:\n");
    scanf("%d", &n);
    printf("\nInput k:\n");
    scanf("%d", &k);
    printf("\n");


    // Initialize pointers
    int *cpu_a, *cpu_b, *cpu_result, *cpu_c;

    // Allocate memory to the pointers on the host
    cudaMallocHost((void **) &cpu_a, sizeof(int)*m*n); // matrix a
    cudaMallocHost((void **) &cpu_b, sizeof(int)*n*k); // matrix b
    cudaMallocHost((void **) &cpu_c, sizeof(int)*m*k); // cpu memory for gpu result
    cudaMallocHost((void **) &cpu_result, sizeof(int)*m*k); // cpu result

    // Generate the matrices
    // cpu_a
    for (int i = 0; i < m; i++)
    {
        for (int j = 0; j < n; j++)
        {
            cpu_a[i * n + j] = rand () % 1024;
        }
    }

    // cpu_b
    for (int i = 0; i < n; i++)
    {
        for (int j = 0; j < k; j++)
        {
            cpu_b[n * k + j] = rand () % 1024;
        }
    }


    // variable to keep track of time
    float gpu_time;

    // create start and stop events
    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    // ******************************************************************************
    // ================================ GPU =========================================
    // ******************************************************************************

    // the final matrix will have size m x k
    // we need to spawn enough threads to compute all of the entries

    unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
    unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;

    printf("---------------------------------------------\n");
    printf("The resulting matrix will be of size %d x %d\n", m, k);
    printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
    printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
    printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
    printf("---------------------------------------------\n\n");
    printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
    getchar();
    getchar();

    // start to count execution time of GPU version
    cudaEventRecord(start, 0);

    // Allocate memory space on the device
    int *gpu_a, *gpu_b, *gpu_c;
    cudaMalloc((void **) &gpu_a, sizeof(int)*m*n);
    cudaMalloc((void **) &gpu_b, sizeof(int)*n*k);
    cudaMalloc((void **) &gpu_c, sizeof(int)*m*k);

    // copy matrix A and B from host to device memory
    cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
    cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);

    dim3 dimGrid(grid_cols, grid_rows);
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);

    // Launch kernel
    // Kernels will always be launched using triple brackets
    // the first input in the triple brackets is the dimension of the grid
    // the second is the dimension of the block
    gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);

    // Transefer results from device to host
    cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
    cudaThreadSynchronize();

    // time counting terminate
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    // compute time elapse on GPU computing
    cudaEventElapsedTime(&gpu_time, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);

    printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
    getchar();

    // start to count execution time of GPU version
    cudaEventRecord(start, 0);

    // copy matrix A and B from host to device memory
    cudaMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
    cudaMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);

    // Launch kernel
    // Kernels will always be launched using triple brackets
    // the first input in the triple brackets is the dimension of the grid
    // the second is the dimension of the block
    gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);

    // Transefer results from device to host
    cudaMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
    cudaThreadSynchronize();

    // time counting terminate
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);

    // compute time elapse on GPU computing
    cudaEventElapsedTime(&gpu_time, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);

    // fin
    return 0;
}
	.file	"tmpxft_00385073_00000000-6_mat_mult_tile.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
	.type	_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
	.globl	_Z19gpu_matrix_mult_onePiS_S_iii
	.type	_Z19gpu_matrix_mult_onePiS_S_iii, @function
_Z19gpu_matrix_mult_onePiS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z19gpu_matrix_mult_onePiS_S_iii, .-_Z19gpu_matrix_mult_onePiS_S_iii
	.globl	_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
	.type	_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, @function
_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii, .-_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
	.globl	_Z19gpu_matrix_mult_twoPiS_S_iii
	.type	_Z19gpu_matrix_mult_twoPiS_S_iii, @function
_Z19gpu_matrix_mult_twoPiS_S_iii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2055:
	.size	_Z19gpu_matrix_mult_twoPiS_S_iii, .-_Z19gpu_matrix_mult_twoPiS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"---------------------------------------------\n"
.LC1:
	.string	"We will be multiplying two matrices\n"
.LC2:
	.string	"The first will be of size m x n\n"
.LC3:
	.string	"The second will be of size n x k\n"
.LC4:
	.string	"I will have you choose these dimensions!\n"
.LC5:
	.string	"---------------------------------------------\n\n"
.LC6:
	.string	"Input m:\n"
.LC7:
	.string	"%d"
.LC8:
	.string	"\nInput n:\n"
.LC9:
	.string	"\nInput k:\n"
.LC10:
	.string	"\n"
.LC11:
	.string	"The resulting matrix will be of size %d x %d\n"
.LC12:
	.string	"\nI am launching a grid size of %d x %d blocks\n"
.LC13:
	.string	"Each block will be %d x %d threads\n"
.LC14:
	.string	"This will give you %d x %d available threads\n"
.LC15:
	.string	"Press ENTER to begin computation on GPU (w/o tiling)...\n"
.LC16:
	.string	"Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
.LC17:
	.string	"Press ENTER to begin computation on GPU (w/tiling)...\n"
.LC18:
	.string	"Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$2, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	.LC0(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%r13, %rsi
	leaq	.LC5(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	.LC7(%rip), %rbx
	addq	$-128, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	leaq	8(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	leaq	12(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	leaq	16(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	8(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	24(%rsp), %rdi
	movl	$1024, %ebx
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movslq	12(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	32(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movslq	8(%rsp), %rsi
	movslq	16(%rsp), %rax
	xorl	%ebp, %ebp
	leaq	48(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movslq	8(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	40(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
.L14:
	xorl	%r14d, %r14d
	cmpl	%ebp, 8(%rsp)
	jle	.L26
.L16:
	cmpl	%r14d, 12(%rsp)
	jle	.L27
	call	rand@PLT
	movl	12(%rsp), %ecx
	cltd
	idivl	%ebx
	movq	24(%rsp), %rax
	imull	%ebp, %ecx
	addl	%r14d, %ecx
	incl	%r14d
	movslq	%ecx, %rcx
	movl	%edx, (%rax,%rcx,4)
	jmp	.L16
.L27:
	incl	%ebp
	jmp	.L14
.L26:
	movl	$1024, %ebx
.L17:
	cmpl	%r14d, 12(%rsp)
	jle	.L28
	xorl	%ebp, %ebp
.L19:
	cmpl	%ebp, 16(%rsp)
	jle	.L29
	call	rand@PLT
	movl	12(%rsp), %ecx
	imull	16(%rsp), %ecx
	cltd
	idivl	%ebx
	movq	32(%rsp), %rax
	addl	%ebp, %ecx
	incl	%ebp
	movslq	%ecx, %rcx
	movl	%edx, (%rax,%rcx,4)
	jmp	.L19
.L29:
	incl	%r14d
	jmp	.L17
.L28:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	8(%rsp), %eax
	movl	$16, %ecx
	movq	%r13, %rsi
	movl	$2, %edi
	addl	$15, %eax
	cltd
	idivl	%ecx
	movl	%eax, %ebx
	movl	16(%rsp), %eax
	addl	$15, %eax
	cltd
	idivl	%ecx
	movl	%eax, %ebp
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	16(%rsp), %ecx
	movl	8(%rsp), %edx
	xorl	%eax, %eax
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%ebp, %ecx
	movl	%ebx, %edx
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$16, %ecx
	movl	$16, %edx
	xorl	%eax, %eax
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%ebp, %ecx
	movl	%ebx, %edx
	leaq	.LC14(%rip), %rsi
	sall	$4, %ecx
	sall	$4, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	getchar@PLT
	call	getchar@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movslq	8(%rsp), %rsi
	movslq	12(%rsp), %rax
	leaq	72(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	12(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	80(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	88(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rdx
	movslq	12(%rsp), %rax
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	imulq	%rax, %rdx
	movq	%rdi, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	12(%rsp), %rdx
	movslq	16(%rsp), %rax
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	imulq	%rax, %rdx
	movq	%rdi, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	%ebp, 96(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebx, 100(%rsp)
	movq	96(%rsp), %rdi
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movl	$1, 104(%rsp)
	movq	%rdx, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movl	16(%rsp), %r9d
	movl	12(%rsp), %r8d
	movl	8(%rsp), %ecx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z46__device_stub__Z19gpu_matrix_mult_onePiS_S_iiiPiS_S_iii
.L20:
	movslq	8(%rsp), %rdx
	movslq	16(%rsp), %rax
	movl	$2, %ecx
	leaq	20(%rsp), %rbx
	movq	88(%rsp), %rsi
	movq	48(%rsp), %rdi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	movl	12(%rsp), %ecx
	movl	16(%rsp), %r9d
	movb	$1, %al
	movl	8(%rsp), %edx
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	20(%rsp), %xmm0
	movl	%ecx, %r8d
	call	__printf_chk@PLT
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	getchar@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movslq	8(%rsp), %rdx
	movslq	12(%rsp), %rax
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	imulq	%rax, %rdx
	movq	%rdi, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	12(%rsp), %rdx
	movslq	16(%rsp), %rax
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	imulq	%rax, %rdx
	movq	%rdi, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	116(%rsp), %ecx
	movl	104(%rsp), %esi
	xorl	%r9d, %r9d
	movq	108(%rsp), %rdx
	movq	96(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movl	16(%rsp), %r9d
	movl	12(%rsp), %r8d
	movl	8(%rsp), %ecx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z46__device_stub__Z19gpu_matrix_mult_twoPiS_S_iiiPiS_S_iii
.L21:
	movslq	8(%rsp), %rdx
	movslq	16(%rsp), %rax
	movl	$2, %ecx
	movq	88(%rsp), %rsi
	movq	48(%rsp), %rdi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	%rbx, %rdi
	call	cudaEventElapsedTime@PLT
	movl	12(%rsp), %ecx
	movl	16(%rsp), %r9d
	movb	$1, %al
	movl	8(%rsp), %edx
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	20(%rsp), %xmm0
	movl	%ecx, %r8d
	call	__printf_chk@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC19:
	.string	"_Z19gpu_matrix_mult_twoPiS_S_iii"
.LC20:
	.string	"_Z19gpu_matrix_mult_onePiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19gpu_matrix_mult_twoPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19gpu_matrix_mult_onePiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define TILE_WIDTH 16

__global__ void gpu_matrix_mult_one(int *a, int *b, int *c, int m, int n, int k)
{
    int row = blockIdx.y * blockDim.y + threadIdx.y; // get the row
    int col = blockIdx.x * blockDim.x + threadIdx.x; // get the column
    int sum = 0; // initialize the sum

    if( col < k && row < m) // check to make sure that the thread needs to compute
    {
        for(int i = 0; i < n; i++)
        {
            sum += a[row * n + i] * b[i * k + col];
        }
        c[row * k + col] = sum;
    }
}

__global__ void gpu_matrix_mult_two(int *d_M, int *d_N, int *d_P, int m, int n, int k)
{

    // shared memory for tiling
    __shared__ int Mds [TILE_WIDTH][TILE_WIDTH];
    __shared__ int Nds [TILE_WIDTH][TILE_WIDTH];

    int bx = blockIdx.x;  int by = blockIdx.y;
    int tx = threadIdx.x; int ty = threadIdx.y;

    // recall that TILE_WIDTH = blockDim
    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    int pval = 0;

    // this loop is iterating through cols of M and rows of N
    // recall that n is the shared inner dimension, that's why we're using it
    // to define our loop size
    for (int ph = 0; ph < n / TILE_WIDTH; ph++){
        // boundary check for shared Mds
        if (row < k && ph * TILE_WIDTH + tx < m){
            // saving tile from M
            /* indexing thought exercise:
             * "row * k" gets us to our desired row in M
             * adding "ph * TILE_WIDTH" moves our tile over to the desired tile location
             * adding "tx" moves us to the desired location within the tile
             * */
            Mds[ty][tx] = d_M[row * k + ph * TILE_WIDTH + tx];
        }
        // boundary check
        if (ph*TILE_WIDTH + ty < k && col < m){
            // saving tile from N
            /* indexing thought exercise:
             * "ph * TILE_WIDTH" moves the tile "down" to the desired location
             * adding "ty" gets us to the desired location within the tile
             * multiplying by "k" does the magic (remember row major order)
             * adding col moves the tile to the desired column*/
            Nds[ty][tx] = d_N[(ph * TILE_WIDTH + ty) * k + col];
        }

        __syncthreads();  // execution barrier

        for (int j = 0; j < TILE_WIDTH; j++){
            // performing part of inner product
            pval += Mds[ty][j] * Nds[j][tx];
        }

        __syncthreads();
    }
    if (row < k && col < m){
        d_P[row * k + col] = pval;
    }
}

int main(int argc, char const *argv[])
{
    int m, n, k; // init matrix dimensions
    printf("---------------------------------------------\n");
    printf("We will be multiplying two matrices\n");
    printf("The first will be of size m x n\n");
    printf("The second will be of size n x k\n");
    printf("I will have you choose these dimensions!\n");
    printf("---------------------------------------------\n\n");
    printf("Input m:\n");
    scanf("%d", &m);
    printf("\nInput n:\n");
    scanf("%d", &n);
    printf("\nInput k:\n");
    scanf("%d", &k);
    printf("\n");


    // Initialize pointers
    int *cpu_a, *cpu_b, *cpu_result, *cpu_c;

    // Allocate memory to the pointers on the host
    hipHostMalloc((void **) &cpu_a, sizeof(int)*m*n, hipHostMallocDefault); // matrix a
    hipHostMalloc((void **) &cpu_b, sizeof(int)*n*k, hipHostMallocDefault); // matrix b
    hipHostMalloc((void **) &cpu_c, sizeof(int)*m*k, hipHostMallocDefault); // cpu memory for gpu result
    hipHostMalloc((void **) &cpu_result, sizeof(int)*m*k, hipHostMallocDefault); // cpu result

    // Generate the matrices
    // cpu_a
    for (int i = 0; i < m; i++)
    {
        for (int j = 0; j < n; j++)
        {
            cpu_a[i * n + j] = rand () % 1024;
        }
    }

    // cpu_b
    for (int i = 0; i < n; i++)
    {
        for (int j = 0; j < k; j++)
        {
            cpu_b[n * k + j] = rand () % 1024;
        }
    }


    // variable to keep track of time
    float gpu_time;

    // create start and stop events
    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    // ******************************************************************************
    // ================================ GPU =========================================
    // ******************************************************************************

    // the final matrix will have size m x k
    // we need to spawn enough threads to compute all of the entries

    unsigned int grid_rows = (m + TILE_WIDTH - 1) / TILE_WIDTH;
    unsigned int grid_cols = (k + TILE_WIDTH - 1) / TILE_WIDTH;

    printf("---------------------------------------------\n");
    printf("The resulting matrix will be of size %d x %d\n", m, k);
    printf("\nI am launching a grid size of %d x %d blocks\n", grid_rows, grid_cols);
    printf("Each block will be %d x %d threads\n",TILE_WIDTH,TILE_WIDTH);
    printf("This will give you %d x %d available threads\n",grid_rows*TILE_WIDTH,grid_cols*TILE_WIDTH);
    printf("---------------------------------------------\n\n");
    printf("Press ENTER to begin computation on GPU (w/o tiling)...\n");
    getchar();
    getchar();

    // start to count execution time of GPU version
    hipEventRecord(start, 0);

    // Allocate memory space on the device
    int *gpu_a, *gpu_b, *gpu_c;
    hipMalloc((void **) &gpu_a, sizeof(int)*m*n);
    hipMalloc((void **) &gpu_b, sizeof(int)*n*k);
    hipMalloc((void **) &gpu_c, sizeof(int)*m*k);

    // copy matrix A and B from host to device memory
    hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
    hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);

    dim3 dimGrid(grid_cols, grid_rows);
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);

    // Launch kernel
    // Kernels will always be launched using triple brackets
    // the first input in the triple brackets is the dimension of the grid
    // the second is the dimension of the block
    gpu_matrix_mult_one<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);

    // Transefer results from device to host
    hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
    hipDeviceSynchronize();

    // time counting terminate
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    // compute time elapse on GPU computing
    hipEventElapsedTime(&gpu_time, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n", m, n, n, k, gpu_time);

    printf("Press ENTER to begin computation on GPU (w/tiling)...\n");
    getchar();

    // start to count execution time of GPU version
    hipEventRecord(start, 0);

    // copy matrix A and B from host to device memory
    hipMemcpy(gpu_a, gpu_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
    hipMemcpy(gpu_b, gpu_b, sizeof(int)*n*k, hipMemcpyHostToDevice);

    // Launch kernel
    // Kernels will always be launched using triple brackets
    // the first input in the triple brackets is the dimension of the grid
    // the second is the dimension of the block
    gpu_matrix_mult_two<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c, m, n, k);

    // Transefer results from device to host
    hipMemcpy(cpu_c, gpu_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
    hipDeviceSynchronize();

    // time counting terminate
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);

    // compute time elapse on GPU computing
    hipEventElapsedTime(&gpu_time, start, stop);
    printf("Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n", m, n, n, k, gpu_time);

    // fin
    return 0;
}
	.text
	.file	"mat_mult_tile.hip"
	.globl	_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
	.type	_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19gpu_matrix_mult_onePiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii, .Lfunc_end0-_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii # -- Begin function _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
	.type	_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii,@function
_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii: # @_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19gpu_matrix_mult_twoPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii, .Lfunc_end1-_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movl	$.Lstr.10, %edi
	callq	puts@PLT
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
	leaq	20(%rsp), %rbx
	movl	$.L.str.7, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	leaq	16(%rsp), %r14
	movl	$.L.str.7, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.Lstr.8, %edi
	callq	puts@PLT
	leaq	12(%rsp), %r15
	movl	$.L.str.7, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$10, %edi
	callq	putchar@PLT
	movslq	(%rbx), %rax
	movslq	(%r14), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	88(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%r14), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	80(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%rbx), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	72(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%rbx), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	96(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	(%rbx), %ecx
	movl	(%r14), %eax
	testl	%ecx, %ecx
	jle	.LBB2_6
.LBB2_1:                                # %.preheader55
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
	testl	%eax, %eax
	jle	.LBB2_5
# %bb.2:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_1 Depth=1
	movslq	%r12d, %rbx
	xorl	%r14d, %r14d
.LBB2_3:                                # %.lr.ph
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	88(%rsp), %rcx
	movslq	16(%rsp), %rdx
	imulq	%rbx, %rdx
	addq	%r14, %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	16(%rsp), %eax
	incq	%r14
	cmpl	%eax, %r14d
	jl	.LBB2_3
# %bb.4:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB2_1 Depth=1
	movl	20(%rsp), %ecx
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_1 Depth=1
	incl	%r12d
	cmpl	%ecx, %r12d
	jl	.LBB2_1
.LBB2_6:                                # %.preheader54
	testl	%eax, %eax
	jle	.LBB2_13
# %bb.7:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	movl	12(%rsp), %ecx
.LBB2_8:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_10 Depth 2
	testl	%ecx, %ecx
	jle	.LBB2_12
# %bb.9:                                # %.lr.ph59.preheader
                                        #   in Loop: Header=BB2_8 Depth=1
	xorl	%r14d, %r14d
.LBB2_10:                               # %.lr.ph59
                                        #   Parent Loop BB2_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	80(%rsp), %rcx
	movslq	16(%rsp), %rdx
	movslq	12(%rsp), %rsi
	imulq	%rdx, %rsi
	addq	%r14, %rsi
	movl	%eax, (%rcx,%rsi,4)
	movl	12(%rsp), %ecx
	incq	%r14
	cmpl	%ecx, %r14d
	jl	.LBB2_10
# %bb.11:                               # %._crit_edge60.loopexit
                                        #   in Loop: Header=BB2_8 Depth=1
	movl	16(%rsp), %eax
.LBB2_12:                               # %._crit_edge60
                                        #   in Loop: Header=BB2_8 Depth=1
	incl	%ebx
	cmpl	%eax, %ebx
	jl	.LBB2_8
.LBB2_13:                               # %._crit_edge62
	movabsq	$68719476752, %rbx              # imm = 0x1000000010
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movl	20(%rsp), %r13d
	leal	15(%r13), %eax
	addl	$30, %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	movl	%r13d, %r14d
	sarl	$4, %r14d
	movl	12(%rsp), %ebp
	leal	15(%rbp), %eax
	addl	$30, %ebp
	testl	%eax, %eax
	cmovnsl	%eax, %ebp
	movl	%ebp, %r15d
	sarl	$4, %r15d
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	movl	20(%rsp), %esi
	movl	12(%rsp), %edx
	movl	$.L.str.11, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.12, %edi
	movl	%r14d, %esi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.13, %edi
	movl	$16, %esi
	movl	$16, %edx
	xorl	%eax, %eax
	callq	printf
	andl	$-16, %r13d
	andl	$-16, %ebp
	movl	$.L.str.14, %edi
	movl	%r13d, %esi
	movl	%ebp, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.10, %edi
	callq	puts@PLT
	movl	$.Lstr.11, %edi
	callq	puts@PLT
	callq	getchar
	callq	getchar
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	48(%rsp), %r13
	movq	%r13, %rdi
	callq	hipMalloc
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movslq	20(%rsp), %rax
	movslq	12(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rdi, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rdi, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	shlq	$32, %r14
	orq	%r15, %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	20(%rsp), %ecx
	movl	16(%rsp), %r8d
	movl	12(%rsp), %r9d
	callq	_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
.LBB2_15:
	movq	72(%rsp), %rdi
	movq	32(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	68(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movl	20(%rsp), %esi
	movl	16(%rsp), %ecx
	movl	12(%rsp), %r8d
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.16, %edi
	movl	%ecx, %edx
	movb	$1, %al
	callq	printf
	movl	$.Lstr.12, %edi
	callq	puts@PLT
	callq	getchar
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	48(%rsp), %rdi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rdi, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movslq	16(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rdi, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_17
# %bb.16:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	20(%rsp), %ecx
	movl	16(%rsp), %r8d
	movl	12(%rsp), %r9d
	callq	_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
.LBB2_17:
	movq	72(%rsp), %rdi
	movq	32(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	12(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	68(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	20(%rsp), %esi
	movl	16(%rsp), %ecx
	movl	12(%rsp), %r8d
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.18, %edi
	movl	%ecx, %edx
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19gpu_matrix_mult_onePiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19gpu_matrix_mult_twoPiS_S_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19gpu_matrix_mult_onePiS_S_iii,@object # @_Z19gpu_matrix_mult_onePiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z19gpu_matrix_mult_onePiS_S_iii
	.p2align	3, 0x0
_Z19gpu_matrix_mult_onePiS_S_iii:
	.quad	_Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
	.size	_Z19gpu_matrix_mult_onePiS_S_iii, 8

	.type	_Z19gpu_matrix_mult_twoPiS_S_iii,@object # @_Z19gpu_matrix_mult_twoPiS_S_iii
	.globl	_Z19gpu_matrix_mult_twoPiS_S_iii
	.p2align	3, 0x0
_Z19gpu_matrix_mult_twoPiS_S_iii:
	.quad	_Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
	.size	_Z19gpu_matrix_mult_twoPiS_S_iii, 8

	.type	.L.str.7,@object                # @.str.7
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.7:
	.asciz	"%d"
	.size	.L.str.7, 3

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"The resulting matrix will be of size %d x %d\n"
	.size	.L.str.11, 46

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"\nI am launching a grid size of %d x %d blocks\n"
	.size	.L.str.12, 47

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Each block will be %d x %d threads\n"
	.size	.L.str.13, 36

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"This will give you %d x %d available threads\n"
	.size	.L.str.14, 46

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITHOUT tiling: %f ms.\n\n"
	.size	.L.str.16, 87

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Time elapsed on matrix multiplication of %dx%d * %dx%d on GPU WITH tiling: %f ms.\n\n"
	.size	.L.str.18, 84

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19gpu_matrix_mult_onePiS_S_iii"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19gpu_matrix_mult_twoPiS_S_iii"
	.size	.L__unnamed_2, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.1,@object                 # @str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
	.asciz	"We will be multiplying two matrices"
	.size	.Lstr.1, 36

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"The first will be of size m x n"
	.size	.Lstr.2, 32

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"The second will be of size n x k"
	.size	.Lstr.3, 33

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"I will have you choose these dimensions!"
	.size	.Lstr.4, 41

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Input m:"
	.size	.Lstr.6, 9

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"\nInput n:"
	.size	.Lstr.7, 10

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"\nInput k:"
	.size	.Lstr.8, 10

	.type	.Lstr.9,@object                 # @str.9
.Lstr.9:
	.asciz	"---------------------------------------------"
	.size	.Lstr.9, 46

	.type	.Lstr.10,@object                # @str.10
.Lstr.10:
	.asciz	"---------------------------------------------\n"
	.size	.Lstr.10, 47

	.type	.Lstr.11,@object                # @str.11
.Lstr.11:
	.asciz	"Press ENTER to begin computation on GPU (w/o tiling)..."
	.size	.Lstr.11, 56

	.type	.Lstr.12,@object                # @str.12
.Lstr.12:
	.asciz	"Press ENTER to begin computation on GPU (w/tiling)..."
	.size	.Lstr.12, 54

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__gpu_matrix_mult_onePiS_S_iii
	.addrsig_sym _Z34__device_stub__gpu_matrix_mult_twoPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19gpu_matrix_mult_onePiS_S_iii
	.addrsig_sym _Z19gpu_matrix_mult_twoPiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19gpu_matrix_mult_onePiS_S_iii ; -- Begin function _Z19gpu_matrix_mult_onePiS_S_iii
	.globl	_Z19gpu_matrix_mult_onePiS_S_iii
	.p2align	8
	.type	_Z19gpu_matrix_mult_onePiS_S_iii,@function
_Z19gpu_matrix_mult_onePiS_S_iii:       ; @_Z19gpu_matrix_mult_onePiS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s5
	v_mov_b32_e32 v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_add_i32 s5, s5, -1
	s_cmp_eq_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v8, v[3:4], off
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s6, v5
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v2, 0
.LBB0_5:                                ; %Flow54
	v_mad_u64_u32 v[3:4], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19gpu_matrix_mult_onePiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19gpu_matrix_mult_onePiS_S_iii, .Lfunc_end0-_Z19gpu_matrix_mult_onePiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19gpu_matrix_mult_twoPiS_S_iii ; -- Begin function _Z19gpu_matrix_mult_twoPiS_S_iii
	.globl	_Z19gpu_matrix_mult_twoPiS_S_iii
	.p2align	8
	.type	_Z19gpu_matrix_mult_twoPiS_S_iii,@function
_Z19gpu_matrix_mult_twoPiS_S_iii:       ; @_Z19gpu_matrix_mult_twoPiS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, s15, 4, v3
	v_lshl_add_u32 v0, s14, 4, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v2
	v_cmp_gt_i32_e64 s0, s4, v0
	s_cmp_lt_i32 s5, 16
	s_cbranch_scc1 .LBB1_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v1, 2, v4
	v_lshlrev_b32_e32 v5, 6, v3
	s_ashr_i32 s1, s5, 31
	v_mul_lo_u32 v7, v2, s6
	s_lshr_b32 s1, s1, 28
	v_add_nc_u32_e32 v6, 0x400, v1
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v8, v5, v1
	s_add_i32 s1, s5, s1
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v6, v5
	s_ashr_i32 s5, s1, 4
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	s_lshl_b32 s12, s7, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, s12, v4
	v_cmp_gt_i32_e64 s1, s4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v10, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s8, v10
	v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10
.LBB1_4:                                ; %._crit_edge64
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v10, s12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s6, v10
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s1
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[11:12], null, v10, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s10, v10
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v10
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_mov_b32_e32 v10, v6
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s1, v5
	s_add_i32 s1, s1, 4
	ds_load_b32 v13, v10
	ds_load_b32 v14, v11
	s_cmp_eq_u32 s1, 64
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[11:12], null, v13, v14, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v1, v11 :: v_dual_add_nc_u32 v10, 64, v10
	s_cbranch_scc0 .LBB1_7
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_9:                                ; %Flow88
	v_cmp_gt_i32_e32 vcc_lo, s6, v2
	v_cmp_gt_i32_e64 s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB1_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19gpu_matrix_mult_twoPiS_S_iii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19gpu_matrix_mult_twoPiS_S_iii, .Lfunc_end1-_Z19gpu_matrix_mult_twoPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19gpu_matrix_mult_onePiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19gpu_matrix_mult_onePiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19gpu_matrix_mult_twoPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19gpu_matrix_mult_twoPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
