/*
* FILE: isingV3.cu
* THMMY, 7th semester, Parallel and Distributed Systems: 3rd assignment
* Parallel Implementation with shared memory of the Ising Model
* Authors:
*   Moustaklis Apostolos, 9127, amoustakl@ece.auth.gr
*   Papadakis Charis , 9128, papadakic@ece.auth.gr
* Compile command with :
*   make all
* Run command example:
*   ./src/isingV3
* It will calculate the evolution of the ising Model
* for a given number n  of points and k steps
*/


#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>

// Defines for the block and grid calculation
#define BLOCK_SIZE_X 16
#define BLOCK_SIZE_Y 16
//The dimensions of the lattice
#define N_X 517
#define N_Y 517

// The size of the weights and the radius of the "stencil"
#define WSIZE 5
#define RADIUS 2

//Helper Defines to access easier the arrays
#define old(i,j,n) *(old+(i)*n+j)
#define current(i,j,n) *(current+(i)*n+j)
#define w(i,j) *(w+(i)*5+j)
#define d_w(i,j) *(d_w+(i)*5+j)
#define s_w(i,j) *(s_w+(i)*5+j)
#define d_current(i,j,n) *(d_current+(i)*n+j)
#define d_old(i,j,n) *(d_old+(i)*n+j)
#define G(i,j,n) *(G+(i)*n+j)
#define s_old(i,j) *(s_old + (i)*(BLOCK_SIZE_X+2*RADIUS) + j)



//Functions Declaration
void swapElement(int  ** one, int  ** two);
__global__
   void kernel2D(int *d_current, int *d_old, double *d_w, int n , int * d_flag);
void ising( int *G, double *w, int k, int n);


//! Ising model evolution
/*!

  \param G      Spins on the square lattice             [n-by-n]
  \param w      Weight matrix                           [5-by-5]
  \param k      Number of iterations                    [scalar]
  \param n      Number of lattice points per dim        [scalar]

  NOTE: Both matrices G and w are stored in row-major format.
*/

void ising( int *G, double *w, int k, int n){

  //Grid and block construction
  dim3 block(BLOCK_SIZE_X,BLOCK_SIZE_Y);
  int grid_size_x  = (N_X + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
  int grid_size_y  = (N_Y + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
  dim3 grid(grid_size_x,grid_size_y);
  //Device memory allocation
  int * old = (int*) malloc(n*n*(size_t)sizeof(int)); // old spin lattice
  int * current = (int*) malloc(n*n*(size_t)sizeof(int)); // current spin lattice

  //Leak check
  if(old==NULL || current == NULL){
      printf("Problem at memory allocation at host \n");
      exit(0);
      }

  int * d_old;
  int * d_current;
  double * d_w;
  int *d_flag ;
  int flag ;
  //Host memory allocation and leak check
  if( cudaMalloc((void **)&d_old ,n*n*(size_t)sizeof(int)) != cudaSuccess  || cudaMalloc((void **)&d_current,n*n*(size_t)sizeof(int))   != cudaSuccess   || cudaMalloc((void **)&d_w, WSIZE*WSIZE*(size_t)sizeof(double))   != cudaSuccess || cudaMalloc(&d_flag,(size_t)sizeof(int)) !=cudaSuccess){
    printf("Problem at memory allocation");
    exit(0);
  }
  //Copy memory from host to device
  cudaMemcpy(d_w, w, WSIZE*WSIZE*sizeof(double), cudaMemcpyHostToDevice );
  cudaMemcpy(d_old, G, n*n*sizeof(int), cudaMemcpyHostToDevice );


  // run for k steps
  for(int l=0; l<k; l++){
    flag = 0;
    kernel2D<<<grid,block>>>(d_current, d_old, d_w, n  , d_flag );
    cudaDeviceSynchronize();

  //  cudaMemcpy(old, d_old, n*n*sizeof(int), cudaMemcpyDeviceToHost );
    cudaMemcpy(current, d_current, n*n*sizeof(int), cudaMemcpyDeviceToHost );
    // save result in G
    memcpy(G , current , n*n*sizeof(int));

    // swap the pointers for the next iteration
    swapElement(&d_old,&d_current);

    cudaMemcpy(&flag , d_flag , (size_t)sizeof(int), cudaMemcpyDeviceToHost);
    // terminate if no changes are made
    if(flag){
        printf("terminated: spin values stay same (step %d)\n" , l);
      exit(0);
    }
  }
  //Memory deallocation
  free(old);
  free(current);
  cudaFree(d_old);
  cudaFree(d_current);
  cudaFree(d_w);
}

//Helper function to swap the pointers of the arrays
void swapElement(int  ** one, int  ** two) {
  int  * temp = * one;
  * one = * two;
  * two = temp;
}

 //The kernel function that updates the values of the ising model
__global__
void kernel2D(int *d_current, int *d_old, double *d_w, int n , int * d_flag){

  double influence = 0;
  // Compute global  column and row indices
  int r = blockIdx.x * blockDim.x + threadIdx.x;
  int c = blockIdx.y * blockDim.y + threadIdx.y;
  // Compute local  column and row indices
  int lxindex = threadIdx.x + RADIUS;
  int lyindex = threadIdx.y + RADIUS;
  //The strides
  int strideX = blockDim.x*gridDim.x ;
  int strideY = blockDim.y*gridDim.y ;

  __shared__ double s_w[WSIZE*WSIZE];
  __shared__ int s_old[(BLOCK_SIZE_X + 2*RADIUS)*(BLOCK_SIZE_Y + 2*RADIUS)];

  //Fully Parallel Shared weights
  //incase we have sufficient amount of threads ( threads at X > WSIZE AND  threads at Y > WSIZE)
  if(blockDim.x > WSIZE && blockDim.y > WSIZE ){
    if(threadIdx.x < WSIZE && threadIdx.y < WSIZE){
      s_w(threadIdx.x, threadIdx.y) = d_w(threadIdx.x, threadIdx.y);
    }
  }
  //Otherwise
  //threadIdx.x == 0  , threadIdx.y == 0 will copy
  else{
    if(threadIdx.x == 0 && threadIdx.y == 0){
      for(int i = 0 ; i<WSIZE ; i++){
        for(int j =0; j<WSIZE ; j++){
          s_w(i,j)=d_w(i,j);
        }
      }
    }
  }
  __syncthreads();

  // // Read input elements into shared memory
  for(int i=r; i<n+RADIUS; i+= strideX){
    for(int j=c; j<n+RADIUS ; j+= strideY ){

      // window for old to shared
      s_old(lxindex,lyindex) = d_old((i+n)%n,(j+n)%n,n);
      __syncthreads();

      //stencil at  x
      if( threadIdx.y < RADIUS){
        s_old( lxindex , lyindex - RADIUS ) = d_old((i + n)%n , (j-RADIUS+n)%n , n);
        s_old(lxindex  , lyindex + BLOCK_SIZE_Y ) = d_old( (i + n )%n , (j+BLOCK_SIZE_X + n)%n , n);
      }

      //stencil at  y
      if( threadIdx.x < RADIUS){
        s_old(lxindex  - RADIUS,lyindex ) = d_old( (i-RADIUS+n)%n , (j+n)%n   , n );
        s_old( lxindex + BLOCK_SIZE_Y,lyindex ) = d_old(( i +BLOCK_SIZE_X +n)%n , (j +  n)%n     , n );
      }

      //4X4 squares at the corners
      if(threadIdx.x < RADIUS && threadIdx.y < RADIUS ){
        //panw aristera
        s_old(lxindex - RADIUS , lyindex - RADIUS ) = d_old ( ( i - RADIUS + n)%n , (j-RADIUS + n )%n  , n );
        //katw deksia
        s_old(lxindex +  BLOCK_SIZE_X , lyindex + BLOCK_SIZE_Y  ) = d_old( (i  + BLOCK_SIZE_X + n  )%n , (j + BLOCK_SIZE_Y +n  )%n , n);
        //katw aristera
        s_old(lxindex - RADIUS, lyindex +  BLOCK_SIZE_Y  )= d_old ((i - RADIUS + n)%n  , (j  + BLOCK_SIZE_X )%n, n);
        //panw deksia
        s_old(lxindex + BLOCK_SIZE_X,lyindex - RADIUS  ) = d_old ((i + BLOCK_SIZE_X+n  )%n , (j -RADIUS + n )%n   , n );
      }
      __syncthreads();

      if((i<n)&&(j<n)){
        influence = 0;
        for(int ii=0; ii<WSIZE ; ii++){
          for(int jj=0 ; jj<WSIZE ; jj++){
            if((ii==2) && (jj==2))
            continue;
          //influence calculation
            influence += s_w(ii,jj) * s_old( threadIdx.x + ii,threadIdx.y +  jj );
          }
        }

        // // magnetic moment gets the value of the SIGN of the weighted influence of its neighbors
        if(fabs(influence) < 10e-7){
          d_current(i,j,n) =  s_old(lxindex, lyindex  ); // remains the same in the case that the weighted influence is zero
        }
        else if(influence > 10e-7){
          d_current(i,j,n) = 1;
          *d_flag = 0;

        }
        else if(influence < 0){
          d_current(i,j,n) = -1;
          *d_flag = 0;
        }
      }
      __syncthreads();
    }
  }

}

	.file	"tmpxft_002ff04b_00000000-6_isingV3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11swapElementPPiS0_
	.type	_Z11swapElementPPiS0_, @function
_Z11swapElementPPiS0_:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	movq	(%rsi), %rdx
	movq	%rdx, (%rdi)
	movq	%rax, (%rsi)
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z11swapElementPPiS0_, .-_Z11swapElementPPiS0_
	.globl	_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_
	.type	_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_, @function
_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z8kernel2DPiS_PdiS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L3:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_, .-_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_
	.globl	_Z8kernel2DPiS_PdiS_
	.type	_Z8kernel2DPiS_PdiS_, @function
_Z8kernel2DPiS_PdiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_
	.cfi_endproc
.LFE2054:
	.size	_Z8kernel2DPiS_PdiS_, .-_Z8kernel2DPiS_PdiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Problem at memory allocation at host \n"
.LC1:
	.string	"Problem at memory allocation"
.LC2:
	.string	"terminated: spin values stay same (step %d)\n"
	.text
	.globl	_Z5isingPiPdii
	.type	_Z5isingPiPdii, @function
_Z5isingPiPdii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	movabsq	$68719476752, %rax
	movl	$1, 72(%rsp)
	movl	$1, 84(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$141733920801, %rax
	movq	%rax, 76(%rsp)
	movl	%ecx, %eax
	imull	%ecx, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, %r12
	call	malloc@PLT
	testq	%r12, %r12
	je	.L19
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L10
.L19:
	leaq	.LC0(%rip), %rsi
	jmp	.L21
.L10:
	movq	(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L12
.L13:
	leaq	.LC1(%rip), %rsi
.L21:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L22:
	xorl	%edi, %edi
	call	exit@PLT
.L12:
	movq	(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L13
	leaq	48(%rsp), %rdi
	movl	$200, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L13
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L13
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	xorl	%r13d, %r13d
	movl	$200, %edx
	leaq	28(%rsp), %r15
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
.L14:
	cmpl	%r14d, %r13d
	jge	.L23
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%eax, %eax
	xorl	%r9d, %r9d
	movq	76(%rsp), %rdi
	movl	84(%rsp), %esi
	xorl	%r8d, %r8d
	movl	%eax, 28(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	56(%rsp), %r8
	movq	48(%rsp), %rdx
	movl	%ebp, %ecx
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z34__device_stub__Z8kernel2DPiS_PdiS_PiS_PdiS_
.L15:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movq	(%rsp), %rcx
	movq	%rbx, %rsi
	rep movsb
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rax
	movq	%r15, %rdi
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%rdx, 32(%rsp)
	movl	$4, %edx
	movq	%rax, 40(%rsp)
	call	cudaMemcpy@PLT
	cmpl	$0, 28(%rsp)
	je	.L16
	movl	%r13d, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L22
.L16:
	incl	%r13d
	jmp	.L14
.L23:
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z5isingPiPdii, .-_Z5isingPiPdii
	.section	.rodata.str1.1
.LC3:
	.string	"_Z8kernel2DPiS_PdiS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8kernel2DPiS_PdiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
* FILE: isingV3.cu
* THMMY, 7th semester, Parallel and Distributed Systems: 3rd assignment
* Parallel Implementation with shared memory of the Ising Model
* Authors:
*   Moustaklis Apostolos, 9127, amoustakl@ece.auth.gr
*   Papadakis Charis , 9128, papadakic@ece.auth.gr
* Compile command with :
*   make all
* Run command example:
*   ./src/isingV3
* It will calculate the evolution of the ising Model
* for a given number n  of points and k steps
*/



#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>

// Defines for the block and grid calculation
#define BLOCK_SIZE_X 16
#define BLOCK_SIZE_Y 16
//The dimensions of the lattice
#define N_X 517
#define N_Y 517

// The size of the weights and the radius of the "stencil"
#define WSIZE 5
#define RADIUS 2

//Helper Defines to access easier the arrays
#define old(i,j,n) *(old+(i)*n+j)
#define current(i,j,n) *(current+(i)*n+j)
#define w(i,j) *(w+(i)*5+j)
#define d_w(i,j) *(d_w+(i)*5+j)
#define s_w(i,j) *(s_w+(i)*5+j)
#define d_current(i,j,n) *(d_current+(i)*n+j)
#define d_old(i,j,n) *(d_old+(i)*n+j)
#define G(i,j,n) *(G+(i)*n+j)
#define s_old(i,j) *(s_old + (i)*(BLOCK_SIZE_X+2*RADIUS) + j)



//Functions Declaration
void swapElement(int  ** one, int  ** two);
__global__
   void kernel2D(int *d_current, int *d_old, double *d_w, int n , int * d_flag);
void ising( int *G, double *w, int k, int n);


//! Ising model evolution
/*!

  \param G      Spins on the square lattice             [n-by-n]
  \param w      Weight matrix                           [5-by-5]
  \param k      Number of iterations                    [scalar]
  \param n      Number of lattice points per dim        [scalar]

  NOTE: Both matrices G and w are stored in row-major format.
*/

void ising( int *G, double *w, int k, int n){

  //Grid and block construction
  dim3 block(BLOCK_SIZE_X,BLOCK_SIZE_Y);
  int grid_size_x  = (N_X + BLOCK_SIZE_X - 1) / BLOCK_SIZE_X;
  int grid_size_y  = (N_Y + BLOCK_SIZE_Y - 1) / BLOCK_SIZE_Y;
  dim3 grid(grid_size_x,grid_size_y);
  //Device memory allocation
  int * old = (int*) malloc(n*n*(size_t)sizeof(int)); // old spin lattice
  int * current = (int*) malloc(n*n*(size_t)sizeof(int)); // current spin lattice

  //Leak check
  if(old==NULL || current == NULL){
      printf("Problem at memory allocation at host \n");
      exit(0);
      }

  int * d_old;
  int * d_current;
  double * d_w;
  int *d_flag ;
  int flag ;
  //Host memory allocation and leak check
  if( hipMalloc((void **)&d_old ,n*n*(size_t)sizeof(int)) != hipSuccess  || hipMalloc((void **)&d_current,n*n*(size_t)sizeof(int))   != hipSuccess   || hipMalloc((void **)&d_w, WSIZE*WSIZE*(size_t)sizeof(double))   != hipSuccess || hipMalloc(&d_flag,(size_t)sizeof(int)) !=hipSuccess){
    printf("Problem at memory allocation");
    exit(0);
  }
  //Copy memory from host to device
  hipMemcpy(d_w, w, WSIZE*WSIZE*sizeof(double), hipMemcpyHostToDevice );
  hipMemcpy(d_old, G, n*n*sizeof(int), hipMemcpyHostToDevice );


  // run for k steps
  for(int l=0; l<k; l++){
    flag = 0;
    kernel2D<<<grid,block>>>(d_current, d_old, d_w, n  , d_flag );
    hipDeviceSynchronize();

  //  cudaMemcpy(old, d_old, n*n*sizeof(int), cudaMemcpyDeviceToHost );
    hipMemcpy(current, d_current, n*n*sizeof(int), hipMemcpyDeviceToHost );
    // save result in G
    memcpy(G , current , n*n*sizeof(int));

    // swap the pointers for the next iteration
    swapElement(&d_old,&d_current);

    hipMemcpy(&flag , d_flag , (size_t)sizeof(int), hipMemcpyDeviceToHost);
    // terminate if no changes are made
    if(flag){
        printf("terminated: spin values stay same (step %d)\n" , l);
      exit(0);
    }
  }
  //Memory deallocation
  free(old);
  free(current);
  hipFree(d_old);
  hipFree(d_current);
  hipFree(d_w);
}

//Helper function to swap the pointers of the arrays
void swapElement(int  ** one, int  ** two) {
  int  * temp = * one;
  * one = * two;
  * two = temp;
}

 //The kernel function that updates the values of the ising model
__global__
void kernel2D(int *d_current, int *d_old, double *d_w, int n , int * d_flag){

  double influence = 0;
  // Compute global  column and row indices
  int r = blockIdx.x * blockDim.x + threadIdx.x;
  int c = blockIdx.y * blockDim.y + threadIdx.y;
  // Compute local  column and row indices
  int lxindex = threadIdx.x + RADIUS;
  int lyindex = threadIdx.y + RADIUS;
  //The strides
  int strideX = blockDim.x*gridDim.x ;
  int strideY = blockDim.y*gridDim.y ;

  __shared__ double s_w[WSIZE*WSIZE];
  __shared__ int s_old[(BLOCK_SIZE_X + 2*RADIUS)*(BLOCK_SIZE_Y + 2*RADIUS)];

  //Fully Parallel Shared weights
  //incase we have sufficient amount of threads ( threads at X > WSIZE AND  threads at Y > WSIZE)
  if(blockDim.x > WSIZE && blockDim.y > WSIZE ){
    if(threadIdx.x < WSIZE && threadIdx.y < WSIZE){
      s_w(threadIdx.x, threadIdx.y) = d_w(threadIdx.x, threadIdx.y);
    }
  }
  //Otherwise
  //threadIdx.x == 0  , threadIdx.y == 0 will copy
  else{
    if(threadIdx.x == 0 && threadIdx.y == 0){
      for(int i = 0 ; i<WSIZE ; i++){
        for(int j =0; j<WSIZE ; j++){
          s_w(i,j)=d_w(i,j);
        }
      }
    }
  }
  __syncthreads();

  // // Read input elements into shared memory
  for(int i=r; i<n+RADIUS; i+= strideX){
    for(int j=c; j<n+RADIUS ; j+= strideY ){

      // window for old to shared
      s_old(lxindex,lyindex) = d_old((i+n)%n,(j+n)%n,n);
      __syncthreads();

      //stencil at  x
      if( threadIdx.y < RADIUS){
        s_old( lxindex , lyindex - RADIUS ) = d_old((i + n)%n , (j-RADIUS+n)%n , n);
        s_old(lxindex  , lyindex + BLOCK_SIZE_Y ) = d_old( (i + n )%n , (j+BLOCK_SIZE_X + n)%n , n);
      }

      //stencil at  y
      if( threadIdx.x < RADIUS){
        s_old(lxindex  - RADIUS,lyindex ) = d_old( (i-RADIUS+n)%n , (j+n)%n   , n );
        s_old( lxindex + BLOCK_SIZE_Y,lyindex ) = d_old(( i +BLOCK_SIZE_X +n)%n , (j +  n)%n     , n );
      }

      //4X4 squares at the corners
      if(threadIdx.x < RADIUS && threadIdx.y < RADIUS ){
        //panw aristera
        s_old(lxindex - RADIUS , lyindex - RADIUS ) = d_old ( ( i - RADIUS + n)%n , (j-RADIUS + n )%n  , n );
        //katw deksia
        s_old(lxindex +  BLOCK_SIZE_X , lyindex + BLOCK_SIZE_Y  ) = d_old( (i  + BLOCK_SIZE_X + n  )%n , (j + BLOCK_SIZE_Y +n  )%n , n);
        //katw aristera
        s_old(lxindex - RADIUS, lyindex +  BLOCK_SIZE_Y  )= d_old ((i - RADIUS + n)%n  , (j  + BLOCK_SIZE_X )%n, n);
        //panw deksia
        s_old(lxindex + BLOCK_SIZE_X,lyindex - RADIUS  ) = d_old ((i + BLOCK_SIZE_X+n  )%n , (j -RADIUS + n )%n   , n );
      }
      __syncthreads();

      if((i<n)&&(j<n)){
        influence = 0;
        for(int ii=0; ii<WSIZE ; ii++){
          for(int jj=0 ; jj<WSIZE ; jj++){
            if((ii==2) && (jj==2))
            continue;
          //influence calculation
            influence += s_w(ii,jj) * s_old( threadIdx.x + ii,threadIdx.y +  jj );
          }
        }

        // // magnetic moment gets the value of the SIGN of the weighted influence of its neighbors
        if(fabs(influence) < 10e-7){
          d_current(i,j,n) =  s_old(lxindex, lyindex  ); // remains the same in the case that the weighted influence is zero
        }
        else if(influence > 10e-7){
          d_current(i,j,n) = 1;
          *d_flag = 0;

        }
        else if(influence < 0){
          d_current(i,j,n) = -1;
          *d_flag = 0;
        }
      }
      __syncthreads();
    }
  }

}

	.text
	.file	"isingV3.hip"
	.globl	_Z5isingPiPdii                  # -- Begin function _Z5isingPiPdii
	.type	_Z5isingPiPdii,@function
_Z5isingPiPdii:                         # @_Z5isingPiPdii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	%ecx, 44(%rsp)                  # 4-byte Spill
	movl	%ecx, %r15d
	imull	%r15d, %r15d
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	testq	%rax, %rax
	je	.LBB0_14
# %bb.1:
	movq	%rax, %r12
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB0_13
# %bb.2:
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB0_13
# %bb.3:
	leaq	32(%rsp), %rdi
	movl	$200, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB0_13
# %bb.4:
	leaq	48(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB0_13
# %bb.5:
	movq	32(%rsp), %rdi
	movl	$200, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%ebp, %ebp
	jle	.LBB0_11
# %bb.6:                                # %.lr.ph.preheader
	xorl	%r13d, %r13d
	leaq	28(%rsp), %rbx
.LBB0_7:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$0, 28(%rsp)
	movabsq	$141733920801, %rdi             # imm = 0x2100000021
	movl	$1, %esi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_9
# %bb.8:                                #   in Loop: Header=BB0_7 Depth=1
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	48(%rsp), %r8
	movl	44(%rsp), %ecx                  # 4-byte Reload
	callq	_Z23__device_stub__kernel2DPiS_PdiS_
.LBB0_9:                                #   in Loop: Header=BB0_7 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	memcpy@PLT
	movq	16(%rsp), %rax
	movq	8(%rsp), %rcx
	movq	%rcx, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	48(%rsp), %rsi
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 28(%rsp)
	jne	.LBB0_12
# %bb.10:                               #   in Loop: Header=BB0_7 Depth=1
	incl	%r13d
	cmpl	%r13d, %ebp
	jne	.LBB0_7
.LBB0_11:                               # %._crit_edge
	movq	%r12, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_12:
	.cfi_def_cfa_offset 112
	movl	$.L.str.2, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
.LBB0_15:
	xorl	%edi, %edi
	callq	exit
.LBB0_13:
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB0_15
.LBB0_14:
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB0_15
.Lfunc_end0:
	.size	_Z5isingPiPdii, .Lfunc_end0-_Z5isingPiPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel2DPiS_PdiS_ # -- Begin function _Z23__device_stub__kernel2DPiS_PdiS_
	.type	_Z23__device_stub__kernel2DPiS_PdiS_,@function
_Z23__device_stub__kernel2DPiS_PdiS_:   # @_Z23__device_stub__kernel2DPiS_PdiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernel2DPiS_PdiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__kernel2DPiS_PdiS_, .Lfunc_end1-_Z23__device_stub__kernel2DPiS_PdiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11swapElementPPiS0_           # -- Begin function _Z11swapElementPPiS0_
	.type	_Z11swapElementPPiS0_,@function
_Z11swapElementPPiS0_:                  # @_Z11swapElementPPiS0_
	.cfi_startproc
# %bb.0:
	movq	(%rdi), %rax
	movq	(%rsi), %rcx
	movq	%rcx, (%rdi)
	movq	%rax, (%rsi)
	retq
.Lfunc_end2:
	.size	_Z11swapElementPPiS0_, .Lfunc_end2-_Z11swapElementPPiS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel2DPiS_PdiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Problem at memory allocation"
	.size	.L.str.1, 29

	.type	_Z8kernel2DPiS_PdiS_,@object    # @_Z8kernel2DPiS_PdiS_
	.section	.rodata,"a",@progbits
	.globl	_Z8kernel2DPiS_PdiS_
	.p2align	3, 0x0
_Z8kernel2DPiS_PdiS_:
	.quad	_Z23__device_stub__kernel2DPiS_PdiS_
	.size	_Z8kernel2DPiS_PdiS_, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"terminated: spin values stay same (step %d)\n"
	.size	.L.str.2, 45

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8kernel2DPiS_PdiS_"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Problem at memory allocation at host "
	.size	.Lstr, 38

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__kernel2DPiS_PdiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8kernel2DPiS_PdiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8kernel2DPiS_PdiS_    ; -- Begin function _Z8kernel2DPiS_PdiS_
	.globl	_Z8kernel2DPiS_PdiS_
	.p2align	8
	.type	_Z8kernel2DPiS_PdiS_,@function
_Z8kernel2DPiS_PdiS_:                   ; @_Z8kernel2DPiS_PdiS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s6, s[0:1], 0x34
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x28
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_mov_b32 s12, -1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s6, 16
	s_and_b32 s11, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s6, s11, s10
	s_cmp_lt_u32 s6, 6
	s_cbranch_scc0 .LBB0_7
; %bb.1:
	v_or_b32_e32 v0, v3, v4
	s_mov_b32 s12, 0
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_6
; %bb.2:                                ; %.preheader169.preheader
	s_mov_b32 s16, 0
	s_movk_i32 s17, 0x640
	s_mov_b64 s[6:7], s[4:5]
.LBB0_3:                                ; %.preheader169
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_movk_i32 s18, 0xffd8
	s_mov_b64 s[8:9], s[6:7]
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b64 s[20:21], s[8:9], 0x0
	s_add_i32 s19, s17, s18
	s_add_i32 s18, s18, 8
	v_mov_b32_e32 v2, s19
	s_add_u32 s8, s8, 8
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s18, 0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
	ds_store_b64 v2, v[0:1] offset:40
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s16, s16, 1
	s_add_u32 s6, s6, 40
	s_addc_u32 s7, s7, 0
	s_add_i32 s17, s17, 40
	s_cmp_eq_u32 s16, 5
	s_cbranch_scc0 .LBB0_3
.LBB0_6:                                ; %Flow234
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_7:                                ; %Flow236
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_11
; %bb.8:
	v_max_u32_e32 v0, v3, v4
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 5, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_mul_u32_u24_e32 v0, 5, v3
	v_lshlrev_b32_e32 v5, 3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 3, v0
	v_add_co_u32 v0, s4, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v1, null, s5, 0, s4
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[0:1] offset:1600
.LBB0_10:                               ; %Flow235
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_11:                               ; %.loopexit
	s_load_b32 s12, s[0:1], 0x18
	v_mad_u64_u32 v[0:1], null, s14, s11, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s4, exec_lo
	s_add_i32 s13, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s13, v0
	s_cbranch_execz .LBB0_39
; %bb.12:                               ; %.preheader168.lr.ph
	s_ashr_i32 s4, s12, 31
	v_mul_u32_u24_e32 v6, 20, v3
	s_add_i32 s5, s12, s4
	v_dual_mov_b32 v7, -1 :: v_dual_mov_b32 v12, 1
	s_xor_b32 s14, s5, s4
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x20
	v_cvt_f32_u32_e32 v1, s14
	s_sub_i32 s0, 0, s14
	v_cmp_gt_u32_e64 s1, 2, v3
	s_mul_i32 s16, s3, s10
	s_add_i32 s17, s12, -2
	v_rcp_iflag_f32_e32 v1, v1
	s_add_i32 s18, s12, 16
	s_mov_b32 s19, 0
	v_lshlrev_b32_e32 v8, 2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v6, v6, 2, v8
	v_mad_u32_u24 v8, 0x50, v3, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_add_nc_u32_e32 v9, 0xa0, v6
	v_add_nc_u32_e32 v10, 0x5a0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v11, v1
	v_mad_u64_u32 v[1:2], null, s15, s10, v[4:5]
	s_mul_i32 s15, s2, s11
	v_mov_b32_e32 v5, 0
	v_mul_lo_u32 v2, s0, v11
	v_cmp_gt_u32_e64 s0, 2, v4
	s_mov_b32 s10, 0xa0b5ed8d
	s_mov_b32 s11, 0x3eb0c6f7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s13, v1
	v_mul_hi_u32 v2, v11, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v11, v2
.LBB0_13:                               ; %.preheader168
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_22 Depth 3
                                        ;         Child Loop BB0_23 Depth 4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB0_38
; %bb.14:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_add_nc_u32_e32 v4, s18, v0
	v_cmp_gt_i32_e64 s3, s12, v0
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v4
	v_add_nc_u32_e32 v4, v4, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v15
	v_mul_hi_u32 v18, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v18, s14
	v_sub_nc_u32_e32 v4, v4, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v18, s14, v4
	v_add_nc_u32_e32 v3, s17, v0
	v_ashrrev_i32_e32 v14, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v14
	v_xor_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v3, v11
	v_mul_lo_u32 v17, v17, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v17
	v_subrev_nc_u32_e32 v17, s14, v3
	v_add_nc_u32_e32 v2, s12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v2
	v_add_nc_u32_e32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v13
	v_mul_hi_u32 v16, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v16, s14
	v_sub_nc_u32_e32 v2, v2, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s14, v2
	v_cmp_le_u32_e32 vcc_lo, s14, v2
	v_cndmask_b32_e32 v2, v2, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s14, v2
	v_cndmask_b32_e32 v3, v3, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	v_subrev_nc_u32_e32 v17, s14, v3
	v_cndmask_b32_e32 v4, v4, v18, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s14, v4
	v_cndmask_b32_e32 v2, v2, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	v_xor_b32_e32 v16, v2, v13
	v_cndmask_b32_e32 v3, v3, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	v_mul_lo_u32 v2, v0, s12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v13, v16, v13
	v_xor_b32_e32 v3, v3, v14
	v_cndmask_b32_e32 v4, v4, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v13, v13, s12
	v_sub_nc_u32_e32 v14, v3, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v15
	v_ashrrev_i32_e32 v3, 31, v2
	v_sub_nc_u32_e32 v4, v4, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v15, v14, s12
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v17, v4, s12
	v_lshlrev_b64 v[19:20], 2, v[13:14]
	v_ashrrev_i32_e32 v16, 31, v15
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v3, vcc_lo
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[2:3], 2, v[15:16]
	v_add_co_u32 v15, vcc_lo, s6, v19
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[21:22], 2, v[17:18]
	v_add_co_u32 v17, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v3, vcc_lo
	v_mov_b32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s6, v21
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v22, vcc_lo
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_22 Depth 3
                                        ;         Child Loop BB0_23 Depth 4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s12, v2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v21, v3, v11
	v_mul_lo_u32 v21, v21, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v21
	v_subrev_nc_u32_e32 v21, s14, v3
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v21, vcc_lo
	v_subrev_nc_u32_e32 v21, s14, v3
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v21, vcc_lo
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v21, vcc_lo, v15, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v22, vcc_lo, v16, v4, vcc_lo
	global_load_b32 v21, v[21:22], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v21 offset:8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	v_add_nc_u32_e32 v21, s17, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v23, 31, v21
	v_add_nc_u32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v21, v21, v23
	v_mul_hi_u32 v25, v21, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v25, s14
	v_sub_nc_u32_e32 v21, v21, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v25, s14, v21
	v_cmp_le_u32_e32 vcc_lo, s14, v21
	v_dual_cndmask_b32 v21, v21, v25 :: v_dual_add_nc_u32 v22, s18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v24, 31, v22
	v_subrev_nc_u32_e32 v25, s14, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v22, v22, v24
	v_xor_b32_e32 v22, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v26, v22, v11
	v_mul_lo_u32 v26, v26, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v22, v22, v26
	v_subrev_nc_u32_e32 v26, s14, v22
	v_cmp_le_u32_e32 vcc_lo, s14, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v22, v26, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v21
	v_subrev_nc_u32_e32 v26, s14, v22
	v_cndmask_b32_e32 v21, v21, v25, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v21, v21, v23
	v_cndmask_b32_e32 v22, v22, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v23
	v_xor_b32_e32 v22, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v22, v24
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v21, vcc_lo, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v22, vcc_lo, v16, v22, vcc_lo
	v_add_co_u32 v23, vcc_lo, v15, v23
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v24, vcc_lo, v16, v24, vcc_lo
	s_clause 0x1
	global_load_b32 v21, v[21:22], off
	global_load_b32 v22, v[23:24], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v21 offset:160
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v22 offset:72
.LBB0_17:                               ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_and_saveexec_b32 s22, s1
	s_cbranch_execz .LBB0_20
; %bb.18:                               ;   in Loop: Header=BB0_15 Depth=2
	v_add_co_u32 v21, vcc_lo, v17, v3
	v_add_co_ci_u32_e32 v22, vcc_lo, v18, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, v19, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v20, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v21, v[21:22], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v21 offset:8
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v3 offset:8
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_15 Depth=2
	v_add_nc_u32_e32 v4, s17, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v4
	v_add_nc_u32_e32 v4, v4, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v22
	v_mul_hi_u32 v25, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v25, s14
	v_sub_nc_u32_e32 v4, v4, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v25, s14, v4
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	v_dual_cndmask_b32 v4, v4, v25 :: v_dual_add_nc_u32 v3, 16, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v23, 31, v3
	v_subrev_nc_u32_e32 v25, s14, v4
	v_add_nc_u32_e32 v21, s12, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v23
	v_ashrrev_i32_e32 v24, 31, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v23
	v_add_nc_u32_e32 v21, v21, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v26, v3, v11
	v_xor_b32_e32 v21, v21, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v26, v26, s14
	v_mul_hi_u32 v27, v21, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v26
	v_mul_lo_u32 v27, v27, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v26, s14, v3
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	v_sub_nc_u32_e32 v21, v21, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v26, vcc_lo
	v_subrev_nc_u32_e32 v27, s14, v21
	v_cmp_le_u32_e32 vcc_lo, s14, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v26, s14, v3
	v_cndmask_b32_e32 v21, v21, v27, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v27, s14, v21
	v_cndmask_b32_e32 v4, v4, v25, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	v_xor_b32_e32 v4, v4, v22
	v_cndmask_b32_e32 v3, v3, v26, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v25, v3, v23
	v_cndmask_b32_e32 v21, v21, v27, vcc_lo
	v_sub_nc_u32_e32 v3, v4, v22
	v_xor_b32_e32 v26, v21, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v21, v25, v23
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v26, v24
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_add_co_u32 v25, vcc_lo, v17, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_ci_u32_e32 v26, vcc_lo, v18, v4, vcc_lo
	v_add_co_u32 v21, vcc_lo, v17, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, v18, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v23, vcc_lo, v19, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, v20, v24, vcc_lo
	v_add_co_u32 v3, vcc_lo, v19, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v20, v4, vcc_lo
	s_clause 0x3
	global_load_b32 v21, v[21:22], off
	global_load_b32 v22, v[25:26], off
	global_load_b32 v23, v[23:24], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v6, v22, v21 offset1:18
	s_waitcnt vmcnt(1)
	ds_store_b32 v10, v23 offset:72
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v3 offset:1440
.LBB0_20:                               ; %.critedge
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_cmp_gt_i32_e32 vcc_lo, s12, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s23, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s23
	s_cbranch_execz .LBB0_37
; %bb.21:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_15 Depth=2
	v_mov_b32_e32 v3, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v21, v8
	s_mov_b32 s23, 0
	s_movk_i32 s24, 0x640
.LBB0_22:                               ; %.preheader
                                        ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_23 Depth 4
	s_cmp_eq_u32 s23, 2
	s_mov_b32 s25, s24
	s_cselect_b32 s26, -1, 0
	s_mov_b32 s27, 0
.LBB0_23:                               ;   Parent Loop BB0_13 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ;       Parent Loop BB0_22 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s27, 8
	s_cselect_b32 s28, -1, 0
	s_and_b32 s28, s26, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccnz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=4
	v_add_nc_u32_e32 v22, s27, v21
	v_mov_b32_e32 v24, s25
	ds_load_b32 v22, v22
	ds_load_b64 v[24:25], v24
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[22:23], v22
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[3:4], v[24:25], v[22:23], v[3:4]
.LBB0_25:                               ;   in Loop: Header=BB0_23 Depth=4
	s_add_i32 s27, s27, 4
	s_add_i32 s25, s25, 8
	s_cmp_eq_u32 s27, 20
	s_cbranch_scc0 .LBB0_23
; %bb.26:                               ;   in Loop: Header=BB0_22 Depth=3
	v_add_nc_u32_e32 v21, 0x50, v21
	s_add_i32 s23, s23, 1
	s_add_i32 s24, s24, 40
	s_cmp_eq_u32 s23, 5
	s_cbranch_scc0 .LBB0_22
; %bb.27:                               ;   in Loop: Header=BB0_15 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e64 s23, |v[3:4]|, s[10:11]
	s_and_saveexec_b32 s24, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s24
	s_cbranch_execz .LBB0_35
; %bb.28:                               ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s24, exec_lo
	v_cmpx_nlt_f64_e32 s[10:11], v[3:4]
	s_xor_b32 s24, exec_lo, s24
	s_cbranch_execz .LBB0_32
; %bb.29:                               ;   in Loop: Header=BB0_15 Depth=2
	s_mov_b32 s25, exec_lo
	v_cmpx_gt_f64_e32 0, v[3:4]
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_15 Depth=2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, v13, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v4, vcc_lo
	global_store_b32 v[3:4], v7, off
	global_store_b32 v5, v5, s[8:9]
.LBB0_31:                               ; %Flow
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
.LBB0_32:                               ; %Flow223
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_and_not1_saveexec_b32 s24, s24
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_15 Depth=2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, v13, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v4, vcc_lo
	global_store_b32 v[3:4], v12, off
	global_store_b32 v5, v5, s[8:9]
.LBB0_34:                               ; %Flow224
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_35:                               ; %Flow225
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB0_37
; %bb.36:                               ;   in Loop: Header=BB0_15 Depth=2
	ds_load_b32 v21, v9 offset:8
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, v13, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[3:4], v21, off
.LBB0_37:                               ; %Flow227
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v2, s16, v2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmp_le_i32_e32 vcc_lo, s13, v2
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_15
.LBB0_38:                               ; %Flow230
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_add_nc_u32_e32 v0, s15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v0
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_13
.LBB0_39:                               ; %._crit_edge180
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel2DPiS_PdiS_
		.amdhsa_group_segment_fixed_size 1800
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8kernel2DPiS_PdiS_, .Lfunc_end0-_Z8kernel2DPiS_PdiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2536
; NumSgprs: 31
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1800 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1800
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel2DPiS_PdiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     31
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel2DPiS_PdiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
