/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NVIDIA Corporation and its licensors retain all intellectual property and 
 * proprietary rights in and to this software and related documentation and 
 * any modifications thereto.  Any use, reproduction, disclosure, or distribution 
 * of this software and related documentation without an express license 
 * agreement from NVIDIA Corporation is strictly prohibited.
 * 
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#define PI 3.1415926536f

/* 
 * Paint a 2D texture with a moving red/green hatch pattern on a
 * strobing blue background.  Note that this kernel reads to and
 * writes from the texture, hence why this texture was not mapped
 * as WriteDiscard.
 */
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
	int x = blockIdx.x*blockDim.x + threadIdx.x;
    int y = blockIdx.y*blockDim.y + threadIdx.y;
    unsigned char* pixel;
       
    // in the case where, due to quantization into grids, we have
    // more threads than pixels, skip the threads which don't 
    // correspond to valid pixels
	if (x >= width || y >= height) return;
	
    // get a pointer to the pixel at (x,y)
    pixel = (unsigned char*)(surface + y*pitch) + 4*x;

	// populate it
	float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width  - 1.0f ) );
	float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );

	// Color : DirectX BGRA, OpenGL RGBA
	pixel[0] = 255*(0.5f + 0.5f*cos(t));                          // blue
	pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
	pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
	pixel[3] = 255;                                               // alpha	
}

extern "C" void cudaTextureUpdate(void* deviceTexture, int width, int height, float t)
{
    dim3 Db = dim3(16, 16); // block dimensions are fixed to be 256 threads
    dim3 Dg = dim3((width+Db.x-1)/Db.x, (height+Db.y-1)/Db.y);
	
	size_t pitch = width*4;
    cudaKernelTexture2D<<<Dg,Db>>>((unsigned char*)deviceTexture, width, height, pitch, t);
}
	.file	"tmpxft_0029f465_00000000-6_AnimatedTexture.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
	.type	_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, @function
_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19cudaKernelTexture2DPhiimf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, .-_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
	.globl	_Z19cudaKernelTexture2DPhiimf
	.type	_Z19cudaKernelTexture2DPhiimf, @function
_Z19cudaKernelTexture2DPhiimf:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
	.cfi_endproc
.LFE2053:
	.size	_Z19cudaKernelTexture2DPhiimf, .-_Z19cudaKernelTexture2DPhiimf
	.globl	cudaTextureUpdate
	.type	cudaTextureUpdate, @function
cudaTextureUpdate:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leal	15(%rsi), %eax
	movq	%rdi, %r12
	xorl	%r9d, %r9d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	shrl	$4, %eax
	xorl	%r8d, %r8d
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	$1, %ecx
	movl	%esi, %ebx
	movl	$1, %esi
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movl	%eax, 36(%rsp)
	leal	15(%rdx), %eax
	movabsq	$68719476752, %rdx
	shrl	$4, %eax
	movss	%xmm0, 12(%rsp)
	movl	%eax, 40(%rsp)
	movq	36(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L8
	addq	$48, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	leal	0(,%rbx,4), %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	movq	%r12, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	movslq	%ecx, %rcx
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
.L8:
	.cfi_restore_state
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	cudaTextureUpdate, .-cudaTextureUpdate
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19cudaKernelTexture2DPhiimf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19cudaKernelTexture2DPhiimf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NVIDIA Corporation and its licensors retain all intellectual property and 
 * proprietary rights in and to this software and related documentation and 
 * any modifications thereto.  Any use, reproduction, disclosure, or distribution 
 * of this software and related documentation without an express license 
 * agreement from NVIDIA Corporation is strictly prohibited.
 * 
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#define PI 3.1415926536f

/* 
 * Paint a 2D texture with a moving red/green hatch pattern on a
 * strobing blue background.  Note that this kernel reads to and
 * writes from the texture, hence why this texture was not mapped
 * as WriteDiscard.
 */
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
	int x = blockIdx.x*blockDim.x + threadIdx.x;
    int y = blockIdx.y*blockDim.y + threadIdx.y;
    unsigned char* pixel;
       
    // in the case where, due to quantization into grids, we have
    // more threads than pixels, skip the threads which don't 
    // correspond to valid pixels
	if (x >= width || y >= height) return;
	
    // get a pointer to the pixel at (x,y)
    pixel = (unsigned char*)(surface + y*pitch) + 4*x;

	// populate it
	float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width  - 1.0f ) );
	float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );

	// Color : DirectX BGRA, OpenGL RGBA
	pixel[0] = 255*(0.5f + 0.5f*cos(t));                          // blue
	pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
	pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
	pixel[3] = 255;                                               // alpha	
}

extern "C" void cudaTextureUpdate(void* deviceTexture, int width, int height, float t)
{
    dim3 Db = dim3(16, 16); // block dimensions are fixed to be 256 threads
    dim3 Dg = dim3((width+Db.x-1)/Db.x, (height+Db.y-1)/Db.y);
	
	size_t pitch = width*4;
    cudaKernelTexture2D<<<Dg,Db>>>((unsigned char*)deviceTexture, width, height, pitch, t);
}
	.text
	.file	"AnimatedTexture.hip"
	.globl	_Z34__device_stub__cudaKernelTexture2DPhiimf # -- Begin function _Z34__device_stub__cudaKernelTexture2DPhiimf
	.type	_Z34__device_stub__cudaKernelTexture2DPhiimf,@function
_Z34__device_stub__cudaKernelTexture2DPhiimf: # @_Z34__device_stub__cudaKernelTexture2DPhiimf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19cudaKernelTexture2DPhiimf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__cudaKernelTexture2DPhiimf, .Lfunc_end0-_Z34__device_stub__cudaKernelTexture2DPhiimf
	.cfi_endproc
                                        # -- End function
	.globl	cudaTextureUpdate               # -- Begin function cudaTextureUpdate
	.type	cudaTextureUpdate,@function
cudaTextureUpdate:                      # @cudaTextureUpdate
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movl	%edx, %ebx
	movl	%esi, %r14d
	movq	%rdi, %r15
	leal	15(%r14), %eax
	shrl	$4, %eax
	leal	15(%rbx), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 48
	leal	(,%r14,4), %eax
	movslq	%eax, %rcx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__cudaKernelTexture2DPhiimf # TAILCALL
.Lfunc_end1:
	.size	cudaTextureUpdate, .Lfunc_end1-cudaTextureUpdate
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19cudaKernelTexture2DPhiimf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19cudaKernelTexture2DPhiimf,@object # @_Z19cudaKernelTexture2DPhiimf
	.section	.rodata,"a",@progbits
	.globl	_Z19cudaKernelTexture2DPhiimf
	.p2align	3, 0x0
_Z19cudaKernelTexture2DPhiimf:
	.quad	_Z34__device_stub__cudaKernelTexture2DPhiimf
	.size	_Z19cudaKernelTexture2DPhiimf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19cudaKernelTexture2DPhiimf"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__cudaKernelTexture2DPhiimf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19cudaKernelTexture2DPhiimf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19cudaKernelTexture2DPhiimf ; -- Begin function _Z19cudaKernelTexture2DPhiimf
	.globl	_Z19cudaKernelTexture2DPhiimf
	.p2align	8
	.type	_Z19cudaKernelTexture2DPhiimf,@function
_Z19cudaKernelTexture2DPhiimf:          ; @_Z19cudaKernelTexture2DPhiimf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	v_cvt_f32_i32_e32 v2, v0
	v_cvt_f32_i32_e32 v3, s4
	s_load_b32 s4, s[0:1], 0x18
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v2
	v_div_scale_f32 v4, null, v3, v3, v2
	v_div_scale_f32 v7, vcc_lo, v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v8, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v5
	v_fma_f32 v4, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v6
	v_div_fixup_f32 v2, v4, v3, v2
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s4
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, -1.0, v2
	v_fmamk_f32 v2, v2, 0x41200000, v3
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s6, exec_lo, s3
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v10, 0x7fffffff, v2
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v13, v10, s2, 0x800000
	v_lshrrev_b32_e32 v10, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v13, 0
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v13, v[4:5]
	v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v7
	v_add_nc_u32_e32 v12, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v13, v[4:5]
	v_cmp_lt_u32_e64 s2, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
	v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v12
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v14
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v6, v3, s2
	v_mov_b32_e32 v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v13, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0xa2f9836e, v13, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v11, v5, s2
	v_cndmask_b32_e64 v10, v10, v11, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v5, v9, s2
	v_sub_nc_u32_e32 v11, 32, v4
	v_cndmask_b32_e64 v9, v9, v6, s2
	v_cndmask_b32_e64 v10, v10, v8, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v5, s3
	v_cndmask_b32_e64 v5, v5, v9, s3
	v_cndmask_b32_e64 v3, v9, v3, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v10, v8, v11
	v_alignbit_b32 v7, v8, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v12, v10, vcc_lo
	v_alignbit_b32 v10, v5, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_bfe_u32 v7, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	v_alignbit_b32 v8, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v3, v5, v3, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v9
	v_clz_i32_u32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v6, 31, v10
	v_lshlrev_b32_e32 v12, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v8, v5, v6
	v_alignbit_b32 v3, v5, v3, v6
	v_lshrrev_b32_e32 v6, 29, v4
	v_alignbit_b32 v5, v8, v3, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v6, 31, v6
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v6
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v12
	v_sub_nc_u32_e32 v13, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v5, v3, v13
	v_or_b32_e32 v5, v8, v11
	v_add_lshl_u32 v8, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_mul_f32_e32 v9, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v8
	v_fma_f32 v8, 0x3fc90fda, v5, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fmamk_f32 v5, v5, 0x33a22168, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, v3, v6
	v_fmac_f32_e32 v5, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v5
	v_lshrrev_b32_e32 v4, 30, v4
	v_add_nc_u32_e32 v4, v7, v4
.LBB0_3:                                ; %Flow62
	s_and_not1_saveexec_b32 s2, s6
; %bb.4:
	v_mul_f32_e64 v3, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v4, 0xb3a22168, v3
	v_fmamk_f32 v3, v4, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v4, v4
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f32_i32_e32 v5, v1
	v_cvt_f32_i32_e32 v6, s5
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v5
	v_div_scale_f32 v7, null, v6, v6, v5
	v_div_scale_f32 v10, vcc_lo, v5, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
	v_div_fixup_f32 v5, v7, v6, v5
	v_mov_b32_e32 v6, s4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, -1.0, v5
	v_fmamk_f32 v5, v5, 0x41200000, v6
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v5|
	s_xor_b32 s5, exec_lo, s3
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v13, 0x7fffffff, v5
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v16, v13, s2, 0x800000
	v_lshrrev_b32_e32 v13, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v16, 0
	v_add_nc_u32_e32 v14, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v14
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v16, v[7:8]
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v10
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v16, v[7:8]
	v_cmp_lt_u32_e64 s2, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s2
	v_dual_mov_b32 v7, v11 :: v_dual_cndmask_b32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v17, v17, v15
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v17
	v_mov_b32_e32 v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v9, v6, s2
	v_mov_b32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v16, v[7:8]
	v_mov_b32_e32 v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v16, v[7:8]
	v_cndmask_b32_e64 v7, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v8, v13, v11 :: v_dual_add_nc_u32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
	v_cndmask_b32_e32 v12, v12, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v14, v8, s2
	v_cndmask_b32_e64 v13, v13, v14, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v12, s2
	v_sub_nc_u32_e32 v14, 32, v7
	v_cndmask_b32_e64 v12, v12, v9, s2
	v_cndmask_b32_e64 v13, v13, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v8, s3
	v_cndmask_b32_e64 v8, v8, v12, s3
	v_cndmask_b32_e64 v6, v12, v6, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v13, v11, v14
	v_alignbit_b32 v10, v11, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, v15, v13, vcc_lo
	v_alignbit_b32 v13, v8, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	v_bfe_u32 v10, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v13, v8, vcc_lo
	v_alignbit_b32 v11, v7, v9, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, 0, v10
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v6, v8, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v11, v12
	v_xor_b32_e32 v8, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v12
	v_clz_i32_u32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v13, 32, v13
	v_sub_nc_u32_e32 v9, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v11, v8, v9
	v_alignbit_b32 v6, v8, v6, v9
	v_lshrrev_b32_e32 v9, 29, v7
	v_alignbit_b32 v8, v11, v6, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 31, v9
	v_lshrrev_b32_e32 v11, 9, v11
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v8, v6, v16
	v_or_b32_e32 v8, v11, v14
	v_add_lshl_u32 v11, v12, v13, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v11
	v_fma_f32 v11, 0x3fc90fda, v8, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v8, v8, 0x33a22168, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v9
	v_fmac_f32_e32 v8, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v12, v8
	v_lshrrev_b32_e32 v7, 30, v7
	v_add_nc_u32_e32 v7, v10, v7
.LBB0_7:                                ; %Flow61
	s_and_not1_saveexec_b32 s2, s5
; %bb.8:
	v_mul_f32_e64 v6, 0x3f22f983, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v6
	v_fma_f32 v6, 0xbfc90fda, v7, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.9:                                ; %_ZL3cosf.exit33
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_ngt_f32_e64 s2, 0x48000000, |s4|
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_11
; %bb.10:
	s_and_b32 s2, s4, 0x7fffffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s2, 0x7fffff
	s_lshr_b32 s2, s2, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s2, 0xff88
	s_mul_hi_u32 s5, s3, 0xfe5163ab
	s_mul_i32 s6, s3, 0x3c439041
	s_mul_hi_u32 s7, s3, 0x3c439041
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s3, 0xdb629599
	s_mul_hi_u32 s8, s3, 0xdb629599
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s3, 0xf534ddc0
	s_mul_hi_u32 s9, s3, 0xf534ddc0
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s3, 0xfc2757d1
	s_mul_hi_u32 s10, s3, 0xfc2757d1
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s3, 0x4e441529
	s_mul_hi_u32 s11, s3, 0x4e441529
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_cmp_gt_u32 s2, 63
	s_mul_i32 s11, s3, 0xfe5163ab
	s_mul_hi_u32 s12, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s13, s6, s8
	s_cselect_b32 s5, s5, s7
	s_cselect_b32 s6, s11, s6
	s_add_u32 s3, s10, s3
	s_addc_u32 s10, 0, s12
	s_cmp_gt_u32 s2, 63
	s_cselect_b32 s11, 0xffffffc0, 0
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s3, s8, s3
	s_cselect_b32 s8, s9, s10
	s_add_i32 s11, s11, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s2, 0xffffffe0, 0
	s_cselect_b32 s9, s7, s3
	s_cselect_b32 s3, s3, s8
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s8, s5, s13
	s_cselect_b32 s5, s6, s5
	s_add_i32 s2, s2, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s2, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s3, s9, s3
	s_cselect_b32 s9, s7, s9
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s5, s5, s8
	s_add_i32 s6, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s2, 32, s6
	s_cmp_eq_u32 s6, 0
	v_mov_b32_e32 v8, s2
	s_cselect_b32 s6, -1, 0
	v_alignbit_b32 v9, s3, s9, v8
	v_alignbit_b32 v10, s9, s7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v9
	v_cndmask_b32_e64 v9, v10, s9, s6
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v10, s2, v9, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v10, s8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v10
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v8, s7, s5, v8
	v_sub_nc_u32_e32 v12, 31, v11
	v_cndmask_b32_e64 v8, v8, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v8, v8, s5, 30
	s_lshr_b32 s5, s2, 29
	s_lshl_b32 s5, s5, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, s8, v9
	v_xor_b32_e32 v8, s8, v8
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, s6, v13
	v_alignbit_b32 v10, v10, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v8, v9, v8, v12
	v_alignbit_b32 v9, v10, v8, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v12
	v_alignbit_b32 v8, v9, v8, v14
	v_lshrrev_b32_e32 v9, 9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v8, 9, v8
	v_or_b32_e32 v9, v9, v13
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 23, v11
	v_sub_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v9
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3fc90fda, v9, -v10
	v_or_b32_e32 v8, s5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v9, 0x33a22168, v11
	s_lshr_b32 s5, s2, 30
	s_mov_b32 s2, 0
	s_add_i32 s3, s3, s5
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v9
	s_branch .LBB0_12
.LBB0_11:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr8
.LBB0_12:                               ; %Flow
	v_mov_b32_e32 v9, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_14
; %bb.13:
	v_mul_f32_e64 v8, 0x3f22f983, |s4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v9, v8
	v_fma_f32 v8, 0xbfc90fda, v9, |s4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v9, 0xb3a22168, v8
	v_fmamk_f32 v8, v9, 0xa7c234c4, v8
	v_cvt_i32_f32_e32 v9, v9
.LBB0_14:                               ; %_ZL3cosf.exit39
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v12, 31, v1
	v_lshlrev_b32_e32 v0, 2, v0
	v_dual_mul_f32 v14, v3, v3 :: v_dual_and_b32 v15, 1, v4
	v_and_b32_e32 v18, 1, v9
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[10:11], null, v1, s0, s[2:3]
	v_mul_lo_u32 v1, v1, s1
	v_mul_lo_u32 v12, v12, s0
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_fmaak_f32 v21, s0, v14, 0x3c0881c4
	v_fmaak_f32 v22, s1, v14, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add3_u32 v1, v12, v11, v1
	v_mul_f32_e32 v11, v6, v6
	v_ashrrev_i32_e32 v13, 31, v0
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_mul_f32_e32 v12, v8, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v13, vcc_lo
	v_and_b32_e32 v13, 1, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmaak_f32 v16, s0, v12, 0x3c0881c4 :: v_dual_lshlrev_b32 v7, 30, v7
	global_load_u8 v10, v[0:1], off offset:1
	v_fmaak_f32 v17, s1, v12, 0xbab64f3b
	v_lshlrev_b32_e32 v9, 30, v9
	v_lshlrev_b32_e32 v4, 30, v4
	v_fmaak_f32 v16, v12, v16, 0xbe2aaa9d
	v_fmaak_f32 v19, s0, v11, 0x3c0881c4
	v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_and_b32_e32 v4, 0x80000000, v4
	v_dual_mul_f32 v16, v12, v16 :: v_dual_and_b32 v7, 0x80000000, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v8, v16
	v_dual_fmaak_f32 v16, v11, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v19, v14, v21, 0xbe2aaa9d
	v_dual_fmaak_f32 v17, v12, v17, 0xbf000004 :: v_dual_mul_f32 v16, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, v14, v19
	v_fmaak_f32 v20, s1, v11, 0xbab64f3b
	v_fma_f32 v12, v12, v17, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v6, v6, v16 :: v_dual_and_b32 v9, 0x80000000, v9
	v_fmac_f32_e32 v3, v3, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v17, v11, v20, 0x3d2aabf7
	v_cndmask_b32_e64 v8, -v8, v12, vcc_lo
	v_fmaak_f32 v12, v14, v22, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_mov_b32 s1, 0x3e76c4e1
	v_fmaak_f32 v17, v11, v17, 0xbf000004
	v_xor_b32_e32 v8, v9, v8
	v_fmaak_f32 v9, v14, v12, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v11, v11, v17, 1.0
	v_fma_f32 v8, v8, 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v14, v9, 1.0
	v_cndmask_b32_e64 v6, -v6, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, 0x437f0000, v8
	v_xor_b32_e32 v6, v7, v6
	v_cndmask_b32_e64 v3, -v3, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, s4, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v9, v6, 0.5, 0.5
	v_cndmask_b32_e32 v7, 0x7fc00000, v8, vcc_lo
	v_xor_b32_e32 v8, v4, v3
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v6, v7
	v_fma_f32 v8, v8, 0.5, 0.5
	v_cndmask_b32_e32 v7, 0x7fc00000, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
	v_frexp_mant_f32_e64 v5, |v8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v12, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v12, v5, v12
	v_add_f32_e32 v18, -1.0, v12
	v_frexp_mant_f32_e64 v2, |v7|
	v_add_f32_e32 v14, 1.0, v12
	v_cmp_class_f32_e64 s6, v7, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_rcp_f32_e32 v16, v14
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v11, v2, v11
	v_add_f32_e32 v13, 1.0, v11
	v_add_f32_e32 v17, -1.0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v13
	v_add_f32_e32 v20, -1.0, v13
	v_sub_f32_e32 v11, v11, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v19, v17, v15
	s_waitcnt vmcnt(0)
	v_cvt_f64_u32_e32 v[3:4], v10
	v_cvt_f64_u32_e32 v[9:10], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[3:4], 0.5
	v_mul_f64 v[4:5], v[9:10], 0.5
	v_dual_mul_f32 v9, v13, v19 :: v_dual_add_f32 v10, -1.0, v14
	v_mul_f32_e32 v21, v18, v16
	v_frexp_exp_i32_f32_e32 v35, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v13, v19, v13, -v9
	v_sub_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v14, v21
	v_fma_f32 v12, v21, v14, -v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v13, v19, v11 :: v_dual_fmac_f32 v12, v21, v10
	v_dual_add_f32 v10, v9, v13 :: v_dual_add_f32 v11, v22, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v17, v10 :: v_dual_sub_f32 v9, v10, v9
	v_dual_sub_f32 v20, v18, v11 :: v_dual_sub_f32 v17, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v11, v22 :: v_dual_sub_f32 v13, v9, v13
	v_sub_f32_e32 v22, v22, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v17, v10
	v_div_scale_f64 v[9:10], null, 0x406fe000, 0x406fe000, v[2:3]
	v_add_f32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v14, v13
	v_dual_sub_f32 v18, v18, v20 :: v_dual_mul_f32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v18, v11
	v_div_scale_f64 v[11:12], null, 0x406fe000, 0x406fe000, v[4:5]
	v_add_f32_e32 v17, v22, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v22, v19, v13
	v_add_f32_e32 v14, v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v16, v14
	v_add_f32_e32 v23, v21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v22, v19 :: v_dual_sub_f32 v16, v23, v21
	v_sub_f32_e32 v21, v13, v15
	v_mul_f32_e32 v18, v23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v24, v14, v16 :: v_dual_add_f32 v15, v21, v21
	v_mul_f32_e32 v17, v22, v22
	v_fma_f32 v20, v23, v23, -v18
	v_rcp_f64_e32 v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v24, v24
	v_fma_f32 v19, v22, v22, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v23, v16 :: v_dual_fmac_f32 v19, v22, v15
	v_rcp_f64_e32 v[15:16], v[11:12]
	v_dual_add_f32 v26, v18, v20 :: v_dual_add_f32 v25, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v28, s1, v26, 0x3e91f4c4
	v_dual_sub_f32 v18, v26, v18 :: v_dual_fmaak_f32 v27, s1, v25, 0x3e91f4c4
	v_sub_f32_e32 v17, v25, v17
	v_cmp_eq_f32_e64 s1, 1.0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v28, v26, v28, 0x3ecccdef
	v_dual_sub_f32 v32, v20, v18 :: v_dual_fmaak_f32 v27, v25, v27, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v31, v19, v17
	v_frexp_exp_i32_f32_e32 v17, v7
	v_dual_mul_f32 v30, v26, v28 :: v_dual_mul_f32 v29, v25, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, v26, v28, -v30
	v_fma_f32 v33, v25, v27, -v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_dual_mul_f32 v36, v22, v25 :: v_dual_fmac_f32 v33, v31, v27
	v_subrev_co_ci_u32_e32 v27, vcc_lo, 0, v17, vcc_lo
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v34, v32, v28 :: v_dual_add_f32 v37, v29, v33
	v_mul_f32_e32 v28, v23, v26
	v_fma_f32 v38, v25, v22, -v36
	v_cvt_f32_i32_e32 v27, v27
	v_add_f32_e32 v39, v30, v34
	v_sub_f32_e32 v29, v37, v29
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	v_fmac_f32_e32 v38, v25, v21
	v_fma_f32 v40, v26, v23, -v28
	v_dual_add_f32 v41, 0x3f2aaaaa, v37 :: v_dual_add_f32 v42, 0x3f2aaaaa, v39
	v_dual_sub_f32 v30, v39, v30 :: v_dual_sub_f32 v29, v33, v29
	v_dual_fmac_f32 v40, v26, v24 :: v_dual_add_f32 v33, 0xbf2aaaaa, v41
	v_fmac_f32_e32 v38, v31, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v25, v34, v30
	v_add_f32_e32 v30, 0xbf2aaaaa, v42
	v_dual_fmac_f32 v40, v32, v23 :: v_dual_add_f32 v29, 0x31739010, v29
	v_sub_f32_e32 v33, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v25, 0x31739010, v25 :: v_dual_sub_f32 v26, v39, v30
	v_subrev_co_ci_u32_e64 v30, vcc_lo, 0, v35, s0
	v_add_f32_e32 v29, v29, v33
	v_add_f32_e32 v33, v28, v40
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v25, v25, v26
	v_add_f32_e32 v26, v36, v38
	v_ldexp_f32 v23, v23, 1
	v_ldexp_f32 v21, v21, 1
	v_sub_f32_e32 v28, v33, v28
	v_ldexp_f32 v24, v24, 1
	v_dual_sub_f32 v34, v26, v36 :: v_dual_add_f32 v31, v41, v29
	v_add_f32_e32 v32, v42, v25
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	v_cvt_f32_i32_e32 v17, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v38, v34
	v_dual_mul_f32 v36, v26, v31 :: v_dual_mul_f32 v39, v33, v32
	v_sub_f32_e32 v37, v42, v32
	v_dual_sub_f32 v35, v41, v31 :: v_dual_sub_f32 v28, v40, v28
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	v_mul_f32_e32 v20, 0x3f317218, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v25, v25, v37
	v_fma_f32 v37, v33, v32, -v39
	v_fmac_f32_e32 v37, v33, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v37, v28, v32
	v_add_f32_e32 v29, v29, v35
	v_fma_f32 v35, v26, v31, -v36
	v_fma_f32 v28, 0x3f317218, v17, -v20
	v_fmac_f32_e32 v35, v26, v29
	v_add_f32_e32 v26, v39, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, 0xb102e308, v17
	v_sub_f32_e32 v32, v26, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v35, v18, v31
	v_ldexp_f32 v18, v22, 1
	v_dual_add_f32 v31, v23, v26 :: v_dual_sub_f32 v32, v37, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v36, v35
	v_add_f32_e32 v29, v18, v22
	v_dual_mul_f32 v19, 0x3f317218, v27 :: v_dual_sub_f32 v30, v22, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v29, v18
	v_fma_f32 v25, 0x3f317218, v27, -v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v30, v35, v30
	v_dual_sub_f32 v23, v31, v23 :: v_dual_sub_f32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, 0xb102e308, v27
	v_dual_add_f32 v21, v21, v30 :: v_dual_sub_f32 v22, v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v23, v24, v32 :: v_dual_add_f32 v24, v19, v25
	v_add_f32_e32 v21, v21, v18
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v30, v24, v19
	v_add_f32_e32 v26, v29, v21
	v_dual_add_f32 v22, v23, v22 :: v_dual_add_f32 v23, v20, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v25, v30
	v_dual_add_f32 v33, v24, v26 :: v_dual_sub_f32 v32, v23, v20
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v27, v31, v22 :: v_dual_sub_f32 v28, v28, v32
	v_dual_sub_f32 v29, v26, v29 :: v_dual_sub_f32 v30, v27, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v34, v23, v27 :: v_dual_sub_f32 v31, v33, v24
	v_sub_f32_e32 v30, v22, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v35, v34, v23
	v_sub_f32_e32 v29, v21, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v21, v33, v31 :: v_dual_add_f32 v32, v28, v30
	v_sub_f32_e32 v22, v34, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v26, v26, v31 :: v_dual_add_f32 v31, v25, v29
	v_sub_f32_e32 v22, v23, v22
	v_sub_f32_e32 v27, v27, v35
	v_sub_f32_e32 v21, v24, v21
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v23, v26, v21 :: v_dual_sub_f32 v26, v32, v28
	v_add_f32_e32 v24, v27, v22
	v_sub_f32_e32 v35, v31, v25
	v_div_scale_f64 v[21:22], s0, v[4:5], 0x406fe000, v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v36, v32, v24 :: v_dual_sub_f32 v27, v31, v35
	v_dual_sub_f32 v18, v29, v35 :: v_dual_sub_f32 v29, v32, v26
	v_add_f32_e32 v31, v31, v23
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	v_sub_f32_e32 v19, v30, v26
	v_div_scale_f64 v[23:24], vcc_lo, v[2:3], 0x406fe000, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v28, v29 :: v_dual_add_f32 v17, v33, v31
	v_dual_add_f32 v19, v19, v20 :: v_dual_sub_f32 v32, v17, v33
	v_sub_f32_e32 v25, v25, v27
	v_add_f32_e32 v27, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v27, v34
	v_sub_f32_e32 v20, v36, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v18, v18, v25 :: v_dual_sub_f32 v25, v31, v32
	v_add_f32_e32 v18, v18, v25
	v_cndmask_b32_e64 v25, 0x40400000, 1.0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v19, v19, v20
	v_cmp_eq_f32_e64 s1, 1.0, v8
	v_add_f32_e32 v20, v17, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v38, 0.5, v25
	v_add_f32_e32 v26, v27, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, 0x40400000, 1.0, s1
	v_trunc_f32_e32 v36, v25
	v_sub_f32_e32 v17, v20, v17
	v_dual_sub_f32 v27, v26, v27 :: v_dual_mul_f32 v30, v28, v26
	v_trunc_f32_e32 v40, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v31, v18, v17
	v_mul_f64 v[17:18], v[23:24], v[13:14]
	v_sub_f32_e32 v19, v19, v27
	v_fma_f32 v26, v28, v26, -v30
	v_mul_f32_e32 v29, v25, v20
	v_cmp_eq_f32_e64 s2, v40, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v28, v19
	v_fma_f32 v32, v25, v20, -v29
	v_mul_f64 v[19:20], v[21:22], v[15:16]
	v_cmp_class_f32_e64 s1, v29, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v32, v25, v31 :: v_dual_add_f32 v31, v30, v26
	v_add_f32_e32 v27, v29, v32
	v_fma_f64 v[9:10], -v[9:10], v[17:18], v[23:24]
	v_fma_f64 v[11:12], -v[11:12], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v31, v30
	v_cndmask_b32_e64 v33, v27, v29, s1
	v_cmp_class_f32_e64 s1, v30, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v26, v22
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v33|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v31, v30, s1
	v_cmp_eq_f32_e64 s1, 0x42b17218, v33
	v_cndmask_b32_e64 v35, 0, 0x37000000, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e64 s1, 0x42b17218, v34
	v_sub_f32_e32 v39, v33, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, 0, 0x37000000, s1
	v_cmp_eq_f32_e64 s1, v36, v25
	v_trunc_f32_e32 v36, v38
	v_dual_mul_f32 v25, 0x3fb8aa3b, v39 :: v_dual_sub_f32 v42, v34, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e64 s3, v36, v38
	v_fma_f32 v43, 0x3fb8aa3b, v39, -v25
	v_rndne_f32_e32 v44, v25
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 s3, s1, s3
	v_fmac_f32_e32 v43, 0x32a5705f, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v25, v44
	v_dual_add_f32 v24, v25, v43 :: v_dual_sub_f32 v25, v27, v29
	v_cvt_i32_f32_e32 v27, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v32, v25
	v_cndmask_b32_e64 v25, 0, v25, s5
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v34|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v35, v25
	v_cndmask_b32_e64 v22, 0, v22, s5
	v_dual_mul_f32 v41, 0.5, v28 :: v_dual_mul_f32 v28, 0x3fb8aa3b, v42
	v_cmp_ngt_f32_e64 s5, 0xc2ce8ed0, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v37, v22
	v_trunc_f32_e32 v40, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v36, 0x3fb8aa3b, v42, -v28
	v_rndne_f32_e32 v38, v28
	v_cmp_neq_f32_e64 s4, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v36, 0x32a5705f, v42
	v_sub_f32_e32 v23, v28, v38
	v_cvt_i32_f32_e32 v26, v38
	v_div_fixup_f64 v[2:3], v[9:10], 0x406fe000, v[2:3]
	s_and_b32 s4, s2, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v23, v36
	v_exp_f32_e32 v23, v24
	v_cndmask_b32_e64 v24, 1.0, v7, s3
	v_exp_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v23, v23, v27
	v_ldexp_f32 v21, v21, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0, v23, s5
	v_cmp_ngt_f32_e64 s5, 0xc2ce8ed0, v42
	v_cndmask_b32_e64 v26, 1.0, v8, s4
	v_cndmask_b32_e64 v21, 0, v21, s5
	v_cmp_nlt_f32_e64 s5, 0x42b17218, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0x7f800000, v23, s5
	v_cmp_nlt_f32_e64 s5, 0x42b17218, v42
	v_fma_f32 v25, v23, v25, v23
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, 0x7f800000, v21, s5
	v_cmp_class_f32_e64 s5, v8, 0x204
	v_cndmask_b32_e32 v14, v25, v23, vcc_lo
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v13, v21, v22, v21
	v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[19:20]
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v21
	v_bfi_b32 v14, 0x7fffffff, v14, v24
	v_cndmask_b32_e64 v16, 0, v7, s3
	v_cmp_eq_f32_e64 s0, 0, v8
	v_cndmask_b32_e64 v19, 0, v8, s4
	v_cndmask_b32_e32 v13, v13, v21, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v18, 0x7fc00000, v14, s1
	v_cmp_gt_f32_e64 s1, 0, v7
	v_cndmask_b32_e64 v17, 0x7f800000, 0, s0
	v_bfi_b32 v13, 0x7fffffff, v13, v26
	v_cndmask_b32_e64 v15, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s6
	v_cndmask_b32_e64 v14, v14, v18, s1
	v_cmp_gt_f32_e64 s1, 0, v8
	v_bfi_b32 v17, 0x7fffffff, v17, v19
	v_bfi_b32 v15, 0x7fffffff, v15, v16
	v_cndmask_b32_e64 v16, 0x7fc00000, v13, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cndmask_b32_e64 v13, v13, v16, s1
	s_or_b32 vcc_lo, s0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v13, v17, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v7
	v_cndmask_b32_e32 v7, 0x7fc00000, v14, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v8, v8
	v_div_fixup_f64 v[4:5], v[11:12], 0x406fe000, v[4:5]
	v_cvt_f64_f32_e32 v[7:8], v7
	v_cndmask_b32_e32 v13, 0x7fc00000, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[9:10], v13
	v_fma_f64 v[2:3], v[7:8], 0.5, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[9:10], 0.5, v[4:5]
	v_mul_f64 v[2:3], 0x406fe000, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], 0x406fe000, v[4:5]
	v_cvt_i32_f64_e32 v2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v3, v[4:5]
	v_lshlrev_b16 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v6, v2
	v_or_b32_e32 v3, 0xffffff00, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, 0xffff, v2
	v_lshlrev_b32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19cudaKernelTexture2DPhiimf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19cudaKernelTexture2DPhiimf, .Lfunc_end0-_Z19cudaKernelTexture2DPhiimf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5688
; NumSgprs: 18
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19cudaKernelTexture2DPhiimf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19cudaKernelTexture2DPhiimf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
