

__global__ void anisotropy_kernel(float1* imInD, int M,int N, float k, float lambda, short type) {
         
	     int i = blockIdx.x * blockDim.x + threadIdx.x;
         int j = blockIdx.y * blockDim.y + threadIdx.y;
         int index = j+i*M;
         int len = N*M;

        float deltaN; 
		float deltaS;
		float deltaW;
		float deltaE;
		float cN; 
		float cS;
		float cW;
		float cE;
		int indexN; 
		int indexS;
		int indexW;
		int indexE;
		float val;
    
        
        indexN = (j)+(i-1)*(M);
        indexS = (j)+(i+1)*(M);
        indexW = (j-1)+(i)*(M);
        indexE = (j+1)+(i)*(M);        

        if (i>1)
            deltaN = imInD[indexN].x-imInD[index].x;
            
        if (indexS < len)
            deltaS = imInD[indexS].x-imInD[index].x;  
              
        if (j>1)
            deltaW = imInD[indexW].x-imInD[index].x;   
             
        if (indexE < len)
            deltaE = imInD[indexE].x-imInD[index].x;   
      
        if (type==1) {
            cN = exp(-(pow((deltaN / k),2)));
            cS = exp(-(pow((deltaS / k),2)));
            cW = exp(-(pow((deltaW / k),2)));
            cE = exp(-(pow((deltaE / k),2)));  
        } else {
            cN = 1/(1+pow((deltaN / k),2));
            cS = 1/(1+pow((deltaS / k),2));
            cW = 1/(1+pow((deltaW / k),2));
            cE = 1/(1+pow((deltaE / k),2));        
        }

		
		val = (lambda*(cN*deltaN + cS*deltaS + cW*deltaW + cE*deltaE));  
		imInD[index].x += val;

        
		
        __syncthreads();    
}





	.file	"tmpxft_002685f3_00000000-6_Anisotropicfilter_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs
	.type	_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs, @function
_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movw	%cx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z17anisotropy_kernelP6float1iiffs(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs, .-_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs
	.globl	_Z17anisotropy_kernelP6float1iiffs
	.type	_Z17anisotropy_kernelP6float1iiffs, @function
_Z17anisotropy_kernelP6float1iiffs:
.LFB2033:
	.cfi_startproc
	endbr64
	movswl	%cx, %ecx
	jmp	_Z48__device_stub__Z17anisotropy_kernelP6float1iiffsP6float1iiffs
	.cfi_endproc
.LFE2033:
	.size	_Z17anisotropy_kernelP6float1iiffs, .-_Z17anisotropy_kernelP6float1iiffs
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17anisotropy_kernelP6float1iiffs"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17anisotropy_kernelP6float1iiffs(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>


__global__ void anisotropy_kernel(float1* imInD, int M,int N, float k, float lambda, short type) {
         
	     int i = blockIdx.x * blockDim.x + threadIdx.x;
         int j = blockIdx.y * blockDim.y + threadIdx.y;
         int index = j+i*M;
         int len = N*M;

        float deltaN; 
		float deltaS;
		float deltaW;
		float deltaE;
		float cN; 
		float cS;
		float cW;
		float cE;
		int indexN; 
		int indexS;
		int indexW;
		int indexE;
		float val;
    
        
        indexN = (j)+(i-1)*(M);
        indexS = (j)+(i+1)*(M);
        indexW = (j-1)+(i)*(M);
        indexE = (j+1)+(i)*(M);        

        if (i>1)
            deltaN = imInD[indexN].x-imInD[index].x;
            
        if (indexS < len)
            deltaS = imInD[indexS].x-imInD[index].x;  
              
        if (j>1)
            deltaW = imInD[indexW].x-imInD[index].x;   
             
        if (indexE < len)
            deltaE = imInD[indexE].x-imInD[index].x;   
      
        if (type==1) {
            cN = exp(-(pow((deltaN / k),2)));
            cS = exp(-(pow((deltaS / k),2)));
            cW = exp(-(pow((deltaW / k),2)));
            cE = exp(-(pow((deltaE / k),2)));  
        } else {
            cN = 1/(1+pow((deltaN / k),2));
            cS = 1/(1+pow((deltaS / k),2));
            cW = 1/(1+pow((deltaW / k),2));
            cE = 1/(1+pow((deltaE / k),2));        
        }

		
		val = (lambda*(cN*deltaN + cS*deltaS + cW*deltaW + cE*deltaE));  
		imInD[index].x += val;

        
		
        __syncthreads();    
}





	.text
	.file	"Anisotropicfilter_kernel.hip"
	.globl	_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs # -- Begin function _Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.type	_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs,@function
_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs: # @_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	8(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	6(%rsp), %r9
	movw	%cx, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs, .Lfunc_end0-_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs,@object # @_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.section	.rodata,"a",@progbits
	.globl	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.p2align	3, 0x0
_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs:
	.quad	_Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.size	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs"
	.size	.L__unnamed_1, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs ; -- Begin function _Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.globl	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
	.p2align	8
	.type	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs,@function
_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs: ; @_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s3, v[1:2]
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x18
	s_lshr_b32 s0, s2, 16
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_mul_lo_u32 v1, v4, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v2, v1
	v_add_nc_u32_e32 v3, s4, v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmpx_lt_i32_e32 1, v4
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_lshl_b32 s1, s4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_subrev_nc_u32_e32 v4, s1, v3
	v_add_nc_u32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v5, v4, v5
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, v3, v2
	s_mul_i32 s0, s5, s4
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s0, v3
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v3, v4
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_lt_i32_e32 vcc_lo, 1, v2
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_add_nc_u32_e32 v2, -1, v0
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[6:7], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s0, v3
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v3, v7, v6
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_div_scale_f32 v6, null, s6, s6, v5
	v_div_scale_f32 v10, null, s6, s6, v2
	v_div_scale_f32 v7, null, s6, s6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v8, v6
	v_div_scale_f32 v11, null, s6, s6, v3
	v_rcp_f32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v12, v7
	v_div_scale_f32 v15, vcc_lo, v5, s6, v5
	v_rcp_f32_e32 v14, v11
	v_div_scale_f32 v16, s0, v4, s6, v4
	v_fma_f32 v9, -v6, v8, 1.0
	v_div_scale_f32 v17, s1, v2, s6, v2
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v18, -v10, v13, 1.0
	v_div_scale_f32 v21, s2, v3, s6, v3
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v9, -v7, v12, 1.0
	v_fmac_f32_e32 v13, v18, v13
	s_delay_alu instid0(TRANS32_DEP_1)
	v_fma_f32 v20, -v11, v14, 1.0
	s_mov_b32 s4, 0x3e76c4e1
	v_mul_f32_e32 v19, v15, v8
	v_fmac_f32_e32 v12, v9, v12
	s_mov_b32 s14, 0
	v_fmac_f32_e32 v14, v20, v14
	v_mul_f32_e32 v20, v17, v13
	v_fma_f32 v9, -v6, v19, v15
	v_mul_f32_e32 v18, v16, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v22, v21, v14
	v_fmac_f32_e32 v19, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, -v7, v18, v16
	v_fma_f32 v23, -v11, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v6, -v6, v19, v15
	v_fma_f32 v15, -v10, v20, v17
	v_fmac_f32_e32 v18, v9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v22, v23, v14
	v_fmac_f32_e32 v20, v15, v13
	v_div_fmas_f32 v6, v6, v8, v19
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v11, v22, v21
	v_div_fixup_f32 v9, v6, s6, v5
	v_fma_f32 v6, -v7, v18, v16
	v_fma_f32 v7, -v10, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v10, |v9|
	v_div_fmas_f32 v6, v6, v12, v18
	s_mov_b32 vcc_lo, s1
	v_cmp_class_f32_e64 s10, v9, 0x204
	v_div_fmas_f32 v7, v7, v13, v20
	s_mov_b32 vcc_lo, s2
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v10
	v_div_fmas_f32 v12, v8, v14, v22
	v_div_fixup_f32 v8, v6, s6, v4
	v_div_fixup_f32 v7, v7, s6, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, 0, 1, s1
	v_div_fixup_f32 v6, v12, s6, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_frexp_mant_f32_e64 v12, |v8|
	v_frexp_exp_i32_f32_e32 v13, v8
	v_frexp_mant_f32_e64 v15, |v7|
	v_ldexp_f32 v10, v10, v11
	v_frexp_exp_i32_f32_e32 v11, v9
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v12
	v_frexp_mant_f32_e64 v16, |v6|
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v15
	v_cmp_class_f32_e64 s13, v8, 0x204
	v_subrev_co_ci_u32_e64 v11, vcc_lo, 0, v11, s1
	v_cndmask_b32_e64 v17, 0, 1, s2
	v_subrev_co_ci_u32_e64 v13, s1, 0, v13, s2
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v16
	v_cndmask_b32_e64 v19, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v12, v12, v17
	v_cvt_f32_i32_e32 v13, v13
	v_add_f32_e32 v20, -1.0, v10
	v_cndmask_b32_e64 v21, 0, 1, vcc_lo
	v_ldexp_f32 v15, v15, v19
	v_add_f32_e32 v23, 1.0, v12
	v_dual_mul_f32 v29, 0x3f317218, v13 :: v_dual_add_f32 v14, 1.0, v10
	v_cvt_f32_i32_e32 v11, v11
	v_ldexp_f32 v16, v16, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v27, -1.0, v23
	v_rcp_f32_e32 v28, v23
	v_rcp_f32_e32 v18, v14
	v_add_f32_e32 v19, -1.0, v14
	v_mul_f32_e32 v25, 0x3f317218, v11
	v_cmp_class_f32_e64 s12, v7, 0x204
	v_cmp_eq_f32_e64 s2, 0, v7
	v_cmp_class_f32_e64 s11, v6, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f32 v33, 0x3f317218, v11, -v25
	v_mul_f32_e32 v17, v20, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, 0xb102e308, v11
	v_dual_mul_f32 v21, v14, v17 :: v_dual_add_f32 v24, 1.0, v15
	v_sub_f32_e32 v10, v10, v19
	v_add_f32_e32 v19, -1.0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, v17, v14, -v21
	v_add_f32_e32 v31, -1.0, v24
	v_add_f32_e32 v26, -1.0, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v17, v10 :: v_dual_sub_f32 v15, v15, v31
	v_add_f32_e32 v10, 1.0, v16
	v_add_f32_e32 v30, v21, v14
	v_add_f32_e32 v22, -1.0, v12
	v_sub_f32_e32 v12, v12, v27
	v_fma_f32 v27, 0x3f317218, v13, -v29
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v27, 0xb102e308, v13
	v_sub_f32_e32 v21, v30, v21
	v_rcp_f32_e32 v32, v24
	v_add_f32_e32 v34, -1.0, v10
	v_sub_f32_e32 v35, v20, v30
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v20, v20, v35 :: v_dual_mul_f32 v13, v19, v32
	v_sub_f32_e32 v11, v16, v34
	v_rcp_f32_e32 v36, v10
	v_sub_f32_e32 v14, v21, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v20, v30
	v_dual_mul_f32 v31, v24, v13 :: v_dual_mul_f32 v20, v22, v28
	v_add_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v24, v13, v24, -v31
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v21, v26, v36 :: v_dual_add_f32 v14, v35, v14
	v_fmac_f32_e32 v24, v13, v15
	v_dual_add_f32 v35, v29, v27 :: v_dual_mul_f32 v34, v10, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v18, v14
	v_sub_f32_e32 v18, v35, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v21, v10, -v34
	v_fmac_f32_e32 v10, v21, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, v23, v20 :: v_dual_add_f32 v29, v34, v10
	v_fma_f32 v23, v20, v23, -v16
	v_add_f32_e32 v30, v25, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v39, v26, v29
	v_dual_fmac_f32 v23, v20, v12 :: v_dual_sub_f32 v12, v30, v25
	v_add_f32_e32 v25, v31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v16, v23
	v_sub_f32_e32 v31, v25, v31
	v_add_f32_e32 v11, v17, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v37, v22, v15
	v_sub_f32_e32 v17, v11, v17
	v_mul_f32_e32 v38, v11, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v22, v37
	v_sub_f32_e32 v16, v15, v16
	v_fma_f32 v40, v11, v11, -v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v22, v15
	v_sub_f32_e32 v16, v16, v23
	v_sub_f32_e32 v14, v14, v17
	v_dual_sub_f32 v17, v19, v25 :: v_dual_sub_f32 v34, v29, v34
	v_sub_f32_e32 v23, v31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v19, v17
	v_sub_f32_e32 v19, v19, v25
	v_add_f32_e32 v15, v16, v15
	v_add_f32_e32 v41, v14, v14
	v_sub_f32_e32 v24, v26, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v15, v37, v15 :: v_dual_fmac_f32 v40, v11, v41
	v_ldexp_f32 v37, v14, 1
	v_dual_mul_f32 v15, v28, v15 :: v_dual_add_f32 v22, v38, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v16, v23, v19 :: v_dual_fmaak_f32 v19, s4, v22, 0x3e91f4c4
	v_dual_add_f32 v16, v17, v16 :: v_dual_sub_f32 v17, v27, v18
	v_sub_f32_e32 v24, v24, v29
	v_ldexp_f32 v27, v11, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v18, v22, v19, 0x3ecccdef
	v_mul_f32_e32 v16, v32, v16
	v_sub_f32_e32 v10, v34, v10
	v_sub_f32_e32 v19, v22, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v13, v16
	v_add_f32_e32 v10, v10, v24
	v_add_f32_e32 v24, v20, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v40, v19 :: v_dual_mul_f32 v34, v11, v22
	v_dual_sub_f32 v13, v25, v13 :: v_dual_add_f32 v10, v39, v10
	v_mul_f32_e32 v31, v25, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v29, v24, v24
	v_mul_f32_e32 v23, v22, v18
	v_fma_f32 v38, v22, v11, -v34
	v_fma_f32 v26, v22, v18, -v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v38, v22, v14
	v_fmac_f32_e32 v26, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v19, v11
	v_add_f32_e32 v19, v34, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v32, v23, v26 :: v_dual_sub_f32 v13, v16, v13
	v_dual_sub_f32 v16, v32, v23 :: v_dual_add_f32 v23, 0x3f2aaaaa, v32
	v_sub_f32_e32 v20, v24, v20
	v_mul_f32_e32 v10, v36, v10
	v_fma_f32 v36, v25, v25, -v31
	v_ldexp_f32 v18, v24, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v15, v20 :: v_dual_add_f32 v28, v21, v10
	v_sub_f32_e32 v12, v33, v12
	v_fma_f32 v20, v24, v24, -v29
	v_dual_add_f32 v14, v15, v15 :: v_dual_sub_f32 v21, v28, v21
	v_mul_f32_e32 v33, v28, v28
	v_ldexp_f32 v22, v15, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v24, v14
	v_sub_f32_e32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, v28, v28, -v33
	v_add_f32_e32 v11, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v21, v28, v11
	v_add_f32_e32 v11, v29, v20
	v_sub_f32_e32 v16, v26, v16
	v_add_f32_e32 v26, 0xbf2aaaaa, v23
	v_dual_sub_f32 v34, v19, v34 :: v_dual_add_f32 v39, v33, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v40, s4, v11, 0x3e91f4c4
	v_add_f32_e32 v16, 0x31739010, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v26, v32, v26 :: v_dual_sub_f32 v29, v11, v29
	v_dual_sub_f32 v34, v38, v34 :: v_dual_mul_f32 v41, v24, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v16, v26
	v_sub_f32_e32 v20, v20, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v23, v16
	v_dual_add_f32 v32, v13, v13 :: v_dual_sub_f32 v23, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v36, v25, v32
	v_mul_f32_e32 v32, v19, v14
	v_add_f32_e32 v16, v16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v19, v14, -v32
	v_fmac_f32_e32 v23, v19, v16
	v_fmaak_f32 v19, v11, v40, 0x3ecccdef
	v_fma_f32 v40, v11, v24, -v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v23, v34, v14 :: v_dual_sub_f32 v14, v39, v33
	v_mul_f32_e32 v33, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v40, v11, v15
	v_dual_add_f32 v29, v32, v23 :: v_dual_add_f32 v26, v31, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v21, v14
	v_mul_f32_e32 v34, v28, v39
	v_fma_f32 v43, v11, v19, -v33
	v_fma_f32 v21, v39, v28, -v34
	v_sub_f32_e32 v16, v26, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v43, v20, v19
	v_dual_fmac_f32 v21, v39, v10 :: v_dual_sub_f32 v16, v36, v16
	v_add_f32_e32 v36, v27, v29
	v_ldexp_f32 v10, v10, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v36, v27
	v_mul_f32_e32 v31, v25, v26
	v_sub_f32_e32 v27, v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v26, v25, -v31
	v_dual_fmac_f32 v19, v26, v13 :: v_dual_sub_f32 v32, v29, v32
	v_ldexp_f32 v13, v13, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v23, v23, v32
	v_dual_add_f32 v23, v37, v23 :: v_dual_fmaak_f32 v42, s4, v26, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v23, v27
	v_add_f32_e32 v32, v33, v43
	v_sub_f32_e32 v29, v32, v33
	v_add_f32_e32 v33, 0x3f2aaaaa, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v43, v29
	v_add_f32_e32 v23, 0xbf2aaaaa, v33
	v_fmaak_f32 v42, v26, v42, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, 0x31739010, v15
	v_sub_f32_e32 v23, v32, v23
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmaak_f32 v38, s4, v39, 0x3e91f4c4 :: v_dual_mul_f32 v27, v26, v42
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e64 s4, s3, 1
	v_cmp_eq_f32_e64 s3, 0, v6
	v_add_f32_e32 v15, v15, v23
	v_fmaak_f32 v38, v39, v38, 0x3ecccdef
	v_fma_f32 v23, v26, v42, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v37, v33, v15 :: v_dual_mul_f32 v32, v39, v38
	v_fmac_f32_e32 v23, v16, v42
	v_fmac_f32_e32 v19, v16, v25
	v_ldexp_f32 v25, v25, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v33, v33, v37 :: v_dual_fmac_f32 v40, v20, v24
	v_fma_f32 v26, v39, v38, -v32
	v_add_f32_e32 v15, v15, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v39, v41, v40
	v_add_f32_e32 v29, v36, v11
	v_add_f32_e32 v20, v30, v29
	v_sub_f32_e32 v36, v29, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v24, v20, v30 :: v_dual_sub_f32 v11, v11, v36
	v_dual_sub_f32 v36, v39, v41 :: v_dual_sub_f32 v43, v20, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v29, v24 :: v_dual_add_f32 v33, v12, v11
	v_dual_sub_f32 v16, v40, v36 :: v_dual_sub_f32 v29, v30, v43
	v_fmac_f32_e32 v21, v14, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v36, v33, v12
	v_fmac_f32_e32 v26, v14, v38
	v_dual_add_f32 v24, v24, v29 :: v_dual_sub_f32 v11, v11, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v24, v33, v24
	v_mul_f32_e32 v30, v39, v37
	v_fma_f32 v29, v39, v37, -v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v39, v15
	v_dual_fmac_f32 v29, v16, v37 :: v_dual_add_f32 v16, v27, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v16, v27
	v_dual_add_f32 v44, v31, v19 :: v_dual_sub_f32 v15, v33, v36
	v_sub_f32_e32 v23, v23, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v12, v15
	v_sub_f32_e32 v14, v44, v31
	v_add_f32_e32 v31, v20, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v23, 0x31739010, v23
	v_add_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v19, v14
	v_sub_f32_e32 v15, v31, v20
	v_add_f32_e32 v33, v32, v26
	v_frexp_exp_i32_f32_e32 v19, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v24, v15
	v_add_f32_e32 v20, v30, v29
	v_subrev_co_ci_u32_e64 v19, s0, 0, v19, s0
	v_cmp_eq_f32_e64 s0, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, v11, v12
	v_add_f32_e32 v15, v18, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v19, v19
	v_dual_add_f32 v27, v31, v11 :: v_dual_sub_f32 v24, v20, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v15, v18
	v_sub_f32_e32 v18, v29, v24
	v_sub_f32_e32 v24, v33, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v20, v12 :: v_dual_mul_f32 v29, 0, v27
	v_add_f32_e32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v26, v24
	v_add_f32_e32 v12, v18, v12
	v_add_f32_e32 v18, v27, v27
	v_sub_f32_e32 v24, v27, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v24 :: v_dual_add_f32 v30, 0x3f2aaaaa, v33
	v_dual_add_f32 v24, v15, v12 :: v_dual_fmac_f32 v29, 2.0, v11
	v_add_f32_e32 v11, 0x31739010, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v36, 0x3f2aaaaa, v16 :: v_dual_sub_f32 v15, v24, v15
	v_add_f32_e32 v20, 0xbf2aaaaa, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v16, v20
	v_fma_f32 v20, v27, 2.0, -v18
	v_add_f32_e32 v16, v23, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v20, v29
	v_add_f32_e32 v22, v35, v24
	v_sub_f32_e32 v23, v22, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v27, v22, v23
	v_sub_f32_e32 v23, v24, v23
	v_sub_f32_e32 v24, v35, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v26, 0xbf2aaaaa, v30 :: v_dual_add_f32 v23, v23, v24
	v_sub_f32_e32 v26, v33, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v11, v26 :: v_dual_sub_f32 v12, v12, v15
	v_add_f32_e32 v26, v36, v16
	v_dual_add_f32 v29, v17, v12 :: v_dual_sub_f32 v32, v36, v26
	v_mul_f32_e32 v35, v44, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v27, v29, v17 :: v_dual_add_f32 v16, v16, v32
	v_add_f32_e32 v23, v29, v23
	v_sub_f32_e32 v24, v29, v27
	v_add_f32_e32 v29, v30, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v17, v24
	v_fma_f32 v24, v44, v26, -v35
	v_add_f32_e32 v15, v18, v20
	v_cmp_class_f32_e64 s1, v18, 0x204
	v_fmac_f32_e32 v24, v44, v16
	v_add_f32_e32 v16, v34, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v15, v18, s1
	v_sub_f32_e32 v15, v15, v18
	v_fmac_f32_e32 v24, v14, v26
	v_sub_f32_e32 v14, v30, v29
	v_sub_f32_e32 v26, v16, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v20, v15
	v_cmp_eq_f32_e64 s1, 0x42b17218, v31
	v_add_f32_e32 v30, v35, v24
	v_add_f32_e32 v11, v11, v14
	v_sub_f32_e32 v21, v21, v26
	v_cndmask_b32_e64 v33, 0, 0x37000000, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v30, v35
	v_cmp_neq_f32_e64 s1, 0x7f800000, |v31|
	v_sub_f32_e32 v24, v24, v26
	v_sub_f32_e32 v12, v12, v27
	v_add_f32_e32 v27, v22, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, 0, v15, s1
	v_cmp_eq_f32_e64 s1, 0, v8
	v_dual_add_f32 v13, v13, v24 :: v_dual_add_f32 v12, v12, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v27, v22
	v_dual_sub_f32 v22, v23, v22 :: v_dual_mul_f32 v23, v16, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v12, v22
	v_fma_f32 v14, v16, v29, -v23
	v_frexp_exp_i32_f32_e32 v22, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v16, v11 :: v_dual_add_f32 v11, v25, v30
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v21, v29
	v_sub_f32_e32 v21, v11, v25
	v_ldexp_f32 v25, v28, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v22, v22
	v_sub_f32_e32 v21, v30, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v13, v13, v21 :: v_dual_add_f32 v28, v23, v14
	v_dual_sub_f32 v32, v31, v33 :: v_dual_mul_f32 v31, 0x3f317218, v19
	v_sub_f32_e32 v23, v28, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v32
	v_fma_f32 v16, 0x3f317218, v19, -v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v14, v23 :: v_dual_add_f32 v23, v11, v13
	v_fmac_f32_e32 v16, 0xb102e308, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v10, v14 :: v_dual_sub_f32 v11, v23, v11
	v_dual_add_f32 v14, v31, v16 :: v_dual_sub_f32 v11, v13, v11
	v_add_f32_e32 v26, v25, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v18, 0x3fb8aa3b, v32 :: v_dual_sub_f32 v25, v26, v25
	v_fma_f32 v17, 0x3fb8aa3b, v32, -v18
	v_rndne_f32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v28, v25
	v_fmac_f32_e32 v17, 0x32a5705f, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v18, v20
	v_dual_add_f32 v25, v27, v12 :: v_dual_add_f32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v18, v17
	v_add_f32_e32 v18, v14, v23
	v_sub_f32_e32 v21, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v17, v17
	v_sub_f32_e32 v28, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v18, v28
	v_sub_f32_e32 v23, v23, v28
	v_sub_f32_e32 v13, v14, v30
	v_mul_f32_e32 v24, 0x3f317218, v22
	v_add_f32_e32 v27, v26, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v23, v13
	v_fma_f32 v19, 0x3f317218, v22, -v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, 0xb102e308, v22
	v_add_f32_e32 v22, v24, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_add_f32 v29, v22, v27 :: v_dual_sub_f32 v12, v12, v21
	v_sub_f32_e32 v21, v14, v31
	v_sub_f32_e32 v14, v22, v24
	v_dual_sub_f32 v24, v27, v26 :: v_dual_add_f32 v31, v25, v25
	v_sub_f32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v24
	v_dual_add_f32 v23, v14, v10 :: v_dual_sub_f32 v16, v16, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v29, v22 :: v_dual_add_f32 v28, v16, v11
	v_sub_f32_e32 v24, v28, v16
	v_add_f32_e32 v13, v28, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v24 :: v_dual_sub_f32 v26, v29, v21
	v_sub_f32_e32 v21, v27, v21
	v_dual_sub_f32 v19, v22, v26 :: v_dual_sub_f32 v26, v28, v24
	v_fma_f32 v22, v25, 2.0, -v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v21, v19
	v_dual_mul_f32 v21, 0, v25 :: v_dual_sub_f32 v16, v16, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v23, v19
	v_dual_fmac_f32 v21, 2.0, v12 :: v_dual_add_f32 v12, v18, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, v11, v16
	v_cvt_i32_f32_e32 v16, v20
	v_add_f32_e32 v26, v29, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v12, v18
	v_dual_sub_f32 v13, v13, v18 :: v_dual_add_f32 v18, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v13
	v_add_f32_e32 v13, v33, v15
	v_ldexp_f32 v15, v17, v16
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_sub_f32_e32 v25, v23, v14
	v_cmp_class_f32_e64 vcc_lo, v31, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v23, v25
	v_sub_f32_e32 v10, v10, v25
	v_sub_f32_e32 v14, v14, v23
	v_sub_f32_e32 v23, v26, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v14
	v_sub_f32_e32 v14, v19, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v14
	v_add_f32_e32 v14, v31, v18
	v_add_f32_e32 v17, v26, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, v14, v31, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v32
	v_dual_sub_f32 v20, v17, v26 :: v_dual_mul_f32 v23, 0, v17
	v_cndmask_b32_e32 v15, 0x7f800000, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v19
	v_sub_f32_e32 v10, v10, v20
	v_add_f32_e32 v20, v17, v17
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v23, 2.0, v10 :: v_dual_add_f32 v16, v12, v11
	v_fma_f32 v10, v15, v13, v15
	v_sub_f32_e32 v24, v19, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v16, v12
	v_mul_f32_e32 v22, 0, v16
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_mul_f32 v13, 0x3fb8aa3b, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v12
	v_add_f32_e32 v12, v16, v16
	v_fmac_f32_e32 v22, 2.0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v16, 2.0, -v12
	v_fma_f32 v11, v17, 2.0, -v20
	v_cmp_class_f32_e64 vcc_lo, v12, 0x204
	v_fma_f32 v17, 0x3fb8aa3b, v24, -v13
	v_dual_add_f32 v16, v16, v22 :: v_dual_add_f32 v11, v11, v23
	v_rndne_f32_e32 v23, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v17, 0x32a5705f, v24
	v_add_f32_e32 v15, v12, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v20, v11
	v_sub_f32_e32 v13, v13, v23
	v_cvt_i32_f32_e32 v23, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v25, v15, v12, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v20, 0x204
	v_dual_add_f32 v13, v13, v17 :: v_dual_cndmask_b32 v26, v22, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v25
	v_exp_f32_e32 v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v26
	v_cndmask_b32_e64 v28, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v19|
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v9, v23
	v_sub_f32_e32 v17, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v14, v31 :: v_dual_mul_f32 v13, 0x3fb8aa3b, v17
	v_sub_f32_e32 v14, v18, v14
	v_sub_f32_e32 v18, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, 0x3fb8aa3b, v17, -v13
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, 0x3fb8aa3b, v18
	v_rndne_f32_e32 v31, v13
	v_fmac_f32_e32 v30, 0x32a5705f, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v14, v21, v14
	v_fma_f32 v21, 0x3fb8aa3b, v18, -v19
	v_rndne_f32_e32 v29, v19
	v_dual_sub_f32 v13, v13, v31 :: v_dual_sub_f32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, 0x32a5705f, v18
	v_sub_f32_e32 v19, v19, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v13, v30
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v24
	v_add_f32_e32 v15, v19, v21
	v_sub_f32_e32 v19, v22, v20
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v24
	v_sub_f32_e32 v12, v16, v12
	v_exp_f32_e32 v15, v15
	v_cvt_i32_f32_e32 v16, v29
	v_exp_f32_e32 v13, v13
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v25|
	v_cvt_i32_f32_e32 v20, v31
	v_dual_sub_f32 v11, v11, v19 :: v_dual_cndmask_b32 v12, 0, v12
	s_delay_alu instid0(TRANS32_DEP_2)
	v_ldexp_f32 v15, v15, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v18
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_4)
	v_ldexp_f32 v13, v13, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_add_f32 v12, v27, v12 :: v_dual_cndmask_b32 v15, 0, v15
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v26|
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v17
	v_add_f32_e32 v11, v28, v11
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v18
	v_cndmask_b32_e32 v15, 0x7f800000, v15, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v17
	v_fma_f32 v14, v9, v14, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v15, v12, v15
	v_cndmask_b32_e32 v13, 0x7f800000, v13, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9
	v_fma_f32 v11, v13, v11, v13
	v_cndmask_b32_e32 v9, v14, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v15
	v_cndmask_b32_e32 v8, v12, v15, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v13
	v_cndmask_b32_e32 v7, v11, v13, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_10
; %bb.9:
	v_add_f32_e64 v6, |v10|, 1.0
	v_add_f32_e64 v12, |v8|, 1.0
	v_add_f32_e64 v11, |v9|, 1.0
	v_add_f32_e64 v13, |v7|, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v14, null, v6, v6, 1.0
	v_div_scale_f32 v16, null, v12, v12, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v15, null, v11, v11, 1.0
	v_rcp_f32_e32 v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v16
	v_div_scale_f32 v18, null, v13, v13, 1.0
	v_rcp_f32_e32 v19, v15
	v_div_scale_f32 v22, vcc_lo, 1.0, v6, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v21, v18
	v_div_scale_f32 v26, s4, 1.0, v11, 1.0
	v_fma_f32 v23, -v14, v17, 1.0
	v_fma_f32 v25, -v16, v20, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v15, v19, 1.0
	v_dual_fmac_f32 v17, v23, v17 :: v_dual_fmac_f32 v20, v25, v20
	v_div_scale_f32 v23, s5, 1.0, v12, 1.0
	v_fma_f32 v27, -v18, v21, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v24, v19
	v_dual_mul_f32 v25, v22, v17 :: v_dual_mul_f32 v28, v23, v20
	v_div_scale_f32 v24, s6, 1.0, v13, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v14, v25, v22
	v_fma_f32 v32, -v16, v28, v23
	v_fmac_f32_e32 v21, v27, v21
	v_mul_f32_e32 v27, v26, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v25, v30, v17 :: v_dual_fmac_f32 v28, v32, v20
	v_mul_f32_e32 v29, v24, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v15, v27, v26
	v_fma_f32 v14, -v14, v25, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v16, -v16, v28, v23
	v_fma_f32 v33, -v18, v29, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v31, v19
	v_div_fmas_f32 v14, v14, v17, v25
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v29, v33, v21
	v_fma_f32 v15, -v15, v27, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v6, v14, v6, 1.0
	v_fma_f32 v18, -v18, v29, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v15, v15, v19, v27
	s_mov_b32 vcc_lo, s5
	v_cndmask_b32_e64 v6, v6, 0, s10
	v_div_fmas_f32 v16, v16, v20, v28
	s_mov_b32 vcc_lo, s6
	v_div_fixup_f32 v11, v15, v11, 1.0
	v_div_fmas_f32 v17, v18, v21, v29
	v_cndmask_b32_e64 v6, v6, 1.0, s0
	v_div_fixup_f32 v12, v16, v12, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, 0, s13
	v_div_fixup_f32 v13, v17, v13, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, 0, s12
	v_cndmask_b32_e64 v11, v11, 1.0, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, 0, s11
	v_cndmask_b32_e64 v12, v12, 1.0, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, 1.0, s3
	s_branch .LBB0_11
.LBB0_10:
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
.LBB0_11:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_13
; %bb.12:
	v_cndmask_b32_e64 v6, |v10|, 0x7f800000, s10
	v_cndmask_b32_e64 v9, |v9|, 0x7f800000, s13
	v_cndmask_b32_e64 v8, |v8|, 0x7f800000, s12
	v_cndmask_b32_e64 v7, |v7|, 0x7f800000, s11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, 0, s0
	v_cndmask_b32_e64 v9, v9, 0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, 0, s2
	v_cndmask_b32_e64 v7, v7, 0, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v10, 0xbfb8aa3b, v6 :: v_dual_mul_f32 v11, 0xbfb8aa3b, v9
	v_dual_mul_f32 v12, 0xbfb8aa3b, v8 :: v_dual_mul_f32 v13, 0xbfb8aa3b, v7
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v14, 0xbfb8aa3b, v6, -v10
	v_rndne_f32_e32 v15, v10
	v_fma_f32 v16, 0xbfb8aa3b, v9, -v11
	v_rndne_f32_e32 v17, v11
	v_fma_f32 v20, 0xbfb8aa3b, v7, -v13
	v_fmac_f32_e32 v14, 0xb2a5705f, v6
	v_rndne_f32_e32 v21, v13
	v_sub_f32_e32 v10, v10, v15
	v_rndne_f32_e32 v19, v12
	v_dual_sub_f32 v11, v11, v17 :: v_dual_fmac_f32 v20, 0xb2a5705f, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v13, v13, v21
	v_fmac_f32_e32 v16, 0xb2a5705f, v9
	v_add_f32_e32 v10, v10, v14
	v_fma_f32 v18, 0xbfb8aa3b, v8, -v12
	v_cvt_i32_f32_e32 v14, v15
	v_dual_add_f32 v13, v13, v20 :: v_dual_sub_f32 v12, v12, v19
	v_add_f32_e32 v11, v11, v16
	v_exp_f32_e32 v10, v10
	v_cvt_i32_f32_e32 v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_exp_f32_e32 v13, v13
	v_cvt_i32_f32_e32 v16, v19
	v_exp_f32_e32 v11, v11
	v_ldexp_f32 v10, v10, v14
	v_cvt_i32_f32_e32 v14, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v11, v11, v15
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v9
	v_fmac_f32_e32 v18, 0xb2a5705f, v8
	v_ldexp_f32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, 0, v11 :: v_dual_add_f32 v12, v12, v18
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v6
	v_exp_f32_e32 v12, v12
	v_cndmask_b32_e32 v6, 0x7f800000, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v12, v12, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v10, 0, v12, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v7
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v9
	v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v8
	v_cndmask_b32_e32 v12, 0x7f800000, v10, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v7
	v_cndmask_b32_e32 v13, 0x7f800000, v13, vcc_lo
.LBB0_13:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mul_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, v4, v11
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_fmac_f32_e32 v5, v2, v12
	global_load_b32 v7, v[0:1], off
	v_fmac_f32_e32 v5, v3, v13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, s7, v5
	global_store_b32 v[0:1], v7, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs, .Lfunc_end0-_Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5316
; NumSgprs: 18
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           2
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17anisotropy_kernelP15HIP_vector_typeIfLj1EEiiffs.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
