/**************************************************************************
* This file contains implementation of pqp (parallel quadratic programming)
* GPU version optimised with TILE and shared memory for MPC Term Project of HP3 Course.
* Group 7 CSE Dept. IIT KGP
*	Objective function: 1/2 U'QpU + Fp'U + 1/2 Mp
*	Constraints: GpU <= Kp
**************************************************************************/

#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
#include<cuda_runtime.h>

#define NUM_ITER 1000

#define pHorizon 1
#define nState 29
#define nInput 7
#define nOutput 7
#define nDis 1

#define erc 1e-6
#define eac 1e-6
#define eaj 1e-6
#define erj 1e-6

#define TILE_DIM 32
#define BLOCK_ROWS 8
#define BLOCK_SIZE 16
#define BLK_ROWS 32
#define BLK_COLS 32
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS

__global__ void printMat(float *mat, int N, int M)
{
	printf("printing mat\n");
	for(int i=0;i<N;i++)
	{
		for(int j=0;j<M;j++)
		{
			printf("%f ",mat[i*M+j]);
		}
		printf("\n");
	}
	printf("\n");
}



__global__ void initMatCuda(float *mat, float val, int N)	//coarsened							// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		mat[id1] = val;
		mat[id2]=val;
	}
}

/**************************************************************************
* This is utility function initialize the matrix
*   1. Parameter is float type matrix pointer (*mat), float val, 
*		size of matrix 
*   2. Return type void
**************************************************************************/
void initMat(float *mat, float val, int N)								// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (N+1024-1)/1024;

	initMatCuda<<<grid, block>>>(mat, val, N);
}



float *newMatrixCUDA(int n, int m)			
{
	float *tmp = NULL;
	
	cudaError_t err = cudaMalloc((void **)&tmp, n*m*sizeof(float));

	if ( err != cudaSuccess )
	{
		printf (" Failed to allocate device matrix! %s\n", cudaGetErrorString(err));
		exit ( EXIT_FAILURE ) ;
	}

	initMat(tmp, 0, n*m);
	return tmp;
}

/**************************************************************************
* This is utility function for create new  matrix
*   1. Parameter is (int n, int m) dimension of (n X m matrix) , 
*	2. Return pointer of new matrix
*   3. This function create dynamic size matrix using malloc
**************************************************************************/
float *newMatrix(int n, int m)			
{
	float *tmp = (float *)malloc(n*m*sizeof(float));
	for(int i=0;i<n*m;i++)
	{
		tmp[i] = 0;
	}
	return tmp;
}



void copyToDevice(float *dM, float *hM, int n, int m)
{
	int size = n*m;
	cudaMemcpy (dM ,hM, size * sizeof ( float ) , cudaMemcpyHostToDevice );
}

void copyToHost(float *hM, float *dM, int n, int m)
{
	int size = n*m;
	cudaMemcpy (hM ,dM, size * sizeof ( float ) , cudaMemcpyDeviceToHost );
}



__global__ void copyMatrixCuda(float *output, float *mat, int a, int b)		// parallel //coarsened
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<a*b)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		output[id1] = mat[id1];
		output[id2] = mat[id2];
	}
}
/**************************************************************************
* This is utility function for generating addition or substraction 
*	of two matrix
*   1. Parameter is (pointer of matrix1, pointer of matrix2, int sign,int n int m)
*		dimension of (n X m matrix) 
*	2. sign parameters for decide addition or substraction
*	3. Result write back in matrix1
**************************************************************************/
void copyMatrix(float *output, float *mat, int a, int b)		// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (a*b+1024-1)/1024;

	copyMatrixCuda<<<grid,block>>>(output, mat, a, b);
}



__global__ void transposeCuda(float *odata, float *idata, int n, int m)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];
    
  int x = blockIdx.x * TILE_DIM + threadIdx.x;
  int y = blockIdx.y * TILE_DIM + threadIdx.y;
  //int width = gridDim.x * TILE_DIM;

  for(int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
  {
	if(x<m && y<n)
	{
     tile[threadIdx.x][threadIdx.y] = idata[y*m+x];
	}
  }
 
  __syncthreads();
	
  x = blockIdx.y * TILE_DIM + threadIdx.x;  // transpose block offset
  y = blockIdx.x * TILE_DIM + threadIdx.y;

  for(int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
  {
	if(y<m && x<n){
     odata[(y*n) + x] = tile[threadIdx.y][threadIdx.x];
	 }
  }
  
}



void transpose(float *odata, float *idata, int n, int m)
{
	dim3 grid((n+TILE_DIM-1)/TILE_DIM, (m+TILE_DIM-1)/TILE_DIM, 1);
	dim3 block(TILE_DIM, TILE_DIM, 1);

	
	transposeCuda<<<grid,block>>>(odata,idata,n,m);
}

__global__ void matrixMultiplyCuda(float *output, float *matrix1, float *matrix2, int a, int b, int c)
{
	//declare shared memory matrices for matrix1 and matrix2 matrices
	__shared__ float shared_mat1_tile[TILE_SIZE][TILE_SIZE];
	__shared__ float shared_mat2_tile[TILE_SIZE][TILE_SIZE];
	int tsize;
	if(a!=1 && c!=1){	
	tsize=TILE_SIZE;
	}
	else{		
	tsize=1;
	}
	
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	int row = blockIdx.y * blockDim.y + threadIdx.y;

	//check if thread directly maps to the dimensions of the resulting matrix
	if (row < a && col < c)
	{
		float result = 0.0;
		int k;
		int phase;
		
		//calculate output matrix indexes in phases. Each phase shares 
		//TILE_SIZE * TILE_SIZE data copied to the shared matrix mat1 
		//and matrix mat2.
		for (phase = 0; phase <= b/tsize; phase++)
		{
			shared_mat1_tile[ty][tx] = matrix1[row * b + phase * tsize + tx];
			shared_mat2_tile[ty][tx] = matrix2[(phase * tsize + ty) * c + col];
			__syncthreads();
			
			for (k = 0; k < tsize; k++)
			{
				if (k + (phase * tsize) < b) 
				{
					result += (shared_mat1_tile[ty][k] * shared_mat2_tile[k][tx]);
				}
			}
			__syncthreads();
		}	
		output[row * c + col] = result;
	}
}


void matrixMultiply(float *output, float *mat1, int transpose1, float *mat2, int transpose2, int a, int b, int c) 		//mat1-a*b	mat2-b*c 	// parallel
{
	float *tmp = newMatrixCUDA(a,c);
	
	float *matrix1;
	float *matrix2;
	
	if(transpose1 && a!=1 && b!=1)
	{
		matrix1 = newMatrixCUDA(a,b);
		transpose(matrix1, mat1, b,a);
			
	}
	else
	{
		matrix1 = mat1;
	}
	
	if(transpose2 && b!=1 && c!=1)
	{
		matrix2 = newMatrixCUDA(b,c);
		transpose(matrix2, mat1, c,b);
		
	}
	else
	{
		matrix2 = mat2;
	}
	int B_C, B_R;
	if(a!=1 && c!=1)
	{
		B_C=BLK_COLS;
		B_R=BLK_ROWS;
	}
	else{
		B_C=1;
		B_R=1;
	}
	dim3 block(B_C,B_R);
	dim3 grid((c+B_C-1)/B_C,(a+B_R-1)/B_R);
	matrixMultiplyCuda<<<grid, block>>>(output, matrix1, matrix2, a, b, c);
	
	if(transpose1 && a!=1 && b!=1)
	{
		cudaFree(matrix1);
	}
	if(transpose2 && b!=1 && c!=1)
	{
		cudaFree(matrix2);
	}

	cudaFree(tmp);
}



__global__ void matrixAddCuda(float *A, float *B, float sign, int a, int b) 			// adds b to a 	// parallel //coarsened
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<a*b)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		A[id1] += sign * B[id1];
		A[id2] += sign * B[id2];
	}
}

void matrixAdd(float *A, float *B, float sign, int a, int b) 			// adds b to a 	// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (a*b+1024-1)/1024;

	matrixAddCuda<<<grid,block>>>(A,B,sign,a,b);
}



__global__ void negateMatrixCuda(float *mat, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat[id] = -mat[id];
	}
}

void negateMatrix(float *mat, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	negateMatrixCuda<<<grid,block>>>(mat,n,m);
}



__global__ void matrixPosCuda(float *mat1, float *mat2, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat1[id] = fmaxf(0.0, mat2[id]);

	}
}

void matrixPos(float *mat1, float *mat2, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	matrixPosCuda<<<grid,block>>>(mat1,mat2,n,m);
}



__global__ void matrixNegCuda(float *mat1, float *mat2, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat1[id] = fmaxf(0.0, -mat2[id]);
	}
}

void matrixNeg(float *mat1, float *mat2, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	matrixNegCuda<<<grid,block>>>(mat1,mat2,n,m);
}



__global__ void diagonalAddCuda(float *theta, float *tmp, int N)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		// printf("tmp %f\n",tmp[i]);
		theta[id*N+id] = fmaxf(tmp[id],5.0);
	}
}

void diagonalAdd(float *theta, float *tmp, int N)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1024-1)/1024;

	diagonalAddCuda<<<grid,block>>>(theta,tmp,N);
}



__global__ void compareCuda(float *GpU, float *Kp, int *re, int N)				// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		if(GpU[id] > Kp[id]+fmaxf(erc*Kp[id], eac))
		{
			*re = 0;
		}
	}
}

void compare(float *GpU, float *Kp, int *re, int N)				// parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1024-1)/1024;

	compareCuda<<<grid,block>>>(GpU, Kp, re, N);
}




__global__ void updYCuda(float *Y_next, float *numerator, float *denominator, float *Y, int N)   // parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	
	if(id<N)
	{
		Y_next[id] = numerator[id]/denominator[id]*Y[id];
	}
}

void updY(float *Y_next, float *numerator, float *denominator, float *Y, int N)   // parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1023)/1024;
	
	updYCuda<<<grid, block>>>(Y_next, numerator, denominator, Y, N);
}




void Gauss_Jordan(float *A,float *res, int N)
{
    /*
    size=Size of input matrix
    A=input matrix
    res= inverted matrix
    */
    float temp;
    float *matrix = newMatrix(N, 2*N);

    for (int i = 0; i < N; i++) 
    { 
        for (int j = 0; j < 2 * N; j++) 
        { 
            matrix[i*2*N+j]=0;
            if (j == (i + N)) 
                matrix[i*2*N+j] = 1; 
        } 
    }

    for (int i = 0; i < N; i++) 
    { 
        for (int j = 0; j < N; j++) 
        { 
            matrix[i*2*N+j]=A[i*N+j];

        } 
    }

    for (int i = N - 1; i > 0; i--) 
    { 
        if (matrix[(i - 1)*2*N+0] < matrix[i*2*N+0]) 
            for (int j = 0; j < 2 * N; j++) 
            { 
                temp = matrix[i*2*N+j]; 
                matrix[i*2*N+j] = matrix[(i - 1)*2*N+j]; 
                matrix[(i - 1)*2*N+j] = temp; 
            } 
    }

    for (int i = 0; i < N; i++)
    { 

        for (int j = 0; j < N; j++) 
        { 
            if (j != i) 
            { 
                temp = matrix[j*2*N+i] / matrix[i*2*N+i]; 
                for (int k = 0; k < 2 * N; k++) 
                { 
                    matrix[j*2*N+k] -= matrix[i*2*N+k] * temp; 
                } 
            } 
        } 
    } 

    for (int i = 0; i < N; i++)
    { 
        temp = matrix[i*2*N+i]; 
        for (int j = 0; j < 2 * N; j++)
        {
            matrix[i*2*N+j] = matrix[i*2*N+j] / temp; 
        } 
    }

    for (int i = 0; i < N; i++) 
    { 
        for (int j = N; j <2*N; j++) 
        { 
            res[i*N+j-N]=matrix[i*2*N+j];

        } 
    }

    free(matrix);
}



void computeUfromY(float *U, float *Y, float *Fp, float *Gp, float *Qp_inv, int N, int M)
{
	float *tmp = newMatrixCUDA(M,1);
	matrixMultiply(tmp, Gp, 1, Y, 0, M, N, 1);
	matrixAdd(tmp, Fp, 1, M, 1);
	matrixMultiply(U, Qp_inv, 0, tmp, 0, M, M, 1);
	negateMatrix(U, M, 1);
	cudaFree(tmp);
}

void computeFp(float *Fp, float *Fp1, float *Fp2, float *Fp3, float *D, float *x)
{
	matrixMultiply(Fp, Fp1, 0, D, 0, nInput*pHorizon, nDis*pHorizon, 1);
	float *Fp2x = newMatrixCUDA(nInput*pHorizon,1);
	matrixMultiply(Fp2x, Fp2, 0, x, 0, nInput*pHorizon, nState, 1);
	matrixAdd(Fp, Fp2x, 1, nInput*pHorizon, 1);
	matrixAdd(Fp, Fp3, -1, nInput*pHorizon, 1);
	
	cudaFree(Fp2x);	
	// for(int i=0;i<nInput*pHorizon;i++)
	// {
	// 	printf("%f\n", Fp[i]);
	// }
	// printf("\n");
	// printf("%d\n", Fp);
}

void computeMp(float *Mp, float *Mp1, float *Mp2, float *Mp3, float *Mp4, float *Mp5, float *Mp6, float *D, float *x)
{
	initMat(Mp, 0, 1);

	float *tmp = newMatrixCUDA(1,nState);
	matrixMultiply(tmp, x, 1, Mp1, 0, 1, nState, nState);
	matrixMultiply(tmp, tmp, 0, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);
//	printMat<<<1,1>>>(Mp, 1, 1);

	matrixMultiply(tmp, D, 1, Mp2, 0, 1, nDis*pHorizon, nState);
	matrixMultiply(tmp, tmp, 0, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);
	
	matrixMultiply(tmp, Mp4, 1, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	cudaFree(tmp);
	tmp = newMatrixCUDA(1, nDis*pHorizon);
	matrixMultiply(tmp, D, 1, Mp3, 0, 1, nDis*pHorizon, nDis*pHorizon);
	matrixMultiply(tmp, tmp, 0, D, 0, 1, nDis*pHorizon, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	matrixMultiply(tmp, Mp5, 1, D, 0, 1, nDis*pHorizon, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	matrixAdd(Mp, Mp6, 0.5, 1,1);
	cudaFree(tmp);
}

void computeQd(float *Qd, float *Gp_Qp_inv, float *Gp, int N, int M)
{
	matrixMultiply(Qd, Gp_Qp_inv, 0, Gp, 1, N, M, N);	
}

void computeFd(float *Fd, float *Gp_Qp_inv, float *Fp, float *Kp, int N, int M)
{ 
	matrixMultiply(Fd, Gp_Qp_inv, 0, Fp, 0, N, M, 1);
	matrixAdd(Fd, Kp, 1, N, 1);
}

void computeMd(float *Md, float *Fp, float* Qp_inv, float* Mp, int N, int M)
{
	float *tmp = newMatrixCUDA(1,M);
	matrixMultiply(tmp, Fp, 1, Qp_inv, 0, 1, M, M);
	matrixMultiply(Md, tmp, 0, Fp, 0, 1, M, 1);
	matrixAdd(Md, Mp, -1, 1, 1);
	cudaFree(tmp);
}

void convertToDual(float *Qd, float *Fd, float *Md, float *Qp_inv, float *Gp, float *Kp, float *Fp, float *Mp, int N, int M)
{	
	float *Gp_Qp_inv = newMatrixCUDA(N,M);
	matrixMultiply(Gp_Qp_inv, Gp, 0, Qp_inv, 0, N, M, M);
	computeQd(Qd, Gp_Qp_inv, Gp, N, M);
	computeFd(Fd, Gp_Qp_inv, Fp, Kp, N, M);
	computeMd(Md, Fp, Qp_inv, Mp, N, M);

	cudaFree(Gp_Qp_inv);
}

void computeTheta(float *theta, float *Qd, int N)
{
	float *Qdn = newMatrixCUDA(N,N);
	matrixNeg(Qdn, Qd, N, N);

	float *one = newMatrixCUDA(N,1);
	initMat(one, 1, N);

	float *tmp = newMatrixCUDA(N,1);
	matrixMultiply(tmp, Qdn, 0, one, 0, N,N,1);

	diagonalAdd(theta, tmp, N);

	cudaFree(Qdn);
	cudaFree(one);
	cudaFree(tmp);
}

void computeQdp_theta(float *Qdp_theta, float *Qd, float *theta, int N)
{
	matrixPos(Qdp_theta, Qd, N, N);
	matrixAdd(Qdp_theta, theta, 1, N, N);
}

void computeQdn_theta(float *Qdn_theta, float *Qd, float *theta, int N)
{
	matrixNeg(Qdn_theta, Qd, N, N);
	matrixAdd(Qdn_theta, theta, 1, N, N);
}

void computealphaY(float *alphaY, float *ph, float *Qd, float *Y, float *Fd, int N)
{
	float *temp = newMatrixCUDA(1,N);

	matrixMultiply(temp, ph, 1, Qd, 0, 1, N, N);
	matrixMultiply(temp, temp, 0, ph, 0, 1, N, 1);

	if(temp[0] > 0)
	{
		float *temp2 = newMatrixCUDA(1,N);

		matrixMultiply(temp2, Y, 1, Qd, 0, 1, N, N);
		
		matrixAdd(temp2, Fd, 1, 1, N);
		
		matrixMultiply(temp2, temp2, 0, ph, 0, 1, N, 1);

		*alphaY = -temp2[0]/temp[0];

		cudaFree(temp2);
	}
	else
	{
		alphaY = 0;
	}

	cudaFree(temp);
}

void updateY1(float *Y_next, float *Y, float alphaY, float *ph, int N)
{
	copyMatrix(Y_next, Y, N, 1);
	matrixAdd(Y_next, ph, alphaY, N, 1);
}

void updateY2(float *Y_next, float *Y, float *Qdp_theta, float *Qdn_theta, float *Fd, float *Fdp, float *Fdn, int N)
{
	float *numerator = newMatrixCUDA(N,1);
	float *denominator = newMatrixCUDA(N,1);

	matrixMultiply(numerator, Qdn_theta, 0, Y, 0, N, N, 1);
	matrixMultiply(denominator, Qdp_theta, 0, Y, 0, N, N, 1);

	matrixAdd(numerator, Fdn, 1, N, 1);
	matrixAdd(denominator, Fdp, 1, N, 1);

	updY(Y_next, numerator, denominator, Y, N);

	cudaFree(numerator);
	cudaFree(denominator);
}

void computeph(float *ph, float *Qd, float *Y, float *Fd, int N)
{
	matrixMultiply(ph, Qd, 0, Y, 0, N, N, 1);
	matrixAdd(ph, ph, 1, N, 1);
	matrixNeg(ph, ph, N, 1);
}

int checkFeas(float *U, float *Gp, float *Kp, int N, int M)
{
	float *tmp = newMatrixCUDA(N,1);
	matrixMultiply(tmp, Gp, 0, U, 0, N, M, 1);
	int re = 1;
	compare(tmp, Kp, &re, N);

	cudaFree(tmp);
	return re;
}	

float computeCost(float *Z, float *Q, float *F, float *M, int N)
{
	float *J=newMatrixCUDA(1,1);

	float *tmp = newMatrixCUDA(1,N);
	matrixMultiply(tmp, Z, 1, Q, 0, 1, N, N);
	matrixMultiply(tmp, tmp, 0, Z, 0, 1, N, 1);

	matrixAdd(J, tmp, 0.5, 1,1);

	matrixMultiply(tmp, F, 1, Z, 0, 1, N, 1);

	matrixAdd(J, tmp, 1, 1,1);
//	printMat<<<1,1>>>(J,1,1);
//	printMat<<<1,1>>>(M,1,1);
	matrixAdd(J, M, 0.5, 1,1);
	

	float *hJ = newMatrix(1,1);
	copyToHost(hJ,J,1,1);

	float cost = hJ[0];
	free(hJ);
	cudaFree(J);
	cudaFree(tmp);

	return cost;
}

int terminate(float *Y, float *Qd, float *Fd, float *Md, float *U, float *Qp, float *Qp_inv, float *Fp, float *Mp, float *Gp, float *Kp, int N, int M)
{
	computeUfromY(U, Y, Fp, Gp, Qp_inv, N, M);

	if(!checkFeas(U, Gp, Kp, N, M))	return 0;

	float Jd = computeCost(Y, Qd, Fd, Md, N);
	float Jp = computeCost(U, Qp, Fp, Mp, M);

	if(Jp>-Jd)	return 0;
	if(Jp+Jd>eaj)	return 0;
	if((Jp+Jd)/fabs(Jd)>erj) return 0;

	return 1;
}

void solveQuadraticDual(float *Y, float *Qd, float *Fd, float *Md, float *U, float *Qp, float *Qp_inv, float *Fp, float *Mp, float *Gp, float *Kp, int N, int M)
{
	float *theta = newMatrixCUDA(N,N);
	float *Qdp_theta = newMatrixCUDA(N,N);
	float *Qdn_theta = newMatrixCUDA(N,N);
	float *Y_next = newMatrixCUDA(N,1);
	
	float *Fdn = newMatrixCUDA(N,1);
	float *Fdp = newMatrixCUDA(N,1);

	matrixPos(Fdp, Fd, N, 1);
	matrixNeg(Fdn, Fd, N, 1);
	
	computeTheta(theta, Qd, N);
	computeQdp_theta(Qdp_theta, Qd, theta, N);
	computeQdn_theta(Qdn_theta, Qd, theta, N);

	initMat(Y, 1000.0, N);
	// for(int i=0;i<N;i++) Y[i] = i+1;

	float *ph = newMatrixCUDA(N,1);
	long int h=1;
	float alphaY=0;

//	 while(h<NUM_ITER)
	while(!terminate(Y, Qd, Fd, Md, U, Qp, Qp_inv, Fp, Mp, Gp, Kp, N, M))
	{	
		// if(h>100000) break;
//		 printf("h %ld\n",h);
		if(1)
		{
			//update
			// printf("here\n");
			updateY2(Y_next, Y, Qdp_theta, Qdn_theta, Fd, Fdp, Fdn, N);			
			// printf("there\n");
		}
		else
		{
			// printf("accelerating\n");
			// accelerate
			computeph(ph, Qd, Y, Fd, N);
			computealphaY(&alphaY, ph, Qd, Y, Fd, N);
			// printf("alpha %f\n", alphaY);
			
			updateY1(Y_next, Y, alphaY/10, ph, N);

		}

		copyMatrix(Y, Y_next, N, 1);
		// for(int i=0;i<N;i++)
		// {
		// 	printf("%f ",Y[i]);
		// }
		// printf("\n\n");

		h++;
	}
	printf("Printing number of iterations = %ld\n",h);

	cudaFree(theta);
	cudaFree(Qdp_theta);
	cudaFree(Qdn_theta);
	cudaFree(Y_next);
	cudaFree(ph);
	cudaFree(Fdp);
	cudaFree(Fdn);
}

void input(float* qp_inv, float* Fp1, float* Fp2, float * Fp3, float * Mp1, float * Mp2, float * Mp3, float* Mp4, float* Mp5, float* Mp6, float* Gp, float* Kp, float* x, float* D, float* theta, float* Z)
{
	FILE *fptr;
	int i,j;
	float num;

	//Fill Qp_inverse	
	fptr = fopen("./example/Qp_inv.txt","r");
	for(i=0;i<pHorizon*nInput;i++)
	{
		for(j=0;j<pHorizon*nInput;j++)
		{
			fscanf(fptr,"%f", &num);
			qp_inv[j*pHorizon*nInput+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp1
	fptr = fopen("./example/Fp1.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nInput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Fp1[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp2
	fptr = fopen("./example/Fp2.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nInput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Fp2[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp3
	fptr = fopen("./example/Fp3.txt","r");
	for(j=0;j<nInput*pHorizon;j++)
	{
		fscanf(fptr,"%f", &num);
		Fp3[j] = num;
	}
	fclose(fptr);

	//Fill Mp1
	fptr = fopen("./example/Mp1.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nState;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp1[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp2
	fptr = fopen("./example/Mp2.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nDis*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp2[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp3
	fptr = fopen("./example/Mp3.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nDis*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp3[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp4
	fptr = fopen("./example/Mp4.txt","r");
	for(i=0;i<nState;i++)
	{
		fscanf(fptr,"%f", &num);
		Mp4[i] = num;
	}
	fclose(fptr);

	//Fill Mp5
	fptr = fopen("./example/Mp5.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		fscanf(fptr,"%f", &num);
		Mp5[i] = num;
	}
	fclose(fptr);

	//Fill Mp6
	fptr = fopen("./example/Mp6.txt","r");
	fscanf(fptr,"%f", &num);
	Mp6[0] = num;
	fclose(fptr);

	//Fill Gp
	fptr = fopen("./example/Gp.txt","r");
	for(i=0;i<pHorizon*nInput;i++)
	{
		for(j=0;j<4*pHorizon*nInput;j++)
		{
			fscanf(fptr,"%f", &num);
			Gp[j*pHorizon*nInput+i] = num;
		}
	}
	fclose(fptr);

	//Fill Kp
	fptr = fopen("./example/Kp.txt","r");
	for(i=0;i<4*pHorizon*nInput;i++)
	{
		fscanf(fptr,"%f", &num);
		Kp[i] = num;
	}
	fclose(fptr);

	//Fill Z
	fptr = fopen("./example/Z.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nOutput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Z[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Theta
	fptr = fopen("./example/Theta.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nOutput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			theta[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill D
	fptr = fopen("./example/D.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		fscanf(fptr,"%f", &num);
		D[i] = num;
	}
	fclose(fptr);

	//Fill x
	fptr = fopen("./example/x.txt","r");
	for(i=0;i<nState;i++)
	{
		fscanf(fptr,"%f", &num);
		x[i] = num;
	}
	fclose(fptr);
}

int main()
{
	// QP is of parametric from 
	// J(U) = min U 1/2*U'QpU + Fp'U + 1/2*Mp
	// st GpU <= Kp
	
	cudaDeviceReset();

//	float *mat = newMatrixCUDA(32,32);
//	float *trp = newMatrixCUDA(32,32);
//	float *hmat= newMatrix(32,32);
//	float *htrp = newMatrix(32,32);
//
//	int cnt=1;
//
//	for(int i=0;i<10;i++)
//	{
//		for(int j=0;j<5;j++)
//		{
//			hmat[5*i+j] = cnt++;
//		}
//	}
//
//	copyToDevice(mat, hmat, 10,5);
//	transpose(trp, mat, 10,5);
//
//	copyToHost(htrp, trp, 5,10);
//
//	for(int i=0;i<5;i++)
//	{
//		for(int j=0;j<10;j++)
//		{
//			printf("%f ",htrp[10*i+j]);
//		}
//		printf("\n");
//	}

//	return 0;
	int N, M;

	M = pHorizon*nInput;
	N = 4*pHorizon*nInput;

	// host matrix
	float *hQp_inv = newMatrix(M,M);
	float *hQp = newMatrix(M,M);

	float *hFp1;
	float *hFp2;
	float *hFp3;

	float *hMp1;
	float *hMp2;
	float *hMp3;
	float *hMp4;
	float *hMp5;
	float *hMp6;

	float *hFp = newMatrix(nInput*pHorizon,1);
	float *hMp = newMatrix(1,1);
	float *hGp;
	float *hKp;
	float *hx;
	float *hD; 
	float *htheta; 
	float *hZ; 

	hFp1 = newMatrix(nInput*pHorizon, nDis*pHorizon);
	hFp2 = newMatrix(nInput*pHorizon, nState);
	hFp3 = newMatrix(1, nInput*pHorizon);
	hMp1 = newMatrix(nState, nState);
	hMp2 = newMatrix(nDis*pHorizon, nState);
	hMp3 = newMatrix(nDis*pHorizon, nDis*pHorizon);
	hMp4 = newMatrix(1, nState);
	hMp5 = newMatrix(1, nDis*pHorizon);
	hMp6 = newMatrix(1,1);
	hGp = newMatrix(4*pHorizon*nInput, nInput*pHorizon);
	hKp = newMatrix(1,4*pHorizon*nInput);
	hZ = newMatrix(nOutput*pHorizon, nState);
	htheta = newMatrix(nOutput*pHorizon, nDis*pHorizon);
	hD = newMatrix(nDis*pHorizon,1);
	hx = newMatrix(nState, 1);

	// device matrix
	float *Qp_inv = newMatrixCUDA(M,M);
	float *Qp = newMatrixCUDA(M,M);

	float *Fp1;
	float *Fp2;
	float *Fp3;

	float *Mp1;
	float *Mp2;
	float *Mp3;
	float *Mp4;
	float *Mp5;
	float *Mp6;

	float *Fp = newMatrixCUDA(nInput*pHorizon,1);
	float *Mp = newMatrixCUDA(1,1);
	float *Gp;
	float *Kp;
	float *x;
	float *D; 
	float *theta; 
	float *Z; 

	Fp1 = newMatrixCUDA(nInput*pHorizon, nDis*pHorizon);
	Fp2 = newMatrixCUDA(nInput*pHorizon, nState);
	Fp3 = newMatrixCUDA(1, nInput*pHorizon);
	Mp1 = newMatrixCUDA(nState, nState);
	Mp2 = newMatrixCUDA(nDis*pHorizon, nState);
	Mp3 = newMatrixCUDA(nDis*pHorizon, nDis*pHorizon);
	Mp4 = newMatrixCUDA(1, nState);
	Mp5 = newMatrixCUDA(1, nDis*pHorizon);
	Mp6 = newMatrixCUDA(1,1);
	Gp = newMatrixCUDA(4*pHorizon*nInput, nInput*pHorizon);
	Kp = newMatrixCUDA(1,4*pHorizon*nInput);
	Z = newMatrixCUDA(nOutput*pHorizon, nState);
	theta = newMatrixCUDA(nOutput*pHorizon, nDis*pHorizon);
	D = newMatrixCUDA(nDis*pHorizon,1);
	x = newMatrixCUDA(nState, 1);	

	input(hQp_inv, hFp1, hFp2, hFp3, hMp1, hMp2, hMp3, hMp4, hMp5, hMp6, hGp, hKp, hx, hD, htheta, hZ);
	Gauss_Jordan(hQp_inv, hQp, M);
	copyToDevice(Qp_inv, hQp_inv, M, M);
	copyToDevice(Qp, hQp, M, M);
	copyToDevice(Fp1, hFp1, nInput*pHorizon, nDis*pHorizon);
	copyToDevice(Fp2, hFp2, nInput*pHorizon, nState);
	copyToDevice(Fp3, hFp3, 1, nInput*pHorizon);
	copyToDevice(Mp1, hMp1, nState, nState);
	copyToDevice(Mp2, hMp2, nDis*pHorizon, nState);
	copyToDevice(Mp3, hMp3, nDis*pHorizon, nDis*pHorizon);
	copyToDevice(Mp4, hMp4, 1, nState);
	copyToDevice(Mp5, hMp5, 1, nDis*pHorizon);
	copyToDevice(Mp6, hMp6, 1,1);
	copyToDevice(Gp, hGp, 4*pHorizon*nInput, nInput*pHorizon);
	copyToDevice(Kp, hKp, 1,4*pHorizon*nInput);
	copyToDevice(Z, hZ, nOutput*pHorizon, nState);
	copyToDevice(D, hD, nDis*pHorizon,1);
	copyToDevice(theta, htheta, nOutput*pHorizon, nDis*pHorizon);
	copyToDevice(x, hx, nState, 1);

	computeFp(Fp, Fp1, Fp2, Fp3, D, x);
	computeMp(Mp, Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, D, x);
	// printf("Mp %f\n", Mp[0]);
	// printf("er\n");
//	printMat<<<1,1>>>(Mp,1,1);
	// matrices and vectors required for dual form of QP
	float *Qd = newMatrixCUDA(N,N);
	float *Fd = newMatrixCUDA(N,1);
	float *Md = newMatrixCUDA(1,1);	
	float *Y  = newMatrixCUDA(N,1);
	float *U  = newMatrixCUDA(M,1);
	// printf("er\n");
	convertToDual(Qd, Fd, Md, Qp_inv, Gp, Kp, Fp, Mp, N, M);
	// printf("Qd\n");
	// for(int i=0;i<N;i++)
	// {
	// 	for(int j=0;j<N;j++)
	// 	{
	// 		printf("%f ", Qd[i*N+j]);
	// 	}
	// 	printf("\n");
	// }
	// printf("Fd\n");
	// printf("%f\n", Md[0]);
	// for(int i=0;i<N;i++)
	// {
	// 	printf("%f ", Fp[i]);
	// }
	// printf("\n");
	solveQuadraticDual(Y, Qd, Fd, Md, U, Qp, Qp_inv, Fp, Mp, Gp, Kp, N, M);
	// printf("erer\n");

	computeUfromY(U, Y, Fp, Gp, Qp_inv, N, M);

	// U[0] = -6.399018;
	// U[1] = -10.648726;
	// U[2] = -4.792378;
	// U[3] = -7.033428;
	// U[4] = -4.792378;
	// U[5] = -10.648726;
	// U[6] = -6.399018;

	// U[0] = -6.398985;
	// U[1] = -10.646729;
	// U[2] = -4.792132;
	// U[3] = -7.027614;
	// U[4] = -4.792255;
	// U[5] = -10.643004;
	// U[6] = -6.398996;

	float Jp = computeCost(U, Qp, Fp, Mp, M);
	float Jd = computeCost(Y, Qd, Fd, Md, N);

	printf("Jp = %f\n", Jp);
	printf("Jd = %f\n", Jd);
	
	float *hU = newMatrix(M,1);
	float *hY = newMatrix(N,1);

	copyToHost(hU,U,M,1);
	copyToHost(hY,Y,N,1);

	// printf("Printing Y*\n");
	// for(int i=0;i<N;i++)
	// {
	// 	printf("%f\n", hY[i]);
	// }
	printf("Printing U*\n");
	for(int i=0;i<M;i++)
	{
		printf("\t%f\n", hU[i]);
	}

	free(hQp_inv);
	free(hQp);
	free(hFp1);
	free(hFp2);
	free(hFp3);
	free(hMp1);
	free(hMp2);
	free(hMp3);
	free(hMp4);
	free(hMp5);
	free(hMp6); 
	free(hFp);
	free(hMp);
	free(hGp);
	free(hKp);
	free(hx);
	free(hD);
	free(htheta);
	free(hZ);

	cudaFree(Qp_inv);
	cudaFree(Qp);
	cudaFree(Fp1);
	cudaFree(Fp2);
	cudaFree(Fp3);
	cudaFree(Mp1);
	cudaFree(Mp2);
	cudaFree(Mp3);
	cudaFree(Mp4);
	cudaFree(Mp5);
	cudaFree(Mp6); 
	cudaFree(Fp);
	cudaFree(Mp);
	cudaFree(Gp);
	cudaFree(Kp);
	cudaFree(x);
	cudaFree(D);
	cudaFree(theta);
	cudaFree(Z);
	
	cudaFree(Qd);
	cudaFree(Fd);
	cudaFree(Md);
	cudaFree(Y);
	cudaFree(U);
}

	.file	"tmpxft_0038e1e2_00000000-6_PQP_GPU_optimized_coarsened.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2065:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2228:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2228:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z9newMatrixii
	.type	_Z9newMatrixii, @function
_Z9newMatrixii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	imull	%esi, %ebx
	movslq	%ebx, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	xorl	%edx, %edx
.L4:
	cmpl	%edx, %ebx
	jle	.L8
	movl	$0x00000000, (%rax,%rdx,4)
	incq	%rdx
	jmp	.L4
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z9newMatrixii, .-_Z9newMatrixii
	.globl	_Z12copyToDevicePfS_ii
	.type	_Z12copyToDevicePfS_ii, @function
_Z12copyToDevicePfS_ii:
.LFB2030:
	.cfi_startproc
	endbr64
	imull	%ecx, %edx
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z12copyToDevicePfS_ii, .-_Z12copyToDevicePfS_ii
	.globl	_Z10copyToHostPfS_ii
	.type	_Z10copyToHostPfS_ii, @function
_Z10copyToHostPfS_ii:
.LFB2031:
	.cfi_startproc
	endbr64
	imull	%ecx, %edx
	movl	$2, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z10copyToHostPfS_ii, .-_Z10copyToHostPfS_ii
	.globl	_Z12Gauss_JordanPfS_i
	.type	_Z12Gauss_JordanPfS_i, @function
_Z12Gauss_JordanPfS_i:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	movl	%edx, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leal	(%rdx,%rdx), %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%rsi, 8(%rsp)
	movl	%ebp, %esi
	call	_Z9newMatrixii
	movslq	%ebx, %r8
	xorl	%edx, %edx
	movq	%rax, %rdi
	leaq	0(,%r8,8), %r11
	movq	%rax, %r9
	movq	%rax, %rcx
.L12:
	cmpl	%ebx, %edx
	jge	.L47
	xorl	%eax, %eax
	leal	(%rdx,%rbx), %esi
.L14:
	xorps	%xmm0, %xmm0
	cmpl	%eax, %esi
	jne	.L13
	movss	.LC1(%rip), %xmm0
.L13:
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	cmpl	%eax, %ebp
	jg	.L14
	incl	%edx
	addq	%r11, %rcx
	jmp	.L12
.L47:
	leaq	0(,%r8,4), %rsi
	movq	%rdi, %rcx
	xorl	%edx, %edx
.L15:
	cmpl	%ebx, %edx
	jge	.L48
	xorl	%eax, %eax
.L16:
	movss	(%r12,%rax,4), %xmm0
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	cmpl	%eax, %ebx
	jg	.L16
	incl	%edx
	addq	%rsi, %r12
	addq	%r11, %rcx
	jmp	.L15
.L48:
	leal	-1(%rbx), %ecx
	movl	%ebx, %eax
	imull	%ecx, %eax
	movl	%eax, %r12d
	movslq	%eax, %rdx
	addl	%eax, %eax
	subl	%ebx, %r12d
	leaq	(%rdi,%rdx,8), %rsi
	cltq
	movslq	%r12d, %rdx
	addl	%r12d, %r12d
	leaq	(%rdi,%rax,4), %r13
	leaq	(%rdi,%rdx,8), %r10
	movl	%ebp, %edx
	movslq	%r12d, %r12
	negl	%edx
	leaq	(%rdi,%r12,4), %r12
	movslq	%edx, %rdx
	salq	$2, %rdx
.L17:
	testl	%ecx, %ecx
	jle	.L49
	movss	0(%r13), %xmm0
	decl	%ecx
	comiss	(%r12), %xmm0
	ja	.L39
.L20:
	subq	%r11, %rsi
	subq	%r11, %r10
	addq	%rdx, %r12
	addq	%rdx, %r13
	jmp	.L17
.L39:
	xorl	%eax, %eax
.L18:
	cmpl	%eax, %ebp
	jle	.L20
	movss	(%rsi,%rax,4), %xmm0
	movss	(%r10,%rax,4), %xmm1
	movss	%xmm1, (%rsi,%rax,4)
	movss	%xmm0, (%r10,%rax,4)
	incq	%rax
	jmp	.L18
.L49:
	leal	1(%rbp), %r13d
	xorl	%r11d, %r11d
	xorl	%r10d, %r10d
	xorl	%edx, %edx
.L22:
	cmpl	%ebx, %edx
	jge	.L50
	movslq	%r11d, %rax
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	leaq	(%rdi,%rax,4), %r14
	movslq	%r10d, %rax
	leaq	(%rdi,%rax,4), %r15
.L24:
	cmpl	%ecx, %edx
	jne	.L23
.L27:
	incl	%ecx
	addl	%ebx, %esi
	cmpl	%ecx, %ebx
	jne	.L24
	incl	%edx
	addl	%ebp, %r10d
	addl	%r13d, %r11d
	jmp	.L22
.L23:
	leal	(%rdx,%rsi,2), %eax
	cltq
	movss	(%rdi,%rax,4), %xmm1
	movslq	%esi, %rax
	divss	(%r14), %xmm1
	leaq	(%rdi,%rax,8), %r12
	xorl	%eax, %eax
.L26:
	movss	(%r15,%rax,4), %xmm2
	movss	(%r12,%rax,4), %xmm0
	mulss	%xmm1, %xmm2
	subss	%xmm2, %xmm0
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpl	%eax, %ebp
	jg	.L26
	jmp	.L27
.L50:
	movslq	%ebp, %rax
	movq	%rdi, %rcx
	xorl	%edx, %edx
	leaq	0(,%rax,4), %r10
	leaq	4(,%rax,4), %r11
.L29:
	cmpl	%ebx, %edx
	jge	.L51
	movss	(%rcx), %xmm1
	movq	%r9, %rax
	xorl	%esi, %esi
.L30:
	movss	(%rax), %xmm0
	incl	%esi
	addq	$4, %rax
	divss	%xmm1, %xmm0
	movss	%xmm0, -4(%rax)
	cmpl	%esi, %ebp
	jg	.L30
	incl	%edx
	addq	%r10, %r9
	addq	%r11, %rcx
	jmp	.L29
.L51:
	xorl	%edx, %edx
	xorl	%esi, %esi
.L32:
	cmpl	%ebx, %esi
	jge	.L34
	movq	8(%rsp), %rcx
	movslq	%edx, %rax
	leaq	(%rcx,%rax,4), %rcx
	leal	(%rdx,%rdx), %eax
	cltq
	leaq	(%rdi,%rax,4), %r9
	movq	%r8, %rax
.L35:
	cmpl	%eax, %ebp
	jle	.L52
	movss	(%r9,%rax,4), %xmm0
	addq	$4, %rcx
	incq	%rax
	movss	%xmm0, -4(%rcx)
	jmp	.L35
.L52:
	incl	%esi
	addl	%ebx, %edx
	jmp	.L32
.L34:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2042:
	.size	_Z12Gauss_JordanPfS_i, .-_Z12Gauss_JordanPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"r"
.LC3:
	.string	"./example/Qp_inv.txt"
.LC4:
	.string	"%f"
.LC5:
	.string	"./example/Fp1.txt"
.LC6:
	.string	"./example/Fp2.txt"
.LC7:
	.string	"./example/Fp3.txt"
.LC8:
	.string	"./example/Mp1.txt"
.LC9:
	.string	"./example/Mp2.txt"
.LC10:
	.string	"./example/Mp3.txt"
.LC11:
	.string	"./example/Mp4.txt"
.LC12:
	.string	"./example/Mp5.txt"
.LC13:
	.string	"./example/Mp6.txt"
.LC14:
	.string	"./example/Gp.txt"
.LC15:
	.string	"./example/Kp.txt"
.LC16:
	.string	"./example/Z.txt"
.LC17:
	.string	"./example/Theta.txt"
.LC18:
	.string	"./example/D.txt"
.LC19:
	.string	"./example/x.txt"
	.text
	.globl	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	leaq	.LC3(%rip), %rdi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	leaq	.LC2(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%r9, (%rsp)
	movq	%rax, 8(%rsp)
	movq	200(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	208(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	216(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	224(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	232(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	240(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	248(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	256(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	264(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	xorl	%ecx, %ecx
	movq	%rax, %rdi
.L54:
	leaq	(%r14,%rcx,4), %r9
	movl	$7, %r15d
.L55:
	xorl	%eax, %eax
	leaq	116(%rsp), %rdx
	movq	%rcx, 104(%rsp)
	leaq	.LC4(%rip), %rsi
	movq	%r9, 96(%rsp)
	movq	%rdi, 88(%rsp)
	call	__isoc23_fscanf@PLT
	movq	96(%rsp), %r9
	movss	116(%rsp), %xmm0
	movq	88(%rsp), %rdi
	movq	104(%rsp), %rcx
	movss	%xmm0, (%r9)
	addq	$28, %r9
	decl	%r15d
	jne	.L55
	incq	%rcx
	cmpq	$7, %rcx
	jne	.L54
	call	fclose@PLT
	leaq	.LC2(%rip), %rsi
	leaq	.LC5(%rip), %rdi
	xorl	%r14d, %r14d
	call	fopen@PLT
	movq	%rax, %r15
.L57:
	leaq	116(%rsp), %rdx
	leaq	.LC4(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movss	%xmm0, 0(%r13,%r14,4)
	incq	%r14
	cmpq	$7, %r14
	jne	.L57
	movq	%r15, %rdi
	xorl	%r15d, %r15d
	call	fclose@PLT
	leaq	.LC6(%rip), %rdi
	leaq	.LC2(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rdi
.L58:
	leaq	(%r12,%r15,4), %r14
	movl	$7, %r13d
.L59:
	xorl	%eax, %eax
	leaq	116(%rsp), %rdx
	movq	%rdi, 88(%rsp)
	addq	$116, %r14
	leaq	.LC4(%rip), %rsi
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	88(%rsp), %rdi
	movss	%xmm0, -116(%r14)
	decl	%r13d
	jne	.L59
	incq	%r15
	cmpq	$29, %r15
	jne	.L58
	call	fclose@PLT
	leaq	.LC2(%rip), %rsi
	xorl	%r14d, %r14d
	leaq	.LC7(%rip), %rdi
	call	fopen@PLT
	leaq	.LC4(%rip), %r12
	movq	%rax, %r13
.L61:
	leaq	116(%rsp), %rdx
	movq	%r12, %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movss	%xmm0, 0(%rbp,%r14,4)
	incq	%r14
	cmpq	$7, %r14
	jne	.L61
	movq	%r13, %rdi
	leaq	.LC4(%rip), %rbp
	xorl	%r13d, %r13d
	call	fclose@PLT
	leaq	.LC2(%rip), %rsi
	leaq	.LC8(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L62:
	leaq	(%rbx,%r13,4), %r15
	movl	$29, %r14d
.L63:
	leaq	116(%rsp), %rdx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	addq	$116, %r15
	movss	%xmm0, -116(%r15)
	decl	%r14d
	jne	.L63
	incq	%r13
	cmpq	$29, %r13
	jne	.L62
	movq	%r12, %rdi
	xorl	%r13d, %r13d
	leaq	.LC4(%rip), %rbx
	call	fclose@PLT
	leaq	.LC2(%rip), %rsi
	leaq	.LC9(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L65:
	leaq	116(%rsp), %rbp
	movq	%rbx, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	movq	%rbp, %rdx
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	(%rsp), %rax
	movss	%xmm0, (%rax,%r13,4)
	incq	%r13
	cmpq	$29, %r13
	jne	.L65
	movq	%r12, %rdi
	leaq	.LC2(%rip), %r12
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC10(%rip), %rdi
	call	fopen@PLT
	movq	%rbx, %rsi
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rbx
	movq	%rax, %r13
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	8(%rsp), %rax
	movq	%r13, %rdi
	xorl	%r13d, %r13d
	movss	%xmm0, (%rax)
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC11(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L66:
	leaq	116(%rsp), %rbp
	movq	%rbx, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	movq	%rbp, %rdx
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	16(%rsp), %rax
	movss	%xmm0, (%rax,%r13,4)
	incq	%r13
	cmpq	$29, %r13
	jne	.L66
	movq	%r12, %rdi
	leaq	.LC2(%rip), %r12
	xorl	%r14d, %r14d
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC12(%rip), %rdi
	call	fopen@PLT
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movq	%rax, %r13
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	24(%rsp), %rax
	movq	%r13, %rdi
	movss	%xmm0, (%rax)
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC13(%rip), %rdi
	call	fopen@PLT
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movq	%rax, %r13
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	32(%rsp), %rax
	movq	%r13, %rdi
	movss	%xmm0, (%rax)
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC14(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r13
.L67:
	movq	40(%rsp), %rax
	movl	$28, %r15d
	leaq	(%rax,%r14,4), %rbx
.L68:
	leaq	116(%rsp), %rbp
	movq	%r13, %rdi
	xorl	%eax, %eax
	addq	$28, %rbx
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movss	%xmm0, -28(%rbx)
	decl	%r15d
	jne	.L68
	incq	%r14
	cmpq	$7, %r14
	jne	.L67
	movq	%r13, %rdi
	xorl	%r14d, %r14d
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC15(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r13
.L70:
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	48(%rsp), %rax
	movss	%xmm0, (%rax,%r14,4)
	incq	%r14
	cmpq	$28, %r14
	jne	.L70
	movq	%r13, %rdi
	xorl	%r14d, %r14d
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC16(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r13
.L71:
	movq	80(%rsp), %rax
	xorl	%r15d, %r15d
	leaq	(%rax,%r14,4), %rbx
.L72:
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	incl	%r15d
	addq	$116, %rbx
	movss	%xmm0, -116(%rbx)
	cmpl	$7, %r15d
	jne	.L72
	incq	%r14
	cmpq	$29, %r14
	jne	.L71
	movq	%r13, %rdi
	xorl	%r14d, %r14d
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC17(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r13
.L74:
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	72(%rsp), %rax
	movss	%xmm0, (%rax,%r14,4)
	incq	%r14
	cmpq	$7, %r14
	jne	.L74
	movq	%r13, %rdi
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC18(%rip), %rdi
	call	fopen@PLT
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	movq	%rax, %r13
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	64(%rsp), %rax
	movq	%r13, %rdi
	xorl	%r13d, %r13d
	movss	%xmm0, (%rax)
	call	fclose@PLT
	movq	%r12, %rsi
	leaq	.LC19(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L75:
	movq	%rbp, %rdx
	leaq	.LC4(%rip), %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movss	116(%rsp), %xmm0
	movq	56(%rsp), %rax
	movss	%xmm0, (%rax,%r13,4)
	incq	%r13
	cmpq	$29, %r13
	jne	.L75
	movq	%r12, %rdi
	call	fclose@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.globl	_Z29__device_stub__Z8printMatPfiiPfii
	.type	_Z29__device_stub__Z8printMatPfiiPfii, @function
_Z29__device_stub__Z8printMatPfiiPfii:
.LFB2087:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z8printMatPfii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L90:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2087:
	.size	_Z29__device_stub__Z8printMatPfiiPfii, .-_Z29__device_stub__Z8printMatPfiiPfii
	.globl	_Z8printMatPfii
	.type	_Z8printMatPfii, @function
_Z8printMatPfii:
.LFB2088:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8printMatPfiiPfii
	.cfi_endproc
.LFE2088:
	.size	_Z8printMatPfii, .-_Z8printMatPfii
	.globl	_Z33__device_stub__Z11initMatCudaPffiPffi
	.type	_Z33__device_stub__Z11initMatCudaPffiPffi, @function
_Z33__device_stub__Z11initMatCudaPffiPffi:
.LFB2089:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L95
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z11initMatCudaPffi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L95:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L97
	call	__stack_chk_fail@PLT
.L97:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2089:
	.size	_Z33__device_stub__Z11initMatCudaPffiPffi, .-_Z33__device_stub__Z11initMatCudaPffiPffi
	.globl	_Z11initMatCudaPffi
	.type	_Z11initMatCudaPffi, @function
_Z11initMatCudaPffi:
.LFB2090:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z11initMatCudaPffiPffi
	.cfi_endproc
.LFE2090:
	.size	_Z11initMatCudaPffi, .-_Z11initMatCudaPffi
	.globl	_Z7initMatPffi
	.type	_Z7initMatPffi, @function
_Z7initMatPffi:
.LFB2027:
	.cfi_startproc
	endbr64
	leal	1023(%rsi), %eax
	movl	$1024, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	xorl	%r9d, %r9d
	idivl	%ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movl	$8388609, %edx
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$9, %rdx
	movss	%xmm0, 12(%rsp)
	movl	%eax, 36(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L100
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z33__device_stub__Z11initMatCudaPffiPffi
.L100:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7initMatPffi, .-_Z7initMatPffi
	.section	.rodata.str1.1
.LC20:
	.string	" Failed to allocate device matrix! %s\n"
	.text
	.globl	_Z13newMatrixCUDAii
	.type	_Z13newMatrixCUDAii, @function
_Z13newMatrixCUDAii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	xorl	%r9d, %r9d
	imull	%esi, %ebx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movslq	%ebx, %rsi
	movq	%rsp, %rdi
	movq	%r9, (%rsp)
	salq	$2, %rsi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L104
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC20(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L104:
	movq	(%rsp), %rdi
	movl	%ebx, %esi
	xorps	%xmm0, %xmm0
	call	_Z7initMatPffi
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L105
	call	__stack_chk_fail@PLT
.L105:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z13newMatrixCUDAii, .-_Z13newMatrixCUDAii
	.globl	_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii
	.type	_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii, @function
_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii:
.LFB2091:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L107
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14copyMatrixCudaPfS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L107:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L109
	call	__stack_chk_fail@PLT
.L109:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2091:
	.size	_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii, .-_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii
	.globl	_Z14copyMatrixCudaPfS_ii
	.type	_Z14copyMatrixCudaPfS_ii, @function
_Z14copyMatrixCudaPfS_ii:
.LFB2092:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii
	.cfi_endproc
.LFE2092:
	.size	_Z14copyMatrixCudaPfS_ii, .-_Z14copyMatrixCudaPfS_ii
	.globl	_Z10copyMatrixPfS_ii
	.type	_Z10copyMatrixPfS_ii, @function
_Z10copyMatrixPfS_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	xorl	%r9d, %r9d
	imull	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1024, %ecx
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	addl	$1023, %eax
	cltd
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L112
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__Z14copyMatrixCudaPfS_iiPfS_ii
.L112:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z10copyMatrixPfS_ii, .-_Z10copyMatrixPfS_ii
	.globl	_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii
	.type	_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii, @function
_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii:
.LFB2093:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L115
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13transposeCudaPfS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L115:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L117
	call	__stack_chk_fail@PLT
.L117:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2093:
	.size	_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii, .-_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii
	.globl	_Z13transposeCudaPfS_ii
	.type	_Z13transposeCudaPfS_ii, @function
_Z13transposeCudaPfS_ii:
.LFB2094:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii
	.cfi_endproc
.LFE2094:
	.size	_Z13transposeCudaPfS_ii, .-_Z13transposeCudaPfS_ii
	.globl	_Z9transposePfS_ii
	.type	_Z9transposePfS_ii, @function
_Z9transposePfS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	leal	31(%rdx), %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r9d, %r9d
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	xorl	%r8d, %r8d
	movl	$1, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%ecx, %ebp
	movl	$32, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	cltd
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	%eax, 8(%rsp)
	leal	31(%rbp), %eax
	cltd
	idivl	%ecx
	movabsq	$137438953504, %rdx
	movl	$1, %ecx
	movl	%eax, 12(%rsp)
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L120
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r13, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%r12, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z37__device_stub__Z13transposeCudaPfS_iiPfS_ii
.L120:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z9transposePfS_ii, .-_Z9transposePfS_ii
	.globl	_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii
	.type	_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii, @function
_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii:
.LFB2095:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L123
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18matrixMultiplyCudaPfS_S_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L123:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L125
	call	__stack_chk_fail@PLT
.L125:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2095:
	.size	_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii, .-_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii
	.globl	_Z18matrixMultiplyCudaPfS_S_iii
	.type	_Z18matrixMultiplyCudaPfS_S_iii, @function
_Z18matrixMultiplyCudaPfS_S_iii:
.LFB2096:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE2096:
	.size	_Z18matrixMultiplyCudaPfS_S_iii, .-_Z18matrixMultiplyCudaPfS_S_iii
	.globl	_Z14matrixMultiplyPfS_iS_iiii
	.type	_Z14matrixMultiplyPfS_iS_iiii, @function
_Z14matrixMultiplyPfS_iS_iiii:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	136(%rsp), %r14d
	movl	128(%rsp), %eax
	movq	%rdi, 16(%rsp)
	movl	%r9d, %edi
	movq	%rsi, (%rsp)
	movl	%r14d, %esi
	movl	%eax, 24(%rsp)
	call	_Z13newMatrixCUDAii
	cmpl	$1, %ebx
	setne	%r15b
	cmpl	$1, 24(%rsp)
	movq	%rax, 8(%rsp)
	setne	%r8b
	testl	%r12d, %r12d
	movq	(%rsp), %r12
	setne	%al
	andl	%r8d, %eax
	andb	%r15b, %al
	movb	%al, 30(%rsp)
	je	.L129
	movl	24(%rsp), %esi
	movl	%ebx, %edi
	movb	%r8b, 31(%rsp)
	call	_Z13newMatrixCUDAii
	movl	24(%rsp), %edx
	movq	(%rsp), %rsi
	movl	%ebx, %ecx
	movq	%rax, %rdi
	movq	%rax, %r12
	call	_Z9transposePfS_ii
	movb	31(%rsp), %r8b
.L129:
	cmpl	$1, %r14d
	setne	%r9b
	testl	%ebp, %ebp
	setne	%bpl
	andl	%r8d, %ebp
	andb	%r9b, %bpl
	je	.L130
	movl	24(%rsp), %edi
	movl	%r14d, %esi
	movb	%r9b, 31(%rsp)
	call	_Z13newMatrixCUDAii
	movl	24(%rsp), %ecx
	movq	(%rsp), %rsi
	movl	%r14d, %edx
	movq	%rax, %rdi
	movq	%rax, %r13
	call	_Z9transposePfS_ii
	movb	31(%rsp), %r9b
.L130:
	testb	%r15b, %r15b
	je	.L136
	movl	$32, %ecx
	testb	%r9b, %r9b
	jne	.L131
.L136:
	movl	$1, %ecx
.L131:
	leal	-1(%rcx,%r14), %eax
	movl	%ecx, 40(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	movl	%ecx, 44(%rsp)
	movl	$1, %esi
	idivl	%ecx
	movl	%eax, 52(%rsp)
	leal	-1(%rcx,%rbx), %eax
	cltd
	idivl	%ecx
	movq	40(%rsp), %rdx
	movl	$1, %ecx
	movl	%eax, 56(%rsp)
	movq	52(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L132
	movl	24(%rsp), %r8d
	movq	16(%rsp), %rdi
	movl	%r14d, %r9d
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%r12, %rsi
	call	_Z45__device_stub__Z18matrixMultiplyCudaPfS_S_iiiPfS_S_iii
.L132:
	cmpb	$0, 30(%rsp)
	je	.L133
	movq	%r12, %rdi
	call	cudaFree@PLT
.L133:
	testb	%bpl, %bpl
	je	.L134
	movq	%r13, %rdi
	call	cudaFree@PLT
.L134:
	movq	8(%rsp), %rdi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2034:
	.size	_Z14matrixMultiplyPfS_iS_iiii, .-_Z14matrixMultiplyPfS_iS_iiii
	.globl	_Z9computeQdPfS_S_ii
	.type	_Z9computeQdPfS_S_ii, @function
_Z9computeQdPfS_S_ii:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	%ecx, %r9d
	pushq	%rcx
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%edx, %edx
	pushq	%r8
	.cfi_def_cfa_offset 32
	movl	$1, %r8d
	call	_Z14matrixMultiplyPfS_iS_iiii
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z9computeQdPfS_S_ii, .-_Z9computeQdPfS_S_ii
	.globl	_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii
	.type	_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii, @function
_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii:
.LFB2097:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L156
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z13matrixAddCudaPfS_fii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L156:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L158
	call	__stack_chk_fail@PLT
.L158:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2097:
	.size	_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii, .-_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii
	.globl	_Z13matrixAddCudaPfS_fii
	.type	_Z13matrixAddCudaPfS_fii, @function
_Z13matrixAddCudaPfS_fii:
.LFB2098:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii
	.cfi_endproc
.LFE2098:
	.size	_Z13matrixAddCudaPfS_fii, .-_Z13matrixAddCudaPfS_fii
	.globl	_Z9matrixAddPfS_fii
	.type	_Z9matrixAddPfS_fii, @function
_Z9matrixAddPfS_fii:
.LFB2035:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	xorl	%r9d, %r9d
	imull	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1024, %ecx
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	addl	$1023, %eax
	cltd
	idivl	%ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	movss	%xmm0, 12(%rsp)
	movl	%eax, 36(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L161
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__Z13matrixAddCudaPfS_fiiPfS_fii
.L161:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z9matrixAddPfS_fii, .-_Z9matrixAddPfS_fii
	.globl	_Z9computeFpPfS_S_S_S_S_
	.type	_Z9computeFpPfS_S_S_S_S_, @function
_Z9computeFpPfS_S_S_S_S_:
.LFB2044:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%r9, %r14
	movl	$7, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	xorl	%edx, %edx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rcx, %r12
	movq	%r8, %rcx
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	pushq	$1
	.cfi_def_cfa_offset 56
	pushq	$1
	.cfi_def_cfa_offset 64
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 56
	movl	$1, %esi
	popq	%rdx
	.cfi_def_cfa_offset 48
	movl	$7, %edi
	call	_Z13newMatrixCUDAii
	pushq	$1
	.cfi_def_cfa_offset 56
	movl	$7, %r9d
	xorl	%r8d, %r8d
	pushq	$29
	.cfi_def_cfa_offset 64
	movq	%rax, %rdi
	movq	%r14, %rcx
	movq	%r13, %rsi
	xorl	%edx, %edx
	movq	%rax, %rbx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rcx
	.cfi_def_cfa_offset 56
	movq	%rbp, %rdi
	popq	%rsi
	.cfi_def_cfa_offset 48
	movss	.LC1(%rip), %xmm0
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$7, %edx
	call	_Z9matrixAddPfS_fii
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movss	.LC21(%rip), %xmm0
	movl	$7, %edx
	call	_Z9matrixAddPfS_fii
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2044:
	.size	_Z9computeFpPfS_S_S_S_S_, .-_Z9computeFpPfS_S_S_S_S_
	.globl	_Z9computeMpPfS_S_S_S_S_S_S_S_
	.type	_Z9computeMpPfS_S_S_S_S_S_S_S_, @function
_Z9computeMpPfS_S_S_S_S_S_S_S_:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorps	%xmm0, %xmm0
	movq	%rsi, %r15
	movl	$1, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	96(%rsp), %rax
	movq	112(%rsp), %rbp
	movq	%r9, 16(%rsp)
	movq	%rdi, (%rsp)
	movq	%rax, 24(%rsp)
	movq	104(%rsp), %rax
	movq	%rax, 8(%rsp)
	call	_Z7initMatPffi
	movl	$29, %esi
	movl	$1, %edi
	call	_Z13newMatrixCUDAii
	pushq	$29
	.cfi_def_cfa_offset 104
	movq	%r15, %rcx
	movq	%rbp, %rsi
	pushq	$29
	.cfi_def_cfa_offset 112
	movq	%rax, %rdi
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movl	$1, %edx
	movq	%rax, %rbx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
	pushq	$1
	.cfi_def_cfa_offset 104
	pushq	$29
	.cfi_def_cfa_offset 112
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rcx
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rcx
	.cfi_def_cfa_offset 104
	popq	%rsi
	.cfi_def_cfa_offset 96
	movl	$1, %ecx
	movq	(%rsp), %rdi
	movss	.LC22(%rip), %xmm0
	movq	%rbx, %rsi
	movl	$1, %edx
	call	_Z9matrixAddPfS_fii
	pushq	$29
	.cfi_def_cfa_offset 104
	movq	%r14, %rcx
	movq	%rbx, %rdi
	pushq	$1
	.cfi_def_cfa_offset 112
	movq	24(%rsp), %rsi
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movl	$1, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rdi
	.cfi_def_cfa_offset 104
	popq	%r8
	.cfi_def_cfa_offset 96
	pushq	$1
	.cfi_def_cfa_offset 104
	pushq	$29
	.cfi_def_cfa_offset 112
	xorl	%r8d, %r8d
	movq	%rbp, %rcx
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	movl	$1, %r9d
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%r9
	.cfi_def_cfa_offset 104
	popq	%r10
	.cfi_def_cfa_offset 96
	movq	%rbx, %rsi
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$1, %edx
	movss	.LC22(%rip), %xmm0
	call	_Z9matrixAddPfS_fii
	pushq	$1
	.cfi_def_cfa_offset 104
	movl	$1, %r9d
	xorl	%r8d, %r8d
	pushq	$29
	.cfi_def_cfa_offset 112
	movq	%rbp, %rcx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%r11
	.cfi_def_cfa_offset 104
	popq	%rbp
	.cfi_def_cfa_offset 96
	movl	$1, %ecx
	movq	(%rsp), %rdi
	movss	.LC22(%rip), %xmm0
	movl	$1, %edx
	movq	%rbx, %rsi
	call	_Z9matrixAddPfS_fii
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movl	$1, %esi
	movl	$1, %edi
	call	_Z13newMatrixCUDAii
	pushq	$1
	.cfi_def_cfa_offset 104
	movq	%r12, %rcx
	movl	$1, %r9d
	pushq	$1
	.cfi_def_cfa_offset 112
	movq	24(%rsp), %rsi
	movq	%rax, %rdi
	xorl	%r8d, %r8d
	movl	$1, %edx
	movq	%rax, %rbx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%r12
	.cfi_def_cfa_offset 104
	popq	%r13
	.cfi_def_cfa_offset 96
	pushq	$1
	.cfi_def_cfa_offset 104
	pushq	$1
	.cfi_def_cfa_offset 112
	movq	24(%rsp), %rcx
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%r14
	.cfi_def_cfa_offset 104
	popq	%r15
	.cfi_def_cfa_offset 96
	movq	%rbx, %rsi
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$1, %edx
	movss	.LC22(%rip), %xmm0
	call	_Z9matrixAddPfS_fii
	pushq	$1
	.cfi_def_cfa_offset 104
	movl	$1, %r9d
	xorl	%r8d, %r8d
	pushq	$1
	.cfi_def_cfa_offset 112
	movq	24(%rsp), %rcx
	movq	%rbx, %rdi
	movl	$1, %edx
	movq	32(%rsp), %rsi
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
	movq	%rbx, %rsi
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$1, %edx
	movss	.LC22(%rip), %xmm0
	call	_Z9matrixAddPfS_fii
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movss	.LC22(%rip), %xmm0
	movl	$1, %edx
	call	_Z9matrixAddPfS_fii
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2045:
	.size	_Z9computeMpPfS_S_S_S_S_S_S_S_, .-_Z9computeMpPfS_S_S_S_S_S_S_S_
	.globl	_Z9computeFdPfS_S_S_ii
	.type	_Z9computeFdPfS_S_S_ii, @function
_Z9computeFdPfS_S_S_ii:
.LFB2047:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rcx, %r12
	movq	%rdx, %rcx
	xorl	%edx, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%r8d, %ebp
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	pushq	$1
	.cfi_def_cfa_offset 56
	pushq	%r9
	.cfi_def_cfa_offset 64
	movl	%r8d, %r9d
	xorl	%r8d, %r8d
	movq	%rdi, 24(%rsp)
	call	_Z14matrixMultiplyPfS_iS_iiii
	movq	24(%rsp), %rdi
	movl	%ebp, %edx
	movq	%r12, %rsi
	movss	.LC1(%rip), %xmm0
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	movl	$1, %ecx
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii
	.cfi_endproc
.LFE2047:
	.size	_Z9computeFdPfS_S_S_ii, .-_Z9computeFdPfS_S_S_ii
	.globl	_Z9computeMdPfS_S_S_ii
	.type	_Z9computeMdPfS_S_S_ii, @function
_Z9computeMdPfS_S_S_ii:
.LFB2048:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	movl	%r9d, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	movl	$1, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 64
	call	_Z13newMatrixCUDAii
	pushq	%rbx
	.cfi_def_cfa_offset 72
	movq	%r14, %rcx
	movq	%r12, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 80
	movq	%rax, %rdi
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movl	$1, %edx
	movq	%rax, %r15
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rdx
	.cfi_def_cfa_offset 72
	popq	%rcx
	.cfi_def_cfa_offset 64
	pushq	$1
	.cfi_def_cfa_offset 72
	pushq	%rbx
	.cfi_def_cfa_offset 80
	xorl	%r8d, %r8d
	movq	%r12, %rcx
	movq	%r15, %rsi
	movq	%rbp, %rdi
	movl	$1, %r9d
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rsi
	.cfi_def_cfa_offset 72
	movl	$1, %ecx
	popq	%rdi
	.cfi_def_cfa_offset 64
	movss	.LC21(%rip), %xmm0
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	call	_Z9matrixAddPfS_fii
	popq	%r8
	.cfi_def_cfa_offset 56
	movq	%r15, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2048:
	.size	_Z9computeMdPfS_S_S_ii, .-_Z9computeMdPfS_S_S_ii
	.globl	_Z13convertToDualPfS_S_S_S_S_S_S_ii
	.type	_Z13convertToDualPfS_S_S_S_S_S_S_ii, @function
_Z13convertToDualPfS_S_S_S_S_S_S_ii:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	112(%rsp), %rax
	movl	128(%rsp), %ebp
	movq	%rdx, 32(%rsp)
	movl	136(%rsp), %ebx
	movq	%rcx, 16(%rsp)
	movq	%rax, 24(%rsp)
	movq	120(%rsp), %rax
	movl	%ebp, %edi
	movl	%ebx, %esi
	movq	%rax, 40(%rsp)
	call	_Z13newMatrixCUDAii
	movl	%ebp, %r9d
	movq	%r12, %rsi
	xorl	%r8d, %r8d
	movq	%rax, 8(%rsp)
	xorl	%edx, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 120
	pushq	%rbx
	.cfi_def_cfa_offset 128
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdi
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
	movl	%ebx, %r8d
	movq	8(%rsp), %rsi
	movl	%ebp, %ecx
	movq	%r12, %rdx
	movq	%r15, %rdi
	call	_Z9computeQdPfS_S_ii
	movq	24(%rsp), %rdx
	movl	%ebx, %r9d
	movl	%ebp, %r8d
	movq	8(%rsp), %rsi
	movq	%r14, %rcx
	movq	%r13, %rdi
	call	_Z9computeFdPfS_S_S_ii
	movq	32(%rsp), %rdi
	movl	%ebx, %r9d
	movl	%ebp, %r8d
	movq	40(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	24(%rsp), %rsi
	call	_Z9computeMdPfS_S_S_ii
	movq	8(%rsp), %rdi
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2049:
	.size	_Z13convertToDualPfS_S_S_S_S_S_S_ii, .-_Z13convertToDualPfS_S_S_S_S_S_S_ii
	.globl	_Z13computealphaYPfS_S_S_S_i
	.type	_Z13computealphaYPfS_S_S_S_i, @function
_Z13computealphaYPfS_S_S_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	movl	$1, %edi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%rsi, (%rsp)
	movl	%r9d, %esi
	movq	%r8, 8(%rsp)
	call	_Z13newMatrixCUDAii
	pushq	%rbx
	.cfi_def_cfa_offset 88
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rsi
	movq	%rax, %rdi
	movq	%r13, %rcx
	movl	$1, %edx
	movq	%rax, %rbp
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rdi
	.cfi_def_cfa_offset 88
	popq	%r8
	.cfi_def_cfa_offset 80
	pushq	$1
	.cfi_def_cfa_offset 88
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rcx
	movl	$1, %r9d
	xorl	%r8d, %r8d
	xorl	%edx, %edx
	movq	%rbp, %rsi
	movq	%rbp, %rdi
	call	_Z14matrixMultiplyPfS_iS_iiii
	movss	0(%rbp), %xmm1
	xorps	%xmm0, %xmm0
	popq	%r9
	.cfi_def_cfa_offset 88
	popq	%r10
	.cfi_def_cfa_offset 80
	comiss	%xmm0, %xmm1
	jbe	.L175
	movl	%ebx, %esi
	movl	$1, %edi
	call	_Z13newMatrixCUDAii
	pushq	%rbx
	.cfi_def_cfa_offset 88
	movl	$1, %r9d
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movq	%rax, %rdi
	movq	%r13, %rcx
	movl	$1, %edx
	movq	%r15, %rsi
	movq	%rax, %r12
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 88
	movss	.LC1(%rip), %xmm0
	movl	%ebx, %ecx
	popq	%rdx
	.cfi_def_cfa_offset 80
	movq	8(%rsp), %rsi
	movl	$1, %edx
	movq	%r12, %rdi
	call	_Z9matrixAddPfS_fii
	pushq	$1
	.cfi_def_cfa_offset 88
	movq	%r12, %rsi
	movq	%r12, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rcx
	movl	$1, %r9d
	xorl	%r8d, %r8d
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	movss	(%r12), %xmm0
	movq	%r12, %rdi
	xorps	.LC23(%rip), %xmm0
	divss	0(%rbp), %xmm0
	movss	%xmm0, (%r14)
	popq	%rcx
	.cfi_def_cfa_offset 88
	popq	%rsi
	.cfi_def_cfa_offset 80
	call	cudaFree@PLT
.L175:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2053:
	.size	_Z13computealphaYPfS_S_S_S_i, .-_Z13computealphaYPfS_S_S_S_i
	.globl	_Z8updateY1PfS_fS_i
	.type	_Z8updateY1PfS_fS_i, @function
_Z8updateY1PfS_fS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%ecx, %ebp
	movl	$1, %ecx
	movl	%ebp, %edx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, (%rsp)
	movss	%xmm0, 12(%rsp)
	call	_Z10copyMatrixPfS_ii
	movss	12(%rsp), %xmm0
	movl	%ebp, %edx
	movq	%r12, %rsi
	movq	(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	movl	$1, %ecx
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii
	.cfi_endproc
.LFE2054:
	.size	_Z8updateY1PfS_fS_i, .-_Z8updateY1PfS_fS_i
	.globl	_Z11computeCostPfS_S_S_i
	.type	_Z11computeCostPfS_S_S_i, @function
_Z11computeCostPfS_S_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	movl	$1, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	movl	$1, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	_Z13newMatrixCUDAii
	movl	%ebp, %esi
	movl	$1, %edi
	movq	%rax, %rbx
	call	_Z13newMatrixCUDAii
	movq	%r15, %rcx
	movq	%r12, %rsi
	xorl	%r8d, %r8d
	movq	%rax, (%rsp)
	movl	$1, %r9d
	movl	$1, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 88
	pushq	%rbp
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rdi
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
	pushq	$1
	.cfi_def_cfa_offset 88
	pushq	%rbp
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rsi
	movl	$1, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rcx
	xorl	%edx, %edx
	movq	%rsi, %rdi
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rcx
	.cfi_def_cfa_offset 88
	popq	%rsi
	.cfi_def_cfa_offset 80
	movq	%rbx, %rdi
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movl	$1, %edx
	movss	.LC22(%rip), %xmm0
	call	_Z9matrixAddPfS_fii
	pushq	$1
	.cfi_def_cfa_offset 88
	movl	$1, %r9d
	movq	%r12, %rcx
	pushq	%rbp
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rdi
	movq	%r14, %rsi
	xorl	%r8d, %r8d
	movl	$1, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rdi
	.cfi_def_cfa_offset 88
	popq	%r8
	.cfi_def_cfa_offset 80
	movq	%rbx, %rdi
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movl	$1, %edx
	movss	.LC1(%rip), %xmm0
	call	_Z9matrixAddPfS_fii
	movl	$1, %ecx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	movss	.LC22(%rip), %xmm0
	movl	$1, %edx
	call	_Z9matrixAddPfS_fii
	movl	$1, %esi
	movl	$1, %edi
	call	_Z9newMatrixii
	movq	%rbx, %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	%rax, %rbp
	movq	%rax, %rdi
	call	cudaMemcpy@PLT
	movss	0(%rbp), %xmm0
	movq	%rbp, %rdi
	movss	%xmm0, 12(%rsp)
	call	free@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movss	12(%rsp), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z11computeCostPfS_S_S_i, .-_Z11computeCostPfS_S_S_i
	.globl	_Z38__device_stub__Z16negateMatrixCudaPfiiPfii
	.type	_Z38__device_stub__Z16negateMatrixCudaPfiiPfii, @function
_Z38__device_stub__Z16negateMatrixCudaPfiiPfii:
.LFB2099:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L183
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z16negateMatrixCudaPfii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L183:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L185
	call	__stack_chk_fail@PLT
.L185:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2099:
	.size	_Z38__device_stub__Z16negateMatrixCudaPfiiPfii, .-_Z38__device_stub__Z16negateMatrixCudaPfiiPfii
	.globl	_Z16negateMatrixCudaPfii
	.type	_Z16negateMatrixCudaPfii, @function
_Z16negateMatrixCudaPfii:
.LFB2100:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z16negateMatrixCudaPfiiPfii
	.cfi_endproc
.LFE2100:
	.size	_Z16negateMatrixCudaPfii, .-_Z16negateMatrixCudaPfii
	.globl	_Z12negateMatrixPfii
	.type	_Z12negateMatrixPfii, @function
_Z12negateMatrixPfii:
.LFB2036:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1024, %ecx
	movq	%rdi, %r12
	imull	%edx, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%edx, %ebp
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%esi, %ebx
	xorl	%r8d, %r8d
	addl	$1023, %eax
	cltd
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L188
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movl	%ebp, %edx
	movl	%ebx, %esi
	movq	%r12, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__Z16negateMatrixCudaPfiiPfii
.L188:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z12negateMatrixPfii, .-_Z12negateMatrixPfii
	.globl	_Z13computeUfromYPfS_S_S_S_ii
	.type	_Z13computeUfromYPfS_S_S_S_ii, @function
_Z13computeUfromYPfS_S_S_S_ii:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	movl	$1, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	80(%rsp), %ebx
	movl	%r9d, 12(%rsp)
	movl	%ebx, %edi
	call	_Z13newMatrixCUDAii
	xorl	%r8d, %r8d
	movq	%r15, %rcx
	movq	%r14, %rsi
	movq	%rax, (%rsp)
	movl	$1, %edx
	pushq	$1
	.cfi_def_cfa_offset 88
	movl	20(%rsp), %r9d
	pushq	%r9
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rdi
	movl	%ebx, %r9d
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
	movq	%r13, %rsi
	movq	(%rsp), %rdi
	movss	.LC1(%rip), %xmm0
	movl	%ebx, %edx
	movl	$1, %ecx
	call	_Z9matrixAddPfS_fii
	pushq	$1
	.cfi_def_cfa_offset 88
	movl	%ebx, %r9d
	movq	%r12, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rcx
	movq	%rbp, %rdi
	xorl	%r8d, %r8d
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rcx
	.cfi_def_cfa_offset 88
	movq	%rbp, %rdi
	popq	%rsi
	.cfi_def_cfa_offset 80
	movl	$1, %edx
	movl	%ebx, %esi
	call	_Z12negateMatrixPfii
	movq	(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2043:
	.size	_Z13computeUfromYPfS_S_S_S_ii, .-_Z13computeUfromYPfS_S_S_S_ii
	.globl	_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii
	.type	_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii, @function
_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii:
.LFB2101:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L193
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13matrixPosCudaPfS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L193:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L195
	call	__stack_chk_fail@PLT
.L195:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2101:
	.size	_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii, .-_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii
	.globl	_Z13matrixPosCudaPfS_ii
	.type	_Z13matrixPosCudaPfS_ii, @function
_Z13matrixPosCudaPfS_ii:
.LFB2102:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii
	.cfi_endproc
.LFE2102:
	.size	_Z13matrixPosCudaPfS_ii, .-_Z13matrixPosCudaPfS_ii
	.globl	_Z9matrixPosPfS_ii
	.type	_Z9matrixPosPfS_ii, @function
_Z9matrixPosPfS_ii:
.LFB2037:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	xorl	%r9d, %r9d
	imull	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1024, %ecx
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	addl	$1023, %eax
	cltd
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L198
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z37__device_stub__Z13matrixPosCudaPfS_iiPfS_ii
.L198:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z9matrixPosPfS_ii, .-_Z9matrixPosPfS_ii
	.globl	_Z16computeQdp_thetaPfS_S_i
	.type	_Z16computeQdp_thetaPfS_S_i, @function
_Z16computeQdp_thetaPfS_S_i:
.LFB2051:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r12
	movl	%ecx, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%ecx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 8(%rsp)
	call	_Z9matrixPosPfS_ii
	movq	8(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movss	.LC1(%rip), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii
	.cfi_endproc
.LFE2051:
	.size	_Z16computeQdp_thetaPfS_S_i, .-_Z16computeQdp_thetaPfS_S_i
	.globl	_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii
	.type	_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii, @function
_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii:
.LFB2103:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L203
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13matrixNegCudaPfS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L203:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L205
	call	__stack_chk_fail@PLT
.L205:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2103:
	.size	_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii, .-_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii
	.globl	_Z13matrixNegCudaPfS_ii
	.type	_Z13matrixNegCudaPfS_ii, @function
_Z13matrixNegCudaPfS_ii:
.LFB2104:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii
	.cfi_endproc
.LFE2104:
	.size	_Z13matrixNegCudaPfS_ii, .-_Z13matrixNegCudaPfS_ii
	.globl	_Z9matrixNegPfS_ii
	.type	_Z9matrixNegPfS_ii, @function
_Z9matrixNegPfS_ii:
.LFB2038:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	xorl	%r9d, %r9d
	imull	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1024, %ecx
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	addl	$1023, %eax
	cltd
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L208
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z37__device_stub__Z13matrixNegCudaPfS_iiPfS_ii
.L208:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z9matrixNegPfS_ii, .-_Z9matrixNegPfS_ii
	.globl	_Z16computeQdn_thetaPfS_S_i
	.type	_Z16computeQdn_thetaPfS_S_i, @function
_Z16computeQdn_thetaPfS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r12
	movl	%ecx, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%ecx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 8(%rsp)
	call	_Z9matrixNegPfS_ii
	movq	8(%rsp), %rdi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movss	.LC1(%rip), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii
	.cfi_endproc
.LFE2052:
	.size	_Z16computeQdn_thetaPfS_S_i, .-_Z16computeQdn_thetaPfS_S_i
	.globl	_Z9computephPfS_S_S_i
	.type	_Z9computephPfS_S_S_i, @function
_Z9computephPfS_S_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%r8d, %ebp
	movq	%rdx, %rcx
	movl	%r8d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%edx, %edx
	movq	%rdi, %rbx
	pushq	%rax
	.cfi_def_cfa_offset 32
	pushq	$1
	.cfi_def_cfa_offset 40
	pushq	%r8
	.cfi_def_cfa_offset 48
	xorl	%r8d, %r8d
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rdx
	.cfi_def_cfa_offset 40
	movss	.LC1(%rip), %xmm0
	movl	%ebp, %edx
	popq	%rcx
	.cfi_def_cfa_offset 32
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	movl	$1, %ecx
	call	_Z9matrixAddPfS_fii
	popq	%r8
	.cfi_def_cfa_offset 24
	movl	%ebp, %edx
	movq	%rbx, %rsi
	movq	%rbx, %rdi
	movl	$1, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixNegPfS_ii
	.cfi_endproc
.LFE2056:
	.size	_Z9computephPfS_S_S_i, .-_Z9computephPfS_S_S_i
	.globl	_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i
	.type	_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i, @function
_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i:
.LFB2105:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L215
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15diagonalAddCudaPfS_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L215:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L217
	call	__stack_chk_fail@PLT
.L217:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2105:
	.size	_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i, .-_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i
	.globl	_Z15diagonalAddCudaPfS_i
	.type	_Z15diagonalAddCudaPfS_i, @function
_Z15diagonalAddCudaPfS_i:
.LFB2106:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i
	.cfi_endproc
.LFE2106:
	.size	_Z15diagonalAddCudaPfS_i, .-_Z15diagonalAddCudaPfS_i
	.globl	_Z11diagonalAddPfS_i
	.type	_Z11diagonalAddPfS_i, @function
_Z11diagonalAddPfS_i:
.LFB2039:
	.cfi_startproc
	endbr64
	leal	1023(%rdx), %eax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1024, %ecx
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edx, %ebx
	cltd
	idivl	%ecx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L220
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z38__device_stub__Z15diagonalAddCudaPfS_iPfS_i
.L220:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z11diagonalAddPfS_i, .-_Z11diagonalAddPfS_i
	.globl	_Z12computeThetaPfS_i
	.type	_Z12computeThetaPfS_i, @function
_Z12computeThetaPfS_i:
.LFB2050:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	movl	%edx, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	movl	%edx, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	call	_Z13newMatrixCUDAii
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rsi
	movq	%rax, %rdi
	movq	%rax, %r13
	call	_Z9matrixNegPfS_ii
	movl	%ebx, %edi
	movl	$1, %esi
	call	_Z13newMatrixCUDAii
	movss	.LC1(%rip), %xmm0
	movl	%ebx, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	call	_Z7initMatPffi
	movl	%ebx, %edi
	movl	$1, %esi
	call	_Z13newMatrixCUDAii
	pushq	$1
	.cfi_def_cfa_offset 56
	movl	%ebx, %r9d
	movq	%r12, %rcx
	pushq	%rbx
	.cfi_def_cfa_offset 64
	movq	%rax, %rbp
	xorl	%r8d, %r8d
	movq	%r13, %rsi
	movq	%rax, %rdi
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 56
	movq	%rbp, %rsi
	popq	%rdx
	.cfi_def_cfa_offset 48
	movq	%r14, %rdi
	movl	%ebx, %edx
	call	_Z11diagonalAddPfS_i
	movq	%r13, %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	cudaFree@PLT
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2050:
	.size	_Z12computeThetaPfS_i, .-_Z12computeThetaPfS_i
	.globl	_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii
	.type	_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii, @function
_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii:
.LFB2107:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L225
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11compareCudaPfS_Pii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L225:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L227
	call	__stack_chk_fail@PLT
.L227:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2107:
	.size	_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii, .-_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii
	.globl	_Z11compareCudaPfS_Pii
	.type	_Z11compareCudaPfS_Pii, @function
_Z11compareCudaPfS_Pii:
.LFB2108:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii
	.cfi_endproc
.LFE2108:
	.size	_Z11compareCudaPfS_Pii, .-_Z11compareCudaPfS_Pii
	.globl	_Z7comparePfS_Pii
	.type	_Z7comparePfS_Pii, @function
_Z7comparePfS_Pii:
.LFB2040:
	.cfi_startproc
	endbr64
	leal	1023(%rcx), %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdx, %r13
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	cltd
	movq	%rsi, %r12
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%ecx, %ebx
	movl	$1024, %ecx
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L230
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z36__device_stub__Z11compareCudaPfS_PiiPfS_Pii
.L230:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z7comparePfS_Pii, .-_Z7comparePfS_Pii
	.globl	_Z9checkFeasPfS_S_ii
	.type	_Z9checkFeasPfS_S_ii, @function
_Z9checkFeasPfS_S_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r8d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	movl	%ecx, %edi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	movl	$1, %esi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	_Z13newMatrixCUDAii
	pushq	$1
	.cfi_def_cfa_offset 88
	movl	%ebp, %r9d
	xorl	%r8d, %r8d
	pushq	%r15
	.cfi_def_cfa_offset 96
	movq	%rax, %rdi
	movq	%r14, %rcx
	xorl	%edx, %edx
	movq	%r13, %rsi
	movq	%rax, %rbx
	call	_Z14matrixMultiplyPfS_iS_iiii
	movl	%ebp, %ecx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	movl	$1, 20(%rsp)
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
	leaq	4(%rsp), %rdx
	call	_Z7comparePfS_Pii
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movl	4(%rsp), %eax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L234
	call	__stack_chk_fail@PLT
.L234:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z9checkFeasPfS_S_ii, .-_Z9checkFeasPfS_S_ii
	.globl	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	.type	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii, @function
_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r8, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	movq	%rdi, %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r9, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	movq	%r15, %rdi
	subq	$32, %rsp
	.cfi_def_cfa_offset 88
	movl	136(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 96
	movq	96(%rsp), %r8
	movq	120(%rsp), %rcx
	movl	136(%rsp), %r9d
	movq	104(%rsp), %rdx
	call	_Z13computeUfromYPfS_S_S_S_ii
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
	movq	%r15, %rdi
	movl	128(%rsp), %r8d
	movl	120(%rsp), %ecx
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rsi
	call	_Z9checkFeasPfS_S_ii
	testl	%eax, %eax
	jne	.L237
.L239:
	xorl	%eax, %eax
	jmp	.L236
.L237:
	movl	120(%rsp), %r8d
	movq	%r14, %rcx
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	call	_Z11computeCostPfS_S_S_i
	movq	96(%rsp), %rcx
	movq	%rbp, %rsi
	movq	%r15, %rdi
	movl	128(%rsp), %r8d
	movq	88(%rsp), %rdx
	movss	%xmm0, 12(%rsp)
	call	_Z11computeCostPfS_S_S_i
	movss	12(%rsp), %xmm1
	movaps	%xmm1, %xmm2
	xorps	.LC23(%rip), %xmm2
	comiss	%xmm2, %xmm0
	ja	.L239
	addss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm2
	comisd	.LC24(%rip), %xmm2
	ja	.L239
	andps	.LC25(%rip), %xmm1
	xorl	%eax, %eax
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	comisd	.LC24(%rip), %xmm0
	setbe	%al
.L236:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii, .-_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	.globl	_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i
	.type	_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i, @function
_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i:
.LFB2109:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L241
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8updYCudaPfS_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L241:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L243
	call	__stack_chk_fail@PLT
.L243:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2109:
	.size	_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i, .-_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i
	.globl	_Z8updYCudaPfS_S_S_i
	.type	_Z8updYCudaPfS_S_S_i, @function
_Z8updYCudaPfS_S_S_i:
.LFB2110:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE2110:
	.size	_Z8updYCudaPfS_S_S_i, .-_Z8updYCudaPfS_S_S_i
	.globl	_Z4updYPfS_S_S_i
	.type	_Z4updYPfS_S_S_i, @function
_Z4updYPfS_S_S_i:
.LFB2041:
	.cfi_startproc
	endbr64
	leal	1023(%r8), %eax
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rcx, %r14
	xorl	%r9d, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	$1024, %ecx
	movq	%rdx, %r13
	cltd
	idivl	%ecx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movq	%rdi, %rbp
	movq	%rsi, %r12
	movl	$4194305, %edx
	movl	%r8d, %ebx
	salq	$10, %rdx
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L246
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movl	%ebx, %r8d
	movq	%r14, %rcx
	movq	%r13, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__Z8updYCudaPfS_S_S_iPfS_S_S_i
.L246:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z4updYPfS_S_S_i, .-_Z4updYPfS_S_S_i
	.globl	_Z8updateY2PfS_S_S_S_S_S_i
	.type	_Z8updateY2PfS_S_S_S_S_S_i, @function
_Z8updateY2PfS_S_S_S_S_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	104(%rsp), %ebx
	movq	96(%rsp), %r15
	movq	%rdi, 24(%rsp)
	movl	%ebx, %edi
	call	_Z13newMatrixCUDAii
	movl	%ebx, %edi
	movl	$1, %esi
	movq	%rax, 8(%rsp)
	call	_Z13newMatrixCUDAii
	movl	%ebx, %r9d
	movq	%rbp, %rcx
	movq	%r14, %rsi
	movq	%rax, 16(%rsp)
	xorl	%r8d, %r8d
	xorl	%edx, %edx
	pushq	$1
	.cfi_def_cfa_offset 104
	pushq	%rbx
	.cfi_def_cfa_offset 112
	movq	24(%rsp), %rdi
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
	pushq	$1
	.cfi_def_cfa_offset 104
	pushq	%rbx
	.cfi_def_cfa_offset 112
	movq	32(%rsp), %rdi
	movl	%ebx, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rcx
	movq	%r13, %rsi
	xorl	%edx, %edx
	call	_Z14matrixMultiplyPfS_iS_iiii
	popq	%rcx
	.cfi_def_cfa_offset 104
	movss	.LC1(%rip), %xmm0
	movl	%ebx, %edx
	popq	%rsi
	.cfi_def_cfa_offset 96
	movq	8(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	_Z9matrixAddPfS_fii
	movq	16(%rsp), %rdi
	movl	%ebx, %edx
	movq	%r12, %rsi
	movss	.LC1(%rip), %xmm0
	movl	$1, %ecx
	call	_Z9matrixAddPfS_fii
	movq	16(%rsp), %rdx
	movl	%ebx, %r8d
	movq	%rbp, %rcx
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z4updYPfS_S_S_i
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2055:
	.size	_Z8updateY2PfS_S_S_S_S_S_i, .-_Z8updateY2PfS_S_S_S_S_S_i
	.section	.rodata.str1.1
.LC27:
	.string	"Printing number of iterations = %ld\n"
	.text
	.globl	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	.type	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii, @function
_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	200(%rsp), %rax
	movl	232(%rsp), %ebx
	movq	%rdi, 16(%rsp)
	movq	%rsi, 24(%rsp)
	movq	192(%rsp), %r12
	movq	%rax, 104(%rsp)
	movq	208(%rsp), %rax
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	%r8, 88(%rsp)
	movq	224(%rsp), %r14
	movq	%rax, 112(%rsp)
	movq	216(%rsp), %rax
	movq	%r9, 96(%rsp)
	movl	240(%rsp), %r15d
	movq	%rdx, 32(%rsp)
	movq	%rcx, 80(%rsp)
	movq	%rax, 120(%rsp)
	call	_Z13newMatrixCUDAii
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	%rax, 8(%rsp)
	call	_Z13newMatrixCUDAii
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	%rax, 40(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	%ebx, %edi
	movq	%rax, 48(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	%ebx, %edi
	movq	%rax, 56(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	_Z13newMatrixCUDAii
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movl	%ebx, %edx
	movq	%rax, %rdi
	movq	%rax, 64(%rsp)
	call	_Z9matrixPosPfS_ii
	movq	32(%rsp), %rsi
	movl	%ebx, %edx
	movq	%rbp, %rdi
	movl	$1, %ecx
	call	_Z9matrixNegPfS_ii
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%ebx, %edx
	call	_Z12computeThetaPfS_i
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	%ebx, %ecx
	movq	40(%rsp), %rdi
	call	_Z16computeQdp_thetaPfS_S_i
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	%ebx, %ecx
	movq	48(%rsp), %rdi
	call	_Z16computeQdn_thetaPfS_S_i
	movss	.LC26(%rip), %xmm0
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z7initMatPffi
	movl	$1, %esi
	movl	%ebx, %edi
	call	_Z13newMatrixCUDAii
	movq	%rax, 72(%rsp)
.L252:
	pushq	%rax
	.cfi_def_cfa_offset 200
	pushq	%r15
	.cfi_def_cfa_offset 208
	pushq	%rbx
	.cfi_def_cfa_offset 216
	pushq	%r14
	.cfi_def_cfa_offset 224
	pushq	152(%rsp)
	.cfi_def_cfa_offset 232
	pushq	152(%rsp)
	.cfi_def_cfa_offset 240
	pushq	152(%rsp)
	.cfi_def_cfa_offset 248
	pushq	%r12
	.cfi_def_cfa_offset 256
	movq	160(%rsp), %r9
	movq	152(%rsp), %r8
	movq	144(%rsp), %rcx
	movq	96(%rsp), %rdx
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	addq	$64, %rsp
	.cfi_def_cfa_offset 192
	testl	%eax, %eax
	jne	.L255
	pushq	%rbx
	.cfi_def_cfa_offset 200
	incq	%r13
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movq	80(%rsp), %r9
	movq	48(%rsp), %r8
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rcx
	movq	56(%rsp), %rdx
	call	_Z8updateY2PfS_S_S_S_S_S_i
	popq	%rdx
	.cfi_def_cfa_offset 200
	popq	%rcx
	.cfi_def_cfa_offset 192
	movl	%ebx, %edx
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	call	_Z10copyMatrixPfS_ii
	jmp	.L252
.L255:
	movq	%r13, %rdx
	leaq	.LC27(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE2060:
	.size	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii, .-_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	.section	.rodata.str1.1
.LC28:
	.string	"Jp = %f\n"
.LC29:
	.string	"Jd = %f\n"
.LC30:
	.string	"Printing U*\n"
.LC31:
	.string	"\t%f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$328, %rsp
	.cfi_def_cfa_offset 384
	call	cudaDeviceReset@PLT
	movl	$7, %esi
	movl	$7, %edi
	call	_Z9newMatrixii
	movl	$7, %esi
	movl	$7, %edi
	movq	%rax, 40(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 88(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 304(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 312(%rsp)
	call	_Z9newMatrixii
	movl	$29, %esi
	movl	$7, %edi
	movq	%rax, 96(%rsp)
	call	_Z9newMatrixii
	movl	$7, %esi
	movl	$1, %edi
	movq	%rax, 104(%rsp)
	call	_Z9newMatrixii
	movl	$29, %esi
	movl	$29, %edi
	movq	%rax, 112(%rsp)
	call	_Z9newMatrixii
	movl	$29, %esi
	movl	$1, %edi
	movq	%rax, 120(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 128(%rsp)
	call	_Z9newMatrixii
	movl	$29, %esi
	movl	$1, %edi
	movq	%rax, 136(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 144(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 152(%rsp)
	call	_Z9newMatrixii
	movl	$7, %esi
	movl	$28, %edi
	movq	%rax, 160(%rsp)
	call	_Z9newMatrixii
	movl	$28, %esi
	movl	$1, %edi
	movq	%rax, 168(%rsp)
	call	_Z9newMatrixii
	movl	$29, %esi
	movl	$7, %edi
	movq	%rax, 176(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 184(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 192(%rsp)
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$29, %edi
	movq	%rax, 200(%rsp)
	call	_Z9newMatrixii
	movl	$7, %esi
	movl	$7, %edi
	movq	%rax, 208(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$7, %esi
	movl	$7, %edi
	movq	%rax, 8(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 48(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, %rbx
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, %rbp
	call	_Z13newMatrixCUDAii
	movl	$29, %esi
	movl	$7, %edi
	movq	%rax, 216(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$7, %esi
	movl	$1, %edi
	movq	%rax, 224(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$29, %esi
	movl	$29, %edi
	movq	%rax, 232(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$29, %esi
	movl	$1, %edi
	movq	%rax, 240(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 248(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$29, %esi
	movl	$1, %edi
	movq	%rax, 256(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 264(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 272(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$7, %esi
	movl	$28, %edi
	movq	%rax, 280(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$28, %esi
	movl	$1, %edi
	movq	%rax, 16(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$29, %esi
	movl	$7, %edi
	movq	%rax, %r13
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 288(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 296(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$29, %edi
	movq	%rax, 56(%rsp)
	call	_Z13newMatrixCUDAii
	pushq	184(%rsp)
	.cfi_def_cfa_offset 392
	pushq	200(%rsp)
	.cfi_def_cfa_offset 400
	movq	%rax, %r12
	pushq	216(%rsp)
	.cfi_def_cfa_offset 408
	pushq	232(%rsp)
	.cfi_def_cfa_offset 416
	pushq	208(%rsp)
	.cfi_def_cfa_offset 424
	pushq	208(%rsp)
	.cfi_def_cfa_offset 432
	pushq	208(%rsp)
	.cfi_def_cfa_offset 440
	pushq	208(%rsp)
	.cfi_def_cfa_offset 448
	pushq	208(%rsp)
	.cfi_def_cfa_offset 456
	pushq	208(%rsp)
	.cfi_def_cfa_offset 464
	movq	208(%rsp), %r9
	movq	200(%rsp), %r8
	movq	192(%rsp), %rcx
	movq	184(%rsp), %rdx
	movq	176(%rsp), %rsi
	movq	120(%rsp), %rdi
	call	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	movq	120(%rsp), %rdi
	addq	$80, %rsp
	.cfi_def_cfa_offset 384
	movq	88(%rsp), %rsi
	movl	$7, %edx
	call	_Z12Gauss_JordanPfS_i
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$196, %edx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$196, %edx
	call	cudaMemcpy@PLT
	movq	96(%rsp), %rsi
	movl	$1, %ecx
	movq	216(%rsp), %rdi
	movl	$28, %edx
	call	cudaMemcpy@PLT
	movq	104(%rsp), %rsi
	movl	$1, %ecx
	movq	224(%rsp), %rdi
	movl	$812, %edx
	call	cudaMemcpy@PLT
	movq	112(%rsp), %rsi
	movl	$1, %ecx
	movq	232(%rsp), %rdi
	movl	$28, %edx
	call	cudaMemcpy@PLT
	movq	120(%rsp), %rsi
	movl	$1, %ecx
	movq	240(%rsp), %rdi
	movl	$3364, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$116, %edx
	movq	128(%rsp), %rsi
	movq	248(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	136(%rsp), %rsi
	movq	256(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$116, %edx
	movq	144(%rsp), %rsi
	movq	264(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	152(%rsp), %rsi
	movq	272(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	160(%rsp), %rsi
	movq	280(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	168(%rsp), %rsi
	movl	$784, %edx
	call	cudaMemcpy@PLT
	movq	176(%rsp), %rsi
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$112, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$812, %edx
	movq	184(%rsp), %rsi
	movq	288(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	200(%rsp), %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$28, %edx
	movq	192(%rsp), %rsi
	movq	296(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	208(%rsp), %rsi
	movl	$1, %ecx
	movq	%r12, %rdi
	movl	$116, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %r8
	movq	%r12, %r9
	movq	%rbx, %rdi
	movq	232(%rsp), %rcx
	movq	224(%rsp), %rdx
	movq	216(%rsp), %rsi
	call	_Z9computeFpPfS_S_S_S_S_
	movq	%rbp, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 392
	pushq	%r12
	.cfi_def_cfa_offset 400
	pushq	72(%rsp)
	.cfi_def_cfa_offset 408
	pushq	304(%rsp)
	.cfi_def_cfa_offset 416
	movq	304(%rsp), %r9
	movq	296(%rsp), %r8
	movq	288(%rsp), %rcx
	movq	280(%rsp), %rdx
	movq	272(%rsp), %rsi
	call	_Z9computeMpPfS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 384
	movl	$28, %esi
	movl	$28, %edi
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$28, %edi
	movq	%rax, 64(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$1, %edi
	movq	%rax, 72(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$28, %edi
	movq	%rax, 80(%rsp)
	call	_Z13newMatrixCUDAii
	movl	$1, %esi
	movl	$7, %edi
	movq	%rax, 24(%rsp)
	call	_Z13newMatrixCUDAii
	movq	%r13, %r9
	movq	%rax, 32(%rsp)
	pushq	$7
	.cfi_def_cfa_offset 392
	pushq	$28
	.cfi_def_cfa_offset 400
	pushq	%rbp
	.cfi_def_cfa_offset 408
	pushq	%rbx
	.cfi_def_cfa_offset 416
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdi
	call	_Z13convertToDualPfS_S_S_S_S_S_S_ii
	addq	$24, %rsp
	.cfi_def_cfa_offset 392
	pushq	$7
	.cfi_def_cfa_offset 400
	pushq	$28
	.cfi_def_cfa_offset 408
	pushq	%r13
	.cfi_def_cfa_offset 416
	pushq	48(%rsp)
	.cfi_def_cfa_offset 424
	pushq	%rbp
	.cfi_def_cfa_offset 432
	pushq	%rbx
	.cfi_def_cfa_offset 440
	pushq	64(%rsp)
	.cfi_def_cfa_offset 448
	movq	112(%rsp), %r9
	movq	136(%rsp), %rdx
	movq	96(%rsp), %r8
	movq	144(%rsp), %rcx
	movq	128(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	addq	$56, %rsp
	.cfi_def_cfa_offset 392
	movl	$28, %r9d
	movq	%rbx, %rdx
	pushq	$7
	.cfi_def_cfa_offset 400
	movq	24(%rsp), %r8
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdi
	movq	32(%rsp), %rcx
	call	_Z13computeUfromYPfS_S_S_S_ii
	popq	%rdx
	.cfi_def_cfa_offset 392
	popq	%rcx
	.cfi_def_cfa_offset 384
	movl	$7, %r8d
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	call	_Z11computeCostPfS_S_S_i
	movq	80(%rsp), %rcx
	movq	72(%rsp), %rdx
	movl	$28, %r8d
	movq	64(%rsp), %rsi
	movq	24(%rsp), %rdi
	movd	%xmm0, %r15d
	call	_Z11computeCostPfS_S_S_i
	movd	%r15d, %xmm1
	leaq	.LC28(%rip), %rsi
	movb	$1, %al
	movd	%xmm0, %r14d
	movl	$2, %edi
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movd	%r14d, %xmm2
	leaq	.LC29(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm2, %xmm0
	call	__printf_chk@PLT
	movl	$1, %esi
	movl	$7, %edi
	call	_Z9newMatrixii
	movl	$1, %esi
	movl	$28, %edi
	movq	%rax, %r14
	call	_Z9newMatrixii
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$28, %edx
	movq	%rax, %r15
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	%r15, %rdi
	movl	$2, %ecx
	movl	$112, %edx
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
	leaq	.LC30(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L257:
	cvtss2sd	(%r14,%r15,4), %xmm0
	leaq	.LC31(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r15
	cmpq	$7, %r15
	jne	.L257
	movq	40(%rsp), %rdi
	call	free@PLT
	movq	88(%rsp), %rdi
	call	free@PLT
	movq	96(%rsp), %rdi
	call	free@PLT
	movq	104(%rsp), %rdi
	call	free@PLT
	movq	112(%rsp), %rdi
	call	free@PLT
	movq	120(%rsp), %rdi
	call	free@PLT
	movq	128(%rsp), %rdi
	call	free@PLT
	movq	136(%rsp), %rdi
	call	free@PLT
	movq	144(%rsp), %rdi
	call	free@PLT
	movq	152(%rsp), %rdi
	call	free@PLT
	movq	160(%rsp), %rdi
	call	free@PLT
	movq	304(%rsp), %rdi
	call	free@PLT
	movq	312(%rsp), %rdi
	call	free@PLT
	movq	168(%rsp), %rdi
	call	free@PLT
	movq	176(%rsp), %rdi
	call	free@PLT
	movq	208(%rsp), %rdi
	call	free@PLT
	movq	200(%rsp), %rdi
	call	free@PLT
	movq	192(%rsp), %rdi
	call	free@PLT
	movq	184(%rsp), %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movq	224(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rdi
	call	cudaFree@PLT
	movq	240(%rsp), %rdi
	call	cudaFree@PLT
	movq	248(%rsp), %rdi
	call	cudaFree@PLT
	movq	256(%rsp), %rdi
	call	cudaFree@PLT
	movq	264(%rsp), %rdi
	call	cudaFree@PLT
	movq	272(%rsp), %rdi
	call	cudaFree@PLT
	movq	280(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	296(%rsp), %rdi
	call	cudaFree@PLT
	movq	288(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	addq	$328, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	main, .-main
	.section	.rodata.str1.1
.LC32:
	.string	"_Z8updYCudaPfS_S_S_i"
.LC33:
	.string	"_Z11compareCudaPfS_Pii"
.LC34:
	.string	"_Z15diagonalAddCudaPfS_i"
.LC35:
	.string	"_Z13matrixNegCudaPfS_ii"
.LC36:
	.string	"_Z13matrixPosCudaPfS_ii"
.LC37:
	.string	"_Z16negateMatrixCudaPfii"
.LC38:
	.string	"_Z13matrixAddCudaPfS_fii"
.LC39:
	.string	"_Z18matrixMultiplyCudaPfS_S_iii"
.LC40:
	.string	"_Z13transposeCudaPfS_ii"
.LC41:
	.string	"_Z14copyMatrixCudaPfS_ii"
.LC42:
	.string	"_Z11initMatCudaPffi"
.LC43:
	.string	"_Z8printMatPfii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2112:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8updYCudaPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11compareCudaPfS_Pii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15diagonalAddCudaPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13matrixNegCudaPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13matrixPosCudaPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16negateMatrixCudaPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13matrixAddCudaPfS_fii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18matrixMultiplyCudaPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC40(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z13transposeCudaPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14copyMatrixCudaPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11initMatCudaPffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8printMatPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2112:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC21:
	.long	-1082130432
	.align 4
.LC22:
	.long	1056964608
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC23:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC24:
	.long	-1598689907
	.long	1051772663
	.section	.rodata.cst16
	.align 16
.LC25:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4
	.align 4
.LC26:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**************************************************************************
* This file contains implementation of pqp (parallel quadratic programming)
* GPU version optimised with TILE and shared memory for MPC Term Project of HP3 Course.
* Group 7 CSE Dept. IIT KGP
*	Objective function: 1/2 U'QpU + Fp'U + 1/2 Mp
*	Constraints: GpU <= Kp
**************************************************************************/

#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>


#define NUM_ITER 1000

#define pHorizon 1
#define nState 29
#define nInput 7
#define nOutput 7
#define nDis 1

#define erc 1e-6
#define eac 1e-6
#define eaj 1e-6
#define erj 1e-6

#define TILE_DIM 32
#define BLOCK_ROWS 8
#define BLOCK_SIZE 16
#define BLK_ROWS 32
#define BLK_COLS 32
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS

__global__ void printMat(float *mat, int N, int M)
{
	printf("printing mat\n");
	for(int i=0;i<N;i++)
	{
		for(int j=0;j<M;j++)
		{
			printf("%f ",mat[i*M+j]);
		}
		printf("\n");
	}
	printf("\n");
}



__global__ void initMatCuda(float *mat, float val, int N)	//coarsened							// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		mat[id1] = val;
		mat[id2]=val;
	}
}

/**************************************************************************
* This is utility function initialize the matrix
*   1. Parameter is float type matrix pointer (*mat), float val, 
*		size of matrix 
*   2. Return type void
**************************************************************************/
void initMat(float *mat, float val, int N)								// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (N+1024-1)/1024;

	initMatCuda<<<grid, block>>>(mat, val, N);
}



float *newMatrixCUDA(int n, int m)			
{
	float *tmp = NULL;
	
	hipError_t err = hipMalloc((void **)&tmp, n*m*sizeof(float));

	if ( err != hipSuccess )
	{
		printf (" Failed to allocate device matrix! %s\n", hipGetErrorString(err));
		exit ( EXIT_FAILURE ) ;
	}

	initMat(tmp, 0, n*m);
	return tmp;
}

/**************************************************************************
* This is utility function for create new  matrix
*   1. Parameter is (int n, int m) dimension of (n X m matrix) , 
*	2. Return pointer of new matrix
*   3. This function create dynamic size matrix using malloc
**************************************************************************/
float *newMatrix(int n, int m)			
{
	float *tmp = (float *)malloc(n*m*sizeof(float));
	for(int i=0;i<n*m;i++)
	{
		tmp[i] = 0;
	}
	return tmp;
}



void copyToDevice(float *dM, float *hM, int n, int m)
{
	int size = n*m;
	hipMemcpy (dM ,hM, size * sizeof ( float ) , hipMemcpyHostToDevice );
}

void copyToHost(float *hM, float *dM, int n, int m)
{
	int size = n*m;
	hipMemcpy (hM ,dM, size * sizeof ( float ) , hipMemcpyDeviceToHost );
}



__global__ void copyMatrixCuda(float *output, float *mat, int a, int b)		// parallel //coarsened
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<a*b)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		output[id1] = mat[id1];
		output[id2] = mat[id2];
	}
}
/**************************************************************************
* This is utility function for generating addition or substraction 
*	of two matrix
*   1. Parameter is (pointer of matrix1, pointer of matrix2, int sign,int n int m)
*		dimension of (n X m matrix) 
*	2. sign parameters for decide addition or substraction
*	3. Result write back in matrix1
**************************************************************************/
void copyMatrix(float *output, float *mat, int a, int b)		// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (a*b+1024-1)/1024;

	copyMatrixCuda<<<grid,block>>>(output, mat, a, b);
}



__global__ void transposeCuda(float *odata, float *idata, int n, int m)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];
    
  int x = blockIdx.x * TILE_DIM + threadIdx.x;
  int y = blockIdx.y * TILE_DIM + threadIdx.y;
  //int width = gridDim.x * TILE_DIM;

  for(int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
  {
	if(x<m && y<n)
	{
     tile[threadIdx.x][threadIdx.y] = idata[y*m+x];
	}
  }
 
  __syncthreads();
	
  x = blockIdx.y * TILE_DIM + threadIdx.x;  // transpose block offset
  y = blockIdx.x * TILE_DIM + threadIdx.y;

  for(int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
  {
	if(y<m && x<n){
     odata[(y*n) + x] = tile[threadIdx.y][threadIdx.x];
	 }
  }
  
}



void transpose(float *odata, float *idata, int n, int m)
{
	dim3 grid((n+TILE_DIM-1)/TILE_DIM, (m+TILE_DIM-1)/TILE_DIM, 1);
	dim3 block(TILE_DIM, TILE_DIM, 1);

	
	transposeCuda<<<grid,block>>>(odata,idata,n,m);
}

__global__ void matrixMultiplyCuda(float *output, float *matrix1, float *matrix2, int a, int b, int c)
{
	//declare shared memory matrices for matrix1 and matrix2 matrices
	__shared__ float shared_mat1_tile[TILE_SIZE][TILE_SIZE];
	__shared__ float shared_mat2_tile[TILE_SIZE][TILE_SIZE];
	int tsize;
	if(a!=1 && c!=1){	
	tsize=TILE_SIZE;
	}
	else{		
	tsize=1;
	}
	
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	int row = blockIdx.y * blockDim.y + threadIdx.y;

	//check if thread directly maps to the dimensions of the resulting matrix
	if (row < a && col < c)
	{
		float result = 0.0;
		int k;
		int phase;
		
		//calculate output matrix indexes in phases. Each phase shares 
		//TILE_SIZE * TILE_SIZE data copied to the shared matrix mat1 
		//and matrix mat2.
		for (phase = 0; phase <= b/tsize; phase++)
		{
			shared_mat1_tile[ty][tx] = matrix1[row * b + phase * tsize + tx];
			shared_mat2_tile[ty][tx] = matrix2[(phase * tsize + ty) * c + col];
			__syncthreads();
			
			for (k = 0; k < tsize; k++)
			{
				if (k + (phase * tsize) < b) 
				{
					result += (shared_mat1_tile[ty][k] * shared_mat2_tile[k][tx]);
				}
			}
			__syncthreads();
		}	
		output[row * c + col] = result;
	}
}


void matrixMultiply(float *output, float *mat1, int transpose1, float *mat2, int transpose2, int a, int b, int c) 		//mat1-a*b	mat2-b*c 	// parallel
{
	float *tmp = newMatrixCUDA(a,c);
	
	float *matrix1;
	float *matrix2;
	
	if(transpose1 && a!=1 && b!=1)
	{
		matrix1 = newMatrixCUDA(a,b);
		transpose(matrix1, mat1, b,a);
			
	}
	else
	{
		matrix1 = mat1;
	}
	
	if(transpose2 && b!=1 && c!=1)
	{
		matrix2 = newMatrixCUDA(b,c);
		transpose(matrix2, mat1, c,b);
		
	}
	else
	{
		matrix2 = mat2;
	}
	int B_C, B_R;
	if(a!=1 && c!=1)
	{
		B_C=BLK_COLS;
		B_R=BLK_ROWS;
	}
	else{
		B_C=1;
		B_R=1;
	}
	dim3 block(B_C,B_R);
	dim3 grid((c+B_C-1)/B_C,(a+B_R-1)/B_R);
	matrixMultiplyCuda<<<grid, block>>>(output, matrix1, matrix2, a, b, c);
	
	if(transpose1 && a!=1 && b!=1)
	{
		hipFree(matrix1);
	}
	if(transpose2 && b!=1 && c!=1)
	{
		hipFree(matrix2);
	}

	hipFree(tmp);
}



__global__ void matrixAddCuda(float *A, float *B, float sign, int a, int b) 			// adds b to a 	// parallel //coarsened
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<a*b)	
	{
		int id1=2*id+0;
		int id2=2*id+1;
		A[id1] += sign * B[id1];
		A[id2] += sign * B[id2];
	}
}

void matrixAdd(float *A, float *B, float sign, int a, int b) 			// adds b to a 	// parallel
{
	dim3 block = 512; //1024;
	dim3 grid = (a*b+1024-1)/1024;

	matrixAddCuda<<<grid,block>>>(A,B,sign,a,b);
}



__global__ void negateMatrixCuda(float *mat, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat[id] = -mat[id];
	}
}

void negateMatrix(float *mat, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	negateMatrixCuda<<<grid,block>>>(mat,n,m);
}



__global__ void matrixPosCuda(float *mat1, float *mat2, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat1[id] = fmaxf(0.0, mat2[id]);

	}
}

void matrixPos(float *mat1, float *mat2, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	matrixPosCuda<<<grid,block>>>(mat1,mat2,n,m);
}



__global__ void matrixNegCuda(float *mat1, float *mat2, int n, int m)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<n*m)	
	{
		mat1[id] = fmaxf(0.0, -mat2[id]);
	}
}

void matrixNeg(float *mat1, float *mat2, int n, int m)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (n*m+1024-1)/1024;

	matrixNegCuda<<<grid,block>>>(mat1,mat2,n,m);
}



__global__ void diagonalAddCuda(float *theta, float *tmp, int N)			// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		// printf("tmp %f\n",tmp[i]);
		theta[id*N+id] = fmaxf(tmp[id],5.0);
	}
}

void diagonalAdd(float *theta, float *tmp, int N)			// parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1024-1)/1024;

	diagonalAddCuda<<<grid,block>>>(theta,tmp,N);
}



__global__ void compareCuda(float *GpU, float *Kp, int *re, int N)				// parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	if(id<N)	
	{
		if(GpU[id] > Kp[id]+fmaxf(erc*Kp[id], eac))
		{
			*re = 0;
		}
	}
}

void compare(float *GpU, float *Kp, int *re, int N)				// parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1024-1)/1024;

	compareCuda<<<grid,block>>>(GpU, Kp, re, N);
}




__global__ void updYCuda(float *Y_next, float *numerator, float *denominator, float *Y, int N)   // parallel
{
	int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
	int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
	int id = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
	
	if(id<N)
	{
		Y_next[id] = numerator[id]/denominator[id]*Y[id];
	}
}

void updY(float *Y_next, float *numerator, float *denominator, float *Y, int N)   // parallel
{
	dim3 block = 1024;
	dim3 grid = (N+1023)/1024;
	
	updYCuda<<<grid, block>>>(Y_next, numerator, denominator, Y, N);
}




void Gauss_Jordan(float *A,float *res, int N)
{
    /*
    size=Size of input matrix
    A=input matrix
    res= inverted matrix
    */
    float temp;
    float *matrix = newMatrix(N, 2*N);

    for (int i = 0; i < N; i++) 
    { 
        for (int j = 0; j < 2 * N; j++) 
        { 
            matrix[i*2*N+j]=0;
            if (j == (i + N)) 
                matrix[i*2*N+j] = 1; 
        } 
    }

    for (int i = 0; i < N; i++) 
    { 
        for (int j = 0; j < N; j++) 
        { 
            matrix[i*2*N+j]=A[i*N+j];

        } 
    }

    for (int i = N - 1; i > 0; i--) 
    { 
        if (matrix[(i - 1)*2*N+0] < matrix[i*2*N+0]) 
            for (int j = 0; j < 2 * N; j++) 
            { 
                temp = matrix[i*2*N+j]; 
                matrix[i*2*N+j] = matrix[(i - 1)*2*N+j]; 
                matrix[(i - 1)*2*N+j] = temp; 
            } 
    }

    for (int i = 0; i < N; i++)
    { 

        for (int j = 0; j < N; j++) 
        { 
            if (j != i) 
            { 
                temp = matrix[j*2*N+i] / matrix[i*2*N+i]; 
                for (int k = 0; k < 2 * N; k++) 
                { 
                    matrix[j*2*N+k] -= matrix[i*2*N+k] * temp; 
                } 
            } 
        } 
    } 

    for (int i = 0; i < N; i++)
    { 
        temp = matrix[i*2*N+i]; 
        for (int j = 0; j < 2 * N; j++)
        {
            matrix[i*2*N+j] = matrix[i*2*N+j] / temp; 
        } 
    }

    for (int i = 0; i < N; i++) 
    { 
        for (int j = N; j <2*N; j++) 
        { 
            res[i*N+j-N]=matrix[i*2*N+j];

        } 
    }

    free(matrix);
}



void computeUfromY(float *U, float *Y, float *Fp, float *Gp, float *Qp_inv, int N, int M)
{
	float *tmp = newMatrixCUDA(M,1);
	matrixMultiply(tmp, Gp, 1, Y, 0, M, N, 1);
	matrixAdd(tmp, Fp, 1, M, 1);
	matrixMultiply(U, Qp_inv, 0, tmp, 0, M, M, 1);
	negateMatrix(U, M, 1);
	hipFree(tmp);
}

void computeFp(float *Fp, float *Fp1, float *Fp2, float *Fp3, float *D, float *x)
{
	matrixMultiply(Fp, Fp1, 0, D, 0, nInput*pHorizon, nDis*pHorizon, 1);
	float *Fp2x = newMatrixCUDA(nInput*pHorizon,1);
	matrixMultiply(Fp2x, Fp2, 0, x, 0, nInput*pHorizon, nState, 1);
	matrixAdd(Fp, Fp2x, 1, nInput*pHorizon, 1);
	matrixAdd(Fp, Fp3, -1, nInput*pHorizon, 1);
	
	hipFree(Fp2x);	
	// for(int i=0;i<nInput*pHorizon;i++)
	// {
	// 	printf("%f\n", Fp[i]);
	// }
	// printf("\n");
	// printf("%d\n", Fp);
}

void computeMp(float *Mp, float *Mp1, float *Mp2, float *Mp3, float *Mp4, float *Mp5, float *Mp6, float *D, float *x)
{
	initMat(Mp, 0, 1);

	float *tmp = newMatrixCUDA(1,nState);
	matrixMultiply(tmp, x, 1, Mp1, 0, 1, nState, nState);
	matrixMultiply(tmp, tmp, 0, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);
//	printMat<<<1,1>>>(Mp, 1, 1);

	matrixMultiply(tmp, D, 1, Mp2, 0, 1, nDis*pHorizon, nState);
	matrixMultiply(tmp, tmp, 0, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);
	
	matrixMultiply(tmp, Mp4, 1, x, 0, 1, nState, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	hipFree(tmp);
	tmp = newMatrixCUDA(1, nDis*pHorizon);
	matrixMultiply(tmp, D, 1, Mp3, 0, 1, nDis*pHorizon, nDis*pHorizon);
	matrixMultiply(tmp, tmp, 0, D, 0, 1, nDis*pHorizon, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	matrixMultiply(tmp, Mp5, 1, D, 0, 1, nDis*pHorizon, 1);

	matrixAdd(Mp, tmp, 0.5, 1,1);

	matrixAdd(Mp, Mp6, 0.5, 1,1);
	hipFree(tmp);
}

void computeQd(float *Qd, float *Gp_Qp_inv, float *Gp, int N, int M)
{
	matrixMultiply(Qd, Gp_Qp_inv, 0, Gp, 1, N, M, N);	
}

void computeFd(float *Fd, float *Gp_Qp_inv, float *Fp, float *Kp, int N, int M)
{ 
	matrixMultiply(Fd, Gp_Qp_inv, 0, Fp, 0, N, M, 1);
	matrixAdd(Fd, Kp, 1, N, 1);
}

void computeMd(float *Md, float *Fp, float* Qp_inv, float* Mp, int N, int M)
{
	float *tmp = newMatrixCUDA(1,M);
	matrixMultiply(tmp, Fp, 1, Qp_inv, 0, 1, M, M);
	matrixMultiply(Md, tmp, 0, Fp, 0, 1, M, 1);
	matrixAdd(Md, Mp, -1, 1, 1);
	hipFree(tmp);
}

void convertToDual(float *Qd, float *Fd, float *Md, float *Qp_inv, float *Gp, float *Kp, float *Fp, float *Mp, int N, int M)
{	
	float *Gp_Qp_inv = newMatrixCUDA(N,M);
	matrixMultiply(Gp_Qp_inv, Gp, 0, Qp_inv, 0, N, M, M);
	computeQd(Qd, Gp_Qp_inv, Gp, N, M);
	computeFd(Fd, Gp_Qp_inv, Fp, Kp, N, M);
	computeMd(Md, Fp, Qp_inv, Mp, N, M);

	hipFree(Gp_Qp_inv);
}

void computeTheta(float *theta, float *Qd, int N)
{
	float *Qdn = newMatrixCUDA(N,N);
	matrixNeg(Qdn, Qd, N, N);

	float *one = newMatrixCUDA(N,1);
	initMat(one, 1, N);

	float *tmp = newMatrixCUDA(N,1);
	matrixMultiply(tmp, Qdn, 0, one, 0, N,N,1);

	diagonalAdd(theta, tmp, N);

	hipFree(Qdn);
	hipFree(one);
	hipFree(tmp);
}

void computeQdp_theta(float *Qdp_theta, float *Qd, float *theta, int N)
{
	matrixPos(Qdp_theta, Qd, N, N);
	matrixAdd(Qdp_theta, theta, 1, N, N);
}

void computeQdn_theta(float *Qdn_theta, float *Qd, float *theta, int N)
{
	matrixNeg(Qdn_theta, Qd, N, N);
	matrixAdd(Qdn_theta, theta, 1, N, N);
}

void computealphaY(float *alphaY, float *ph, float *Qd, float *Y, float *Fd, int N)
{
	float *temp = newMatrixCUDA(1,N);

	matrixMultiply(temp, ph, 1, Qd, 0, 1, N, N);
	matrixMultiply(temp, temp, 0, ph, 0, 1, N, 1);

	if(temp[0] > 0)
	{
		float *temp2 = newMatrixCUDA(1,N);

		matrixMultiply(temp2, Y, 1, Qd, 0, 1, N, N);
		
		matrixAdd(temp2, Fd, 1, 1, N);
		
		matrixMultiply(temp2, temp2, 0, ph, 0, 1, N, 1);

		*alphaY = -temp2[0]/temp[0];

		hipFree(temp2);
	}
	else
	{
		alphaY = 0;
	}

	hipFree(temp);
}

void updateY1(float *Y_next, float *Y, float alphaY, float *ph, int N)
{
	copyMatrix(Y_next, Y, N, 1);
	matrixAdd(Y_next, ph, alphaY, N, 1);
}

void updateY2(float *Y_next, float *Y, float *Qdp_theta, float *Qdn_theta, float *Fd, float *Fdp, float *Fdn, int N)
{
	float *numerator = newMatrixCUDA(N,1);
	float *denominator = newMatrixCUDA(N,1);

	matrixMultiply(numerator, Qdn_theta, 0, Y, 0, N, N, 1);
	matrixMultiply(denominator, Qdp_theta, 0, Y, 0, N, N, 1);

	matrixAdd(numerator, Fdn, 1, N, 1);
	matrixAdd(denominator, Fdp, 1, N, 1);

	updY(Y_next, numerator, denominator, Y, N);

	hipFree(numerator);
	hipFree(denominator);
}

void computeph(float *ph, float *Qd, float *Y, float *Fd, int N)
{
	matrixMultiply(ph, Qd, 0, Y, 0, N, N, 1);
	matrixAdd(ph, ph, 1, N, 1);
	matrixNeg(ph, ph, N, 1);
}

int checkFeas(float *U, float *Gp, float *Kp, int N, int M)
{
	float *tmp = newMatrixCUDA(N,1);
	matrixMultiply(tmp, Gp, 0, U, 0, N, M, 1);
	int re = 1;
	compare(tmp, Kp, &re, N);

	hipFree(tmp);
	return re;
}	

float computeCost(float *Z, float *Q, float *F, float *M, int N)
{
	float *J=newMatrixCUDA(1,1);

	float *tmp = newMatrixCUDA(1,N);
	matrixMultiply(tmp, Z, 1, Q, 0, 1, N, N);
	matrixMultiply(tmp, tmp, 0, Z, 0, 1, N, 1);

	matrixAdd(J, tmp, 0.5, 1,1);

	matrixMultiply(tmp, F, 1, Z, 0, 1, N, 1);

	matrixAdd(J, tmp, 1, 1,1);
//	printMat<<<1,1>>>(J,1,1);
//	printMat<<<1,1>>>(M,1,1);
	matrixAdd(J, M, 0.5, 1,1);
	

	float *hJ = newMatrix(1,1);
	copyToHost(hJ,J,1,1);

	float cost = hJ[0];
	free(hJ);
	hipFree(J);
	hipFree(tmp);

	return cost;
}

int terminate(float *Y, float *Qd, float *Fd, float *Md, float *U, float *Qp, float *Qp_inv, float *Fp, float *Mp, float *Gp, float *Kp, int N, int M)
{
	computeUfromY(U, Y, Fp, Gp, Qp_inv, N, M);

	if(!checkFeas(U, Gp, Kp, N, M))	return 0;

	float Jd = computeCost(Y, Qd, Fd, Md, N);
	float Jp = computeCost(U, Qp, Fp, Mp, M);

	if(Jp>-Jd)	return 0;
	if(Jp+Jd>eaj)	return 0;
	if((Jp+Jd)/fabs(Jd)>erj) return 0;

	return 1;
}

void solveQuadraticDual(float *Y, float *Qd, float *Fd, float *Md, float *U, float *Qp, float *Qp_inv, float *Fp, float *Mp, float *Gp, float *Kp, int N, int M)
{
	float *theta = newMatrixCUDA(N,N);
	float *Qdp_theta = newMatrixCUDA(N,N);
	float *Qdn_theta = newMatrixCUDA(N,N);
	float *Y_next = newMatrixCUDA(N,1);
	
	float *Fdn = newMatrixCUDA(N,1);
	float *Fdp = newMatrixCUDA(N,1);

	matrixPos(Fdp, Fd, N, 1);
	matrixNeg(Fdn, Fd, N, 1);
	
	computeTheta(theta, Qd, N);
	computeQdp_theta(Qdp_theta, Qd, theta, N);
	computeQdn_theta(Qdn_theta, Qd, theta, N);

	initMat(Y, 1000.0, N);
	// for(int i=0;i<N;i++) Y[i] = i+1;

	float *ph = newMatrixCUDA(N,1);
	long int h=1;
	float alphaY=0;

//	 while(h<NUM_ITER)
	while(!terminate(Y, Qd, Fd, Md, U, Qp, Qp_inv, Fp, Mp, Gp, Kp, N, M))
	{	
		// if(h>100000) break;
//		 printf("h %ld\n",h);
		if(1)
		{
			//update
			// printf("here\n");
			updateY2(Y_next, Y, Qdp_theta, Qdn_theta, Fd, Fdp, Fdn, N);			
			// printf("there\n");
		}
		else
		{
			// printf("accelerating\n");
			// accelerate
			computeph(ph, Qd, Y, Fd, N);
			computealphaY(&alphaY, ph, Qd, Y, Fd, N);
			// printf("alpha %f\n", alphaY);
			
			updateY1(Y_next, Y, alphaY/10, ph, N);

		}

		copyMatrix(Y, Y_next, N, 1);
		// for(int i=0;i<N;i++)
		// {
		// 	printf("%f ",Y[i]);
		// }
		// printf("\n\n");

		h++;
	}
	printf("Printing number of iterations = %ld\n",h);

	hipFree(theta);
	hipFree(Qdp_theta);
	hipFree(Qdn_theta);
	hipFree(Y_next);
	hipFree(ph);
	hipFree(Fdp);
	hipFree(Fdn);
}

void input(float* qp_inv, float* Fp1, float* Fp2, float * Fp3, float * Mp1, float * Mp2, float * Mp3, float* Mp4, float* Mp5, float* Mp6, float* Gp, float* Kp, float* x, float* D, float* theta, float* Z)
{
	FILE *fptr;
	int i,j;
	float num;

	//Fill Qp_inverse	
	fptr = fopen("./example/Qp_inv.txt","r");
	for(i=0;i<pHorizon*nInput;i++)
	{
		for(j=0;j<pHorizon*nInput;j++)
		{
			fscanf(fptr,"%f", &num);
			qp_inv[j*pHorizon*nInput+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp1
	fptr = fopen("./example/Fp1.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nInput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Fp1[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp2
	fptr = fopen("./example/Fp2.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nInput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Fp2[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Fp3
	fptr = fopen("./example/Fp3.txt","r");
	for(j=0;j<nInput*pHorizon;j++)
	{
		fscanf(fptr,"%f", &num);
		Fp3[j] = num;
	}
	fclose(fptr);

	//Fill Mp1
	fptr = fopen("./example/Mp1.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nState;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp1[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp2
	fptr = fopen("./example/Mp2.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nDis*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp2[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp3
	fptr = fopen("./example/Mp3.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nDis*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Mp3[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill Mp4
	fptr = fopen("./example/Mp4.txt","r");
	for(i=0;i<nState;i++)
	{
		fscanf(fptr,"%f", &num);
		Mp4[i] = num;
	}
	fclose(fptr);

	//Fill Mp5
	fptr = fopen("./example/Mp5.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		fscanf(fptr,"%f", &num);
		Mp5[i] = num;
	}
	fclose(fptr);

	//Fill Mp6
	fptr = fopen("./example/Mp6.txt","r");
	fscanf(fptr,"%f", &num);
	Mp6[0] = num;
	fclose(fptr);

	//Fill Gp
	fptr = fopen("./example/Gp.txt","r");
	for(i=0;i<pHorizon*nInput;i++)
	{
		for(j=0;j<4*pHorizon*nInput;j++)
		{
			fscanf(fptr,"%f", &num);
			Gp[j*pHorizon*nInput+i] = num;
		}
	}
	fclose(fptr);

	//Fill Kp
	fptr = fopen("./example/Kp.txt","r");
	for(i=0;i<4*pHorizon*nInput;i++)
	{
		fscanf(fptr,"%f", &num);
		Kp[i] = num;
	}
	fclose(fptr);

	//Fill Z
	fptr = fopen("./example/Z.txt","r");
	for(i=0;i<nState;i++)
	{
		for(j=0;j<nOutput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			Z[j*nState+i] = num;
		}
	}
	fclose(fptr);

	//Fill Theta
	fptr = fopen("./example/Theta.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		for(j=0;j<nOutput*pHorizon;j++)
		{
			fscanf(fptr,"%f", &num);
			theta[j*nDis*pHorizon+i] = num;
		}
	}
	fclose(fptr);

	//Fill D
	fptr = fopen("./example/D.txt","r");
	for(i=0;i<nDis*pHorizon;i++)
	{
		fscanf(fptr,"%f", &num);
		D[i] = num;
	}
	fclose(fptr);

	//Fill x
	fptr = fopen("./example/x.txt","r");
	for(i=0;i<nState;i++)
	{
		fscanf(fptr,"%f", &num);
		x[i] = num;
	}
	fclose(fptr);
}

int main()
{
	// QP is of parametric from 
	// J(U) = min U 1/2*U'QpU + Fp'U + 1/2*Mp
	// st GpU <= Kp
	
	hipDeviceReset();

//	float *mat = newMatrixCUDA(32,32);
//	float *trp = newMatrixCUDA(32,32);
//	float *hmat= newMatrix(32,32);
//	float *htrp = newMatrix(32,32);
//
//	int cnt=1;
//
//	for(int i=0;i<10;i++)
//	{
//		for(int j=0;j<5;j++)
//		{
//			hmat[5*i+j] = cnt++;
//		}
//	}
//
//	copyToDevice(mat, hmat, 10,5);
//	transpose(trp, mat, 10,5);
//
//	copyToHost(htrp, trp, 5,10);
//
//	for(int i=0;i<5;i++)
//	{
//		for(int j=0;j<10;j++)
//		{
//			printf("%f ",htrp[10*i+j]);
//		}
//		printf("\n");
//	}

//	return 0;
	int N, M;

	M = pHorizon*nInput;
	N = 4*pHorizon*nInput;

	// host matrix
	float *hQp_inv = newMatrix(M,M);
	float *hQp = newMatrix(M,M);

	float *hFp1;
	float *hFp2;
	float *hFp3;

	float *hMp1;
	float *hMp2;
	float *hMp3;
	float *hMp4;
	float *hMp5;
	float *hMp6;

	float *hFp = newMatrix(nInput*pHorizon,1);
	float *hMp = newMatrix(1,1);
	float *hGp;
	float *hKp;
	float *hx;
	float *hD; 
	float *htheta; 
	float *hZ; 

	hFp1 = newMatrix(nInput*pHorizon, nDis*pHorizon);
	hFp2 = newMatrix(nInput*pHorizon, nState);
	hFp3 = newMatrix(1, nInput*pHorizon);
	hMp1 = newMatrix(nState, nState);
	hMp2 = newMatrix(nDis*pHorizon, nState);
	hMp3 = newMatrix(nDis*pHorizon, nDis*pHorizon);
	hMp4 = newMatrix(1, nState);
	hMp5 = newMatrix(1, nDis*pHorizon);
	hMp6 = newMatrix(1,1);
	hGp = newMatrix(4*pHorizon*nInput, nInput*pHorizon);
	hKp = newMatrix(1,4*pHorizon*nInput);
	hZ = newMatrix(nOutput*pHorizon, nState);
	htheta = newMatrix(nOutput*pHorizon, nDis*pHorizon);
	hD = newMatrix(nDis*pHorizon,1);
	hx = newMatrix(nState, 1);

	// device matrix
	float *Qp_inv = newMatrixCUDA(M,M);
	float *Qp = newMatrixCUDA(M,M);

	float *Fp1;
	float *Fp2;
	float *Fp3;

	float *Mp1;
	float *Mp2;
	float *Mp3;
	float *Mp4;
	float *Mp5;
	float *Mp6;

	float *Fp = newMatrixCUDA(nInput*pHorizon,1);
	float *Mp = newMatrixCUDA(1,1);
	float *Gp;
	float *Kp;
	float *x;
	float *D; 
	float *theta; 
	float *Z; 

	Fp1 = newMatrixCUDA(nInput*pHorizon, nDis*pHorizon);
	Fp2 = newMatrixCUDA(nInput*pHorizon, nState);
	Fp3 = newMatrixCUDA(1, nInput*pHorizon);
	Mp1 = newMatrixCUDA(nState, nState);
	Mp2 = newMatrixCUDA(nDis*pHorizon, nState);
	Mp3 = newMatrixCUDA(nDis*pHorizon, nDis*pHorizon);
	Mp4 = newMatrixCUDA(1, nState);
	Mp5 = newMatrixCUDA(1, nDis*pHorizon);
	Mp6 = newMatrixCUDA(1,1);
	Gp = newMatrixCUDA(4*pHorizon*nInput, nInput*pHorizon);
	Kp = newMatrixCUDA(1,4*pHorizon*nInput);
	Z = newMatrixCUDA(nOutput*pHorizon, nState);
	theta = newMatrixCUDA(nOutput*pHorizon, nDis*pHorizon);
	D = newMatrixCUDA(nDis*pHorizon,1);
	x = newMatrixCUDA(nState, 1);	

	input(hQp_inv, hFp1, hFp2, hFp3, hMp1, hMp2, hMp3, hMp4, hMp5, hMp6, hGp, hKp, hx, hD, htheta, hZ);
	Gauss_Jordan(hQp_inv, hQp, M);
	copyToDevice(Qp_inv, hQp_inv, M, M);
	copyToDevice(Qp, hQp, M, M);
	copyToDevice(Fp1, hFp1, nInput*pHorizon, nDis*pHorizon);
	copyToDevice(Fp2, hFp2, nInput*pHorizon, nState);
	copyToDevice(Fp3, hFp3, 1, nInput*pHorizon);
	copyToDevice(Mp1, hMp1, nState, nState);
	copyToDevice(Mp2, hMp2, nDis*pHorizon, nState);
	copyToDevice(Mp3, hMp3, nDis*pHorizon, nDis*pHorizon);
	copyToDevice(Mp4, hMp4, 1, nState);
	copyToDevice(Mp5, hMp5, 1, nDis*pHorizon);
	copyToDevice(Mp6, hMp6, 1,1);
	copyToDevice(Gp, hGp, 4*pHorizon*nInput, nInput*pHorizon);
	copyToDevice(Kp, hKp, 1,4*pHorizon*nInput);
	copyToDevice(Z, hZ, nOutput*pHorizon, nState);
	copyToDevice(D, hD, nDis*pHorizon,1);
	copyToDevice(theta, htheta, nOutput*pHorizon, nDis*pHorizon);
	copyToDevice(x, hx, nState, 1);

	computeFp(Fp, Fp1, Fp2, Fp3, D, x);
	computeMp(Mp, Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, D, x);
	// printf("Mp %f\n", Mp[0]);
	// printf("er\n");
//	printMat<<<1,1>>>(Mp,1,1);
	// matrices and vectors required for dual form of QP
	float *Qd = newMatrixCUDA(N,N);
	float *Fd = newMatrixCUDA(N,1);
	float *Md = newMatrixCUDA(1,1);	
	float *Y  = newMatrixCUDA(N,1);
	float *U  = newMatrixCUDA(M,1);
	// printf("er\n");
	convertToDual(Qd, Fd, Md, Qp_inv, Gp, Kp, Fp, Mp, N, M);
	// printf("Qd\n");
	// for(int i=0;i<N;i++)
	// {
	// 	for(int j=0;j<N;j++)
	// 	{
	// 		printf("%f ", Qd[i*N+j]);
	// 	}
	// 	printf("\n");
	// }
	// printf("Fd\n");
	// printf("%f\n", Md[0]);
	// for(int i=0;i<N;i++)
	// {
	// 	printf("%f ", Fp[i]);
	// }
	// printf("\n");
	solveQuadraticDual(Y, Qd, Fd, Md, U, Qp, Qp_inv, Fp, Mp, Gp, Kp, N, M);
	// printf("erer\n");

	computeUfromY(U, Y, Fp, Gp, Qp_inv, N, M);

	// U[0] = -6.399018;
	// U[1] = -10.648726;
	// U[2] = -4.792378;
	// U[3] = -7.033428;
	// U[4] = -4.792378;
	// U[5] = -10.648726;
	// U[6] = -6.399018;

	// U[0] = -6.398985;
	// U[1] = -10.646729;
	// U[2] = -4.792132;
	// U[3] = -7.027614;
	// U[4] = -4.792255;
	// U[5] = -10.643004;
	// U[6] = -6.398996;

	float Jp = computeCost(U, Qp, Fp, Mp, M);
	float Jd = computeCost(Y, Qd, Fd, Md, N);

	printf("Jp = %f\n", Jp);
	printf("Jd = %f\n", Jd);
	
	float *hU = newMatrix(M,1);
	float *hY = newMatrix(N,1);

	copyToHost(hU,U,M,1);
	copyToHost(hY,Y,N,1);

	// printf("Printing Y*\n");
	// for(int i=0;i<N;i++)
	// {
	// 	printf("%f\n", hY[i]);
	// }
	printf("Printing U*\n");
	for(int i=0;i<M;i++)
	{
		printf("\t%f\n", hU[i]);
	}

	free(hQp_inv);
	free(hQp);
	free(hFp1);
	free(hFp2);
	free(hFp3);
	free(hMp1);
	free(hMp2);
	free(hMp3);
	free(hMp4);
	free(hMp5);
	free(hMp6); 
	free(hFp);
	free(hMp);
	free(hGp);
	free(hKp);
	free(hx);
	free(hD);
	free(htheta);
	free(hZ);

	hipFree(Qp_inv);
	hipFree(Qp);
	hipFree(Fp1);
	hipFree(Fp2);
	hipFree(Fp3);
	hipFree(Mp1);
	hipFree(Mp2);
	hipFree(Mp3);
	hipFree(Mp4);
	hipFree(Mp5);
	hipFree(Mp6); 
	hipFree(Fp);
	hipFree(Mp);
	hipFree(Gp);
	hipFree(Kp);
	hipFree(x);
	hipFree(D);
	hipFree(theta);
	hipFree(Z);
	
	hipFree(Qd);
	hipFree(Fd);
	hipFree(Md);
	hipFree(Y);
	hipFree(U);
}

	.text
	.file	"PQP_GPU_optimized_coarsened.hip"
	.globl	_Z23__device_stub__printMatPfii # -- Begin function _Z23__device_stub__printMatPfii
	.type	_Z23__device_stub__printMatPfii,@function
_Z23__device_stub__printMatPfii:        # @_Z23__device_stub__printMatPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8printMatPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__printMatPfii, .Lfunc_end0-_Z23__device_stub__printMatPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__initMatCudaPffi # -- Begin function _Z26__device_stub__initMatCudaPffi
	.type	_Z26__device_stub__initMatCudaPffi,@function
_Z26__device_stub__initMatCudaPffi:     # @_Z26__device_stub__initMatCudaPffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	movq	%rsp, %rdx
	movl	%esi, (%rdx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11initMatCudaPffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__initMatCudaPffi, .Lfunc_end1-_Z26__device_stub__initMatCudaPffi
	.cfi_endproc
                                        # -- End function
	.globl	_Z7initMatPffi                  # -- Begin function _Z7initMatPffi
	.type	_Z7initMatPffi,@function
_Z7initMatPffi:                         # @_Z7initMatPffi
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rdi, %r14
	leal	1023(%rbx), %eax
	leal	2046(%rbx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %esi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z26__device_stub__initMatCudaPffi # TAILCALL
.Lfunc_end2:
	.size	_Z7initMatPffi, .Lfunc_end2-_Z7initMatPffi
	.cfi_endproc
                                        # -- End function
	.globl	_Z13newMatrixCUDAii             # -- Begin function _Z13newMatrixCUDAii
	.type	_Z13newMatrixCUDAii,@function
_Z13newMatrixCUDAii:                    # @_Z13newMatrixCUDAii
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	%edi, %ebx
	leaq	8(%rsp), %rdi
	movq	$0, (%rdi)
	imull	%esi, %ebx
	movslq	%ebx, %rsi
	shlq	$2, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	8(%rsp), %rdi
	xorps	%xmm0, %xmm0
	movl	%ebx, %esi
	callq	_Z7initMatPffi
	movq	8(%rsp), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 32
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z13newMatrixCUDAii, .Lfunc_end3-_Z13newMatrixCUDAii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9newMatrixii                  # -- Begin function _Z9newMatrixii
	.type	_Z9newMatrixii,@function
_Z9newMatrixii:                         # @_Z9newMatrixii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebp
	imull	%esi, %ebp
	movslq	%ebp, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	movq	%rax, %rbx
	testl	%r14d, %r14d
	jle	.LBB4_2
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %edx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB4_2:                                # %._crit_edge
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z9newMatrixii, .Lfunc_end4-_Z9newMatrixii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12copyToDevicePfS_ii          # -- Begin function _Z12copyToDevicePfS_ii
	.type	_Z12copyToDevicePfS_ii,@function
_Z12copyToDevicePfS_ii:                 # @_Z12copyToDevicePfS_ii
	.cfi_startproc
# %bb.0:
	imull	%ecx, %edx
	movslq	%edx, %rdx
	shlq	$2, %rdx
	movl	$1, %ecx
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end5:
	.size	_Z12copyToDevicePfS_ii, .Lfunc_end5-_Z12copyToDevicePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10copyToHostPfS_ii            # -- Begin function _Z10copyToHostPfS_ii
	.type	_Z10copyToHostPfS_ii,@function
_Z10copyToHostPfS_ii:                   # @_Z10copyToHostPfS_ii
	.cfi_startproc
# %bb.0:
	imull	%ecx, %edx
	movslq	%edx, %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end6:
	.size	_Z10copyToHostPfS_ii, .Lfunc_end6-_Z10copyToHostPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__copyMatrixCudaPfS_ii # -- Begin function _Z29__device_stub__copyMatrixCudaPfS_ii
	.type	_Z29__device_stub__copyMatrixCudaPfS_ii,@function
_Z29__device_stub__copyMatrixCudaPfS_ii: # @_Z29__device_stub__copyMatrixCudaPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14copyMatrixCudaPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z29__device_stub__copyMatrixCudaPfS_ii, .Lfunc_end7-_Z29__device_stub__copyMatrixCudaPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10copyMatrixPfS_ii            # -- Begin function _Z10copyMatrixPfS_ii
	.type	_Z10copyMatrixPfS_ii,@function
_Z10copyMatrixPfS_ii:                   # @_Z10copyMatrixPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	%ecx, %edi
	imull	%edx, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z29__device_stub__copyMatrixCudaPfS_ii # TAILCALL
.Lfunc_end8:
	.size	_Z10copyMatrixPfS_ii, .Lfunc_end8-_Z10copyMatrixPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__transposeCudaPfS_ii # -- Begin function _Z28__device_stub__transposeCudaPfS_ii
	.type	_Z28__device_stub__transposeCudaPfS_ii,@function
_Z28__device_stub__transposeCudaPfS_ii: # @_Z28__device_stub__transposeCudaPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13transposeCudaPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z28__device_stub__transposeCudaPfS_ii, .Lfunc_end9-_Z28__device_stub__transposeCudaPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9transposePfS_ii              # -- Begin function _Z9transposePfS_ii
	.type	_Z9transposePfS_ii,@function
_Z9transposePfS_ii:                     # @_Z9transposePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movq	%rsi, %r15
	leal	31(%r14), %eax
	leal	62(%r14), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$5, %ecx
	leal	31(%rbx), %edx
	leal	62(%rbx), %eax
	testl	%edx, %edx
	cmovnsl	%edx, %eax
	movq	%rdi, %r12
	sarl	$5, %eax
	shlq	$32, %rax
	orq	%rcx, %rax
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%rax, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB10_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB10_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__transposeCudaPfS_ii # TAILCALL
.Lfunc_end10:
	.size	_Z9transposePfS_ii, .Lfunc_end10-_Z9transposePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__matrixMultiplyCudaPfS_S_iii # -- Begin function _Z33__device_stub__matrixMultiplyCudaPfS_S_iii
	.type	_Z33__device_stub__matrixMultiplyCudaPfS_S_iii,@function
_Z33__device_stub__matrixMultiplyCudaPfS_S_iii: # @_Z33__device_stub__matrixMultiplyCudaPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18matrixMultiplyCudaPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z33__device_stub__matrixMultiplyCudaPfS_S_iii, .Lfunc_end11-_Z33__device_stub__matrixMultiplyCudaPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14matrixMultiplyPfS_iS_iiii   # -- Begin function _Z14matrixMultiplyPfS_iS_iiii
	.type	_Z14matrixMultiplyPfS_iS_iiii,@function
_Z14matrixMultiplyPfS_iS_iiii:          # @_Z14matrixMultiplyPfS_iS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r15d
	movl	%r8d, %ebx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %r14d
	movq	%rsi, %r13
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movl	104(%rsp), %r12d
	movl	96(%rsp), %ebp
	movl	%r9d, %edi
	movl	%r12d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	testl	%r14d, %r14d
	setne	%al
	cmpl	$1, %r15d
	setne	%cl
	andb	%al, %cl
	cmpl	$1, %ebp
	setne	%r14b
	andb	%cl, %r14b
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	cmpb	$1, %r14b
	jne	.LBB12_2
# %bb.1:
	movl	%r15d, %edi
	movl	%ebp, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rax, %rdi
	movq	%r13, %rsi
	movl	%ebp, %edx
	movl	%r15d, %ecx
	callq	_Z9transposePfS_ii
.LBB12_2:
	cmpl	$1, %ebp
	setne	%al
	testl	%ebx, %ebx
	setne	%cl
	andb	%al, %cl
	cmpl	$1, %r12d
	setne	%bl
	andb	%cl, %bl
	cmpb	$1, %bl
	jne	.LBB12_4
# %bb.3:
	movl	%ebp, %edi
	movl	%r12d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rax, %rdi
	movq	%r13, %rsi
	movl	%r12d, %edx
	movl	%ebp, %ecx
	callq	_Z9transposePfS_ii
.LBB12_4:
	cmpl	$1, %r12d
	setne	%al
	cmpl	$1, %r15d
	setne	%cl
	testb	%al, %cl
	movl	$32, %esi
	movl	$1, %eax
	cmovel	%eax, %esi
	movabsq	$137438953504, %rax             # imm = 0x2000000020
	movabsq	$4294967297, %rcx               # imm = 0x100000001
	cmovneq	%rax, %rcx
	leal	(%r12,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	movl	%eax, %edi
	leal	(%r15,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rax
	orq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_6
# %bb.5:
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	movl	%r12d, %r9d
	callq	_Z33__device_stub__matrixMultiplyCudaPfS_S_iii
.LBB12_6:
	testb	%r14b, %r14b
	je	.LBB12_8
# %bb.7:
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	hipFree
.LBB12_8:
	testb	%bl, %bl
	je	.LBB12_10
# %bb.9:
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
.LBB12_10:
	movq	32(%rsp), %rdi                  # 8-byte Reload
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end12:
	.size	_Z14matrixMultiplyPfS_iS_iiii, .Lfunc_end12-_Z14matrixMultiplyPfS_iS_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matrixAddCudaPfS_fii # -- Begin function _Z28__device_stub__matrixAddCudaPfS_fii
	.type	_Z28__device_stub__matrixAddCudaPfS_fii,@function
_Z28__device_stub__matrixAddCudaPfS_fii: # @_Z28__device_stub__matrixAddCudaPfS_fii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	8(%rsp), %r8
	movl	%edx, (%r8)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matrixAddCudaPfS_fii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z28__device_stub__matrixAddCudaPfS_fii, .Lfunc_end13-_Z28__device_stub__matrixAddCudaPfS_fii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9matrixAddPfS_fii             # -- Begin function _Z9matrixAddPfS_fii
	.type	_Z9matrixAddPfS_fii,@function
_Z9matrixAddPfS_fii:                    # @_Z9matrixAddPfS_fii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	%ecx, %edi
	imull	%edx, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB14_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB14_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__matrixAddCudaPfS_fii # TAILCALL
.Lfunc_end14:
	.size	_Z9matrixAddPfS_fii, .Lfunc_end14-_Z9matrixAddPfS_fii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__negateMatrixCudaPfii # -- Begin function _Z31__device_stub__negateMatrixCudaPfii
	.type	_Z31__device_stub__negateMatrixCudaPfii,@function
_Z31__device_stub__negateMatrixCudaPfii: # @_Z31__device_stub__negateMatrixCudaPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16negateMatrixCudaPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z31__device_stub__negateMatrixCudaPfii, .Lfunc_end15-_Z31__device_stub__negateMatrixCudaPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12negateMatrixPfii            # -- Begin function _Z12negateMatrixPfii
	.type	_Z12negateMatrixPfii,@function
_Z12negateMatrixPfii:                   # @_Z12negateMatrixPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, %r14
	movl	%edx, %edi
	imull	%esi, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB16_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB16_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movl	%ebp, %esi
	movl	%ebx, %edx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z31__device_stub__negateMatrixCudaPfii # TAILCALL
.Lfunc_end16:
	.size	_Z12negateMatrixPfii, .Lfunc_end16-_Z12negateMatrixPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matrixPosCudaPfS_ii # -- Begin function _Z28__device_stub__matrixPosCudaPfS_ii
	.type	_Z28__device_stub__matrixPosCudaPfS_ii,@function
_Z28__device_stub__matrixPosCudaPfS_ii: # @_Z28__device_stub__matrixPosCudaPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matrixPosCudaPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z28__device_stub__matrixPosCudaPfS_ii, .Lfunc_end17-_Z28__device_stub__matrixPosCudaPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9matrixPosPfS_ii              # -- Begin function _Z9matrixPosPfS_ii
	.type	_Z9matrixPosPfS_ii,@function
_Z9matrixPosPfS_ii:                     # @_Z9matrixPosPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	%ecx, %edi
	imull	%edx, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB18_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB18_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__matrixPosCudaPfS_ii # TAILCALL
.Lfunc_end18:
	.size	_Z9matrixPosPfS_ii, .Lfunc_end18-_Z9matrixPosPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matrixNegCudaPfS_ii # -- Begin function _Z28__device_stub__matrixNegCudaPfS_ii
	.type	_Z28__device_stub__matrixNegCudaPfS_ii,@function
_Z28__device_stub__matrixNegCudaPfS_ii: # @_Z28__device_stub__matrixNegCudaPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matrixNegCudaPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z28__device_stub__matrixNegCudaPfS_ii, .Lfunc_end19-_Z28__device_stub__matrixNegCudaPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9matrixNegPfS_ii              # -- Begin function _Z9matrixNegPfS_ii
	.type	_Z9matrixNegPfS_ii,@function
_Z9matrixNegPfS_ii:                     # @_Z9matrixNegPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	%ecx, %edi
	imull	%edx, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB20_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB20_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__matrixNegCudaPfS_ii # TAILCALL
.Lfunc_end20:
	.size	_Z9matrixNegPfS_ii, .Lfunc_end20-_Z9matrixNegPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__diagonalAddCudaPfS_i # -- Begin function _Z30__device_stub__diagonalAddCudaPfS_i
	.type	_Z30__device_stub__diagonalAddCudaPfS_i,@function
_Z30__device_stub__diagonalAddCudaPfS_i: # @_Z30__device_stub__diagonalAddCudaPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15diagonalAddCudaPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z30__device_stub__diagonalAddCudaPfS_i, .Lfunc_end21-_Z30__device_stub__diagonalAddCudaPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11diagonalAddPfS_i            # -- Begin function _Z11diagonalAddPfS_i
	.type	_Z11diagonalAddPfS_i,@function
_Z11diagonalAddPfS_i:                   # @_Z11diagonalAddPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leal	1023(%rbx), %eax
	leal	2046(%rbx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB22_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB22_2:
	.cfi_def_cfa_offset 32
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z30__device_stub__diagonalAddCudaPfS_i # TAILCALL
.Lfunc_end22:
	.size	_Z11diagonalAddPfS_i, .Lfunc_end22-_Z11diagonalAddPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__compareCudaPfS_Pii # -- Begin function _Z26__device_stub__compareCudaPfS_Pii
	.type	_Z26__device_stub__compareCudaPfS_Pii,@function
_Z26__device_stub__compareCudaPfS_Pii:  # @_Z26__device_stub__compareCudaPfS_Pii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11compareCudaPfS_Pii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z26__device_stub__compareCudaPfS_Pii, .Lfunc_end23-_Z26__device_stub__compareCudaPfS_Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z7comparePfS_Pii               # -- Begin function _Z7comparePfS_Pii
	.type	_Z7comparePfS_Pii,@function
_Z7comparePfS_Pii:                      # @_Z7comparePfS_Pii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	leal	1023(%rbx), %eax
	leal	2046(%rbx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB24_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB24_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z26__device_stub__compareCudaPfS_Pii # TAILCALL
.Lfunc_end24:
	.size	_Z7comparePfS_Pii, .Lfunc_end24-_Z7comparePfS_Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__updYCudaPfS_S_S_i # -- Begin function _Z23__device_stub__updYCudaPfS_S_S_i
	.type	_Z23__device_stub__updYCudaPfS_S_S_i,@function
_Z23__device_stub__updYCudaPfS_S_S_i:   # @_Z23__device_stub__updYCudaPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8updYCudaPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	_Z23__device_stub__updYCudaPfS_S_S_i, .Lfunc_end25-_Z23__device_stub__updYCudaPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z4updYPfS_S_S_i                # -- Begin function _Z4updYPfS_S_S_i
	.type	_Z4updYPfS_S_S_i,@function
_Z4updYPfS_S_S_i:                       # @_Z4updYPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%r8d, %ebx
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rsi, %r12
	movq	%rdi, %r13
	leal	1023(%rbx), %eax
	leal	2046(%rbx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB26_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB26_2:
	.cfi_def_cfa_offset 48
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movq	%r14, %rcx
	movl	%ebx, %r8d
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z23__device_stub__updYCudaPfS_S_S_i # TAILCALL
.Lfunc_end26:
	.size	_Z4updYPfS_S_S_i, .Lfunc_end26-_Z4updYPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z12Gauss_JordanPfS_i
.LCPI27_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z12Gauss_JordanPfS_i
	.type	_Z12Gauss_JordanPfS_i,@function
_Z12Gauss_JordanPfS_i:                  # @_Z12Gauss_JordanPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	leal	(%r15,%r15), %ebp
	movl	%ebp, %ebx
	imull	%edx, %ebx
	movslq	%ebx, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	movq	%rax, %r13
	testl	%r14d, %r14d
	jle	.LBB27_2
# %bb.1:                                # %.lr.ph.preheader.i
	movl	%ebx, %edx
	shlq	$2, %rdx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB27_2:                               # %_Z9newMatrixii.exit
	testl	%r15d, %r15d
	jle	.LBB27_37
# %bb.3:                                # %.preheader147.lr.ph
	cmpl	$2, %ebp
	movl	$1, %r14d
	cmovgel	%ebp, %r14d
	movl	%r15d, %ebx
	xorl	%eax, %eax
	movss	.LCPI27_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %ecx
	xorl	%edx, %edx
.LBB27_4:                               # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB27_5 Depth 2
	movslq	%eax, %rsi
	leaq	(,%rsi,4), %rsi
	addq	%r13, %rsi
	movl	%ecx, %ecx
	xorl	%edi, %edi
.LBB27_5:                               #   Parent Loop BB27_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm0, %xmm1
	cmpq	%rdi, %rcx
	je	.LBB27_7
# %bb.6:                                #   in Loop: Header=BB27_5 Depth=2
	xorps	%xmm1, %xmm1
.LBB27_7:                               #   in Loop: Header=BB27_5 Depth=2
	movss	%xmm1, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %r14
	jne	.LBB27_5
# %bb.8:                                # %._crit_edge
                                        #   in Loop: Header=BB27_4 Depth=1
	incq	%rdx
	addl	%ebp, %eax
	incl	%ecx
	cmpq	%rbx, %rdx
	jne	.LBB27_4
# %bb.9:                                # %.preheader146
	testl	%r15d, %r15d
	jle	.LBB27_37
# %bb.10:                               # %.preheader145.lr.ph
	movq	%r12, 16(%rsp)                  # 8-byte Spill
	leaq	(,%rbx,4), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	xorl	%r13d, %r13d
	movq	%rbx, %r12
	movq	%r15, (%rsp)                    # 8-byte Spill
	xorl	%r15d, %r15d
.LBB27_11:                              # %._crit_edge152
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	movq	32(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movslq	%r13d, %r13
	movq	8(%rsp), %rax                   # 8-byte Reload
	leaq	(%rax,%r13,4), %rdi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	callq	memcpy@PLT
	addl	(%rsp), %r15d                   # 4-byte Folded Reload
	addl	%ebp, %r13d
	decq	%r12
	jne	.LBB27_11
# %bb.12:                               # %.preheader144
	movq	(%rsp), %r15                    # 8-byte Reload
	cmpl	$1, %r15d
	movq	16(%rsp), %r12                  # 8-byte Reload
	movq	8(%rsp), %r13                   # 8-byte Reload
	je	.LBB27_18
# %bb.13:                               # %.lr.ph159
	leal	-4(%rbp), %eax
	imull	%r15d, %eax
	leal	-2(%rbp), %ecx
	imull	%r15d, %ecx
	movq	%rbx, %rdx
.LBB27_14:                              # =>This Loop Header: Depth=1
                                        #     Child Loop BB27_16 Depth 2
	leaq	-1(%rdx), %rsi
	leal	-4(,%rdx,2), %edi
	imull	%r15d, %edi
	movslq	%edi, %rdi
	movl	%esi, %r8d
	imull	%r15d, %r8d
	addl	%r8d, %r8d
	movss	(%r13,%r8,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%r13,%rdi,4), %xmm0
	jbe	.LBB27_17
# %bb.15:                               # %.lr.ph155.preheader
                                        #   in Loop: Header=BB27_14 Depth=1
	movslq	%eax, %rdi
	leaq	(,%rdi,4), %rdi
	addq	%r13, %rdi
	movl	%ecx, %r8d
	leaq	(,%r8,4), %r8
	addq	%r13, %r8
	xorl	%r9d, %r9d
.LBB27_16:                              # %.lr.ph155
                                        #   Parent Loop BB27_14 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r8,%r9,4), %xmm0              # xmm0 = mem[0],zero,zero,zero
	movss	(%rdi,%r9,4), %xmm1             # xmm1 = mem[0],zero,zero,zero
	movss	%xmm1, (%r8,%r9,4)
	movss	%xmm0, (%rdi,%r9,4)
	incq	%r9
	cmpq	%r9, %r14
	jne	.LBB27_16
.LBB27_17:                              # %.loopexit143
                                        #   in Loop: Header=BB27_14 Depth=1
	subl	%ebp, %eax
	subl	%ebp, %ecx
	cmpq	$2, %rdx
	movq	%rsi, %rdx
	jg	.LBB27_14
.LBB27_18:                              # %.preheader141
	testl	%r15d, %r15d
	jle	.LBB27_37
# %bb.19:                               # %.preheader140.lr.ph
	cmpl	$2, %ebp
	movl	$1, %eax
	cmovgel	%ebp, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB27_20:                              # %.lr.ph164
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB27_21 Depth 2
                                        #       Child Loop BB27_23 Depth 3
	movl	%ecx, %esi
	leaq	(,%rsi,4), %rsi
	addq	%r13, %rsi
	movl	%edx, %edi
	imull	%r15d, %edi
	addl	%edi, %edi
	leaq	(,%rdx,4), %r8
	addq	%r13, %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB27_21:                              #   Parent Loop BB27_20 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB27_23 Depth 3
	cmpq	%rdx, %r10
	je	.LBB27_24
# %bb.22:                               # %.lr.ph162.preheader
                                        #   in Loop: Header=BB27_21 Depth=2
	movl	%r9d, %r11d
	leaq	(,%r11,4), %r11
	addq	%r13, %r11
	movl	%r10d, %r14d
	imull	%r15d, %r14d
	addl	%r14d, %r14d
	movss	(%r8,%r14,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
	divss	(%r8,%rdi,4), %xmm0
	xorl	%r14d, %r14d
.LBB27_23:                              # %.lr.ph162
                                        #   Parent Loop BB27_20 Depth=1
                                        #     Parent Loop BB27_21 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rsi,%r14,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm1
	movss	(%r11,%r14,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	%xmm1, %xmm2
	movss	%xmm2, (%r11,%r14,4)
	incq	%r14
	cmpq	%r14, %rax
	jne	.LBB27_23
.LBB27_24:                              # %.loopexit
                                        #   in Loop: Header=BB27_21 Depth=2
	incq	%r10
	addl	%ebp, %r9d
	cmpq	%rbx, %r10
	jne	.LBB27_21
# %bb.25:                               # %._crit_edge165
                                        #   in Loop: Header=BB27_20 Depth=1
	incq	%rdx
	addl	%ebp, %ecx
	cmpq	%rbx, %rdx
	jne	.LBB27_20
# %bb.26:                               # %.preheader139
	testl	%r15d, %r15d
	jle	.LBB27_37
# %bb.27:                               # %.lr.ph172
	cmpl	$2, %ebp
	movl	$1, %eax
	cmovgel	%ebp, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB27_28:                              # %.lr.ph169.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB27_29 Depth 2
	movl	%ecx, %esi
	leaq	(,%rsi,4), %rsi
	addq	%r13, %rsi
	movl	%edx, %edi
	imull	%r15d, %edi
	addl	%edi, %edi
	leaq	(,%rdx,4), %r8
	addq	%r13, %r8
	movss	(%r8,%rdi,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
	xorl	%edi, %edi
.LBB27_29:                              # %.lr.ph169
                                        #   Parent Loop BB27_28 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rsi,%rdi,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %rax
	jne	.LBB27_29
# %bb.30:                               # %._crit_edge170
                                        #   in Loop: Header=BB27_28 Depth=1
	incq	%rdx
	addl	%ebp, %ecx
	cmpq	%rbx, %rdx
	jne	.LBB27_28
# %bb.31:                               # %.preheader138
	testl	%r15d, %r15d
	jle	.LBB27_37
# %bb.32:                               # %.preheader.lr.ph
	movl	%ebp, %eax
	leaq	(,%rbx,4), %rcx
	addq	%r13, %rcx
	subq	%rbx, %rax
	xorl	%edx, %edx
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB27_33:                              # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB27_35 Depth 2
	cmpl	%r15d, %ebp
	jle	.LBB27_36
# %bb.34:                               # %.lr.ph174
                                        #   in Loop: Header=BB27_33 Depth=1
	movslq	%esi, %r8
	leaq	(%rcx,%r8,4), %r8
	xorl	%r9d, %r9d
.LBB27_35:                              #   Parent Loop BB27_33 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r8,%r9,4), %xmm0              # xmm0 = mem[0],zero,zero,zero
	leal	(%rdx,%r9), %r10d
	movslq	%r10d, %r10
	movss	%xmm0, (%r12,%r10,4)
	incq	%r9
	cmpq	%r9, %rax
	jne	.LBB27_35
.LBB27_36:                              # %._crit_edge175
                                        #   in Loop: Header=BB27_33 Depth=1
	incq	%rdi
	addl	%ebp, %esi
	addq	%rbx, %rdx
	cmpq	%rbx, %rdi
	jne	.LBB27_33
.LBB27_37:                              # %._crit_edge177
	movq	%r13, %rdi
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end27:
	.size	_Z12Gauss_JordanPfS_i, .Lfunc_end27-_Z12Gauss_JordanPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13computeUfromYPfS_S_S_S_ii
.LCPI28_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z13computeUfromYPfS_S_S_S_ii
	.type	_Z13computeUfromYPfS_S_S_S_ii,@function
_Z13computeUfromYPfS_S_S_S_ii:          # @_Z13computeUfromYPfS_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r13d
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	movq	%rcx, %rbp
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movl	80(%rsp), %r14d
	movl	%r14d, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r15
	movq	%rax, %rdi
	movq	%rbp, %rsi
	movl	$1, %edx
	movq	%r12, %rcx
	xorl	%r8d, %r8d
	movl	%r14d, %r9d
	movl	$1, %eax
	pushq	%rax
	movl	$1, %r12d
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI28_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r15, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%rbx, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	xorl	%edx, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	%r14d, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$1, %edx
	callq	_Z12negateMatrixPfii
	movq	%r15, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end28:
	.size	_Z13computeUfromYPfS_S_S_S_ii, .Lfunc_end28-_Z13computeUfromYPfS_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9computeFpPfS_S_S_S_S_
.LCPI29_0:
	.long	0x3f800000                      # float 1
.LCPI29_1:
	.long	0xbf800000                      # float -1
	.text
	.globl	_Z9computeFpPfS_S_S_S_S_
	.type	_Z9computeFpPfS_S_S_S_S_,@function
_Z9computeFpPfS_S_S_S_S_:               # @_Z9computeFpPfS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %r15
	movq	%rcx, %rbx
	movq	%rdx, %r13
	movq	%rdi, %r14
	movl	$1, %ebp
	xorl	%edx, %edx
	movq	%r8, %rcx
	xorl	%r8d, %r8d
	movl	$7, %r9d
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$7, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r12
	movq	%rax, %rdi
	movq	%r13, %rsi
	xorl	%edx, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	$7, %r9d
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	$29
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI29_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %rdi
	movq	%r12, %rsi
	movl	$7, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movss	.LCPI29_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$7, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r12, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end29:
	.size	_Z9computeFpPfS_S_S_S_S_, .Lfunc_end29-_Z9computeFpPfS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9computeMpPfS_S_S_S_S_S_S_S_
.LCPI30_0:
	.long	0x3f000000                      # float 0.5
	.text
	.globl	_Z9computeMpPfS_S_S_S_S_S_S_S_
	.type	_Z9computeMpPfS_S_S_S_S_S_S_S_,@function
_Z9computeMpPfS_S_S_S_S_S_S_S_:         # @_Z9computeMpPfS_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 40(%rsp)                   # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movq	%rsi, %rbp
	movq	%rdi, %rbx
	movq	112(%rsp), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	120(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	128(%rsp), %r15
	movl	$1, %r13d
	xorps	%xmm0, %xmm0
	movl	$1, %esi
	callq	_Z7initMatPffi
	movl	$29, %r12d
	movl	$1, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%r15, %rsi
	movl	$1, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	movq	8(%rsp), %rbp                   # 8-byte Reload
	movq	%rbp, %rsi
	movl	$1, %edx
	movq	16(%rsp), %rcx                  # 8-byte Reload
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	callq	hipFree
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%rbp, %rsi
	movl	$1, %edx
	movq	32(%rsp), %rcx                  # 8-byte Reload
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%rbx, %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movss	.LCPI30_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end30:
	.size	_Z9computeMpPfS_S_S_S_S_S_S_S_, .Lfunc_end30-_Z9computeMpPfS_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z9computeQdPfS_S_ii            # -- Begin function _Z9computeQdPfS_S_ii
	.type	_Z9computeQdPfS_S_ii,@function
_Z9computeQdPfS_S_ii:                   # @_Z9computeQdPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	%r8d, %eax
	movl	%ecx, %r9d
	movq	%rdx, %rcx
	xorl	%edx, %edx
	movl	$1, %r8d
	pushq	%r9
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	_Z9computeQdPfS_S_ii, .Lfunc_end31-_Z9computeQdPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9computeFdPfS_S_S_ii
.LCPI32_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z9computeFdPfS_S_S_ii
	.type	_Z9computeFdPfS_S_S_ii,@function
_Z9computeFdPfS_S_S_ii:                 # @_Z9computeFdPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%r9d, %eax
	movl	%r8d, %ebx
	movq	%rcx, %r14
	movq	%rdx, %rcx
	movq	%rdi, %r15
	xorl	%edx, %edx
	xorl	%r8d, %r8d
	movl	%ebx, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI32_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii             # TAILCALL
.Lfunc_end32:
	.size	_Z9computeFdPfS_S_S_ii, .Lfunc_end32-_Z9computeFdPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9computeMdPfS_S_S_ii
.LCPI33_0:
	.long	0xbf800000                      # float -1
	.text
	.globl	_Z9computeMdPfS_S_S_ii
	.type	_Z9computeMdPfS_S_S_ii,@function
_Z9computeMdPfS_S_S_ii:                 # @_Z9computeMdPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r12d
	movq	%rcx, %rbx
	movq	%rdx, %r13
	movq	%rsi, %rbp
	movq	%rdi, %r14
	movl	$1, %edi
	movl	%r9d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r15
	movq	%rax, %rdi
	movq	%rbp, %rsi
	movl	$1, %edx
	movq	%r13, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI33_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r15, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end33:
	.size	_Z9computeMdPfS_S_S_ii, .Lfunc_end33-_Z9computeMdPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13convertToDualPfS_S_S_S_S_S_S_ii
.LCPI34_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z13convertToDualPfS_S_S_S_S_S_S_ii
	.type	_Z13convertToDualPfS_S_S_S_S_S_S_ii,@function
_Z13convertToDualPfS_S_S_S_S_S_S_ii:    # @_Z13convertToDualPfS_S_S_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 32(%rsp)                   # 8-byte Spill
	movq	%r8, %rbx
	movq	%rcx, %r15
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	movq	%rdi, %r13
	movq	120(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	112(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	128(%rsp), %ebp
	movl	136(%rsp), %r12d
	movl	%ebp, %edi
	movl	%r12d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	%ebp, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r13, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%rbx, %rcx
	movl	$1, %r8d
	movl	%ebp, %r9d
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	8(%rsp), %r15                   # 8-byte Reload
	movq	%r15, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rcx
	xorl	%r8d, %r8d
	movl	%ebp, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI34_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r15, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movl	%ebp, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%rbx, %rsi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movq	40(%rsp), %rcx                  # 8-byte Reload
	movl	%r12d, %r9d
	callq	_Z9computeMdPfS_S_S_ii
	movq	%r14, %rdi
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end34:
	.size	_Z13convertToDualPfS_S_S_S_S_S_S_ii, .Lfunc_end34-_Z13convertToDualPfS_S_S_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z12computeThetaPfS_i
.LCPI35_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z12computeThetaPfS_i
	.type	_Z12computeThetaPfS_i,@function
_Z12computeThetaPfS_i:                  # @_Z12computeThetaPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rsi, %r12
	movq	%rdi, %r14
	movl	%edx, %edi
	movl	%edx, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r15
	movq	%rax, %rdi
	movq	%r12, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z9matrixNegPfS_ii
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r12
	movss	.LCPI35_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_Z7initMatPffi
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r13
	movq	%rax, %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	movq	%r12, %rcx
	xorl	%r8d, %r8d
	movl	%ebx, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r13, %rsi
	movl	%ebx, %edx
	callq	_Z11diagonalAddPfS_i
	movq	%r15, %rdi
	callq	hipFree
	movq	%r12, %rdi
	callq	hipFree
	movq	%r13, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end35:
	.size	_Z12computeThetaPfS_i, .Lfunc_end35-_Z12computeThetaPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z16computeQdp_thetaPfS_S_i
.LCPI36_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z16computeQdp_thetaPfS_S_i
	.type	_Z16computeQdp_thetaPfS_S_i,@function
_Z16computeQdp_thetaPfS_S_i:            # @_Z16computeQdp_thetaPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movq	%rdi, %r15
	movl	%ecx, %edx
	callq	_Z9matrixPosPfS_ii
	movss	.LCPI36_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii             # TAILCALL
.Lfunc_end36:
	.size	_Z16computeQdp_thetaPfS_S_i, .Lfunc_end36-_Z16computeQdp_thetaPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z16computeQdn_thetaPfS_S_i
.LCPI37_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z16computeQdn_thetaPfS_S_i
	.type	_Z16computeQdn_thetaPfS_S_i,@function
_Z16computeQdn_thetaPfS_S_i:            # @_Z16computeQdn_thetaPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movq	%rdi, %r15
	movl	%ecx, %edx
	callq	_Z9matrixNegPfS_ii
	movss	.LCPI37_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii             # TAILCALL
.Lfunc_end37:
	.size	_Z16computeQdn_thetaPfS_S_i, .Lfunc_end37-_Z16computeQdn_thetaPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13computealphaYPfS_S_S_S_i
.LCPI38_0:
	.long	0x3f800000                      # float 1
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI38_1:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.text
	.globl	_Z13computealphaYPfS_S_S_S_i
	.type	_Z13computealphaYPfS_S_S_S_i,@function
_Z13computealphaYPfS_S_S_S_i:           # @_Z13computealphaYPfS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r15d
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	movq	%rcx, %rbx
	movq	%rdx, %rbp
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	$1, %edi
	movl	%r9d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%r12, %rsi
	movl	$1, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%r12, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	(%r14), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm1
	ucomiss	%xmm1, %xmm0
	jbe	.LBB38_2
# %bb.1:
	movl	$1, %edi
	movl	%r15d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	movq	%rax, %r13
	movq	%rax, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	movq	%rbp, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI38_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r13, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %edx
	movl	%r15d, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r13, %rdi
	movq	%r13, %rsi
	xorl	%edx, %edx
	movq	%r12, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	xorps	.LCPI38_1(%rip), %xmm0
	divss	(%r14), %xmm0
	movq	8(%rsp), %rax                   # 8-byte Reload
	movss	%xmm0, (%rax)
	movq	%r13, %rdi
	callq	hipFree
.LBB38_2:
	movq	%r14, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end38:
	.size	_Z13computealphaYPfS_S_S_S_i, .Lfunc_end38-_Z13computealphaYPfS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z8updateY1PfS_fS_i             # -- Begin function _Z8updateY1PfS_fS_i
	.type	_Z8updateY1PfS_fS_i,@function
_Z8updateY1PfS_fS_i:                    # @_Z8updateY1PfS_fS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%rdi, %r15
	movl	%ecx, %edx
	movl	$1, %ecx
	callq	_Z10copyMatrixPfS_ii
	movq	%r15, %rdi
	movq	%r14, %rsi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %edx
	movl	$1, %ecx
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixAddPfS_fii             # TAILCALL
.Lfunc_end39:
	.size	_Z8updateY1PfS_fS_i, .Lfunc_end39-_Z8updateY1PfS_fS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8updateY2PfS_S_S_S_S_S_i
.LCPI40_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z8updateY2PfS_S_S_S_S_S_i
	.type	_Z8updateY2PfS_S_S_S_S_S_i,@function
_Z8updateY2PfS_S_S_S_S_S_i:             # @_Z8updateY2PfS_S_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 8(%rsp)                    # 8-byte Spill
	movq	%rcx, %r15
	movq	%rdx, %r13
	movq	%rsi, %rbx
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movq	80(%rsp), %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	movl	88(%rsp), %r14d
	movl	%r14d, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r12
	movl	%r14d, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %rbp
	movq	%r12, %rdi
	movq	%r15, %rsi
	xorl	%edx, %edx
	movq	%rbx, %rcx
	xorl	%r8d, %r8d
	movl	%r14d, %r9d
	movl	$1, %eax
	pushq	%rax
	movl	$1, %r15d
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbp, %rdi
	movq	%r13, %rsi
	xorl	%edx, %edx
	movq	%rbx, %rcx
	xorl	%r8d, %r8d
	movl	%r14d, %r9d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI40_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r12, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%rbp, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movss	.LCPI40_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rsi
	movq	%rbp, %rdx
	movq	%rbx, %rcx
	movl	%r14d, %r8d
	callq	_Z4updYPfS_S_S_i
	movq	%r12, %rdi
	callq	hipFree
	movq	%rbp, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end40:
	.size	_Z8updateY2PfS_S_S_S_S_S_i, .Lfunc_end40-_Z8updateY2PfS_S_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9computephPfS_S_S_i
.LCPI41_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z9computephPfS_S_S_i
	.type	_Z9computephPfS_S_S_i,@function
_Z9computephPfS_S_S_i:                  # @_Z9computephPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%r8d, %ebx
	movq	%rdx, %rcx
	movq	%rdi, %r14
	xorl	%edx, %edx
	xorl	%r8d, %r8d
	movl	%ebx, %r9d
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI41_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z9matrixNegPfS_ii              # TAILCALL
.Lfunc_end41:
	.size	_Z9computephPfS_S_S_i, .Lfunc_end41-_Z9computephPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9checkFeasPfS_S_ii            # -- Begin function _Z9checkFeasPfS_S_ii
	.type	_Z9checkFeasPfS_S_ii,@function
_Z9checkFeasPfS_S_ii:                   # @_Z9checkFeasPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r14d
	movl	%ecx, %ebx
	movq	%rdx, %r15
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	%ecx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %rbp
	movq	%rax, %rdi
	movq	%r12, %rsi
	xorl	%edx, %edx
	movq	%r13, %rcx
	xorl	%r8d, %r8d
	movl	%ebx, %r9d
	movl	$1, %eax
	pushq	%rax
	movl	$1, %r12d
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	leaq	4(%rsp), %r14
	movl	%r12d, (%r14)
	movq	%rbp, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	callq	_Z7comparePfS_Pii
	movq	%rbp, %rdi
	callq	hipFree
	movl	(%r14), %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end42:
	.size	_Z9checkFeasPfS_S_ii, .Lfunc_end42-_Z9checkFeasPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z11computeCostPfS_S_S_i
.LCPI43_0:
	.long	0x3f000000                      # float 0.5
.LCPI43_1:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z11computeCostPfS_S_S_i
	.type	_Z11computeCostPfS_S_S_i,@function
_Z11computeCostPfS_S_S_i:               # @_Z11computeCostPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r12d
	movq	%rcx, (%rsp)                    # 8-byte Spill
	movq	%rdx, %rbp
	movq	%rsi, %r15
	movq	%rdi, %r13
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %rbx
	movl	$1, %edi
	movl	%r12d, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	movq	%r15, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r14, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	movq	%r13, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movl	$1, %eax
	pushq	%rax
	movl	$1, %r15d
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI43_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%r14, %rdi
	movq	%rbp, %rsi
	movl	$1, %edx
	movq	%r13, %rcx
	xorl	%r8d, %r8d
	movl	$1, %r9d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z14matrixMultiplyPfS_iS_iiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	.LCPI43_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	%rbx, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movss	.LCPI43_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	$1, %edx
	movl	$1, %ecx
	callq	_Z9matrixAddPfS_fii
	movl	$4, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$0, (%rax)
	movl	$4, %edx
	movq	%rax, %rdi
	movq	%rbx, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movq	%r15, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end43:
	.size	_Z11computeCostPfS_S_S_i, .Lfunc_end43-_Z11computeCostPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
.LCPI44_0:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
.LCPI44_2:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI44_1:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	.type	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii,@function
_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii:   # @_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movq	%r8, %r15
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %rbp
	movl	160(%rsp), %r12d
	movl	152(%rsp), %r13d
	movq	120(%rsp), %rdx
	movq	136(%rsp), %rbx
	movq	112(%rsp), %r8
	movl	%r12d, (%rsp)
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movq	%rbx, %rcx
	movl	%r13d, %r9d
	callq	_Z13computeUfromYPfS_S_S_S_ii
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movq	144(%rsp), %rdx
	movl	%r13d, %ecx
	movl	%r12d, %r8d
	callq	_Z9checkFeasPfS_S_ii
	xorl	%ebx, %ebx
	testl	%eax, %eax
	je	.LBB44_4
# %bb.1:
	movq	128(%rsp), %r12
	movq	%rbp, %rdi
	movq	%r14, %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	%r13d, %r8d
	callq	_Z11computeCostPfS_S_S_i
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movq	%r15, %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	120(%rsp), %rdx
	movq	%r12, %rcx
	movl	160(%rsp), %r8d
	callq	_Z11computeCostPfS_S_S_i
	movaps	16(%rsp), %xmm2                 # 16-byte Reload
	movaps	.LCPI44_0(%rip), %xmm1          # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
	xorps	%xmm2, %xmm1
	ucomiss	%xmm1, %xmm0
	ja	.LBB44_4
# %bb.2:
	addss	%xmm2, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm1
	ucomisd	.LCPI44_1(%rip), %xmm1
	ja	.LBB44_4
# %bb.3:
	andps	.LCPI44_2(%rip), %xmm2
	divss	%xmm2, %xmm0
	cvtss2sd	%xmm0, %xmm0
	xorl	%ebx, %ebx
	ucomisd	.LCPI44_1(%rip), %xmm0
	setbe	%bl
.LBB44_4:
	movl	%ebx, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end44:
	.size	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii, .Lfunc_end44-_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
.LCPI45_0:
	.long	0x3f800000                      # float 1
.LCPI45_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	.type	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii,@function
_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii: # @_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 72(%rsp)                   # 8-byte Spill
	movq	%r8, 88(%rsp)                   # 8-byte Spill
	movq	%rcx, 104(%rsp)                 # 8-byte Spill
	movq	%rdx, %r15
	movq	%rsi, 96(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbp
	movl	256(%rsp), %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	248(%rsp), %ebx
	movq	240(%rsp), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	232(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	224(%rsp), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	216(%rsp), %rax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	208(%rsp), %rax
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r13
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r12
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rax, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_Z9matrixPosPfS_ii
	movq	%r14, 48(%rsp)                  # 8-byte Spill
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_Z9matrixNegPfS_ii
	movq	%r13, %rdi
	movq	96(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movl	%ebx, %edx
	callq	_Z12computeThetaPfS_i
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z9matrixPosPfS_ii
	movss	.LCPI45_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%r12, 80(%rsp)                  # 8-byte Spill
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z9matrixAddPfS_fii
	movq	8(%rsp), %r12                   # 8-byte Reload
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z9matrixNegPfS_ii
	movq	%r12, %rdi
	movq	%r13, 136(%rsp)                 # 8-byte Spill
	movq	%r13, %rsi
	movss	.LCPI45_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z9matrixAddPfS_fii
	movss	.LCPI45_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	%rbp, %rdi
	movl	%ebx, %esi
	callq	_Z7initMatPffi
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %rdi
	movq	%r14, %rsi
	movq	%r15, 152(%rsp)                 # 8-byte Spill
	movq	%r15, %rdx
	movq	112(%rsp), %rcx                 # 8-byte Reload
	movq	96(%rsp), %r8                   # 8-byte Reload
	movq	80(%rsp), %r9                   # 8-byte Reload
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	movq	168(%rsp), %rax                 # 8-byte Reload
	movq	%rax, %r12
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movq	184(%rsp), %rax                 # 8-byte Reload
	movq	%rax, %r15
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
	movl	$1, %r14d
	testl	%eax, %eax
	jne	.LBB45_3
# %bb.1:                                # %.lr.ph.preheader
	movq	32(%rsp), %r13                  # 8-byte Reload
.LBB45_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movq	%rbp, %rsi
	movq	80(%rsp), %rdx                  # 8-byte Reload
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movq	16(%rsp), %r9                   # 8-byte Reload
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z8updateY2PfS_S_S_S_S_S_i
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_Z10copyMatrixPfS_ii
	incq	%r14
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	152(%rsp), %rdx                 # 8-byte Reload
	movq	112(%rsp), %rcx                 # 8-byte Reload
	movq	96(%rsp), %r8                   # 8-byte Reload
	movq	80(%rsp), %r9                   # 8-byte Reload
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z9terminatePfS_S_S_S_S_S_S_S_S_S_ii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
	testl	%eax, %eax
	je	.LBB45_2
.LBB45_3:                               # %._crit_edge
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	136(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	hipFree
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	112(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	48(%rsp), %rdi                  # 8-byte Reload
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end45:
	.size	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii, .Lfunc_end45-_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.type	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@function
_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_: # @_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 24(%rsp)                   # 8-byte Spill
	movq	%r8, %r14
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movq	%rdx, %r12
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	movq	%rdi, %rbp
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r15
	xorl	%eax, %eax
.LBB46_1:                               # %.preheader144
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB46_2 Depth 2
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	$-196, %r13
.LBB46_2:                               #   Parent Loop BB46_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 196(%rbp,%r13)
	addq	$28, %r13
	jne	.LBB46_2
# %bb.3:                                #   in Loop: Header=BB46_1 Depth=1
	movq	32(%rsp), %rax                  # 8-byte Reload
	incq	%rax
	addq	$4, %rbp
	cmpq	$7, %rax
	jne	.LBB46_1
# %bb.4:                                # %.critedge
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.5, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r15
	xorl	%r13d, %r13d
	movq	8(%rsp), %rbp                   # 8-byte Reload
.LBB46_5:                               # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rbp,%r13,4)
	incq	%r13
	cmpq	$7, %r13
	jne	.LBB46_5
# %bb.6:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.6, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r15
	xorl	%r13d, %r13d
.LBB46_7:                               # %.preheader143
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB46_8 Depth 2
	movq	$-812, %rbp                     # imm = 0xFCD4
.LBB46_8:                               #   Parent Loop BB46_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 812(%r12,%rbp)
	addq	$116, %rbp
	jne	.LBB46_8
# %bb.9:                                #   in Loop: Header=BB46_7 Depth=1
	incq	%r13
	addq	$4, %r12
	cmpq	$29, %r13
	jne	.LBB46_7
# %bb.10:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.7, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r15
	xorl	%r12d, %r12d
	movq	16(%rsp), %r13                  # 8-byte Reload
.LBB46_11:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r13,%r12,4)
	incq	%r12
	cmpq	$7, %r12
	jne	.LBB46_11
# %bb.12:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.8, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r15
	xorl	%r12d, %r12d
	movq	128(%rsp), %rbp
.LBB46_13:                              # %.preheader142
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB46_14 Depth 2
	movq	$-3364, %r13                    # imm = 0xF2DC
.LBB46_14:                              #   Parent Loop BB46_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 3364(%r14,%r13)
	addq	$116, %r13
	jne	.LBB46_14
# %bb.15:                               #   in Loop: Header=BB46_13 Depth=1
	incq	%r12
	addq	$4, %r14
	cmpq	$29, %r12
	jne	.LBB46_13
# %bb.16:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.9, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r14
	xorl	%r15d, %r15d
	movq	24(%rsp), %r12                  # 8-byte Reload
.LBB46_17:                              # %.critedge130
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12,%r15,4)
	incq	%r15
	cmpq	$29, %r15
	jne	.LBB46_17
# %bb.18:                               # %.critedge132
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.10, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %rbx
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	96(%rsp), %rax
	movss	%xmm0, (%rax)
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.11, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movq	168(%rsp), %r13
	movq	104(%rsp), %r12
.LBB46_19:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12,%r15,4)
	incq	%r15
	cmpq	$29, %r15
	jne	.LBB46_19
# %bb.20:                               # %.critedge136
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.12, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %rbx
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	112(%rsp), %rax
	movss	%xmm0, (%rax)
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.13, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	120(%rsp), %rax
	movss	%xmm0, (%rax)
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.14, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB46_21:                              # %.preheader141
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB46_22 Depth 2
	movq	$-784, %r12                     # imm = 0xFCF0
.LBB46_22:                              #   Parent Loop BB46_21 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 784(%rbp,%r12)
	addq	$28, %r12
	jne	.LBB46_22
# %bb.23:                               #   in Loop: Header=BB46_21 Depth=1
	incq	%r15
	addq	$4, %rbp
	cmpq	$7, %r15
	jne	.LBB46_21
# %bb.24:
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.15, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r14
	xorl	%r15d, %r15d
	movq	136(%rsp), %r12
.LBB46_25:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12,%r15,4)
	incq	%r15
	cmpq	$28, %r15
	jne	.LBB46_25
# %bb.26:
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.16, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r14
	xorl	%r15d, %r15d
.LBB46_27:                              # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB46_28 Depth 2
	movq	$-812, %r12                     # imm = 0xFCD4
.LBB46_28:                              #   Parent Loop BB46_27 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 812(%r13,%r12)
	addq	$116, %r12
	jne	.LBB46_28
# %bb.29:                               #   in Loop: Header=BB46_27 Depth=1
	incq	%r15
	addq	$4, %r13
	cmpq	$29, %r15
	jne	.LBB46_27
# %bb.30:                               # %.critedge138
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.17, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	4(%rsp), %r14
	xorl	%r15d, %r15d
	movq	160(%rsp), %r12
.LBB46_31:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12,%r15,4)
	incq	%r15
	cmpq	$7, %r15
	jne	.LBB46_31
# %bb.32:                               # %.critedge140
	movq	%rbx, %rdi
	callq	fclose
	movl	$.L.str.18, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %rbx
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	152(%rsp), %rax
	movss	%xmm0, (%rax)
	movq	%r14, %rdi
	callq	fclose
	movl	$.L.str.19, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movq	144(%rsp), %r12
.LBB46_33:                              # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movss	4(%rsp), %xmm0                  # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r12,%r15,4)
	incq	%r15
	cmpq	$29, %r15
	jne	.LBB46_33
# %bb.34:
	movq	%r14, %rdi
	callq	fclose
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end46:
	.size	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end46-_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$344, %rsp                      # imm = 0x158
	.cfi_def_cfa_offset 400
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	callq	hipDeviceReset
	movl	$1, %edi
	movl	$196, %esi
	callq	calloc@PLT
	movq	%rax, %rbp
	movl	$1, %edi
	movl	$196, %esi
	callq	calloc@PLT
	movq	%rax, 320(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$28, %esi
	callq	calloc@PLT
	movq	%rax, %r13
	movl	$1, %edi
	movl	$812, %esi                      # imm = 0x32C
	callq	calloc@PLT
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$28, %esi
	callq	calloc@PLT
	movq	%rax, %r15
	movq	%rax, 312(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$3364, %esi                     # imm = 0xD24
	callq	calloc@PLT
	movq	%rax, 304(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$116, %esi
	callq	calloc@PLT
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movl	$4, %edi
	callq	malloc
	movq	%rax, 296(%rsp)                 # 8-byte Spill
	xorl	%ebx, %ebx
	movl	%ebx, (%rax)
	movl	$1, %edi
	movl	$116, %esi
	callq	calloc@PLT
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movl	$4, %edi
	callq	malloc
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movl	%ebx, (%rax)
	movl	$4, %edi
	callq	malloc
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movl	%ebx, (%rax)
	movl	$1, %edi
	movl	$784, %esi                      # imm = 0x310
	callq	calloc@PLT
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$112, %esi
	callq	calloc@PLT
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$812, %esi                      # imm = 0x32C
	callq	calloc@PLT
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$28, %esi
	callq	calloc@PLT
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movl	$4, %edi
	callq	malloc
	movl	%ebx, (%rax)
	movq	%rax, %r14
	movq	%rax, 288(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$116, %esi
	callq	calloc@PLT
	movq	%rax, %r12
	movq	%rax, 280(%rsp)                 # 8-byte Spill
	movl	$7, %edi
	movl	$7, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movl	$7, %edi
	movl	$7, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	$7, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movl	$7, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movl	$7, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$7, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	$29, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 264(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 256(%rsp)                 # 8-byte Spill
	movl	$28, %edi
	movl	$7, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$28, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	$7, %edi
	movl	$29, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 272(%rsp)                 # 8-byte Spill
	movl	$7, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 248(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 240(%rsp)                 # 8-byte Spill
	movl	$29, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 232(%rsp)                 # 8-byte Spill
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	184(%rsp), %rdx                 # 8-byte Reload
	movq	%r15, %rcx
	movq	304(%rsp), %r15                 # 8-byte Reload
	movq	%r15, %r8
	movq	176(%rsp), %r9                  # 8-byte Reload
	pushq	128(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	144(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	232(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	movq	368(%rsp), %r14                 # 8-byte Reload
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z5inputPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	movq	%rbp, %rdi
	movq	320(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rsi
	movl	$7, %edx
	callq	_Z12Gauss_JordanPfS_i
	movl	$196, %edx
	movq	96(%rsp), %rdi                  # 8-byte Reload
	movq	%rbp, 336(%rsp)                 # 8-byte Spill
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$196, %edx
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$28, %edx
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, 328(%rsp)                 # 8-byte Spill
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$812, %edx                      # imm = 0x32C
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	184(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$28, %edx
	movq	72(%rsp), %rdi                  # 8-byte Reload
	movq	312(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$3364, %edx                     # imm = 0xD24
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$116, %edx
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	176(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %edx
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$116, %edx
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	168(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %edx
	movq	264(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movq	152(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %edx
	movq	256(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movq	136(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$784, %edx                      # imm = 0x310
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$112, %edx
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$812, %edx                      # imm = 0x32C
	movq	272(%rsp), %rdi                 # 8-byte Reload
	movq	128(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$4, %edx
	movq	240(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rdi
	movq	288(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$28, %edx
	movq	248(%rsp), %rdi                 # 8-byte Reload
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$116, %edx
	movq	232(%rsp), %r15                 # 8-byte Reload
	movq	%r15, %rdi
	movq	280(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	160(%rsp), %rdi                 # 8-byte Reload
	movq	88(%rsp), %rsi                  # 8-byte Reload
	movq	80(%rsp), %rdx                  # 8-byte Reload
	movq	72(%rsp), %rcx                  # 8-byte Reload
	movq	%r12, %r8
	movq	%r15, %r9
	callq	_Z9computeFpPfS_S_S_S_S_
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	152(%rsp), %rbp                 # 8-byte Reload
	movq	%rbp, %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movq	56(%rsp), %rcx                  # 8-byte Reload
	movq	48(%rsp), %r8                   # 8-byte Reload
	movq	%r13, %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z9computeMpPfS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$28, %edi
	movl	$28, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r15
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	$28, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r14
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, %r13
	movl	$28, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 200(%rsp)                 # 8-byte Spill
	movl	$7, %edi
	movl	$1, %esi
	callq	_Z13newMatrixCUDAii
	movq	%rax, 224(%rsp)                 # 8-byte Spill
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movq	%r13, 216(%rsp)                 # 8-byte Spill
	movq	96(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rcx
	movq	16(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %r8
	movq	8(%rsp), %r9                    # 8-byte Reload
	movl	$7, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	$28, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movq	%rbp, %r12
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	movq	184(%rsp), %rbp                 # 8-byte Reload
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	callq	_Z13convertToDualPfS_S_S_S_S_S_S_ii
	addq	$24, %rsp
	.cfi_adjust_cfa_offset -24
	movq	208(%rsp), %rdi                 # 8-byte Reload
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	216(%rsp), %rdx                 # 8-byte Reload
	movq	%r13, %rcx
	movq	232(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %r8
	movq	32(%rsp), %r9                   # 8-byte Reload
	movl	$7, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	$28, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	callq	_Z18solveQuadraticDualPfS_S_S_S_S_S_S_S_S_S_ii
	addq	$56, %rsp
	.cfi_adjust_cfa_offset -56
	movq	%r13, %rdi
	movq	208(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rsi
	movq	%rbp, %rdx
	movq	24(%rsp), %rcx                  # 8-byte Reload
	movq	%r15, %r8
	movl	$28, %r9d
	movl	$7, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z13computeUfromYPfS_S_S_S_ii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movq	%r13, %rdi
	movq	%r13, %r14
	movq	208(%rsp), %r13                 # 8-byte Reload
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movq	144(%rsp), %rcx                 # 8-byte Reload
	movl	$7, %r8d
	callq	_Z11computeCostPfS_S_S_i
	movss	%xmm0, 196(%rsp)                # 4-byte Spill
	movq	%r12, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %r15
	movq	%r13, %rdx
	movq	216(%rsp), %rcx                 # 8-byte Reload
	movl	$28, %r8d
	callq	_Z11computeCostPfS_S_S_i
	movss	%xmm0, 192(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	196(%rsp), %xmm0                # 4-byte Folded Reload
	movl	$.L.str.20, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	192(%rsp), %xmm0                # 4-byte Folded Reload
	movl	$.L.str.21, %edi
	movb	$1, %al
	callq	printf
	movl	$1, %edi
	movl	$28, %esi
	callq	calloc@PLT
	movq	%rax, %r13
	movl	$1, %edi
	movl	$112, %esi
	callq	calloc@PLT
	movq	%rax, %rbp
	movl	$28, %edx
	movq	%r13, %rdi
	movq	%r14, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$112, %edx
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB47_1:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%rbx,4), %xmm0
	movl	$.L.str.23, %edi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$7, %rbx
	jne	.LBB47_1
# %bb.2:
	movq	336(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	320(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	328(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	184(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	312(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	304(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	176(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	296(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	168(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	152(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	136(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	120(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	112(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	280(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	288(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	104(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	128(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	96(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	88(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	64(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	56(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	264(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	256(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	160(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	144(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	hipFree
	movq	232(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	240(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	248(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	272(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	hipFree
	movq	%r15, %rdi
	callq	hipFree
	movq	216(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	movq	%r12, %rdi
	callq	hipFree
	movq	224(%rsp), %rdi                 # 8-byte Reload
	callq	hipFree
	xorl	%eax, %eax
	addq	$344, %rsp                      # imm = 0x158
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end47:
	.size	main, .Lfunc_end47-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB48_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB48_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8printMatPfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11initMatCudaPffi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14copyMatrixCudaPfS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13transposeCudaPfS_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18matrixMultiplyCudaPfS_S_iii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matrixAddCudaPfS_fii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16negateMatrixCudaPfii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matrixPosCudaPfS_ii, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matrixNegCudaPfS_ii, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15diagonalAddCudaPfS_i, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11compareCudaPfS_Pii, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8updYCudaPfS_S_S_i, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end48:
	.size	__hip_module_ctor, .Lfunc_end48-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB49_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB49_2:
	retq
.Lfunc_end49:
	.size	__hip_module_dtor, .Lfunc_end49-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8printMatPfii,@object         # @_Z8printMatPfii
	.section	.rodata,"a",@progbits
	.globl	_Z8printMatPfii
	.p2align	3, 0x0
_Z8printMatPfii:
	.quad	_Z23__device_stub__printMatPfii
	.size	_Z8printMatPfii, 8

	.type	_Z11initMatCudaPffi,@object     # @_Z11initMatCudaPffi
	.globl	_Z11initMatCudaPffi
	.p2align	3, 0x0
_Z11initMatCudaPffi:
	.quad	_Z26__device_stub__initMatCudaPffi
	.size	_Z11initMatCudaPffi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" Failed to allocate device matrix! %s\n"
	.size	.L.str, 39

	.type	_Z14copyMatrixCudaPfS_ii,@object # @_Z14copyMatrixCudaPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z14copyMatrixCudaPfS_ii
	.p2align	3, 0x0
_Z14copyMatrixCudaPfS_ii:
	.quad	_Z29__device_stub__copyMatrixCudaPfS_ii
	.size	_Z14copyMatrixCudaPfS_ii, 8

	.type	_Z13transposeCudaPfS_ii,@object # @_Z13transposeCudaPfS_ii
	.globl	_Z13transposeCudaPfS_ii
	.p2align	3, 0x0
_Z13transposeCudaPfS_ii:
	.quad	_Z28__device_stub__transposeCudaPfS_ii
	.size	_Z13transposeCudaPfS_ii, 8

	.type	_Z18matrixMultiplyCudaPfS_S_iii,@object # @_Z18matrixMultiplyCudaPfS_S_iii
	.globl	_Z18matrixMultiplyCudaPfS_S_iii
	.p2align	3, 0x0
_Z18matrixMultiplyCudaPfS_S_iii:
	.quad	_Z33__device_stub__matrixMultiplyCudaPfS_S_iii
	.size	_Z18matrixMultiplyCudaPfS_S_iii, 8

	.type	_Z13matrixAddCudaPfS_fii,@object # @_Z13matrixAddCudaPfS_fii
	.globl	_Z13matrixAddCudaPfS_fii
	.p2align	3, 0x0
_Z13matrixAddCudaPfS_fii:
	.quad	_Z28__device_stub__matrixAddCudaPfS_fii
	.size	_Z13matrixAddCudaPfS_fii, 8

	.type	_Z16negateMatrixCudaPfii,@object # @_Z16negateMatrixCudaPfii
	.globl	_Z16negateMatrixCudaPfii
	.p2align	3, 0x0
_Z16negateMatrixCudaPfii:
	.quad	_Z31__device_stub__negateMatrixCudaPfii
	.size	_Z16negateMatrixCudaPfii, 8

	.type	_Z13matrixPosCudaPfS_ii,@object # @_Z13matrixPosCudaPfS_ii
	.globl	_Z13matrixPosCudaPfS_ii
	.p2align	3, 0x0
_Z13matrixPosCudaPfS_ii:
	.quad	_Z28__device_stub__matrixPosCudaPfS_ii
	.size	_Z13matrixPosCudaPfS_ii, 8

	.type	_Z13matrixNegCudaPfS_ii,@object # @_Z13matrixNegCudaPfS_ii
	.globl	_Z13matrixNegCudaPfS_ii
	.p2align	3, 0x0
_Z13matrixNegCudaPfS_ii:
	.quad	_Z28__device_stub__matrixNegCudaPfS_ii
	.size	_Z13matrixNegCudaPfS_ii, 8

	.type	_Z15diagonalAddCudaPfS_i,@object # @_Z15diagonalAddCudaPfS_i
	.globl	_Z15diagonalAddCudaPfS_i
	.p2align	3, 0x0
_Z15diagonalAddCudaPfS_i:
	.quad	_Z30__device_stub__diagonalAddCudaPfS_i
	.size	_Z15diagonalAddCudaPfS_i, 8

	.type	_Z11compareCudaPfS_Pii,@object  # @_Z11compareCudaPfS_Pii
	.globl	_Z11compareCudaPfS_Pii
	.p2align	3, 0x0
_Z11compareCudaPfS_Pii:
	.quad	_Z26__device_stub__compareCudaPfS_Pii
	.size	_Z11compareCudaPfS_Pii, 8

	.type	_Z8updYCudaPfS_S_S_i,@object    # @_Z8updYCudaPfS_S_S_i
	.globl	_Z8updYCudaPfS_S_S_i
	.p2align	3, 0x0
_Z8updYCudaPfS_S_S_i:
	.quad	_Z23__device_stub__updYCudaPfS_S_S_i
	.size	_Z8updYCudaPfS_S_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Printing number of iterations = %ld\n"
	.size	.L.str.1, 37

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"./example/Qp_inv.txt"
	.size	.L.str.2, 21

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"r"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%f"
	.size	.L.str.4, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"./example/Fp1.txt"
	.size	.L.str.5, 18

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"./example/Fp2.txt"
	.size	.L.str.6, 18

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"./example/Fp3.txt"
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"./example/Mp1.txt"
	.size	.L.str.8, 18

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"./example/Mp2.txt"
	.size	.L.str.9, 18

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"./example/Mp3.txt"
	.size	.L.str.10, 18

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"./example/Mp4.txt"
	.size	.L.str.11, 18

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"./example/Mp5.txt"
	.size	.L.str.12, 18

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"./example/Mp6.txt"
	.size	.L.str.13, 18

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"./example/Gp.txt"
	.size	.L.str.14, 17

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"./example/Kp.txt"
	.size	.L.str.15, 17

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"./example/Z.txt"
	.size	.L.str.16, 16

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"./example/Theta.txt"
	.size	.L.str.17, 20

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"./example/D.txt"
	.size	.L.str.18, 16

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"./example/x.txt"
	.size	.L.str.19, 16

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"Jp = %f\n"
	.size	.L.str.20, 9

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"Jd = %f\n"
	.size	.L.str.21, 9

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"\t%f\n"
	.size	.L.str.23, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8printMatPfii"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11initMatCudaPffi"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14copyMatrixCudaPfS_ii"
	.size	.L__unnamed_3, 25

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13transposeCudaPfS_ii"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z18matrixMultiplyCudaPfS_S_iii"
	.size	.L__unnamed_5, 32

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z13matrixAddCudaPfS_fii"
	.size	.L__unnamed_6, 25

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z16negateMatrixCudaPfii"
	.size	.L__unnamed_7, 25

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z13matrixPosCudaPfS_ii"
	.size	.L__unnamed_8, 24

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z13matrixNegCudaPfS_ii"
	.size	.L__unnamed_9, 24

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z15diagonalAddCudaPfS_i"
	.size	.L__unnamed_10, 25

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z11compareCudaPfS_Pii"
	.size	.L__unnamed_11, 23

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z8updYCudaPfS_S_S_i"
	.size	.L__unnamed_12, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Printing U*"
	.size	.Lstr, 12

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__printMatPfii
	.addrsig_sym _Z26__device_stub__initMatCudaPffi
	.addrsig_sym _Z29__device_stub__copyMatrixCudaPfS_ii
	.addrsig_sym _Z28__device_stub__transposeCudaPfS_ii
	.addrsig_sym _Z33__device_stub__matrixMultiplyCudaPfS_S_iii
	.addrsig_sym _Z28__device_stub__matrixAddCudaPfS_fii
	.addrsig_sym _Z31__device_stub__negateMatrixCudaPfii
	.addrsig_sym _Z28__device_stub__matrixPosCudaPfS_ii
	.addrsig_sym _Z28__device_stub__matrixNegCudaPfS_ii
	.addrsig_sym _Z30__device_stub__diagonalAddCudaPfS_i
	.addrsig_sym _Z26__device_stub__compareCudaPfS_Pii
	.addrsig_sym _Z23__device_stub__updYCudaPfS_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8printMatPfii
	.addrsig_sym _Z11initMatCudaPffi
	.addrsig_sym _Z14copyMatrixCudaPfS_ii
	.addrsig_sym _Z13transposeCudaPfS_ii
	.addrsig_sym _Z18matrixMultiplyCudaPfS_S_iii
	.addrsig_sym _Z13matrixAddCudaPfS_fii
	.addrsig_sym _Z16negateMatrixCudaPfii
	.addrsig_sym _Z13matrixPosCudaPfS_ii
	.addrsig_sym _Z13matrixNegCudaPfS_ii
	.addrsig_sym _Z15diagonalAddCudaPfS_i
	.addrsig_sym _Z11compareCudaPfS_Pii
	.addrsig_sym _Z8updYCudaPfS_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	v_or_b32_e32 v2, 2, v0
	v_cmp_eq_u32_e64 s0, 0, v6
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v2, v0, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u64_e32 0, v[7:8]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v11, 2 :: v_dual_and_b32 v6, 2, v10
	v_mov_b32_e32 v30, 0
	v_and_b32_e32 v0, -3, v10
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v12, 1
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v32, 0, v5 :: v_dual_cndmask_b32 v31, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v31
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v31
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[9:10], 3, v[31:32]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, v8
	v_mov_b32_e32 v13, v7
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v10, v[13:14]
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v15, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow232
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow234
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow236
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[7:8]
	flat_load_u8 v3, v[7:8] offset:1
	flat_load_u8 v9, v[7:8] offset:2
	flat_load_u8 v10, v[7:8] offset:3
	flat_load_u8 v13, v[7:8] offset:5
	flat_load_u8 v14, v[7:8] offset:4
	v_mov_b32_e32 v16, v30
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v3, 8, v3
	s_clause 0x1
	flat_load_u8 v15, v[7:8] offset:7
	flat_load_d16_hi_u8 v16, v[7:8] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v15
	v_add_nc_u32_e32 v15, -8, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v16, v9
	v_add_co_u32 v9, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v15
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v15
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v15
	flat_load_u8 v16, v[16:17]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v16, v13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow227
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow229
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr15
.LBB0_16:                               ; %Flow231
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v13, v[9:10]
	flat_load_u8 v14, v[9:10] offset:1
	flat_load_u8 v16, v[9:10] offset:2
	flat_load_u8 v17, v[9:10] offset:3
	flat_load_u8 v18, v[9:10] offset:5
	flat_load_u8 v19, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v20, v30 :: v_dual_and_b32 v13, 0xffff, v13
	s_clause 0x1
	flat_load_u8 v21, v[9:10] offset:7
	flat_load_d16_hi_u8 v20, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v14, 8, v14
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 24, v17
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v18
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v16, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v19, v14
	v_add_nc_u32_e32 v17, -8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v20, v16
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow222
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_23:                               ; %Flow224
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow226
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[9:10]
	flat_load_u8 v16, v[9:10] offset:1
	flat_load_u8 v18, v[9:10] offset:2
	flat_load_u8 v19, v[9:10] offset:3
	flat_load_u8 v20, v[9:10] offset:5
	flat_load_u8 v21, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v22, v30 :: v_dual_and_b32 v15, 0xffff, v15
	s_clause 0x1
	flat_load_u8 v23, v[9:10] offset:7
	flat_load_d16_hi_u8 v22, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v16, 8, v16
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v21, v16
	v_add_nc_u32_e32 v19, -8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v22, v18
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v19
	flat_load_u8 v20, v[20:21]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v21, s11 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v20, v17
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow217
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_31:                               ; %Flow219
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr19
.LBB0_32:                               ; %Flow221
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[9:10]
	flat_load_u8 v18, v[9:10] offset:1
	flat_load_u8 v20, v[9:10] offset:2
	flat_load_u8 v21, v[9:10] offset:3
	flat_load_u8 v22, v[9:10] offset:5
	flat_load_u8 v23, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v30 :: v_dual_and_b32 v17, 0xffff, v17
	s_clause 0x1
	flat_load_u8 v25, v[9:10] offset:7
	flat_load_d16_hi_u8 v24, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v20, 16, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v20, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	v_add_nc_u32_e32 v21, -8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v20, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v24, v20
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow212
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_39:                               ; %Flow214
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow216
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v23, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[9:10]
	flat_load_u8 v20, v[9:10] offset:1
	flat_load_u8 v22, v[9:10] offset:2
	flat_load_u8 v23, v[9:10] offset:3
	flat_load_u8 v24, v[9:10] offset:5
	flat_load_u8 v25, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v26, v30 :: v_dual_and_b32 v19, 0xffff, v19
	s_clause 0x1
	flat_load_u8 v27, v[9:10] offset:7
	flat_load_d16_hi_u8 v26, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v20, 8, v20
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v24
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v25, v20
	v_add_nc_u32_e32 v23, -8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v26, v22
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v23
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v23
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v23
	flat_load_u8 v24, v[24:25]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v25, s11 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v24, v21
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow207
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_47:                               ; %Flow209
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr23
.LBB0_48:                               ; %Flow211
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[9:10]
	flat_load_u8 v22, v[9:10] offset:1
	flat_load_u8 v24, v[9:10] offset:2
	flat_load_u8 v25, v[9:10] offset:3
	flat_load_u8 v26, v[9:10] offset:5
	flat_load_u8 v27, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v30 :: v_dual_and_b32 v21, 0xffff, v21
	s_clause 0x1
	flat_load_u8 v29, v[9:10] offset:7
	flat_load_d16_hi_u8 v28, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v24, 16, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v24, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	v_add_nc_u32_e32 v25, -8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v24, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v24
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v26, v[9:10]
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v26, 0xffff, v26
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow202
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow204
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow206
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[9:10]
	flat_load_u8 v24, v[9:10] offset:1
	flat_load_u8 v25, v[9:10] offset:2
	flat_load_u8 v26, v[9:10] offset:3
	flat_load_u8 v27, v[9:10] offset:5
	flat_load_u8 v28, v[9:10] offset:4
	v_mov_b32_e32 v29, v30
	s_clause 0x1
	flat_load_u8 v34, v[9:10] offset:7
	flat_load_d16_hi_u8 v29, v[9:10] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v9, 0xffff, v23
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v10, 8, v24
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v25
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_or_b32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v10, 24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v23, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v28, v24
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v34
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v24, v10, v29, v23
	v_or3_b32 v23, v9, 0, 0
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v33
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 24
	v_mul_hi_u32 v34, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v34, v10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v10, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[34:35], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[10:11]
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow199
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow201
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v26, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[34:35], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v9, 0, v1
	v_or_b32_e32 v10, v0, v6
	v_lshl_add_u32 v34, v31, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v10, v0
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[0:3], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s16
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s15, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[13:14], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v30, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow197
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v30, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow198
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow192
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[0:3], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_cndmask_b32 v13, v13, v17
	v_and_b32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v13, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v17, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v15, v2
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[2:3], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v31
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v32, vcc_lo
	v_add_co_u32 v7, s0, v7, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, v8, v32, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr10
.LBB0_87:                               ; %Flow253
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[5:6]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, 24, v[11:12]
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_93:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB0_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow248
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, -1
.LBB0_110:                              ; %Flow242
                                        ;   in Loop: Header=BB0_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_116:                              ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5708
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z8printMatPfii         ; -- Begin function _Z8printMatPfii
	.globl	_Z8printMatPfii
	.p2align	8
	.type	_Z8printMatPfii,@function
_Z8printMatPfii:                        ; @_Z8printMatPfii
; %bb.0:
	s_load_b64 s[24:25], s[0:1], 0x60
	v_mbcnt_lo_u32_b32 v42, -1, 0
	v_mov_b32_e32 v6, 0
	s_mov_b64 s[18:19], s[0:1]
	s_mov_b32 s32, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v42
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_6
; %bb.1:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[24:25] offset:40
	global_load_b64 v[5:6], v0, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB1_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s3, 0
.LBB1_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[24:25] offset:40
	global_load_b64 v[10:11], v0, s[24:25]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_3
; %bb.4:                                ; %Flow279
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_5:                                ; %Flow281
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s2, v6
	v_readfirstlane_b32 s3, v7
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[24:25] offset:40
	global_load_b128 v[0:3], v5, s[24:25]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, v5
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v11, vcc_lo, s8, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s11, s8
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v13, s11
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v11, s9
	v_mov_b32_e32 v10, s8
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_15
; %bb.9:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s5, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v10, s[24:25] offset:40
	v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB1_11
.LBB1_10:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_10
.LBB1_11:                               ; %Flow277
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	global_load_b64 v[2:3], v5, s[24:25] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_13
; %bb.12:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_13:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_15
; %bb.14:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_15:                               ; %Flow278
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_16:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_16 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_18:                               ;   in Loop: Header=BB1_16 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_16 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_21
.LBB1_20:                               ;   in Loop: Header=BB1_16 Depth=1
	s_mov_b32 s1, -1
.LBB1_21:                               ; %Flow272
                                        ;   in Loop: Header=BB1_16 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_16
; %bb.22:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_26
; %bb.23:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[24:25] offset:40
	global_load_b64 v[9:10], v8, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v8, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_26
; %bb.24:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_25:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_25
.LBB1_26:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_load_b64 s[26:27], s[18:19], 0x8
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v6, 1
	s_cselect_b32 s4, 14, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_mov_b32 s21, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	s_cmp_lt_i32 s26, 1
	s_cbranch_scc1 .LBB1_113
; %bb.27:                               ; %.preheader41.lr.ph
	s_cmp_gt_i32 s27, 0
	s_load_b64 s[28:29], s[18:19], 0x0
	s_cselect_b32 s33, -1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	v_dual_mov_b32 v38, 0 :: v_dual_mov_b32 v45, 2
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v36, 33
	s_cselect_b32 s2, -1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.2@rel32@lo+4
	s_addc_u32 s1, s1, .str.2@rel32@hi+12
	v_cndmask_b32_e64 v0, 0, 1, s2
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s34, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, 0, 1, s0
	v_mov_b32_e32 v46, 1
	v_lshlrev_b32_e32 v40, 2, v0
	v_lshlrev_b32_e32 v41, 1, v1
.LBB1_28:                               ; %.preheader41
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_30 Depth 2
                                        ;       Child Loop BB1_33 Depth 3
                                        ;       Child Loop BB1_41 Depth 3
                                        ;       Child Loop BB1_47 Depth 3
                                        ;       Child Loop BB1_56 Depth 3
                                        ;       Child Loop BB1_60 Depth 3
                                        ;       Child Loop BB1_68 Depth 3
                                        ;       Child Loop BB1_74 Depth 3
                                        ;       Child Loop BB1_83 Depth 3
                                        ;     Child Loop BB1_88 Depth 2
                                        ;     Child Loop BB1_96 Depth 2
                                        ;     Child Loop BB1_102 Depth 2
                                        ;     Child Loop BB1_111 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB1_85
; %bb.29:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mul_i32 s35, s34, s27
	s_mov_b32 s36, 0
.LBB1_30:                               ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_33 Depth 3
                                        ;       Child Loop BB1_41 Depth 3
                                        ;       Child Loop BB1_47 Depth 3
                                        ;       Child Loop BB1_56 Depth 3
                                        ;       Child Loop BB1_60 Depth 3
                                        ;       Child Loop BB1_68 Depth 3
                                        ;       Child Loop BB1_74 Depth 3
                                        ;       Child Loop BB1_83 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s20, s36, s35
	v_dual_mov_b32 v37, v42 :: v_dual_mov_b32 v4, 0
	s_lshl_b64 s[0:1], s[20:21], 2
	v_mov_b32_e32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s28, s0
	s_addc_u32 s1, s29, s1
	global_load_b32 v47, v38, s[0:1]
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v37
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_36
; %bb.31:                               ;   in Loop: Header=BB1_30 Depth=2
	global_load_b64 v[2:3], v38, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[24:25] offset:40
	global_load_b64 v[4:5], v38, s[24:25]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_35
; %bb.32:                               ; %.preheader3.i.i.i31.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s3, 0
.LBB1_33:                               ; %.preheader3.i.i.i31
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[24:25] offset:40
	global_load_b64 v[6:7], v38, s[24:25]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_33
; %bb.34:                               ; %Flow261
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_35:                               ; %Flow263
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_36:                               ; %.loopexit4.i.i.i26
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[24:25] offset:40
	global_load_b128 v[0:3], v38, s[24:25]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_38
; %bb.37:                               ;   in Loop: Header=BB1_30 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v38
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_38:                               ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s20, s21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s21
	s_mov_b32 s23, s21
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_46
; %bb.39:                               ;   in Loop: Header=BB1_30 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v38, s[24:25] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_42
; %bb.40:                               ; %.preheader1.i.i.i29.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s8, 0
.LBB1_41:                               ; %.preheader1.i.i.i29
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_41
.LBB1_42:                               ; %Flow259
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[24:25] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_44
; %bb.43:                               ;   in Loop: Header=BB1_30 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_44:                               ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_46
; %bb.45:                               ;   in Loop: Header=BB1_30 Depth=2
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_46:                               ; %Flow260
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_47:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_49
; %bb.48:                               ;   in Loop: Header=BB1_47 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_49:                               ;   in Loop: Header=BB1_47 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_51
; %bb.50:                               ;   in Loop: Header=BB1_47 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_52
.LBB1_51:                               ;   in Loop: Header=BB1_47 Depth=3
	s_mov_b32 s1, -1
.LBB1_52:                               ; %Flow254
                                        ;   in Loop: Header=BB1_47 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_47
; %bb.53:                               ;   in Loop: Header=BB1_30 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_57
; %bb.54:                               ;   in Loop: Header=BB1_30 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[24:25] offset:40
	global_load_b64 v[8:9], v38, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v38, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_57
; %bb.55:                               ; %.preheader.i.i.i28.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s0, 0
.LBB1_56:                               ; %.preheader.i.i.i28
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_56
.LBB1_57:                               ; %__ockl_printf_begin.exit32
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, v40 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_dual_mov_b32 v37, v42 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v37
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_63
; %bb.58:                               ;   in Loop: Header=BB1_30 Depth=2
	global_load_b64 v[4:5], v38, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[24:25] offset:40
	global_load_b64 v[6:7], v38, s[24:25]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_62
; %bb.59:                               ; %.preheader3.i.i.i38.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s3, 0
.LBB1_60:                               ; %.preheader3.i.i.i38
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[24:25] offset:40
	global_load_b64 v[8:9], v38, s[24:25]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_60
; %bb.61:                               ; %Flow247
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_62:                               ; %Flow249
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_63:                               ; %.loopexit4.i.i.i33
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[24:25] offset:40
	global_load_b128 v[4:7], v38, s[24:25]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_65
; %bb.64:                               ;   in Loop: Header=BB1_30 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v38
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s8, v5, vcc_lo
	global_store_b128 v[2:3], v[43:46], off offset:8
.LBB1_65:                               ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	v_cvt_f64_f32_e32 v[2:3], v47
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[8:9], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s20, s21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s22, s21
	s_mov_b32 s23, s21
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s20 :: v_dual_mov_b32 v7, s21
	v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_73
; %bb.66:                               ;   in Loop: Header=BB1_30 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[24:25] offset:32 glc
	global_load_b64 v[0:1], v38, s[24:25] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_69
; %bb.67:                               ; %.preheader1.i.i.i36.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s8, 0
.LBB1_68:                               ; %.preheader1.i.i.i36
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_68
.LBB1_69:                               ; %Flow245
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[24:25] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_71
; %bb.70:                               ;   in Loop: Header=BB1_30 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_71:                               ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_73
; %bb.72:                               ;   in Loop: Header=BB1_30 Depth=2
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_73:                               ; %Flow246
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_74:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_76
; %bb.75:                               ;   in Loop: Header=BB1_74 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_76:                               ;   in Loop: Header=BB1_74 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_78
; %bb.77:                               ;   in Loop: Header=BB1_74 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_79
.LBB1_78:                               ;   in Loop: Header=BB1_74 Depth=3
	s_mov_b32 s1, -1
.LBB1_79:                               ; %Flow240
                                        ;   in Loop: Header=BB1_74 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_74
; %bb.80:                               ;   in Loop: Header=BB1_30 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_84
; %bb.81:                               ;   in Loop: Header=BB1_30 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[24:25] offset:40
	global_load_b64 v[6:7], v38, s[24:25] offset:24 glc
	global_load_b64 v[4:5], v38, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_84
; %bb.82:                               ; %.preheader.i.i.i35.preheader
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_mov_b32 s0, 0
.LBB1_83:                               ; %.preheader.i.i.i35
                                        ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_83
.LBB1_84:                               ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB1_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s36, s36, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s36, s27
	s_cbranch_scc0 .LBB1_30
.LBB1_85:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_28 Depth=1
	v_dual_mov_b32 v37, v42 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_91
; %bb.86:                               ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[2:3], v38, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[24:25] offset:40
	global_load_b64 v[4:5], v38, s[24:25]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_90
; %bb.87:                               ; %.preheader3.i.i.i24.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s3, 0
.LBB1_88:                               ; %.preheader3.i.i.i24
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[24:25] offset:40
	global_load_b64 v[6:7], v38, s[24:25]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_88
; %bb.89:                               ; %Flow233
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_90:                               ; %Flow235
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_91:                               ; %.loopexit4.i.i.i19
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[24:25] offset:40
	global_load_b128 v[0:3], v38, s[24:25]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_93
; %bb.92:                               ;   in Loop: Header=BB1_28 Depth=1
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v38
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_93:                               ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s20, s21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s21
	s_mov_b32 s23, s21
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_101
; %bb.94:                               ;   in Loop: Header=BB1_28 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v38, s[24:25] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_97
; %bb.95:                               ; %.preheader1.i.i.i22.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s8, 0
.LBB1_96:                               ; %.preheader1.i.i.i22
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_96
.LBB1_97:                               ; %Flow231
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[24:25] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_99
; %bb.98:                               ;   in Loop: Header=BB1_28 Depth=1
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_99:                               ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_101
; %bb.100:                              ;   in Loop: Header=BB1_28 Depth=1
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_101:                              ; %Flow232
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_102:                              ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_104
; %bb.103:                              ;   in Loop: Header=BB1_102 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_104:                              ;   in Loop: Header=BB1_102 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_106
; %bb.105:                              ;   in Loop: Header=BB1_102 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_107
.LBB1_106:                              ;   in Loop: Header=BB1_102 Depth=2
	s_mov_b32 s1, -1
.LBB1_107:                              ; %Flow226
                                        ;   in Loop: Header=BB1_102 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_102
; %bb.108:                              ;   in Loop: Header=BB1_28 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_112
; %bb.109:                              ;   in Loop: Header=BB1_28 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[24:25] offset:40
	global_load_b64 v[8:9], v38, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v38, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_112
; %bb.110:                              ; %.preheader.i.i.i21.preheader
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_mov_b32 s0, 0
.LBB1_111:                              ; %.preheader.i.i.i21
                                        ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_111
.LBB1_112:                              ; %__ockl_printf_begin.exit25
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.2@rel32@lo+4
	s_addc_u32 s1, s1, .str.2@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, v41 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, 1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	s_add_i32 s34, s34, 1
	s_cmp_eq_u32 s34, s26
	s_cbranch_scc0 .LBB1_28
.LBB1_113:                              ; %._crit_edge53
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v42
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v42
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_119
; %bb.114:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v0, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[24:25] offset:40
	global_load_b64 v[3:4], v0, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v6
	v_and_b32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v3, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
	global_load_b64 v[4:5], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[6:7]
	s_cbranch_execz .LBB1_118
; %bb.115:                              ; %.preheader3.i.i.i17.preheader
	s_mov_b32 s3, 0
.LBB1_116:                              ; %.preheader3.i.i.i17
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[24:25] offset:40
	global_load_b64 v[8:9], v0, s[24:25]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, v1, v6
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
	v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
	global_load_b64 v[4:5], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_116
; %bb.117:                              ; %Flow219
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_118:                              ; %Flow221
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_119:                              ; %.loopexit4.i.i.i12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v43, 0
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_clause 0x1
	global_load_b64 v[6:7], v43, s[24:25] offset:40
	global_load_b128 v[0:3], v43, s[24:25]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_121
; %bb.120:
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, v43
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo
	v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB1_121:
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[42:43]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	s_mov_b32 s11, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v42, 33 :: v_dual_mov_b32 v45, v43
	v_mov_b32_e32 v44, v43
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
	s_clause 0x3
	global_store_b128 v[6:7], v[42:45], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_129
; %bb.122:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2
	v_mov_b32_e32 v12, s3
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v10, s[24:25] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB1_125
; %bb.123:                              ; %.preheader1.i.i.i15.preheader
	s_mov_b32 s8, 0
.LBB1_124:                              ; %.preheader1.i.i.i15
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_124
.LBB1_125:                              ; %Flow217
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	global_load_b64 v[2:3], v5, s[24:25] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_127
; %bb.126:
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_127:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_129
; %bb.128:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_129:                              ; %Flow218
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_130:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_132
; %bb.131:                              ;   in Loop: Header=BB1_130 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_132:                              ;   in Loop: Header=BB1_130 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_134
; %bb.133:                              ;   in Loop: Header=BB1_130 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_135
.LBB1_134:                              ;   in Loop: Header=BB1_130 Depth=1
	s_mov_b32 s1, -1
.LBB1_135:                              ; %Flow212
                                        ;   in Loop: Header=BB1_130 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_130
; %bb.136:
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_140
; %bb.137:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[24:25] offset:40
	global_load_b64 v[9:10], v8, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v8, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_140
; %bb.138:                              ; %.preheader.i.i.i14.preheader
	s_mov_b32 s0, 0
.LBB1_139:                              ; %.preheader.i.i.i14
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_139
.LBB1_140:                              ; %__ockl_printf_begin.exit18
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.2@rel32@lo+4
	s_addc_u32 s1, s1, .str.2@rel32@hi+12
	v_mov_b32_e32 v6, 1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v5, 0
	s_cselect_b32 s2, -1, 0
	v_mov_b32_e32 v3, s1
	v_cndmask_b32_e64 v2, 0, 1, s2
	s_add_u32 s8, s18, 16
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	v_lshlrev_b32_e32 v4, 1, v2
	v_mov_b32_e32 v2, s0
	s_swappc_b64 s[30:31], s[2:3]
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8printMatPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 48
		.amdhsa_next_free_sgpr 37
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8printMatPfii, .Lfunc_end1-_Z8printMatPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7252
; NumSgprs: 39
; NumVgprs: 48
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 39
; NumVGPRsForWavesPerEU: 48
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11initMatCudaPffi     ; -- Begin function _Z11initMatCudaPffi
	.globl	_Z11initMatCudaPffi
	.p2align	8
	.type	_Z11initMatCudaPffi,@function
_Z11initMatCudaPffi:                    ; @_Z11initMatCudaPffi
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x1c
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s7, s6
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v0
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v3, s4 :: v_dual_lshlrev_b32 v0, 1, v0
	v_mov_b32_e32 v2, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11initMatCudaPffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11initMatCudaPffi, .Lfunc_end2-_Z11initMatCudaPffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z14copyMatrixCudaPfS_ii ; -- Begin function _Z14copyMatrixCudaPfS_ii
	.globl	_Z14copyMatrixCudaPfS_ii
	.p2align	8
	.type	_Z14copyMatrixCudaPfS_ii,@function
_Z14copyMatrixCudaPfS_ii:               ; @_Z14copyMatrixCudaPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x24
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s7, s6
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off offset:4
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14copyMatrixCudaPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z14copyMatrixCudaPfS_ii, .Lfunc_end3-_Z14copyMatrixCudaPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13transposeCudaPfS_ii ; -- Begin function _Z13transposeCudaPfS_ii
	.globl	_Z13transposeCudaPfS_ii
	.p2align	8
	.type	_Z13transposeCudaPfS_ii,@function
_Z13transposeCudaPfS_ii:                ; @_Z13transposeCudaPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s8, s14, 5
	s_lshl_b32 s9, s15, 5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, s8, v3
	v_add_nc_u32_e32 v1, s9, v2
	v_lshlrev_b32_e32 v6, 2, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v1, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s0, s2, v1
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, s6, v4
	v_add_co_ci_u32_e64 v1, s1, s7, v5, s1
	v_mad_u32_u24 v4, 0x84, v3, v6
	s_mov_b32 s1, -8
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_3
; %bb.2:                                ;   in Loop: Header=BB4_1 Depth=1
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
.LBB4_3:                                ;   in Loop: Header=BB4_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s1, s1, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 23
	s_cbranch_scc0 .LBB4_1
; %bb.4:
	v_add_nc_u32_e32 v0, s9, v3
	v_add_nc_u32_e32 v1, s8, v2
	v_lshlrev_b32_e32 v6, 2, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_cmp_gt_i32_e64 s0, s2, v0
	v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	v_mad_u32_u24 v2, 0x84, v2, v6
	buffer_gl0_inv
	s_and_b32 s0, s0, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v0, s1, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s1, s5, v4, s1
	s_mov_b32 s1, -8
.LBB4_5:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB4_7
; %bb.6:                                ;   in Loop: Header=BB4_5 Depth=1
	ds_load_b32 v3, v2
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB4_7:                                ;   in Loop: Header=BB4_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s1, s1, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 23
	s_cbranch_scc0 .LBB4_5
; %bb.8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13transposeCudaPfS_ii
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13transposeCudaPfS_ii, .Lfunc_end4-_Z13transposeCudaPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18matrixMultiplyCudaPfS_S_iii ; -- Begin function _Z18matrixMultiplyCudaPfS_S_iii
	.globl	_Z18matrixMultiplyCudaPfS_S_iii
	.p2align	8
	.type	_Z18matrixMultiplyCudaPfS_S_iii,@function
_Z18matrixMultiplyCudaPfS_S_iii:        ; @_Z18matrixMultiplyCudaPfS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v6, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_10
; %bb.1:                                ; %.preheader
	s_cmp_lg_u32 s4, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s6, 1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s2, s3
	s_and_b32 s2, s7, exec_lo
	s_cselect_b32 s2, 32, 1
	s_ashr_i32 s12, s5, 31
	v_cvt_f32_ubyte0_e32 v2, s2
	s_sub_i32 s4, 0, s2
	s_add_i32 s8, s5, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s13, s8, s12
	v_rcp_iflag_f32_e32 v2, v2
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s3, v2
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s3
	s_mul_hi_u32 s4, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s4
	s_mul_hi_u32 s3, s13, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s3, s2
	s_sub_i32 s4, s13, s4
	s_add_i32 s13, s3, 1
	s_sub_i32 s14, s4, s2
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s3, s13, s3
	s_cselect_b32 s4, s14, s4
	s_add_i32 s13, s3, 1
	s_cmp_ge_u32 s4, s2
	s_mov_b32 s4, 0
	s_cselect_b32 s3, s13, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s12
	s_sub_i32 s3, s3, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, 0
	s_cbranch_scc1 .LBB5_9
; %bb.2:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v6
	v_lshlrev_b32_e32 v7, 7, v3
	s_and_b32 s7, s7, exec_lo
	s_cselect_b32 s7, 5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v8, 0x1000, v2
	v_mad_u64_u32 v[4:5], null, v0, s5, v[6:7]
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v8, v7
.LBB5_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_4 Depth 2
	s_lshl_b32 s12, s4, s7
	s_mov_b32 s13, s2
	v_add_nc_u32_e32 v10, s12, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, s12, v4
	v_mad_u64_u32 v[11:12], null, v10, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s0, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	global_load_b32 v13, v[9:10], off
	global_load_b32 v11, v[11:12], off
	v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v9, v8
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_4:                                ;   Parent Loop BB5_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_ge_i32 s12, s5
	s_cbranch_scc1 .LBB5_6
; %bb.5:                                ;   in Loop: Header=BB5_4 Depth=2
	ds_load_b32 v11, v10
	ds_load_b32 v12, v9
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v11, v12
.LBB5_6:                                ;   in Loop: Header=BB5_4 Depth=2
	v_add_nc_u32_e32 v10, 4, v10
	v_add_nc_u32_e32 v9, 0x80, v9
	s_add_i32 s13, s13, -1
	s_add_i32 s12, s12, 1
	s_cmp_lg_u32 s13, 0
	s_cbranch_scc1 .LBB5_4
; %bb.7:                                ;   in Loop: Header=BB5_3 Depth=1
	s_add_i32 s12, s4, 1
	s_cmp_lg_u32 s4, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB5_9
; %bb.8:                                ;   in Loop: Header=BB5_3 Depth=1
	s_mov_b32 s4, s12
	s_branch .LBB5_3
.LBB5_9:                                ; %._crit_edge
	v_mad_u64_u32 v[3:4], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB5_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18matrixMultiplyCudaPfS_S_iii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z18matrixMultiplyCudaPfS_S_iii, .Lfunc_end5-_Z18matrixMultiplyCudaPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 672
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z13matrixAddCudaPfS_fii ; -- Begin function _Z13matrixAddCudaPfS_fii
	.globl	_Z13matrixAddCudaPfS_fii
	.p2align	8
	.type	_Z13matrixAddCudaPfS_fii,@function
_Z13matrixAddCudaPfS_fii:               ; @_Z13matrixAddCudaPfS_fii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b64 s[8:9], s[0:1], 0x2c
	v_bfe_u32 v1, v0, 20, 10
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_and_b32 s3, s9, 0xffff
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s2, s8, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s2, s8, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s6, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b64 v[4:5], v[0:1], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v4, s4, v6, v4
	global_store_b32 v[0:1], v4, off
	global_load_b32 v2, v[2:3], off offset:4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, s4, v2
	global_store_b32 v[0:1], v5, off offset:4
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matrixAddCudaPfS_fii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z13matrixAddCudaPfS_fii, .Lfunc_end6-_Z13matrixAddCudaPfS_fii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z16negateMatrixCudaPfii ; -- Begin function _Z16negateMatrixCudaPfii
	.globl	_Z16negateMatrixCudaPfii
	.p2align	8
	.type	_Z16negateMatrixCudaPfii,@function
_Z16negateMatrixCudaPfii:               ; @_Z16negateMatrixCudaPfii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x1c
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s7, s6
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v2, 0x80000000, v2
	global_store_b32 v[0:1], v2, off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16negateMatrixCudaPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z16negateMatrixCudaPfii, .Lfunc_end7-_Z16negateMatrixCudaPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13matrixPosCudaPfS_ii ; -- Begin function _Z13matrixPosCudaPfS_ii
	.globl	_Z13matrixPosCudaPfS_ii
	.p2align	8
	.type	_Z13matrixPosCudaPfS_ii,@function
_Z13matrixPosCudaPfS_ii:                ; @_Z13matrixPosCudaPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x24
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s7, s6
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_max_f32_e32 v2, v2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f32_e32 v2, 0, v2
	global_store_b32 v[0:1], v2, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matrixPosCudaPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z13matrixPosCudaPfS_ii, .Lfunc_end8-_Z13matrixPosCudaPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13matrixNegCudaPfS_ii ; -- Begin function _Z13matrixNegCudaPfS_ii
	.globl	_Z13matrixNegCudaPfS_ii
	.p2align	8
	.type	_Z13matrixNegCudaPfS_ii,@function
_Z13matrixNegCudaPfS_ii:                ; @_Z13matrixNegCudaPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x24
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s7, s6
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB9_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_max_f32_e64 v2, -v2, -v2
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f32_e32 v2, 0, v2
	global_store_b32 v[0:1], v2, off
.LBB9_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matrixNegCudaPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z13matrixNegCudaPfS_ii, .Lfunc_end9-_Z13matrixNegCudaPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z15diagonalAddCudaPfS_i ; -- Begin function _Z15diagonalAddCudaPfS_i
	.globl	_Z15diagonalAddCudaPfS_i
	.p2align	8
	.type	_Z15diagonalAddCudaPfS_i,@function
_Z15diagonalAddCudaPfS_i:               ; @_Z15diagonalAddCudaPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b64 s[4:5], s[0:1], 0x24
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_and_b32 s3, s5, 0xffff
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_load_b32 s2, s[0:1], 0x10
	s_lshr_b32 s3, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB10_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	v_mad_u64_u32 v[1:2], null, v0, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_max_f32_e32 v3, v3, v3
	v_max_f32_e32 v2, 0x40a00000, v3
	global_store_b32 v[0:1], v2, off
.LBB10_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15diagonalAddCudaPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z15diagonalAddCudaPfS_i, .Lfunc_end10-_Z15diagonalAddCudaPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z11compareCudaPfS_Pii  ; -- Begin function _Z11compareCudaPfS_Pii
	.globl	_Z11compareCudaPfS_Pii
	.p2align	8
	.type	_Z11compareCudaPfS_Pii,@function
_Z11compareCudaPfS_Pii:                 ; @_Z11compareCudaPfS_Pii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b64 s[4:5], s[0:1], 0x2c
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_and_b32 s3, s5, 0xffff
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_load_b32 s2, s[0:1], 0x18
	s_lshr_b32 s3, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB11_3
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s2, 0xa0b5ed8d
	s_mov_b32 s3, 0x3eb0c6f7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[0:1], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[2:3]
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f32_e32 v0, 0x358637bd, v0
	v_add_f32_e32 v0, v2, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, v3, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB11_3
; %bb.2:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v0, s[0:1]
.LBB11_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11compareCudaPfS_Pii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z11compareCudaPfS_Pii, .Lfunc_end11-_Z11compareCudaPfS_Pii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z8updYCudaPfS_S_S_i    ; -- Begin function _Z8updYCudaPfS_S_S_i
	.globl	_Z8updYCudaPfS_S_S_i
	.p2align	8
	.type	_Z8updYCudaPfS_S_S_i,@function
_Z8updYCudaPfS_S_S_i:                   ; @_Z8updYCudaPfS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_load_b64 s[4:5], s[0:1], 0x34
	v_bfe_u32 v1, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_and_b32 s3, s5, 0xffff
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	s_load_b32 s2, s[0:1], 0x20
	s_lshr_b32 s3, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB12_2
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v3, null, v4, v4, v6
	v_div_scale_f32 v8, vcc_lo, v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v3, v5, 1.0
	v_fmac_f32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v8, v5
	v_fma_f32 v9, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v5
	v_fma_f32 v3, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v3, v5, v7
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_div_fixup_f32 v3, v3, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB12_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8updYCudaPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
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		.amdhsa_next_free_sgpr 16
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		.amdhsa_float_denorm_mode_16_64 3
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		.amdhsa_memory_ordered 1
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		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
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	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z8updYCudaPfS_S_S_i, .Lfunc_end12-_Z8updYCudaPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
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	.size	.str, 14

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"%f "
	.size	.str.1, 4

	.type	.str.2,@object                  ; @.str.2
.str.2:
	.asciz	"\n"
	.size	.str.2, 2

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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amdhsa.version:
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...

	.end_amdgpu_metadata
