#include<stdio.h>
#include <cuda.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
        int col=threadIdx.x+blockIdx.x*blockDim.x;
        int row=threadIdx.y+blockIdx.y*blockDim.y;
        int num=col+row*n;
        int neighbor=0;
        //cell in the middle has eight neighbors,
        //a cell in a corner has only three neighbors,
        //a cell on an edge has five neighbors. 
    if(col<n && row<n){     
        //corner 3
            //In order to move to corner,
            //it should move either diagonal or move left/right and move up/down
        //top left corner
        if(col==0 && row==0){
            neighbor+=x[num+1]; //move right
            neighbor+=x[num+n];  //move bottom
            neighbor+=x[num+n+1]; //bottom right
        }
        //bottom left corner
        else if(col==0 && row==n-1){
            neighbor+=x[num+1];   //move right
            neighbor+=x[num-n];   //move up
            neighbor+=x[num-n+1]; //top right
        }
        //bottom right
        else if(col==n-1 && row==n-1){  
                neighbor+=x[num-1];   //move left
                neighbor+=x[num-n];  //move up
                neighbor+=x[num-n-1]; //top left
        }
        //edge 5
        //In order to move to edge
        // it should just move to left/right/up/down (including corner)
        //top edge
        else if(row==0 && col>0 && col<n-1){    
                neighbor+=x[num-1]; //left
                neighbor+=x[num+1]; //right
                neighbor+=x[num+n-1]; //bottom left -- corner
                neighbor+=x[num+n];   //bottom
                neighbor+=x[num+n+1]; //bottom right -- corner
        }
        //bottom edge
        else if(row==n-1 && col>0 && col<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num+1]; //right
                neighbor+=x[num-n+1]; //Top right-- corner
                neighbor+=x[num-n];   //Top
                neighbor+=x[num-n-1]; //Top left -- corner   
        }
        //Left edge
        else if(col==0 && row>0 && row<n-1){    
                neighbor+=x[num+1]; //right
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n+1]; //Top right-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n+1]; //Bottom right-- corner     
        }
        //Right edge
        else if(col==n-1 && row>0 && row<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n-1]; //Top left-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n-1]; //Bottom left-- corner       
        }
         //Right edge
        else if(col==n-1 && row>0 && row<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n-1]; //Top left-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n-1]; //Bottom left-- corner       
        }

        //cell in the middle has eight neighbors,        
        else{   
                neighbor+=x[num-1];//left  
                neighbor+=x[num+1];   //right
                neighbor+=x[num-n-1];//top left
                neighbor+=x[num-n];    //top
                neighbor+=x[num-n+1];  //top right
                neighbor+=x[num+n-1];  //bottom left
                neighbor+=x[num+n];    //bottom
                neighbor+=x[num+n+1];  //bottom right
        }
        //Die : 0
        //Live: 1
        //A live cell with zero or one live neighbor dies from loneliness.
        if(x[num]==1 && (neighbor ==0 || neighbor ==1))
                y[num]=0;
        //A live cell with four or more live neighbors dies due to overpopulation.
        else if(x[num]==1 && neighbor>=4)
                y[num]=0;
        //A dead cell with two or three live neighbors becomes alive.
        else if(x[num]==1 && (neighbor==2 || neighbor==3))
                y[num]=1;
        //Otherwise, a cell's state stays unchanged
        else
            y[num] = x[num];
    }
}


int main(void){
        int i,j,k;
        int row= 6;
        int col= 4;
        int start[row][col];
        int Round[row][col];
        dim3 threadsPerBlock(32,32);
        dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
        int* x;
        int* y;
        int generation =1;// maximum generation/iteration
        float milliseconds=0;
        cudaEvent_t t_start,t_stop;
        cudaEventCreate(&t_start);
        cudaEventCreate(&t_stop);
        //Initilazie the matrix of the x Generated cell
        for(i=0;i<row;i++)
                for(j=0;j<col;j++)
                        start[i][j]=rand()%2;
         //Initilazie the matrix of the y Generated cell
        for(i=0;i<row;i++)
                for(j=0;j<col;j++)
                        Round[i][j]=0;
   
        cudaMalloc((void **) &x,sizeof(int)*row*col);
        cudaMemcpy(x,start,sizeof(int)*row*col,cudaMemcpyHostToDevice);


        printf("Start\n");
        printf("-------\n");
        for(i=0;i<row;i++)
        {
                for(j=0;j<col;j++)
                {
                    if(start[i][j]){
                        printf(" 0");
                    }
                    else{
                        printf(" 1");
                    }
                }
                printf("\n");
        }

        for(k=0;k<= generation;k++)
        {  
            cudaEventRecord(t_start);
            compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
            cudaEventRecord(t_stop);
            cudaMalloc((void **) &y,sizeof(int)*row*col);

            cudaMemcpy(Round,y,sizeof(int)*row*col,cudaMemcpyDeviceToHost);

                printf("\n Round %d \n",k);
                printf("-------\n");
                    for(i=0;i<row;i++)
                    {
                        for(j=0;j<col;j++)
                        {
                            if(Round[i][j])
                            {
                                   printf(" 0");
                            }
                            else{
                                printf(" 1");
                            }
                        }
                        printf("\n");
                    }   
        cudaEventElapsedTime(&milliseconds,t_start,t_stop);
        printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
      
    }
        

        return 0;
}



	.file	"tmpxft_002eb00c_00000000-6_game.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z7computePiS_iPiS_i
	.type	_Z29__device_stub__Z7computePiS_iPiS_i, @function
_Z29__device_stub__Z7computePiS_iPiS_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7computePiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z29__device_stub__Z7computePiS_iPiS_i, .-_Z29__device_stub__Z7computePiS_iPiS_i
	.globl	_Z7computePiS_i
	.type	_Z7computePiS_i, @function
_Z7computePiS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7computePiS_iPiS_i
	.cfi_endproc
.LFE2053:
	.size	_Z7computePiS_i, .-_Z7computePiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Start\n"
.LC2:
	.string	"-------\n"
.LC3:
	.string	" 0"
.LC4:
	.string	" 1"
.LC5:
	.string	"\n"
.LC6:
	.string	"\n Round %d \n"
.LC7:
	.string	"Time taken for this computation = %f milliseconds\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$2, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	movabsq	$4294967328, %rax
	leaq	32(%rsp), %rdi
	movq	%rcx, 60(%rsp)
	leaq	72(%rsp), %rbp
	movl	$1, 68(%rsp)
	leaq	168(%rsp), %rbx
	movq	%rbp, %r13
	movl	$0x00000000, 12(%rsp)
	movq	%rax, 52(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
.L9:
	xorl	%r12d, %r12d
.L10:
	call	rand@PLT
	cltd
	idivl	%r14d
	movl	%edx, 0(%r13,%r12,4)
	incq	%r12
	cmpq	$4, %r12
	jne	.L10
	addq	$16, %r13
	cmpq	%rbx, %r13
	jne	.L9
	leaq	264(%rsp), %r14
	movq	%rbx, %rax
.L12:
	xorl	%edx, %edx
	addq	$16, %rax
	movl	%edx, -16(%rax)
	movl	%edx, -12(%rax)
	movl	%edx, -8(%rax)
	movl	%edx, -4(%rax)
	cmpq	%r14, %rax
	jne	.L12
	leaq	16(%rsp), %rdi
	movl	$96, %esi
	leaq	.LC4(%rip), %r12
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$96, %edx
	call	cudaMemcpy@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L13:
	xorl	%r13d, %r13d
.L16:
	cmpl	$0, 0(%rbp,%r13,4)
	leaq	.LC3(%rip), %rsi
	jne	.L32
	movq	%r12, %rsi
.L32:
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$4, %r13
	jne	.L16
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$16, %rbp
	call	__printf_chk@PLT
	cmpq	%rbx, %rbp
	jne	.L13
	xorl	%r13d, %r13d
.L17:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movl	$32, 48(%rsp)
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	48(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	24(%rsp), %rdi
	movl	$6, %edx
	movq	%rdi, %rsi
	call	_Z29__device_stub__Z7computePiS_iPiS_i
.L18:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbx, %r12
	leaq	.LC4(%rip), %r15
	call	cudaEventRecord@PLT
	leaq	24(%rsp), %rdi
	movl	$96, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$96, %edx
	call	cudaMemcpy@PLT
	movl	%r13d, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	xorl	%ebp, %ebp
.L22:
	cmpl	$0, (%r12,%rbp,4)
	leaq	.LC3(%rip), %rsi
	jne	.L33
	movq	%r15, %rsi
.L33:
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$4, %rbp
	jne	.L22
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$16, %r12
	call	__printf_chk@PLT
	cmpq	%r14, %r12
	jne	.L19
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdx
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	testl	%r13d, %r13d
	jne	.L34
	movl	$1, %r13d
	jmp	.L17
.L34:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z7computePiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7computePiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
        int col=threadIdx.x+blockIdx.x*blockDim.x;
        int row=threadIdx.y+blockIdx.y*blockDim.y;
        int num=col+row*n;
        int neighbor=0;
        //cell in the middle has eight neighbors,
        //a cell in a corner has only three neighbors,
        //a cell on an edge has five neighbors. 
    if(col<n && row<n){     
        //corner 3
            //In order to move to corner,
            //it should move either diagonal or move left/right and move up/down
        //top left corner
        if(col==0 && row==0){
            neighbor+=x[num+1]; //move right
            neighbor+=x[num+n];  //move bottom
            neighbor+=x[num+n+1]; //bottom right
        }
        //bottom left corner
        else if(col==0 && row==n-1){
            neighbor+=x[num+1];   //move right
            neighbor+=x[num-n];   //move up
            neighbor+=x[num-n+1]; //top right
        }
        //bottom right
        else if(col==n-1 && row==n-1){  
                neighbor+=x[num-1];   //move left
                neighbor+=x[num-n];  //move up
                neighbor+=x[num-n-1]; //top left
        }
        //edge 5
        //In order to move to edge
        // it should just move to left/right/up/down (including corner)
        //top edge
        else if(row==0 && col>0 && col<n-1){    
                neighbor+=x[num-1]; //left
                neighbor+=x[num+1]; //right
                neighbor+=x[num+n-1]; //bottom left -- corner
                neighbor+=x[num+n];   //bottom
                neighbor+=x[num+n+1]; //bottom right -- corner
        }
        //bottom edge
        else if(row==n-1 && col>0 && col<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num+1]; //right
                neighbor+=x[num-n+1]; //Top right-- corner
                neighbor+=x[num-n];   //Top
                neighbor+=x[num-n-1]; //Top left -- corner   
        }
        //Left edge
        else if(col==0 && row>0 && row<n-1){    
                neighbor+=x[num+1]; //right
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n+1]; //Top right-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n+1]; //Bottom right-- corner     
        }
        //Right edge
        else if(col==n-1 && row>0 && row<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n-1]; //Top left-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n-1]; //Bottom left-- corner       
        }
         //Right edge
        else if(col==n-1 && row>0 && row<n-1){  
                neighbor+=x[num-1]; //left
                neighbor+=x[num-n]; //Top
                neighbor+=x[num-n-1]; //Top left-- corner
                neighbor+=x[num+n];   //Bottom
                neighbor+=x[num+n-1]; //Bottom left-- corner       
        }

        //cell in the middle has eight neighbors,        
        else{   
                neighbor+=x[num-1];//left  
                neighbor+=x[num+1];   //right
                neighbor+=x[num-n-1];//top left
                neighbor+=x[num-n];    //top
                neighbor+=x[num-n+1];  //top right
                neighbor+=x[num+n-1];  //bottom left
                neighbor+=x[num+n];    //bottom
                neighbor+=x[num+n+1];  //bottom right
        }
        //Die : 0
        //Live: 1
        //A live cell with zero or one live neighbor dies from loneliness.
        if(x[num]==1 && (neighbor ==0 || neighbor ==1))
                y[num]=0;
        //A live cell with four or more live neighbors dies due to overpopulation.
        else if(x[num]==1 && neighbor>=4)
                y[num]=0;
        //A dead cell with two or three live neighbors becomes alive.
        else if(x[num]==1 && (neighbor==2 || neighbor==3))
                y[num]=1;
        //Otherwise, a cell's state stays unchanged
        else
            y[num] = x[num];
    }
}


int main(void){
        int i,j,k;
        int row= 6;
        int col= 4;
        int start[row][col];
        int Round[row][col];
        dim3 threadsPerBlock(32,32);
        dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
        int* x;
        int* y;
        int generation =1;// maximum generation/iteration
        float milliseconds=0;
        hipEvent_t t_start,t_stop;
        hipEventCreate(&t_start);
        hipEventCreate(&t_stop);
        //Initilazie the matrix of the x Generated cell
        for(i=0;i<row;i++)
                for(j=0;j<col;j++)
                        start[i][j]=rand()%2;
         //Initilazie the matrix of the y Generated cell
        for(i=0;i<row;i++)
                for(j=0;j<col;j++)
                        Round[i][j]=0;
   
        hipMalloc((void **) &x,sizeof(int)*row*col);
        hipMemcpy(x,start,sizeof(int)*row*col,hipMemcpyHostToDevice);


        printf("Start\n");
        printf("-------\n");
        for(i=0;i<row;i++)
        {
                for(j=0;j<col;j++)
                {
                    if(start[i][j]){
                        printf(" 0");
                    }
                    else{
                        printf(" 1");
                    }
                }
                printf("\n");
        }

        for(k=0;k<= generation;k++)
        {  
            hipEventRecord(t_start);
            compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
            hipEventRecord(t_stop);
            hipMalloc((void **) &y,sizeof(int)*row*col);

            hipMemcpy(Round,y,sizeof(int)*row*col,hipMemcpyDeviceToHost);

                printf("\n Round %d \n",k);
                printf("-------\n");
                    for(i=0;i<row;i++)
                    {
                        for(j=0;j<col;j++)
                        {
                            if(Round[i][j])
                            {
                                   printf(" 0");
                            }
                            else{
                                printf(" 1");
                            }
                        }
                        printf("\n");
                    }   
        hipEventElapsedTime(&milliseconds,t_start,t_stop);
        printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
      
    }
        

        return 0;
}



	.text
	.file	"game.hip"
	.globl	_Z22__device_stub__computePiS_i # -- Begin function _Z22__device_stub__computePiS_i
	.type	_Z22__device_stub__computePiS_i,@function
_Z22__device_stub__computePiS_i:        # @_Z22__device_stub__computePiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7computePiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__computePiS_i, .Lfunc_end0-_Z22__device_stub__computePiS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$0, 12(%rsp)
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	144(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB1_1:                                # %.preheader74
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r15d, %r15d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	andl	$-2, %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	incq	%r15
	cmpq	$4, %r15
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r14
	addq	$16, %rbx
	cmpq	$6, %r14
	jne	.LBB1_1
# %bb.4:                                # %.preheader72.preheader
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 128(%rsp)
	movaps	%xmm0, 112(%rsp)
	movaps	%xmm0, 96(%rsp)
	movaps	%xmm0, 80(%rsp)
	movaps	%xmm0, 64(%rsp)
	movaps	%xmm0, 48(%rsp)
	leaq	40(%rsp), %rbx
	movl	$96, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	144(%rsp), %rbx
	movl	$96, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB1_5:                                # %.preheader71
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_6 Depth 2
	xorl	%r15d, %r15d
.LBB1_6:                                #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	$0, (%rbx,%r15,4)
	movl	$.L.str.3, %edi
	je	.LBB1_8
# %bb.7:                                #   in Loop: Header=BB1_6 Depth=2
	movl	$.L.str.2, %edi
.LBB1_8:                                #   in Loop: Header=BB1_6 Depth=2
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$4, %r15
	jne	.LBB1_6
# %bb.9:                                #   in Loop: Header=BB1_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$16, %rbx
	cmpq	$6, %r14
	jne	.LBB1_5
# %bb.10:                               # %.preheader70.preheader
	movb	$1, %r13b
	leaq	48(%rsp), %r15
	leaq	12(%rsp), %r12
	xorl	%ebp, %ebp
.LBB1_11:                               # %.preheader70
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_14 Depth 2
                                        #       Child Loop BB1_15 Depth 3
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	xorl	%edi, %edi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:                               #   in Loop: Header=BB1_11 Depth=1
	movq	32(%rsp), %rdi
	movq	%rdi, %rsi
	movl	$6, %edx
	callq	_Z22__device_stub__computePiS_i
.LBB1_13:                               #   in Loop: Header=BB1_11 Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$96, %esi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movq	32(%rsp), %rsi
	movl	$96, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	%r15, %rbp
	xorl	%ebx, %ebx
.LBB1_14:                               # %.preheader
                                        #   Parent Loop BB1_11 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_15 Depth 3
	xorl	%r14d, %r14d
.LBB1_15:                               #   Parent Loop BB1_11 Depth=1
                                        #     Parent Loop BB1_14 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	cmpl	$0, (%rbp,%r14,4)
	movl	$.L.str.3, %edi
	je	.LBB1_17
# %bb.16:                               #   in Loop: Header=BB1_15 Depth=3
	movl	$.L.str.2, %edi
.LBB1_17:                               #   in Loop: Header=BB1_15 Depth=3
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$4, %r14
	jne	.LBB1_15
# %bb.18:                               #   in Loop: Header=BB1_14 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	incq	%rbx
	addq	$16, %rbp
	cmpq	$6, %rbx
	jne	.LBB1_14
# %bb.19:                               #   in Loop: Header=BB1_11 Depth=1
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movl	$1, %ebp
	testb	$1, %r13b
	movl	$0, %r13d
	jne	.LBB1_11
# %bb.20:
	xorl	%eax, %eax
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7computePiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7computePiS_i,@object         # @_Z7computePiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z7computePiS_i
	.p2align	3, 0x0
_Z7computePiS_i:
	.quad	_Z22__device_stub__computePiS_i
	.size	_Z7computePiS_i, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	" 0"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" 1"
	.size	.L.str.3, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\n Round %d \n"
	.size	.L.str.5, 13

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Time taken for this computation = %f milliseconds\n\n"
	.size	.L.str.6, 52

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7computePiS_i"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Start"
	.size	.Lstr, 6

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"-------"
	.size	.Lstr.2, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__computePiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7computePiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7computePiS_i         ; -- Begin function _Z7computePiS_i
	.globl	_Z7computePiS_i
	.p2align	8
	.type	_Z7computePiS_i,@function
_Z7computePiS_i:                        ; @_Z7computePiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
	v_mad_u64_u32 v[6:7], null, s14, s2, v[1:2]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v0, v6, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v0
	s_cbranch_execz .LBB0_41
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_or_b32_e32 v2, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, v4, s6, v[6:7]
                                        ; implicit-def: $vgpr7
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.2:
	s_add_i32 s7, s6, -1
	v_cmp_eq_u32_e64 s0, 0, v6
	v_cmp_eq_u32_e64 s1, s7, v4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_xor_b32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_xor_b32 s12, exec_lo, s3
	s_cbranch_execz .LBB0_24
; %bb.3:
	v_cmp_eq_u32_e32 vcc_lo, s7, v6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_b32 s2, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, -1
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s3
	s_cbranch_execz .LBB0_21
; %bb.4:
	v_cmp_eq_u32_e64 s4, 0, v4
	v_cmp_lt_i32_e64 s2, 0, v6
	v_cmp_gt_i32_e64 s3, s7, v6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s4, s2, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, -1
	s_and_saveexec_b32 s14, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s14
	s_cbranch_execz .LBB0_18
; %bb.5:
	s_and_b32 s1, s2, s1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s3, s1
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.6:
	v_cmp_lt_i32_e64 s1, 0, v4
	v_cmp_gt_i32_e64 s2, s7, v4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s7, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s7
	s_cbranch_execz .LBB0_12
; %bb.7:
	v_ashrrev_i32_e32 v1, 31, v0
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, s0, s8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v3, s0
	s_and_b32 s0, vcc_lo, s1
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_b32 s0, s2, s0
	global_load_b32 v6, v[4:5], off offset:-4
	s_xor_b32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_subrev_nc_u32_e32 v2, s6, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[16:17], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[4:5], off offset:4
	global_load_b96 v[7:9], v[2:3], off offset:-4
	v_add_co_u32 v2, vcc_lo, v4, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	global_load_b64 v[4:5], v[2:3], off offset:-4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(1)
	v_add3_u32 v6, v10, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v6, v8, v9
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v6, v4, v5
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr4
.LBB0_9:                                ; %Flow266
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_subrev_nc_u32_e32 v2, s6, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[16:17], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, s16
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[2:3], v[2:3], off offset:-4
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v3, v3, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v3, v2, v7
	v_add_co_u32 v2, vcc_lo, v4, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo
.LBB0_11:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_12:                               ; %Flow268
	s_and_not1_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[14:15], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v4, s14
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v5, vcc_lo
	s_clause 0x2
	global_load_b32 v4, v[4:5], off offset:4
	global_load_b64 v[2:3], v[2:3], off
	global_load_b32 v5, v[8:9], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v2, v3, v5
	v_add_co_u32 v2, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v9, vcc_lo
.LBB0_14:                               ; %Flow269
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_15:                               ; %Flow270
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[4:5], off offset:-4
	global_load_b32 v7, v[4:5], off offset:4
	global_load_b64 v[4:5], v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v6, v7, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v6, v5, v4
.LBB0_17:                               ; %Flow271
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_18:                               ; %Flow272
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[6:7], 2
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[2:3], off offset:-4
	global_load_b32 v7, v[2:3], off offset:4
	global_load_b64 v[2:3], v[4:5], off offset:-4
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v6, v7, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v6, v2, v3
	v_add_co_u32 v2, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
.LBB0_20:                               ; %Flow273
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_21:                               ; %Flow274
	s_and_not1_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off offset:-4
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v5, v4
.LBB0_23:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_24:                               ; %Flow276
	s_and_not1_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off offset:4
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v5, v4
.LBB0_26:                               ; %Flow277
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_27:                               ; %Flow278
	s_and_not1_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_29
; %bb.28:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[2:3], s[6:7], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off offset:4
	global_load_b32 v3, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v3, v2
	v_add_co_u32 v2, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
.LBB0_29:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v3, v[2:3], off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v3, v7, v3
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s0, 1, v2
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s1, 1, v3
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_39
; %bb.30:
	v_cmp_gt_i32_e64 s0, 4, v3
	s_xor_b32 s3, vcc_lo, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_36
; %bb.31:
	v_and_b32_e32 v3, -2, v3
	v_add_co_u32 v0, s0, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s0, s11, v1, s0
	v_cmp_ne_u32_e32 vcc_lo, 2, v3
	s_or_b32 s0, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_xor_b32 s0, exec_lo, s3
	s_cbranch_execz .LBB0_33
; %bb.32:
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_33:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_35
; %bb.34:
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB0_35:                               ; %Flow261
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_36:                               ; %Flow262
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_38
; %bb.37:
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB0_38:                               ; %Flow263
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_39:                               ; %Flow264
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_41
; %bb.40:
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB0_41:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7computePiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7computePiS_i, .Lfunc_end0-_Z7computePiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1828
; NumSgprs: 20
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7computePiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7computePiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
