//
// Created by root on 2020/11/19.
//

#include "stdio.h"
#include "cuda_runtime.h"

#define BDIMX 32
#define BDIMY 32

__global__ void transposeNaiveGem(int *in, int *out, int nx, int ny) {
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    int y = threadIdx.y + blockIdx.y * blockDim.y;

    if (x < nx && y < ny) {
        out[x * ny + y] = in[y * nx + x];
    }
}

__global__ void transposeNaiveGem2(int *in, int *out, int nx, int ny) {
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    int y = threadIdx.y + blockIdx.y * blockDim.y;

    if (x < nx && y < ny) {
        out[y * nx + x] = in[x * ny + y];
        // store is combined but load not
        // Bytes count per request in Pascal seems lower than 128
    }
}

__global__ void transposeSmem(int *in, int *out, int nx, int ny) {
    int ix = blockIdx.x * blockDim.x + threadIdx.x; // thread x coordinate in block(origin matrix)
    int iy = blockIdx.y * blockDim.y + threadIdx.y; // thread y coordinate in block(origin matrix)

    __shared__ int tile[BDIMX][BDIMY];
//    __shared__ int tile[BDIMX][BDIMY + 1]; // We can append one column per row to eliminate store bank conflict

    int ti = iy * nx + ix; // thread data index in matrix / coordinate in origin matrix

    int bidx = threadIdx.y * blockDim.x + threadIdx.x; // thread index in block
    int irow = bidx / blockDim.y; // row of current thread in block
    int icol = bidx % blockDim.y; // column of current thread in block

    ix = blockIdx.y * blockDim.y + icol; // x coordinate in transpose matrix
    iy = blockIdx.x * blockDim.x + irow; // y coordinate in transpose matrix
    int to = iy * ny + ix; // coordinate in transpose matrix

    if (ix < nx && iy < ny) {
        tile[threadIdx.x][threadIdx.y] = in[ti]; // We got bank conflict here, but both the throughput and speed are still higher than global memory
        __syncthreads();
        out[to] = tile[irow][icol]; // Just change the index of data in array
    }
}

__global__ void transposeSmemUnrollPad(int *in, int *out, int nx, int ny) {
    int ix = blockDim.x * blockIdx.x * 2 + threadIdx.x; // thread start x index in block
    int iy = blockDim.y * blockIdx.y + threadIdx.y; // thread start y index in block

    __shared__ int tile[BDIMX * 2][BDIMY + 1];

    int ti = iy * nx + ix; // start data index in block

    int bidx = threadIdx.y * blockDim.x + threadIdx.x; // thread start index in block
    int irow = bidx / blockDim.x; // row in origin matrix
    int icol = bidx % blockDim.x; // column in origin matrix

    int outputIndex = ix * ny + blockIdx.y * BDIMY + irow; // data index in the output array

    if (icol < nx && irow < ny) {
        tile[icol][irow] = in[ti];
        __syncthreads();
        out[outputIndex] = tile[icol][irow];
    }

    if (icol + blockDim.x < nx && irow < ny) {
        tile[icol + blockDim.x][irow] = in[ti + blockDim.x];
        __syncthreads();
        out[outputIndex + blockDim.x * ny] = tile[icol + blockDim.x][irow];
    }
}

int main() {
    int nx = 1024, ny = 1024;
    int nBytes = nx * ny * sizeof(int);

    int *h_in = (int *) malloc(nBytes);
    int *h_out = (int *) malloc(nBytes);

    for (int i = 0; i < nx * ny; i++) {
        h_in[i] = i;
    }

    int *d_in;
    int *d_out;

    cudaMalloc(&d_in, nBytes);
    cudaMalloc(&d_out, nBytes);

    cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice);

    dim3 blockDim(BDIMX, BDIMY);
    dim3 gridDim((nx + blockDim.x - 1) / blockDim.x, (ny + blockDim.y - 1) / blockDim.y);

    transposeNaiveGem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    cudaDeviceSynchronize();
    cudaMemcpy(h_out, d_out, nBytes, cudaMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }
//
//    printf("\n====================\n");

    memset(h_out, 0, nBytes);
    cudaMemset(d_out, 0, nBytes);

    dim3 blockDim_(BDIMX, BDIMY);
    dim3 gridDim_((nx + 2 * blockDim_.x - 1) / (2 * blockDim_.x), (ny + blockDim_.y - 1) / blockDim_.y);

    printf("grid_: (%d, %d), block_: (%d, %d)\n", gridDim_.x, gridDim_.y, blockDim_.x, blockDim_.y);
    transposeSmemUnrollPad<<<gridDim_, blockDim_>>>(d_in, d_out, nx, ny);
    cudaDeviceSynchronize();
    cudaMemcpy(h_out, d_out, nBytes, cudaMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }
//
//    printf("\n====================\n");

    memset(h_out, 0, nBytes);
    cudaMemset(d_out, 0, nBytes);

    transposeSmem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    cudaDeviceSynchronize();
    cudaMemcpy(h_out, d_out, nBytes, cudaMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }

    memset(h_out, 0, nBytes);
    cudaMemset(d_out, 0, nBytes);

    transposeSmem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    cudaDeviceSynchronize();
    cudaMemcpy(h_out, d_out, nBytes, cudaMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }

    cudaFree(d_in);
    cudaFree(d_out);
    free(h_in);
    free(h_out);
}

	.file	"tmpxft_002a2336_00000000-6_transposeMatrixWithSharedMemory.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii
	.type	_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii, @function
_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17transposeNaiveGemPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii, .-_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii
	.globl	_Z17transposeNaiveGemPiS_ii
	.type	_Z17transposeNaiveGemPiS_ii, @function
_Z17transposeNaiveGemPiS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z17transposeNaiveGemPiS_ii, .-_Z17transposeNaiveGemPiS_ii
	.globl	_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii
	.type	_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii, @function
_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18transposeNaiveGem2PiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii, .-_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii
	.globl	_Z18transposeNaiveGem2PiS_ii
	.type	_Z18transposeNaiveGem2PiS_ii, @function
_Z18transposeNaiveGem2PiS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18transposeNaiveGem2PiS_iiPiS_ii
	.cfi_endproc
.LFE2055:
	.size	_Z18transposeNaiveGem2PiS_ii, .-_Z18transposeNaiveGem2PiS_ii
	.globl	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii
	.type	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii, @function
_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13transposeSmemPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii, .-_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii
	.globl	_Z13transposeSmemPiS_ii
	.type	_Z13transposeSmemPiS_ii, @function
_Z13transposeSmemPiS_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii
	.cfi_endproc
.LFE2057:
	.size	_Z13transposeSmemPiS_ii, .-_Z13transposeSmemPiS_ii
	.globl	_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii
	.type	_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii, @function
_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22transposeSmemUnrollPadPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii, .-_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii
	.globl	_Z22transposeSmemUnrollPadPiS_ii
	.type	_Z22transposeSmemUnrollPadPiS_ii, @function
_Z22transposeSmemUnrollPadPiS_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii
	.cfi_endproc
.LFE2059:
	.size	_Z22transposeSmemUnrollPadPiS_ii, .-_Z22transposeSmemUnrollPadPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"grid_: (%d, %d), block_: (%d, %d)\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$4194304, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L24:
	movl	%eax, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax
	jne	.L24
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdi
	movl	$1, %esi
	movl	$1, 44(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 36(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1024, %ecx
	movl	$1024, %edx
	call	_Z41__device_stub__Z17transposeNaiveGemPiS_iiPiS_ii
.L25:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	$1048576, %ecx
	movq	%rbx, %rdi
	rep stosl
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4194304, %edx
	call	cudaMemset@PLT
	movl	$32, %r9d
	movl	$32, %r8d
	movl	$32, %ecx
	movl	$16, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movabsq	$137438953488, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1024, %ecx
	movl	$1024, %edx
	call	_Z46__device_stub__Z22transposeSmemUnrollPadPiS_iiPiS_ii
.L26:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	$1048576, %ecx
	movq	%rbx, %rdi
	rep stosl
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4194304, %edx
	call	cudaMemset@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1024, %ecx
	movl	$1024, %edx
	call	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii
.L27:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	$1048576, %ecx
	movq	%rbx, %rdi
	rep stosl
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4194304, %edx
	call	cudaMemset@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1024, %ecx
	movl	$1024, %edx
	call	_Z37__device_stub__Z13transposeSmemPiS_iiPiS_ii
.L28:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z22transposeSmemUnrollPadPiS_ii"
.LC2:
	.string	"_Z13transposeSmemPiS_ii"
.LC3:
	.string	"_Z18transposeNaiveGem2PiS_ii"
.LC4:
	.string	"_Z17transposeNaiveGemPiS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22transposeSmemUnrollPadPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13transposeSmemPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18transposeNaiveGem2PiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17transposeNaiveGemPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//
// Created by root on 2020/11/19.
//

#include "stdio.h"
#include "hip/hip_runtime.h"

#define BDIMX 32
#define BDIMY 32

__global__ void transposeNaiveGem(int *in, int *out, int nx, int ny) {
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    int y = threadIdx.y + blockIdx.y * blockDim.y;

    if (x < nx && y < ny) {
        out[x * ny + y] = in[y * nx + x];
    }
}

__global__ void transposeNaiveGem2(int *in, int *out, int nx, int ny) {
    int x = threadIdx.x + blockIdx.x * blockDim.x;
    int y = threadIdx.y + blockIdx.y * blockDim.y;

    if (x < nx && y < ny) {
        out[y * nx + x] = in[x * ny + y];
        // store is combined but load not
        // Bytes count per request in Pascal seems lower than 128
    }
}

__global__ void transposeSmem(int *in, int *out, int nx, int ny) {
    int ix = blockIdx.x * blockDim.x + threadIdx.x; // thread x coordinate in block(origin matrix)
    int iy = blockIdx.y * blockDim.y + threadIdx.y; // thread y coordinate in block(origin matrix)

    __shared__ int tile[BDIMX][BDIMY];
//    __shared__ int tile[BDIMX][BDIMY + 1]; // We can append one column per row to eliminate store bank conflict

    int ti = iy * nx + ix; // thread data index in matrix / coordinate in origin matrix

    int bidx = threadIdx.y * blockDim.x + threadIdx.x; // thread index in block
    int irow = bidx / blockDim.y; // row of current thread in block
    int icol = bidx % blockDim.y; // column of current thread in block

    ix = blockIdx.y * blockDim.y + icol; // x coordinate in transpose matrix
    iy = blockIdx.x * blockDim.x + irow; // y coordinate in transpose matrix
    int to = iy * ny + ix; // coordinate in transpose matrix

    if (ix < nx && iy < ny) {
        tile[threadIdx.x][threadIdx.y] = in[ti]; // We got bank conflict here, but both the throughput and speed are still higher than global memory
        __syncthreads();
        out[to] = tile[irow][icol]; // Just change the index of data in array
    }
}

__global__ void transposeSmemUnrollPad(int *in, int *out, int nx, int ny) {
    int ix = blockDim.x * blockIdx.x * 2 + threadIdx.x; // thread start x index in block
    int iy = blockDim.y * blockIdx.y + threadIdx.y; // thread start y index in block

    __shared__ int tile[BDIMX * 2][BDIMY + 1];

    int ti = iy * nx + ix; // start data index in block

    int bidx = threadIdx.y * blockDim.x + threadIdx.x; // thread start index in block
    int irow = bidx / blockDim.x; // row in origin matrix
    int icol = bidx % blockDim.x; // column in origin matrix

    int outputIndex = ix * ny + blockIdx.y * BDIMY + irow; // data index in the output array

    if (icol < nx && irow < ny) {
        tile[icol][irow] = in[ti];
        __syncthreads();
        out[outputIndex] = tile[icol][irow];
    }

    if (icol + blockDim.x < nx && irow < ny) {
        tile[icol + blockDim.x][irow] = in[ti + blockDim.x];
        __syncthreads();
        out[outputIndex + blockDim.x * ny] = tile[icol + blockDim.x][irow];
    }
}

int main() {
    int nx = 1024, ny = 1024;
    int nBytes = nx * ny * sizeof(int);

    int *h_in = (int *) malloc(nBytes);
    int *h_out = (int *) malloc(nBytes);

    for (int i = 0; i < nx * ny; i++) {
        h_in[i] = i;
    }

    int *d_in;
    int *d_out;

    hipMalloc(&d_in, nBytes);
    hipMalloc(&d_out, nBytes);

    hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice);

    dim3 blockDim(BDIMX, BDIMY);
    dim3 gridDim((nx + blockDim.x - 1) / blockDim.x, (ny + blockDim.y - 1) / blockDim.y);

    transposeNaiveGem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    hipDeviceSynchronize();
    hipMemcpy(h_out, d_out, nBytes, hipMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }
//
//    printf("\n====================\n");

    memset(h_out, 0, nBytes);
    hipMemset(d_out, 0, nBytes);

    dim3 blockDim_(BDIMX, BDIMY);
    dim3 gridDim_((nx + 2 * blockDim_.x - 1) / (2 * blockDim_.x), (ny + blockDim_.y - 1) / blockDim_.y);

    printf("grid_: (%d, %d), block_: (%d, %d)\n", gridDim_.x, gridDim_.y, blockDim_.x, blockDim_.y);
    transposeSmemUnrollPad<<<gridDim_, blockDim_>>>(d_in, d_out, nx, ny);
    hipDeviceSynchronize();
    hipMemcpy(h_out, d_out, nBytes, hipMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }
//
//    printf("\n====================\n");

    memset(h_out, 0, nBytes);
    hipMemset(d_out, 0, nBytes);

    transposeSmem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    hipDeviceSynchronize();
    hipMemcpy(h_out, d_out, nBytes, hipMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }

    memset(h_out, 0, nBytes);
    hipMemset(d_out, 0, nBytes);

    transposeSmem<<<gridDim, blockDim>>>(d_in, d_out, nx, ny);
    hipDeviceSynchronize();
    hipMemcpy(h_out, d_out, nBytes, hipMemcpyDeviceToHost);
//    for (int i = 0; i < nx * ny; i++) {
//        printf("%d->", h_out[i]);
//    }

    hipFree(d_in);
    hipFree(d_out);
    free(h_in);
    free(h_out);
}

	.text
	.file	"transposeMatrixWithSharedMemory.hip"
	.globl	_Z32__device_stub__transposeNaiveGemPiS_ii # -- Begin function _Z32__device_stub__transposeNaiveGemPiS_ii
	.type	_Z32__device_stub__transposeNaiveGemPiS_ii,@function
_Z32__device_stub__transposeNaiveGemPiS_ii: # @_Z32__device_stub__transposeNaiveGemPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17transposeNaiveGemPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__transposeNaiveGemPiS_ii, .Lfunc_end0-_Z32__device_stub__transposeNaiveGemPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__transposeNaiveGem2PiS_ii # -- Begin function _Z33__device_stub__transposeNaiveGem2PiS_ii
	.type	_Z33__device_stub__transposeNaiveGem2PiS_ii,@function
_Z33__device_stub__transposeNaiveGem2PiS_ii: # @_Z33__device_stub__transposeNaiveGem2PiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18transposeNaiveGem2PiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__transposeNaiveGem2PiS_ii, .Lfunc_end1-_Z33__device_stub__transposeNaiveGem2PiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__transposeSmemPiS_ii # -- Begin function _Z28__device_stub__transposeSmemPiS_ii
	.type	_Z28__device_stub__transposeSmemPiS_ii,@function
_Z28__device_stub__transposeSmemPiS_ii: # @_Z28__device_stub__transposeSmemPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13transposeSmemPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__transposeSmemPiS_ii, .Lfunc_end2-_Z28__device_stub__transposeSmemPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__transposeSmemUnrollPadPiS_ii # -- Begin function _Z37__device_stub__transposeSmemUnrollPadPiS_ii
	.type	_Z37__device_stub__transposeSmemUnrollPadPiS_ii,@function
_Z37__device_stub__transposeSmemUnrollPadPiS_ii: # @_Z37__device_stub__transposeSmemUnrollPadPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22transposeSmemUnrollPadPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z37__device_stub__transposeSmemUnrollPadPiS_ii, .Lfunc_end3-_Z37__device_stub__transposeSmemUnrollPadPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %rbx
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %r14
	xorl	%eax, %eax
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB4_1
# %bb.2:
	movabsq	$137438953504, %r15             # imm = 0x2000000020
	leaq	16(%rsp), %r12
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z32__device_stub__transposeNaiveGemPiS_ii
.LBB4_4:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movq	8(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	xorl	%esi, %esi
	callq	hipMemset
	movl	$.L.str, %edi
	movl	$16, %esi
	movl	$32, %edx
	movl	$32, %ecx
	movl	$32, %r8d
	xorl	%eax, %eax
	callq	printf
	leaq	-16(%r15), %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z37__device_stub__transposeSmemUnrollPadPiS_ii
.LBB4_6:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movq	8(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	xorl	%esi, %esi
	callq	hipMemset
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z28__device_stub__transposeSmemPiS_ii
.LBB4_8:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movq	8(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	xorl	%esi, %esi
	callq	hipMemset
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movl	$1024, %ecx                     # imm = 0x400
	callq	_Z28__device_stub__transposeSmemPiS_ii
.LBB4_10:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17transposeNaiveGemPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18transposeNaiveGem2PiS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13transposeSmemPiS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22transposeSmemUnrollPadPiS_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17transposeNaiveGemPiS_ii,@object # @_Z17transposeNaiveGemPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z17transposeNaiveGemPiS_ii
	.p2align	3, 0x0
_Z17transposeNaiveGemPiS_ii:
	.quad	_Z32__device_stub__transposeNaiveGemPiS_ii
	.size	_Z17transposeNaiveGemPiS_ii, 8

	.type	_Z18transposeNaiveGem2PiS_ii,@object # @_Z18transposeNaiveGem2PiS_ii
	.globl	_Z18transposeNaiveGem2PiS_ii
	.p2align	3, 0x0
_Z18transposeNaiveGem2PiS_ii:
	.quad	_Z33__device_stub__transposeNaiveGem2PiS_ii
	.size	_Z18transposeNaiveGem2PiS_ii, 8

	.type	_Z13transposeSmemPiS_ii,@object # @_Z13transposeSmemPiS_ii
	.globl	_Z13transposeSmemPiS_ii
	.p2align	3, 0x0
_Z13transposeSmemPiS_ii:
	.quad	_Z28__device_stub__transposeSmemPiS_ii
	.size	_Z13transposeSmemPiS_ii, 8

	.type	_Z22transposeSmemUnrollPadPiS_ii,@object # @_Z22transposeSmemUnrollPadPiS_ii
	.globl	_Z22transposeSmemUnrollPadPiS_ii
	.p2align	3, 0x0
_Z22transposeSmemUnrollPadPiS_ii:
	.quad	_Z37__device_stub__transposeSmemUnrollPadPiS_ii
	.size	_Z22transposeSmemUnrollPadPiS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"grid_: (%d, %d), block_: (%d, %d)\n"
	.size	.L.str, 35

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17transposeNaiveGemPiS_ii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18transposeNaiveGem2PiS_ii"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13transposeSmemPiS_ii"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z22transposeSmemUnrollPadPiS_ii"
	.size	.L__unnamed_4, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__transposeNaiveGemPiS_ii
	.addrsig_sym _Z33__device_stub__transposeNaiveGem2PiS_ii
	.addrsig_sym _Z28__device_stub__transposeSmemPiS_ii
	.addrsig_sym _Z37__device_stub__transposeSmemUnrollPadPiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17transposeNaiveGemPiS_ii
	.addrsig_sym _Z18transposeNaiveGem2PiS_ii
	.addrsig_sym _Z13transposeSmemPiS_ii
	.addrsig_sym _Z22transposeSmemUnrollPadPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17transposeNaiveGemPiS_ii ; -- Begin function _Z17transposeNaiveGemPiS_ii
	.globl	_Z17transposeNaiveGemPiS_ii
	.p2align	8
	.type	_Z17transposeNaiveGemPiS_ii,@function
_Z17transposeNaiveGemPiS_ii:            ; @_Z17transposeNaiveGemPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17transposeNaiveGemPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17transposeNaiveGemPiS_ii, .Lfunc_end0-_Z17transposeNaiveGemPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18transposeNaiveGem2PiS_ii ; -- Begin function _Z18transposeNaiveGem2PiS_ii
	.globl	_Z18transposeNaiveGem2PiS_ii
	.p2align	8
	.type	_Z18transposeNaiveGem2PiS_ii,@function
_Z18transposeNaiveGem2PiS_ii:           ; @_Z18transposeNaiveGem2PiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18transposeNaiveGem2PiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18transposeNaiveGem2PiS_ii, .Lfunc_end1-_Z18transposeNaiveGem2PiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z13transposeSmemPiS_ii ; -- Begin function _Z13transposeSmemPiS_ii
	.globl	_Z13transposeSmemPiS_ii
	.p2align	8
	.type	_Z13transposeSmemPiS_ii,@function
_Z13transposeSmemPiS_ii:                ; @_Z13transposeSmemPiS_ii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s4, 0, s3
	s_mul_i32 s15, s15, s3
	s_mul_i32 s14, s14, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s4, v3
	s_load_b64 s[4:5], s[0:1], 0x10
	v_mul_hi_u32 v4, v3, v1
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v0, v2, s2, v1
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v4, v3, s3
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_subrev_nc_u32_e32 v6, s3, v4
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, 1, v3
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s3
	v_add_nc_u32_e32 v5, s14, v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_add_nc_u32_e32 v0, s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_add_nc_u32_e32 v6, s15, v2
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 2, v2
	v_lshlrev_b32_e32 v4, 2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s4
	v_add3_u32 v6, s14, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	v_lshl_add_u32 v7, v1, 7, v2
	v_mad_u64_u32 v[1:2], null, v5, s5, v[0:1]
	v_lshl_add_u32 v0, v3, 7, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13transposeSmemPiS_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13transposeSmemPiS_ii, .Lfunc_end2-_Z13transposeSmemPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22transposeSmemUnrollPadPiS_ii ; -- Begin function _Z22transposeSmemUnrollPadPiS_ii
	.globl	_Z22transposeSmemUnrollPadPiS_ii
	.p2align	8
	.type	_Z22transposeSmemUnrollPadPiS_ii,@function
_Z22transposeSmemUnrollPadPiS_ii:       ; @_Z22transposeSmemUnrollPadPiS_ii
; %bb.0:
	s_load_b32 s9, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s9, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v1, s8
	s_sub_i32 s2, 0, s8
	v_mad_u32_u24 v5, v0, s8, v3
	s_mul_i32 s14, s14, s8
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s2, v1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshr_b32 s0, s9, 16
	s_lshl_b32 s1, s15, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v5, v1
	v_mul_lo_u32 v2, v1, s8
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v5, v2
	v_subrev_nc_u32_e32 v6, s8, v2
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v6
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	v_cndmask_b32_e32 v4, v1, v4, vcc_lo
	v_lshl_add_u32 v1, s14, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v4, s8
	v_mad_u64_u32 v[6:7], null, s15, s0, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v0, v1, s3
	v_cmp_gt_i32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v5, v5, v2
	v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v0, v4, s1, v0
	v_cmp_gt_i32_e64 s0, s2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mul_lo_u32 v3, 0x84, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s4, v6
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshl_add_u32 v3, v4, 2, v3
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_add_co_u32 v6, s0, s6, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[6:7], v3, off
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v1, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s2, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s8, v2
	v_mul_lo_u32 v1, 0x84, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_lshl_add_u32 v4, v4, 2, v1
	v_mad_u64_u32 v[1:2], null, s8, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_mov_b32_e32 v2, v3
	global_load_b32 v5, v[5:6], off
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v4
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v4, off
.LBB3_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22transposeSmemUnrollPadPiS_ii
		.amdhsa_group_segment_fixed_size 8448
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z22transposeSmemUnrollPadPiS_ii, .Lfunc_end3-_Z22transposeSmemUnrollPadPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 648
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8448 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17transposeNaiveGemPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17transposeNaiveGemPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18transposeNaiveGem2PiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18transposeNaiveGem2PiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13transposeSmemPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13transposeSmemPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8448
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22transposeSmemUnrollPadPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22transposeSmemUnrollPadPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
