#include <stdio.h>
#include <stdlib.h>

#define NUM_ELEMENTS 8192
#define MAX_THREADS_PER_BLOCK 1024
#define KERNEL_LOOP 100000

__host__ void generate_rand_data(unsigned int * host_data_ptr)
{
        for(unsigned int i=0; i < NUM_ELEMENTS; i++)
        {
                host_data_ptr[i] = (unsigned int) rand();
        }
}

__global__ void test_gpu_global(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place value directly in register
                float tmp = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += data[tid];
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__global__ void test_gpu_register(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place value directly in register
                float tmp = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += tmp;
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__global__ void test_gpu_shared(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        __shared__ unsigned int tmp_0[NUM_ELEMENTS];
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place valude directly in shared
                tmp_0[tid] = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                float tmp;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += tmp_0[tid];
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__host__ void start_measure(cudaEvent_t * start, cudaEvent_t *stop){
        cudaEventCreate(start,0);
        cudaEventCreate(stop,0);
        cudaEventRecord(*start, 0);
}

__host__ void stop_measure(cudaEvent_t* start, cudaEvent_t * stop, float &time) {
        cudaEventRecord(*stop, 0);
        cudaEventSynchronize(*stop);
        cudaEventElapsedTime(&time, *start, *stop);
}

// Create display function to ensure output is the same for both kernels
__host__ void display_data(const unsigned int * const in_data, const unsigned int * const out_data) {
        for(int i = 0; i < 20; i ++){
                printf("i=%i, input_data = %u, output_data = %u\n", i, in_data[i], out_data[i]);
        }
}

__host__ void gpu_kernel(void)
{
        const unsigned int num_elements = NUM_ELEMENTS;
        const unsigned int num_threads = MAX_THREADS_PER_BLOCK;
        const unsigned int num_blocks = num_elements/num_threads;
        const unsigned int num_bytes = num_elements * sizeof(unsigned int);
        const unsigned int kernel_loop = KERNEL_LOOP;

        // Prep Host data
        unsigned int * host_pinned;
        unsigned int * host_pinned_final;
        cudaMallocHost((void**)&host_pinned, num_bytes);
        cudaMallocHost((void**)&host_pinned_final, num_bytes);
        generate_rand_data(host_pinned);

        // Prep Device data
        unsigned int * data_gpu;
        cudaMalloc(&data_gpu, num_bytes);

         // Define measurement 
        float time;
        cudaEvent_t kernel_start, kernel_stop;
        cudaEvent_t kernel_start1, kernel_stop1;
        cudaEvent_t kernel_start2, kernel_stop2;


        // Run Test with gpu shared
        cudaMemcpy(data_gpu, host_pinned, num_bytes, cudaMemcpyHostToDevice);
        start_measure(&kernel_start, &kernel_stop);
        test_gpu_global<<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start, &kernel_stop, time);
        printf("test_gpu_global took %f\n", time);

        cudaMemcpy(host_pinned_final, data_gpu, num_bytes,cudaMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        
        // Run Test with gpu registers
        cudaMemcpy(data_gpu, host_pinned, num_bytes, cudaMemcpyHostToDevice);    // referesh data
        start_measure(&kernel_start1, &kernel_stop1);
        test_gpu_shared <<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start1, &kernel_stop1, time);
        printf("test_gpu_shared took %f\n", time);

        cudaMemcpy(host_pinned_final, data_gpu, num_bytes,cudaMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        // Run Test with gpu global
        cudaMemcpy(data_gpu, host_pinned, num_bytes, cudaMemcpyHostToDevice);    // referesh data
        start_measure(&kernel_start2, &kernel_stop2);
        test_gpu_register <<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start2, &kernel_stop2, time);
        printf("test_gpu_register took %f\n", time);

        cudaMemcpy(host_pinned_final, data_gpu, num_bytes,cudaMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        cudaFree((void* ) data_gpu);
        cudaFreeHost(host_pinned_final);
        cudaFreeHost(host_pinned);
        cudaDeviceReset();

}


/**
 * Host function that prepares data array and passes it to the CUDA kernel.
 */
int main(void) {
        // Find out statistics of GPU 
        int nDevices;
        cudaGetDeviceCount(&nDevices);
        for (int i = 0; i < nDevices; i++) {
                cudaDeviceProp prop;
                cudaGetDeviceProperties(&prop, i);
                printf("maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
        }
	gpu_kernel();

	return EXIT_SUCCESS;
}
	.file	"tmpxft_0022237d_00000000-6_register.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18generate_rand_dataPj
	.type	_Z18generate_rand_dataPj, @function
_Z18generate_rand_dataPj:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 32
.L3:
	call	rand@PLT
	movl	%eax, 0(%rbp,%rbx,4)
	incq	%rbx
	cmpq	$8192, %rbx
	jne	.L3
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z18generate_rand_dataPj, .-_Z18generate_rand_dataPj
	.globl	_Z13start_measurePP10CUevent_stS1_
	.type	_Z13start_measurePP10CUevent_stS1_, @function
_Z13start_measurePP10CUevent_stS1_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	xorl	%esi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	cudaEventCreateWithFlags@PLT
	movq	%rbp, %rdi
	xorl	%esi, %esi
	call	cudaEventCreateWithFlags@PLT
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	cudaEventRecord@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z13start_measurePP10CUevent_stS1_, .-_Z13start_measurePP10CUevent_stS1_
	.globl	_Z12stop_measurePP10CUevent_stS1_Rf
	.type	_Z12stop_measurePP10CUevent_stS1_Rf, @function
_Z12stop_measurePP10CUevent_stS1_Rf:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rsi, %rbx
	xorl	%esi, %esi
	movq	(%rbx), %rdi
	call	cudaEventRecord@PLT
	movq	(%rbx), %rdi
	call	cudaEventSynchronize@PLT
	movq	(%rbx), %rdx
	movq	(%r12), %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	cudaEventElapsedTime@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z12stop_measurePP10CUevent_stS1_Rf, .-_Z12stop_measurePP10CUevent_stS1_Rf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"i=%i, input_data = %u, output_data = %u\n"
	.text
	.globl	_Z12display_dataPKjS0_
	.type	_Z12display_dataPKjS0_, @function
_Z12display_dataPKjS0_:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
.L12:
	movl	(%r12,%rbx,4), %ecx
	movl	0(%rbp,%rbx,4), %r8d
	movl	%ebx, %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$20, %rbx
	jne	.L12
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z12display_dataPKjS0_, .-_Z12display_dataPKjS0_
	.globl	_Z37__device_stub__Z15test_gpu_globalPjjjPjjj
	.type	_Z37__device_stub__Z15test_gpu_globalPjjjPjjj, @function
_Z37__device_stub__Z15test_gpu_globalPjjjPjjj:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15test_gpu_globalPjjj(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L15:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z37__device_stub__Z15test_gpu_globalPjjjPjjj, .-_Z37__device_stub__Z15test_gpu_globalPjjjPjjj
	.globl	_Z15test_gpu_globalPjjj
	.type	_Z15test_gpu_globalPjjj, @function
_Z15test_gpu_globalPjjj:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z15test_gpu_globalPjjjPjjj
	.cfi_endproc
.LFE2058:
	.size	_Z15test_gpu_globalPjjj, .-_Z15test_gpu_globalPjjj
	.globl	_Z39__device_stub__Z17test_gpu_registerPjjjPjjj
	.type	_Z39__device_stub__Z17test_gpu_registerPjjjPjjj, @function
_Z39__device_stub__Z17test_gpu_registerPjjjPjjj:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17test_gpu_registerPjjj(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L20:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z39__device_stub__Z17test_gpu_registerPjjjPjjj, .-_Z39__device_stub__Z17test_gpu_registerPjjjPjjj
	.globl	_Z17test_gpu_registerPjjj
	.type	_Z17test_gpu_registerPjjj, @function
_Z17test_gpu_registerPjjj:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17test_gpu_registerPjjjPjjj
	.cfi_endproc
.LFE2060:
	.size	_Z17test_gpu_registerPjjj, .-_Z17test_gpu_registerPjjj
	.globl	_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj
	.type	_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj, @function
_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15test_gpu_sharedPjjj(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L25:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj, .-_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj
	.globl	_Z15test_gpu_sharedPjjj
	.type	_Z15test_gpu_sharedPjjj, @function
_Z15test_gpu_sharedPjjj:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj
	.cfi_endproc
.LFE2062:
	.size	_Z15test_gpu_sharedPjjj, .-_Z15test_gpu_sharedPjjj
	.section	.rodata.str1.1
.LC1:
	.string	"test_gpu_global took %f\n"
.LC2:
	.string	"test_gpu_shared took %f\n"
.LC3:
	.string	"test_gpu_register took %f\n"
	.text
	.globl	_Z10gpu_kernelv
	.type	_Z10gpu_kernelv, @function
_Z10gpu_kernelv:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$32768, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$112, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	leaq	40(%rsp), %r12
	call	cudaMallocHost@PLT
	movl	$32768, %esi
	leaq	16(%rsp), %rdi
	leaq	32(%rsp), %rbp
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rdi
	call	_Z18generate_rand_dataPj
	leaq	24(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z13start_measurePP10CUevent_stS1_
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870913, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	24(%rsp), %rdi
	movl	$100000, %edx
	movl	$8192, %esi
	call	_Z37__device_stub__Z15test_gpu_globalPjjjPjjj
.L31:
	leaq	4(%rsp), %rbx
	movq	%r12, %rsi
	leaq	56(%rsp), %r12
	movq	%rbp, %rdi
	movq	%rbx, %rdx
	leaq	48(%rsp), %rbp
	call	_Z12stop_measurePP10CUevent_stS1_Rf
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z12display_dataPKjS0_
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z13start_measurePP10CUevent_stS1_
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870913, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	24(%rsp), %rdi
	movl	$100000, %edx
	movl	$8192, %esi
	call	_Z37__device_stub__Z15test_gpu_sharedPjjjPjjj
.L32:
	movq	%rbx, %rdx
	movq	%r12, %rsi
	leaq	72(%rsp), %r12
	movq	%rbp, %rdi
	call	_Z12stop_measurePP10CUevent_stS1_Rf
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$32768, %edx
	leaq	64(%rsp), %rbp
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z12display_dataPKjS0_
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z13start_measurePP10CUevent_stS1_
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870913, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	24(%rsp), %rdi
	movl	$100000, %edx
	movl	$8192, %esi
	call	_Z39__device_stub__Z17test_gpu_registerPjjjPjjj
.L33:
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z12stop_measurePP10CUevent_stS1_Rf
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z12display_dataPKjS0_
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	call	cudaDeviceReset@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$112, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z10gpu_kernelv, .-_Z10gpu_kernelv
	.section	.rodata.str1.1
.LC4:
	.string	"maxThreadsPerBlock: %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC4(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$1064, %rsp
	.cfi_def_cfa_offset 1088
	movq	%fs:40, %rax
	movq	%rax, 1048(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
.L37:
	cmpl	%ebx, 12(%rsp)
	jle	.L41
	movl	%ebx, %esi
	leaq	16(%rsp), %rdi
	incl	%ebx
	call	cudaGetDeviceProperties_v2@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	336(%rsp), %edx
	call	__printf_chk@PLT
	jmp	.L37
.L41:
	call	_Z10gpu_kernelv
	movq	1048(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$1064, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15test_gpu_sharedPjjj"
.LC6:
	.string	"_Z17test_gpu_registerPjjj"
.LC7:
	.string	"_Z15test_gpu_globalPjjj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15test_gpu_sharedPjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17test_gpu_registerPjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15test_gpu_globalPjjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

#define NUM_ELEMENTS 8192
#define MAX_THREADS_PER_BLOCK 1024
#define KERNEL_LOOP 100000

__host__ void generate_rand_data(unsigned int * host_data_ptr)
{
        for(unsigned int i=0; i < NUM_ELEMENTS; i++)
        {
                host_data_ptr[i] = (unsigned int) rand();
        }
}

__global__ void test_gpu_global(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place value directly in register
                float tmp = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += data[tid];
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__global__ void test_gpu_register(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place value directly in register
                float tmp = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += tmp;
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__global__ void test_gpu_shared(unsigned int * const data, 
                                        const unsigned int num_elements,
                                        const unsigned int loop_iter)
{
        const unsigned int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
        __shared__ unsigned int tmp_0[NUM_ELEMENTS];
        if(tid < num_elements)
        {
                // compute the average of this thread's left and right neighbors and place in register
                // Place valude directly in shared
                tmp_0[tid] = (data[tid > 0 ? tid - 1 : NUM_ELEMENTS-1] + data[tid < NUM_ELEMENTS-1 ? tid + 1 : 0]) * 0.5f;
                float tmp;
                for(int i = 0; i < KERNEL_LOOP; i++) {
                        tmp += tmp_0[tid];
                }
                data[tid] = tmp;
                __syncthreads();
        }
}

__host__ void start_measure(hipEvent_t * start, hipEvent_t *stop){
        hipEventCreateWithFlags(start,0);
        hipEventCreateWithFlags(stop,0);
        hipEventRecord(*start, 0);
}

__host__ void stop_measure(hipEvent_t* start, hipEvent_t * stop, float &time) {
        hipEventRecord(*stop, 0);
        hipEventSynchronize(*stop);
        hipEventElapsedTime(&time, *start, *stop);
}

// Create display function to ensure output is the same for both kernels
__host__ void display_data(const unsigned int * const in_data, const unsigned int * const out_data) {
        for(int i = 0; i < 20; i ++){
                printf("i=%i, input_data = %u, output_data = %u\n", i, in_data[i], out_data[i]);
        }
}

__host__ void gpu_kernel(void)
{
        const unsigned int num_elements = NUM_ELEMENTS;
        const unsigned int num_threads = MAX_THREADS_PER_BLOCK;
        const unsigned int num_blocks = num_elements/num_threads;
        const unsigned int num_bytes = num_elements * sizeof(unsigned int);
        const unsigned int kernel_loop = KERNEL_LOOP;

        // Prep Host data
        unsigned int * host_pinned;
        unsigned int * host_pinned_final;
        hipHostMalloc((void**)&host_pinned, num_bytes, hipHostMallocDefault);
        hipHostMalloc((void**)&host_pinned_final, num_bytes, hipHostMallocDefault);
        generate_rand_data(host_pinned);

        // Prep Device data
        unsigned int * data_gpu;
        hipMalloc(&data_gpu, num_bytes);

         // Define measurement 
        float time;
        hipEvent_t kernel_start, kernel_stop;
        hipEvent_t kernel_start1, kernel_stop1;
        hipEvent_t kernel_start2, kernel_stop2;


        // Run Test with gpu shared
        hipMemcpy(data_gpu, host_pinned, num_bytes, hipMemcpyHostToDevice);
        start_measure(&kernel_start, &kernel_stop);
        test_gpu_global<<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start, &kernel_stop, time);
        printf("test_gpu_global took %f\n", time);

        hipMemcpy(host_pinned_final, data_gpu, num_bytes,hipMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        
        // Run Test with gpu registers
        hipMemcpy(data_gpu, host_pinned, num_bytes, hipMemcpyHostToDevice);    // referesh data
        start_measure(&kernel_start1, &kernel_stop1);
        test_gpu_shared <<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start1, &kernel_stop1, time);
        printf("test_gpu_shared took %f\n", time);

        hipMemcpy(host_pinned_final, data_gpu, num_bytes,hipMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        // Run Test with gpu global
        hipMemcpy(data_gpu, host_pinned, num_bytes, hipMemcpyHostToDevice);    // referesh data
        start_measure(&kernel_start2, &kernel_stop2);
        test_gpu_register <<<num_blocks, num_threads>>>(data_gpu, num_elements, kernel_loop);
        stop_measure(&kernel_start2, &kernel_stop2, time);
        printf("test_gpu_register took %f\n", time);

        hipMemcpy(host_pinned_final, data_gpu, num_bytes,hipMemcpyDeviceToHost);
        display_data(host_pinned, host_pinned_final);

        hipFree((void* ) data_gpu);
        hipHostFree(host_pinned_final);
        hipHostFree(host_pinned);
        hipDeviceReset();

}


/**
 * Host function that prepares data array and passes it to the CUDA kernel.
 */
int main(void) {
        // Find out statistics of GPU 
        int nDevices;
        hipGetDeviceCount(&nDevices);
        for (int i = 0; i < nDevices; i++) {
                hipDeviceProp_t prop;
                hipGetDeviceProperties(&prop, i);
                printf("maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
        }
	gpu_kernel();

	return EXIT_SUCCESS;
}
	.text
	.file	"register.hip"
	.globl	_Z18generate_rand_dataPj        # -- Begin function _Z18generate_rand_dataPj
	.type	_Z18generate_rand_dataPj,@function
_Z18generate_rand_dataPj:               # @_Z18generate_rand_dataPj
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	xorl	%r14d, %r14d
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	movl	%eax, (%rbx,%r14,4)
	incq	%r14
	cmpq	$8192, %r14                     # imm = 0x2000
	jne	.LBB0_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18generate_rand_dataPj, .Lfunc_end0-_Z18generate_rand_dataPj
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__test_gpu_globalPjjj # -- Begin function _Z30__device_stub__test_gpu_globalPjjj
	.type	_Z30__device_stub__test_gpu_globalPjjj,@function
_Z30__device_stub__test_gpu_globalPjjj: # @_Z30__device_stub__test_gpu_globalPjjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15test_gpu_globalPjjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__test_gpu_globalPjjj, .Lfunc_end1-_Z30__device_stub__test_gpu_globalPjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__test_gpu_registerPjjj # -- Begin function _Z32__device_stub__test_gpu_registerPjjj
	.type	_Z32__device_stub__test_gpu_registerPjjj,@function
_Z32__device_stub__test_gpu_registerPjjj: # @_Z32__device_stub__test_gpu_registerPjjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17test_gpu_registerPjjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__test_gpu_registerPjjj, .Lfunc_end2-_Z32__device_stub__test_gpu_registerPjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__test_gpu_sharedPjjj # -- Begin function _Z30__device_stub__test_gpu_sharedPjjj
	.type	_Z30__device_stub__test_gpu_sharedPjjj,@function
_Z30__device_stub__test_gpu_sharedPjjj: # @_Z30__device_stub__test_gpu_sharedPjjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15test_gpu_sharedPjjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__test_gpu_sharedPjjj, .Lfunc_end3-_Z30__device_stub__test_gpu_sharedPjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z13start_measurePP11ihipEvent_tS1_ # -- Begin function _Z13start_measurePP11ihipEvent_tS1_
	.type	_Z13start_measurePP11ihipEvent_tS1_,@function
_Z13start_measurePP11ihipEvent_tS1_:    # @_Z13start_measurePP11ihipEvent_tS1_
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movq	(%r14), %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	hipEventRecord                  # TAILCALL
.Lfunc_end4:
	.size	_Z13start_measurePP11ihipEvent_tS1_, .Lfunc_end4-_Z13start_measurePP11ihipEvent_tS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z12stop_measurePP11ihipEvent_tS1_Rf # -- Begin function _Z12stop_measurePP11ihipEvent_tS1_Rf
	.type	_Z12stop_measurePP11ihipEvent_tS1_Rf,@function
_Z12stop_measurePP11ihipEvent_tS1_Rf:   # @_Z12stop_measurePP11ihipEvent_tS1_Rf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	(%rsi), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	callq	hipEventSynchronize
	movq	(%r15), %rsi
	movq	(%r14), %rdx
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipEventElapsedTime             # TAILCALL
.Lfunc_end5:
	.size	_Z12stop_measurePP11ihipEvent_tS1_Rf, .Lfunc_end5-_Z12stop_measurePP11ihipEvent_tS1_Rf
	.cfi_endproc
                                        # -- End function
	.globl	_Z12display_dataPKjS0_          # -- Begin function _Z12display_dataPKjS0_
	.type	_Z12display_dataPKjS0_,@function
_Z12display_dataPKjS0_:                 # @_Z12display_dataPKjS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	xorl	%r15d, %r15d
.LBB6_1:                                # =>This Inner Loop Header: Depth=1
	movl	(%r14,%r15,4), %edx
	movl	(%rbx,%r15,4), %ecx
	movl	$.L.str, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$20, %r15
	jne	.LBB6_1
# %bb.2:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z12display_dataPKjS0_, .Lfunc_end6-_Z12display_dataPKjS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z10gpu_kernelv                 # -- Begin function _Z10gpu_kernelv
	.type	_Z10gpu_kernelv,@function
_Z10gpu_kernelv:                        # @_Z10gpu_kernelv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	16(%rsp), %rbx
	xorl	%r14d, %r14d
	movl	$32768, %esi                    # imm = 0x8000
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	8(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%rbx), %rbx
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	movl	%eax, (%rbx,%r14,4)
	incq	%r14
	cmpq	$8192, %r14                     # imm = 0x2000
	jne	.LBB7_1
# %bb.2:                                # %_Z18generate_rand_dataPj.exit
	movabsq	$4294967304, %rbx               # imm = 0x100000008
	movq	%rsp, %r14
	movl	$32768, %esi                    # imm = 0x8000
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	16(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %rdi
	leaq	64(%rsp), %rsi
	callq	_Z13start_measurePP11ihipEvent_tS1_
	leaq	1016(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_4
# %bb.3:
	movq	(%rsp), %rdi
	movl	$8192, %esi                     # imm = 0x2000
	movl	$100000, %edx                   # imm = 0x186A0
	callq	_Z30__device_stub__test_gpu_globalPjjj
.LBB7_4:
	leaq	72(%rsp), %rdi
	leaq	64(%rsp), %rsi
	leaq	28(%rsp), %r15
	movq	%r15, %rdx
	callq	_Z12stop_measurePP11ihipEvent_tS1_Rf
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %r12
	movq	8(%rsp), %r13
	xorl	%r15d, %r15d
.LBB7_5:                                # =>This Inner Loop Header: Depth=1
	movl	(%r12,%r15,4), %edx
	movl	(%r13,%r15,4), %ecx
	movl	$.L.str, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$20, %r15
	jne	.LBB7_5
# %bb.6:                                # %_Z12display_dataPKjS0_.exit
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rdi
	leaq	48(%rsp), %rsi
	callq	_Z13start_measurePP11ihipEvent_tS1_
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.7:
	movq	(%rsp), %rdi
	movl	$8192, %esi                     # imm = 0x2000
	movl	$100000, %edx                   # imm = 0x186A0
	callq	_Z30__device_stub__test_gpu_sharedPjjj
.LBB7_8:
	leaq	56(%rsp), %rdi
	leaq	48(%rsp), %rsi
	leaq	28(%rsp), %r15
	movq	%r15, %rdx
	callq	_Z12stop_measurePP11ihipEvent_tS1_Rf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %r12
	movq	8(%rsp), %r13
	xorl	%r15d, %r15d
.LBB7_9:                                # =>This Inner Loop Header: Depth=1
	movl	(%r12,%r15,4), %edx
	movl	(%r13,%r15,4), %ecx
	movl	$.L.str, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$20, %r15
	jne	.LBB7_9
# %bb.10:                               # %_Z12display_dataPKjS0_.exit19
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rdi
	leaq	32(%rsp), %rsi
	callq	_Z13start_measurePP11ihipEvent_tS1_
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_12
# %bb.11:
	movq	(%rsp), %rdi
	movl	$8192, %esi                     # imm = 0x2000
	movl	$100000, %edx                   # imm = 0x186A0
	callq	_Z32__device_stub__test_gpu_registerPjjj
.LBB7_12:
	leaq	40(%rsp), %rdi
	leaq	32(%rsp), %rsi
	leaq	28(%rsp), %rbx
	movq	%rbx, %rdx
	callq	_Z12stop_measurePP11ihipEvent_tS1_Rf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %r14
	movq	8(%rsp), %r15
	xorl	%ebx, %ebx
.LBB7_13:                               # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rbx,4), %edx
	movl	(%r15,%rbx,4), %ecx
	movl	$.L.str, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$20, %rbx
	jne	.LBB7_13
# %bb.14:                               # %_Z12display_dataPKjS0_.exit23
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipHostFree
	movq	16(%rsp), %rdi
	callq	hipHostFree
	callq	hipDeviceReset
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z10gpu_kernelv, .Lfunc_end7-_Z10gpu_kernelv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$1480, %rsp                     # imm = 0x5C8
	.cfi_def_cfa_offset 1504
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	leaq	4(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	jle	.LBB8_3
# %bb.1:                                # %.lr.ph
	leaq	8(%rsp), %rbx
	xorl	%ebp, %ebp
.LBB8_2:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	%ebp, %esi
	callq	hipGetDevicePropertiesR0600
	movl	328(%rsp), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	incl	%ebp
	cmpl	4(%rsp), %ebp
	jl	.LBB8_2
.LBB8_3:                                # %._crit_edge
	callq	_Z10gpu_kernelv
	xorl	%eax, %eax
	addq	$1480, %rsp                     # imm = 0x5C8
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	main, .Lfunc_end8-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15test_gpu_globalPjjj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17test_gpu_registerPjjj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15test_gpu_sharedPjjj, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15test_gpu_globalPjjj,@object # @_Z15test_gpu_globalPjjj
	.section	.rodata,"a",@progbits
	.globl	_Z15test_gpu_globalPjjj
	.p2align	3, 0x0
_Z15test_gpu_globalPjjj:
	.quad	_Z30__device_stub__test_gpu_globalPjjj
	.size	_Z15test_gpu_globalPjjj, 8

	.type	_Z17test_gpu_registerPjjj,@object # @_Z17test_gpu_registerPjjj
	.globl	_Z17test_gpu_registerPjjj
	.p2align	3, 0x0
_Z17test_gpu_registerPjjj:
	.quad	_Z32__device_stub__test_gpu_registerPjjj
	.size	_Z17test_gpu_registerPjjj, 8

	.type	_Z15test_gpu_sharedPjjj,@object # @_Z15test_gpu_sharedPjjj
	.globl	_Z15test_gpu_sharedPjjj
	.p2align	3, 0x0
_Z15test_gpu_sharedPjjj:
	.quad	_Z30__device_stub__test_gpu_sharedPjjj
	.size	_Z15test_gpu_sharedPjjj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"i=%i, input_data = %u, output_data = %u\n"
	.size	.L.str, 41

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"test_gpu_global took %f\n"
	.size	.L.str.1, 25

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"test_gpu_shared took %f\n"
	.size	.L.str.2, 25

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"test_gpu_register took %f\n"
	.size	.L.str.3, 27

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"maxThreadsPerBlock: %d\n"
	.size	.L.str.4, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15test_gpu_globalPjjj"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17test_gpu_registerPjjj"
	.size	.L__unnamed_2, 26

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z15test_gpu_sharedPjjj"
	.size	.L__unnamed_3, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__test_gpu_globalPjjj
	.addrsig_sym _Z32__device_stub__test_gpu_registerPjjj
	.addrsig_sym _Z30__device_stub__test_gpu_sharedPjjj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15test_gpu_globalPjjj
	.addrsig_sym _Z17test_gpu_registerPjjj
	.addrsig_sym _Z15test_gpu_sharedPjjj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15test_gpu_globalPjjj ; -- Begin function _Z15test_gpu_globalPjjj
	.globl	_Z15test_gpu_globalPjjj
	.p2align	8
	.type	_Z15test_gpu_globalPjjj,@function
_Z15test_gpu_globalPjjj:                ; @_Z15test_gpu_globalPjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v0, -1, v1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x1fff, v0
	v_add_nc_u32_e32 v0, 1, v1
	v_cmp_gt_u32_e32 vcc_lo, 0x1fff, v1
	v_mov_b32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_cndmask_b32_e32 v3, 0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[5:6], off
	global_load_b32 v3, v[3:4], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0x186a0
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v2, v2
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v3, v4
	v_mul_f32_e32 v2, 0.5, v2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v2, v2, v3
	s_add_i32 s0, s0, -1
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15test_gpu_globalPjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15test_gpu_globalPjjj, .Lfunc_end0-_Z15test_gpu_globalPjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17test_gpu_registerPjjj ; -- Begin function _Z17test_gpu_registerPjjj
	.globl	_Z17test_gpu_registerPjjj
	.p2align	8
	.type	_Z17test_gpu_registerPjjj,@function
_Z17test_gpu_registerPjjj:              ; @_Z17test_gpu_registerPjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, -1, v1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_mov_b32 s2, 0x186a0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x1fff, v0, vcc_lo
	v_add_nc_u32_e32 v0, 1, v1
	v_cmp_gt_u32_e32 vcc_lo, 0x1fff, v1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, v0
	v_mul_f32_e32 v0, 0.5, v0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v0, v0, v0
	s_add_i32 s2, s2, -1
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc0 .LBB1_2
; %bb.3:
	v_mov_b32_e32 v2, 0
	v_cvt_u32_f32_e32 v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB1_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17test_gpu_registerPjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17test_gpu_registerPjjj, .Lfunc_end1-_Z17test_gpu_registerPjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15test_gpu_sharedPjjj ; -- Begin function _Z15test_gpu_sharedPjjj
	.globl	_Z15test_gpu_sharedPjjj
	.p2align	8
	.type	_Z15test_gpu_sharedPjjj,@function
_Z15test_gpu_sharedPjjj:                ; @_Z15test_gpu_sharedPjjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, -1, v1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_mov_b32 s2, 0x186a0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x1fff, v0, vcc_lo
	v_add_nc_u32_e32 v0, 1, v1
	v_cmp_gt_u32_e32 vcc_lo, 0x1fff, v1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, v0
	v_mul_f32_e32 v0, 0.5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_f32_u32_e32 v2, v0
                                        ; implicit-def: $vgpr0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v0, v0, v2
	s_add_i32 s2, s2, -1
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc0 .LBB2_2
; %bb.3:
	v_mov_b32_e32 v2, 0
	v_cvt_u32_f32_e32 v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB2_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15test_gpu_sharedPjjj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z15test_gpu_sharedPjjj, .Lfunc_end2-_Z15test_gpu_sharedPjjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15test_gpu_globalPjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15test_gpu_globalPjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17test_gpu_registerPjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17test_gpu_registerPjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15test_gpu_sharedPjjj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15test_gpu_sharedPjjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
