extern "C"
__global__ void applyKernels(   float* kernels_hat,
                                float* kernels_hat_sum_2,
                                float* inimg,
                                float* pos2zncc,
                                float* pos2sigma,
                                float* pos2vx,
                                float* pos2vy,
                                int*   pos,
                                int L,
                                int N,
                                int scale,
                                int dimsx,
                                int dimsy,
                                int N_threads,
                                int NN)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int tid = index;

    while (tid < NN)
    {

        int x = pos[2 * tid];
        int y = pos[2 * tid + 1];
        int L2 = L / 2;

        float imgVal;
        float imgValsAvg = 0;

        for (int pidx = 0; pidx < L*L; pidx++) {

            int xx = x + (pidx % L) - L2;
            int yy = y + (pidx / L) - L2;

            imgVal = (xx>=0 && xx<dimsx && yy>=0 && yy<dimsy)?inimg[xx + yy * dimsx]:0;

            imgValsAvg += imgVal;

        }

        imgValsAvg /= (float) (L*L);

        for (int didx = 0; didx < N; didx++) {

            float num = 0;
            float den = 0;
            float zncc;

            for (int pidx = 0; pidx < L*L; pidx++) {

                // sample from the image
                int xx = x + (pidx % L) - L2;
                int yy = y + (pidx / L) - L2;

                imgVal = (xx>=0 && xx<dimsx && yy>=0 && yy<dimsy)?inimg[xx + yy * dimsx]:0;
 
                num += (imgVal - imgValsAvg) * kernels_hat[scale*N*L*L + didx*L*L + pidx];
                den += (imgVal - imgValsAvg) * (imgVal - imgValsAvg);

            }

            zncc = num / (float) sqrtf(den * kernels_hat_sum_2[didx + scale*N]);

            if (zncc > pos2zncc[tid]) {
                
                pos2zncc[tid] = zncc;
                
                pos2sigma[tid] = scale;

                float ang = didx * (3.141592654 / N);

                float vx = -sinf(ang);
                float vy =  cosf(ang);

                pos2vx[tid] = vx;
                pos2vy[tid] = vy; 

            }

        }

        tid += N_threads;

    }

 }
	.file	"tmpxft_0034d1bd_00000000-6_zncc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii
	.type	_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii, @function
_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	%rsp, %rax
	movq	%rax, 184(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 280
	leaq	applyKernels(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 288
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii, .-_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii
	.globl	applyKernels
	.type	applyKernels, @function
applyKernels:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z12applyKernelsPfS_S_S_S_S_S_PiiiiiiiiPfS_S_S_S_S_S_Piiiiiiii
	.cfi_endproc
.LFE2033:
	.size	applyKernels, .-applyKernels
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"applyKernels"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	applyKernels(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"
__global__ void applyKernels(   float* kernels_hat,
                                float* kernels_hat_sum_2,
                                float* inimg,
                                float* pos2zncc,
                                float* pos2sigma,
                                float* pos2vx,
                                float* pos2vy,
                                int*   pos,
                                int L,
                                int N,
                                int scale,
                                int dimsx,
                                int dimsy,
                                int N_threads,
                                int NN)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int tid = index;

    while (tid < NN)
    {

        int x = pos[2 * tid];
        int y = pos[2 * tid + 1];
        int L2 = L / 2;

        float imgVal;
        float imgValsAvg = 0;

        for (int pidx = 0; pidx < L*L; pidx++) {

            int xx = x + (pidx % L) - L2;
            int yy = y + (pidx / L) - L2;

            imgVal = (xx>=0 && xx<dimsx && yy>=0 && yy<dimsy)?inimg[xx + yy * dimsx]:0;

            imgValsAvg += imgVal;

        }

        imgValsAvg /= (float) (L*L);

        for (int didx = 0; didx < N; didx++) {

            float num = 0;
            float den = 0;
            float zncc;

            for (int pidx = 0; pidx < L*L; pidx++) {

                // sample from the image
                int xx = x + (pidx % L) - L2;
                int yy = y + (pidx / L) - L2;

                imgVal = (xx>=0 && xx<dimsx && yy>=0 && yy<dimsy)?inimg[xx + yy * dimsx]:0;
 
                num += (imgVal - imgValsAvg) * kernels_hat[scale*N*L*L + didx*L*L + pidx];
                den += (imgVal - imgValsAvg) * (imgVal - imgValsAvg);

            }

            zncc = num / (float) sqrtf(den * kernels_hat_sum_2[didx + scale*N]);

            if (zncc > pos2zncc[tid]) {
                
                pos2zncc[tid] = zncc;
                
                pos2sigma[tid] = scale;

                float ang = didx * (3.141592654 / N);

                float vx = -sinf(ang);
                float vy =  cosf(ang);

                pos2vx[tid] = vx;
                pos2vy[tid] = vy; 

            }

        }

        tid += N_threads;

    }

 }
	.text
	.file	"zncc.hip"
	.globl	__device_stub__applyKernels     # -- Begin function __device_stub__applyKernels
	.type	__device_stub__applyKernels,@function
__device_stub__applyKernels:            # @__device_stub__applyKernels
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$applyKernels, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__applyKernels, .Lfunc_end0-__device_stub__applyKernels
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$applyKernels, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	applyKernels,@object            # @applyKernels
	.section	.rodata,"a",@progbits
	.globl	applyKernels
	.p2align	3, 0x0
applyKernels:
	.quad	__device_stub__applyKernels
	.size	applyKernels, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"applyKernels"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__applyKernels
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym applyKernels
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	applyKernels            ; -- Begin function applyKernels
	.globl	applyKernels
	.p2align	8
	.type	applyKernels,@function
applyKernels:                           ; @applyKernels
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b128 s[20:23], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s22, v1
	s_cbranch_execz .LBB0_32
; %bb.1:                                ; %.lr.ph153
	s_load_b128 s[24:27], s[0:1], 0x40
	s_mov_b32 s4, 0x54524550
	s_mov_b32 s5, 0x400921fb
	s_mov_b32 s31, 0
	s_mov_b32 s36, 0xb94c1982
	s_mov_b32 s37, 0x37d75334
	v_mov_b32_e32 v17, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[2:3], s25
	s_lshr_b32 s2, s24, 31
	s_mul_i32 s30, s24, s24
	s_add_i32 s2, s24, s2
	v_cvt_f32_i32_e32 v15, s30
	s_ashr_i32 s2, s2, 1
	v_cvt_f32_i32_e32 v16, s26
	s_sub_i32 s2, 0, s2
	s_cmp_lg_u32 s24, 0
	s_mul_i32 s33, s26, s25
	s_cselect_b32 s3, -1, 0
	s_cmp_gt_i32 s25, 0
	s_mul_i32 s35, s33, s30
	s_cselect_b32 s23, -1, 0
	s_ashr_i32 s28, s24, 31
	s_max_u32 s26, s30, 1
	s_add_i32 s6, s24, s28
	s_sub_i32 s24, 0, s24
	s_xor_b32 s29, s6, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s29
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], s[4:5]
	v_div_scale_f64 v[10:11], vcc_lo, s[4:5], v[2:3], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v0, v0
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[4:5], v[2:3], s[4:5]
	s_load_b512 s[4:19], s[0:1], 0x0
	v_readfirstlane_b32 s0, v0
	s_sub_i32 s1, 0, s29
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s1, s0, s1
	s_add_i32 s34, s0, s1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_11 Depth 2
                                        ;       Child Loop BB0_13 Depth 3
	v_lshlrev_b32_e32 v5, 1, v1
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s3
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v18, s2, v6
	v_add_nc_u32_e32 v19, s2, v5
	s_cbranch_vccnz .LBB0_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	s_mov_b32 s38, 0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s0, s38, s34
	v_mov_b32_e32 v2, 0
	s_mul_i32 s1, s0, s29
	s_add_i32 s39, s0, 1
	s_sub_i32 s1, s38, s1
	s_sub_i32 s40, s1, s29
	s_cmp_ge_u32 s1, s29
	s_cselect_b32 s0, s39, s0
	s_cselect_b32 s1, s40, s1
	s_add_i32 s39, s0, 1
	s_cmp_ge_u32 s1, s29
	s_cselect_b32 s0, s39, s0
	s_mov_b32 s39, exec_lo
	s_xor_b32 s0, s0, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s28
	s_mul_i32 s1, s24, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s1, s38, v19
	v_cmpx_lt_i32_e32 -1, v0
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, s0, v18
	v_cmp_gt_i32_e32 vcc_lo, s27, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s20, v5
	v_cmp_lt_i32_e64 s1, -1, v5
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_mad_u64_u32 v[6:7], null, v5, s27, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v2, v[5:6], off
.LBB0_7:                                ; %Flow226
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s39
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v13, v13, v2
	s_add_i32 s38, s38, 1
	s_cmp_eq_u32 s26, s38
	s_cbranch_scc0 .LBB0_4
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_not1_b32 vcc_lo, exec_lo, s23
	s_cbranch_vccnz .LBB0_31
; %bb.10:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_div_scale_f32 v0, null, v15, v15, v13
	v_div_scale_f32 v9, vcc_lo, v13, v15, v13
	v_lshlrev_b64 v[20:21], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v0
	s_mov_b32 s38, 0
	s_mov_b32 s39, s35
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v0, v11, 1.0
	v_fmac_f32_e32 v11, v5, v11
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v9, v11
	v_fma_f32 v7, -v0, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v7, v11
	v_add_co_u32 v7, s0, s10, v20
	v_add_co_ci_u32_e64 v8, s0, s11, v21, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v0, v12, v9
	v_add_co_u32 v9, s0, s12, v20
	v_add_co_ci_u32_e64 v10, s0, s13, v21, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v0, v0, v11, v12
	v_add_co_u32 v11, vcc_lo, s14, v20
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v21, vcc_lo
	v_div_fixup_f32 v2, v0, v15, v13
	v_add_co_u32 v13, vcc_lo, s16, v20
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v21, vcc_lo
.LBB0_11:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_13 Depth 3
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v20, 0
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_18
; %bb.12:                               ; %.lr.ph145
                                        ;   in Loop: Header=BB0_11 Depth=2
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v20, 0
	s_mov_b32 s40, 0
.LBB0_13:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s0, s40, s34
	v_mov_b32_e32 v22, 0
	s_mul_i32 s1, s0, s29
	s_add_i32 s41, s0, 1
	s_sub_i32 s1, s40, s1
	s_sub_i32 s42, s1, s29
	s_cmp_ge_u32 s1, s29
	s_cselect_b32 s0, s41, s0
	s_cselect_b32 s1, s42, s1
	s_add_i32 s41, s0, 1
	s_cmp_ge_u32 s1, s29
	s_cselect_b32 s0, s41, s0
	s_mov_b32 s41, exec_lo
	s_xor_b32 s0, s0, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s28
	s_mul_i32 s1, s24, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s1, s40, v19
	v_cmpx_lt_i32_e32 -1, v0
	s_cbranch_execz .LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=3
	v_dual_mov_b32 v22, 0 :: v_dual_add_nc_u32 v23, s0, v18
	v_cmp_gt_i32_e32 vcc_lo, s27, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s20, v23
	v_cmp_lt_i32_e64 s1, -1, v23
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=3
	v_mad_u64_u32 v[24:25], null, v23, s27, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v25, 31, v24
	v_lshlrev_b64 v[22:23], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v22, vcc_lo, s8, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v23, vcc_lo
	global_load_b32 v22, v[22:23], off
.LBB0_16:                               ; %Flow221
                                        ;   in Loop: Header=BB0_13 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:                               ;   in Loop: Header=BB0_13 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s41
	s_add_i32 s0, s39, s40
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v22, v22, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v21, v22, v22
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_add_i32 s40, s40, 1
	global_load_b32 v0, v17, s[0:1]
	s_cmp_eq_u32 s26, s40
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v20, v22, v0
	s_cbranch_scc0 .LBB0_13
.LBB0_18:                               ; %Flow223
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_add_i32 s0, s38, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_load_b32 v0, v17, s[0:1]
	global_load_b32 v22, v[7:8], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, v21, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v21, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, -1, v21
	v_add_nc_u32_e32 v24, 1, v21
	v_fma_f32 v25, -v23, v21, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v24, v21, v0
	v_cmp_ge_f32_e64 s0, 0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v23, s0
	v_cmp_lt_f32_e64 s0, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, v21, v24, s0
	s_mov_b32 s0, exec_lo
	v_mul_f32_e32 v23, 0x37800000, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v21, v23, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v0, v21, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v21, null, v0, v0, v20
	v_rcp_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v21, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v20, v0, v20
	v_mul_f32_e32 v25, v24, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v21, v25, v24
	v_fmac_f32_e32 v25, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v21, v25, v24
	v_div_fmas_f32 v21, v21, v23, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v20, v21, v0, v20
	s_waitcnt vmcnt(0)
	v_cmpx_gt_f32_e32 v20, v22
	s_cbranch_execz .LBB0_30
; %bb.19:                               ;   in Loop: Header=BB0_11 Depth=2
	v_mul_f64 v[21:22], v[3:4], v[5:6]
	global_store_b32 v[7:8], v20, off
	global_store_b32 v[9:10], v16, off
	v_cvt_f32_f64_e32 v0, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e64 s40, 0x48000000, |v0|
	v_readfirstlane_b32 s1, v0
	s_and_b32 vcc_lo, exec_lo, s40
	s_delay_alu instid0(VALU_DEP_1)
	s_bitset0_b32 s1, 31
	s_cbranch_vccz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_11 Depth=2
	s_and_b32 s41, s1, 0x7fffff
	s_lshr_b32 s42, s1, 23
	s_bitset1_b32 s41, 23
	s_addk_i32 s42, 0xff88
	s_mul_hi_u32 s43, s41, 0xfe5163ab
	s_mul_i32 s44, s41, 0x3c439041
	s_mul_hi_u32 s45, s41, 0x3c439041
	s_add_u32 s43, s43, s44
	s_addc_u32 s44, 0, s45
	s_mul_i32 s45, s41, 0xdb629599
	s_mul_hi_u32 s46, s41, 0xdb629599
	s_add_u32 s44, s44, s45
	s_addc_u32 s45, 0, s46
	s_mul_i32 s46, s41, 0xf534ddc0
	s_mul_hi_u32 s47, s41, 0xf534ddc0
	s_add_u32 s45, s45, s46
	s_addc_u32 s46, 0, s47
	s_mul_i32 s47, s41, 0xfc2757d1
	s_mul_hi_u32 s48, s41, 0xfc2757d1
	s_add_u32 s46, s46, s47
	s_addc_u32 s47, 0, s48
	s_mul_i32 s48, s41, 0x4e441529
	s_mul_hi_u32 s49, s41, 0x4e441529
	s_add_u32 s47, s47, s48
	s_addc_u32 s48, 0, s49
	s_cmp_gt_u32 s42, 63
	s_mul_i32 s49, s41, 0xfe5163ab
	s_mul_hi_u32 s50, s41, 0xa2f9836e
	s_mul_i32 s41, s41, 0xa2f9836e
	s_cselect_b32 s51, s44, s46
	s_cselect_b32 s43, s43, s45
	s_cselect_b32 s44, s49, s44
	s_add_u32 s41, s48, s41
	s_addc_u32 s48, 0, s50
	s_cmp_gt_u32 s42, 63
	s_cselect_b32 s49, 0xffffffc0, 0
	s_cselect_b32 s45, s45, s47
	s_cselect_b32 s41, s46, s41
	s_cselect_b32 s46, s47, s48
	s_add_i32 s49, s49, s42
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s49, 31
	s_cselect_b32 s42, 0xffffffe0, 0
	s_cselect_b32 s47, s45, s41
	s_cselect_b32 s41, s41, s46
	s_cselect_b32 s45, s51, s45
	s_cselect_b32 s46, s43, s51
	s_cselect_b32 s43, s44, s43
	s_add_i32 s42, s42, s49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s42, 31
	s_cselect_b32 s44, 0xffffffe0, 0
	s_cselect_b32 s41, s47, s41
	s_cselect_b32 s47, s45, s47
	s_cselect_b32 s45, s46, s45
	s_cselect_b32 s43, s43, s46
	s_add_i32 s44, s44, s42
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s42, 32, s44
	s_cmp_eq_u32 s44, 0
	v_mov_b32_e32 v20, s42
	s_cselect_b32 s44, -1, 0
	v_alignbit_b32 v21, s41, s47, v20
	v_alignbit_b32 v22, s47, s45, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s42, v21
	v_cndmask_b32_e64 v21, v22, s47, s44
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s41, s41, s42
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v22, s41, v21, 30
	s_bfe_u32 s42, s41, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s46, 0, s42
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v22, s46, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v23, v22
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v25, 23, v23
	v_alignbit_b32 v20, s45, s43, v20
	v_sub_nc_u32_e32 v24, 31, v23
	v_cndmask_b32_e64 v20, v20, s45, s44
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v21, v21, v20, 30
	v_alignbit_b32 v20, v20, s43, 30
	s_lshr_b32 s43, s41, 29
	s_lshr_b32 s41, s41, 30
	s_lshl_b32 s43, s43, 31
	v_xor_b32_e32 v21, s46, v21
	v_xor_b32_e32 v20, s46, v20
	s_or_b32 s44, s43, 0.5
	s_add_i32 s42, s42, s41
	v_sub_nc_u32_e32 v25, s44, v25
	v_alignbit_b32 v22, v22, v21, v24
	v_alignbit_b32 v20, v21, v20, v24
	s_mov_b32 s41, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v22, v20, 9
	v_lshrrev_b32_e32 v22, 9, v22
	v_clz_i32_u32_e32 v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v24, 32, v24
	v_sub_nc_u32_e32 v26, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v21, v20, v26
	v_or_b32_e32 v21, v22, v25
	v_add_nc_u32_e32 v23, v24, v23
	v_lshrrev_b32_e32 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v23, 0x3fc90fda, v21 :: v_dual_lshlrev_b32 v22, 23, v23
	v_sub_nc_u32_e32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3fc90fda, v21, -v23
	v_add_nc_u32_e32 v20, 0x33000000, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x33a22168, v21
	v_or_b32_e32 v20, s43, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, 0x3fc90fda, v20
	v_add_f32_e32 v20, v23, v22
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_11 Depth=2
	s_mov_b32 s41, -1
                                        ; implicit-def: $sgpr42
                                        ; implicit-def: $vgpr20
.LBB0_22:                               ; %Flow219
                                        ;   in Loop: Header=BB0_11 Depth=2
	v_mov_b32_e32 v21, s42
	s_and_not1_b32 vcc_lo, exec_lo, s41
	s_cbranch_vccnz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_11 Depth=2
	v_mul_f32_e64 v20, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v21, v20
	v_fma_f32 v20, 0xbfc90fda, v21, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0xb3a22168, v21
	v_fmac_f32_e32 v20, 0xa7c234c4, v21
	v_cvt_i32_f32_e32 v21, v21
.LBB0_24:                               ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_and_b32 vcc_lo, exec_lo, s40
	s_cbranch_vccz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_11 Depth=2
	s_and_b32 s40, s1, 0x7fffff
	s_lshr_b32 s41, s1, 23
	s_bitset1_b32 s40, 23
	s_addk_i32 s41, 0xff88
	s_mul_hi_u32 s42, s40, 0xfe5163ab
	s_mul_i32 s43, s40, 0x3c439041
	s_mul_hi_u32 s44, s40, 0x3c439041
	s_add_u32 s42, s42, s43
	s_addc_u32 s43, 0, s44
	s_mul_i32 s44, s40, 0xdb629599
	s_mul_hi_u32 s45, s40, 0xdb629599
	s_add_u32 s43, s43, s44
	s_addc_u32 s44, 0, s45
	s_mul_i32 s45, s40, 0xf534ddc0
	s_mul_hi_u32 s46, s40, 0xf534ddc0
	s_add_u32 s44, s44, s45
	s_addc_u32 s45, 0, s46
	s_mul_i32 s46, s40, 0xfc2757d1
	s_mul_hi_u32 s47, s40, 0xfc2757d1
	s_add_u32 s45, s45, s46
	s_addc_u32 s46, 0, s47
	s_mul_i32 s47, s40, 0x4e441529
	s_mul_hi_u32 s48, s40, 0x4e441529
	s_add_u32 s46, s46, s47
	s_addc_u32 s47, 0, s48
	s_cmp_gt_u32 s41, 63
	s_mul_i32 s48, s40, 0xfe5163ab
	s_mul_hi_u32 s49, s40, 0xa2f9836e
	s_mul_i32 s40, s40, 0xa2f9836e
	s_cselect_b32 s50, s43, s45
	s_cselect_b32 s42, s42, s44
	s_cselect_b32 s43, s48, s43
	s_add_u32 s40, s47, s40
	s_addc_u32 s47, 0, s49
	s_cmp_gt_u32 s41, 63
	s_cselect_b32 s48, 0xffffffc0, 0
	s_cselect_b32 s44, s44, s46
	s_cselect_b32 s40, s45, s40
	s_cselect_b32 s45, s46, s47
	s_add_i32 s48, s48, s41
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s48, 31
	s_cselect_b32 s41, 0xffffffe0, 0
	s_cselect_b32 s46, s44, s40
	s_cselect_b32 s40, s40, s45
	s_cselect_b32 s44, s50, s44
	s_cselect_b32 s45, s42, s50
	s_cselect_b32 s42, s43, s42
	s_add_i32 s41, s41, s48
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s41, 31
	s_cselect_b32 s43, 0xffffffe0, 0
	s_cselect_b32 s40, s46, s40
	s_cselect_b32 s46, s44, s46
	s_cselect_b32 s44, s45, s44
	s_cselect_b32 s42, s42, s45
	s_add_i32 s43, s43, s41
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s41, 32, s43
	s_cmp_eq_u32 s43, 0
	v_mov_b32_e32 v22, s41
	s_cselect_b32 s43, -1, 0
	v_alignbit_b32 v23, s40, s46, v22
	v_alignbit_b32 v24, s46, s44, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s41, v23
	v_cndmask_b32_e64 v23, v24, s46, s43
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s40, s40, s41
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v24, s40, v23, 30
	s_bfe_u32 s41, s40, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s45, 0, s41
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v24, s45, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v25, v24
	v_min_u32_e32 v25, 32, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v27, 23, v25
	v_alignbit_b32 v22, s44, s42, v22
	v_sub_nc_u32_e32 v26, 31, v25
	v_cndmask_b32_e64 v22, v22, s44, s43
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v23, v23, v22, 30
	v_alignbit_b32 v22, v22, s42, 30
	s_lshr_b32 s42, s40, 29
	s_lshr_b32 s40, s40, 30
	s_lshl_b32 s42, s42, 31
	v_xor_b32_e32 v23, s45, v23
	v_xor_b32_e32 v22, s45, v22
	s_or_b32 s43, s42, 0.5
	s_add_i32 s41, s41, s40
	v_sub_nc_u32_e32 v27, s43, v27
	v_alignbit_b32 v24, v24, v23, v26
	v_alignbit_b32 v22, v23, v22, v26
	s_mov_b32 s40, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v23, v24, v22, 9
	v_lshrrev_b32_e32 v24, 9, v24
	v_clz_i32_u32_e32 v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v26, 32, v26
	v_sub_nc_u32_e32 v28, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v23, v22, v28
	v_or_b32_e32 v23, v24, v27
	v_add_nc_u32_e32 v25, v26, v25
	v_lshrrev_b32_e32 v22, 9, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v25, 0x3fc90fda, v23 :: v_dual_lshlrev_b32 v24, 23, v25
	v_sub_nc_u32_e32 v22, v22, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, 0x3fc90fda, v23, -v25
	v_add_nc_u32_e32 v22, 0x33000000, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, 0x33a22168, v23
	v_or_b32_e32 v22, s42, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, 0x3fc90fda, v22
	v_add_f32_e32 v22, v25, v24
	s_branch .LBB0_27
.LBB0_26:                               ;   in Loop: Header=BB0_11 Depth=2
	s_mov_b32 s40, -1
                                        ; implicit-def: $sgpr41
                                        ; implicit-def: $vgpr22
.LBB0_27:                               ; %Flow
                                        ;   in Loop: Header=BB0_11 Depth=2
	v_mov_b32_e32 v23, s41
	s_and_not1_b32 vcc_lo, exec_lo, s40
	s_cbranch_vccnz .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_11 Depth=2
	v_mul_f32_e64 v22, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v23, v22
	v_fma_f32 v22, 0xbfc90fda, v23, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, 0xb3a22168, v23
	v_fmac_f32_e32 v22, 0xa7c234c4, v23
	v_cvt_i32_f32_e32 v23, v23
.LBB0_29:                               ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB0_11 Depth=2
	v_dual_mul_f32 v24, v20, v20 :: v_dual_and_b32 v25, 1, v21
	v_lshlrev_b32_e32 v21, 30, v21
	v_xor_b32_e32 v29, s1, v0
	v_mul_f32_e32 v28, v22, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmaak_f32 v26, s36, v24, 0x3c0881c4
	v_dual_fmaak_f32 v27, s37, v24, 0xbab64f3b :: v_dual_and_b32 v30, 1, v23
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	v_fmaak_f32 v31, s36, v28, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v26, v24, v26, 0xbe2aaa9d :: v_dual_lshlrev_b32 v23, 30, v23
	v_fmaak_f32 v32, s37, v28, 0xbab64f3b
	v_and_b32_e32 v21, 0x80000000, v21
	v_fmaak_f32 v31, v28, v31, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v26, v24, v26 :: v_dual_and_b32 v23, 0x80000000, v23
	v_fmaak_f32 v32, v28, v32, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v21, v29, v21
	v_fmac_f32_e32 v20, v20, v26
	v_mul_f32_e32 v26, v28, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v27, v24, v27, 0x3d2aabf7 :: v_dual_fmac_f32 v22, v22, v26
	v_fmaak_f32 v27, v24, v27, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, v24, v27, 1.0
	v_fmaak_f32 v27, v28, v32, 0xbf000004
	v_cndmask_b32_e32 v20, v24, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v24, v28, v27, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v30
	v_xor_b32_e32 v20, v21, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, -v22, v24, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_cndmask_b32_e32 v0, 0x7fc00000, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v20, v23, v21
	v_xor_b32_e32 v0, 0x80000000, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0x7fc00000, v20, vcc_lo
	global_store_b32 v[11:12], v0, off
	global_store_b32 v[13:14], v20, off
.LBB0_30:                               ; %Flow220
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[5:6], v[5:6], 1.0
	s_add_i32 s38, s38, 1
	s_add_i32 s39, s39, s30
	s_cmp_eq_u32 s38, s25
	s_cbranch_scc0 .LBB0_11
.LBB0_31:                               ; %._crit_edge150
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s22, v1
	s_or_b32 s31, vcc_lo, s31
	s_and_not1_b32 exec_lo, exec_lo, s31
	s_cbranch_execnz .LBB0_2
.LBB0_32:                               ; %._crit_edge154
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel applyKernels
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 52
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	applyKernels, .Lfunc_end0-applyKernels
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3304
; NumSgprs: 54
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 54
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           applyKernels
    .private_segment_fixed_size: 0
    .sgpr_count:     54
    .sgpr_spill_count: 0
    .symbol:         applyKernels.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
